JP2007129115A - Manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device containing a method polishing the flattening of the surface of a super junction structure for forming a drift layer for a super junction semiconductor device, by a flatness at a higher degree without deteriorating the precision of an alignment marker by a simplified process. <P>SOLUTION: In a first polishing process, parallel insulating films for forming trenches, parallel trenches formed while using the parallel insulating films as masks, and markers are formed on the surface of a semiconductor substrate laminating one conductivity type semiconductor layer on a low-resistance semiconductor substrate; the parallel trenches are filled inside the parallel trenches with the other conductivity type semiconductor layers; and the projections of the filling are removed. In a second polishing process, the semiconductor layers as lower layers are polished after polishing the parallel insulating films and the other conductivity type semiconductor layer. In the manufacturing method for a semiconductor element, the first polishing process and the second polishing process are conducted continuously. The manufacturing method for the semiconductor element uses polishing slurry having different polishing rates to the insulating films and the semiconductor layers respectively in the first and second polishing processes. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly, by epitaxially growing a second conductivity type semiconductor in a plurality of trenches formed perpendicular to the main surface of the first conductivity type semiconductor substrate, the first conductivity type. The remaining regions of the semiconductor substrate and the second conductivity type semiconductor regions formed by the epitaxial growth are perpendicular to the main surface and are alternately in parallel with each other, so that the main surface is perpendicular to the main surface and parallel to each other. The present invention relates to a method for manufacturing a semiconductor device improved so as to efficiently form a so-called superjunction structure having a plurality of pn junction surfaces.

Generally, semiconductor elements are classified into a horizontal element in which electrodes are formed on one side of a semiconductor substrate and a vertical element having electrodes on both sides. In the vertical semiconductor element, the direction in which the drift current flows in the on state is the same as the direction in which the depletion layer due to the reverse bias voltage extends in the off state. In a normal planar n-channel vertical MOSFET (insulated gate field effect transistor), the high-resistance n ⁻ drift layer portion functions as a region in which a drift current flows in the vertical direction when in the on state. Therefore, if the current path of the n ⁻ drift layer is shortened, the drift resistance is lowered, so that the effect of reducing the substantial on-resistance of the MOSFET can be obtained.
On the other hand, the portion of the high resistance n ⁻ drift layer is depleted in the off state to increase the breakdown voltage. Therefore, when the n ⁻ drift layer is thinned, the width of the drain-base depletion layer proceeding from the pn junction between the P base region and the drift region is narrowed, and the critical electric field strength of silicon is reached quickly. It will decline. On the contrary, in a semiconductor device with a high breakdown voltage, since the n ⁻ drift layer is thick, the on-resistance increases and the loss increases. Thus, there is a trade-off relationship between on-resistance and breakdown voltage. This trade-off relationship is also known to hold in semiconductor devices such as IGBTs (insulated gate bipolar transistors), bipolar transistors, and diodes. This trade-off relationship is also common to lateral semiconductor elements in which the direction in which the drift current flows in the on state and the direction in which the depletion layer extends in the off state are different. As a solution to the above-described problem due to the trade-off relationship, a super junction semiconductor element having a parallel pn layer structure in which an n-type drift region and a p-type partition region having a high impurity concentration are alternately and repeatedly joined is used as a drift layer. Known (Patent Documents 1, 2, 3, 4). In the semiconductor element having such a structure, even when the impurity concentration of the parallel pn layer structure is high, the depletion layer spreads laterally from each pn junction extending in the vertical direction of the parallel pn layer structure in the off state, and drifts. Since the entire region is depleted, a high breakdown voltage can be achieved.

The superjunction semiconductor element as described above has a complicated superjunction structure, and it is difficult to produce the superjunction structure on a semiconductor substrate at low cost. As a method for mass-producing a semiconductor substrate having such a parallel pn layer structure at a low cost and with a high yield rate, a parallel trench is formed in an n-type silicon semiconductor substrate, and the inside of the trench is epitaxially grown of a p-type silicon semiconductor. A method of forming a superjunction structure by embedding with a layer is known (Patent Documents 5, 6, 7, and 8).
In this method, as shown in FIG. 9, for a wafer in which an n-type silicon epitaxial layer 2 is formed on an n ⁺⁺ type silicon semiconductor substrate 1, trenches 2-2 are formed using an oxide film 4 provided on the wafer surface as an etching mask. After the formation, when the p-type silicon semiconductor 2-1 is filled in the trench 2-2 by epitaxial growth, a step of 1 to several μm, the oxide film 4, the p-type epitaxial silicon layer 2-1, etc. are formed on the wafer surface. Since the protrusion is present and is not flat, the surface of the semiconductor substrate needs to be polished by a CMP (Chemical Mechanical Polishing) apparatus or the like to remove the oxide film 4 and the p-type epitaxial silicon layer 2-1 and planarize it. .

  As a modification, as shown in FIG. 10A, the wafer surface is polished and planarized by a CMP apparatus using the oxide film 4 used as a mask during trench etching as a stopper film, and thereafter, FIG. After removing the oxide film 4 by immersing in hydrofluoric acid etching as shown in FIG. 3, the surface of the n-type epitaxial silicon layer 2-1 on the surface is polished again by the CMP apparatus, and further to the depth shown by the dotted line 2-3. A method of polishing a wafer to a mirror surface is known (Patent Document 13). However, in the manufacture of this type of semiconductor substrate (wafer), the polished wafer surface becomes a perfect mirror surface, making it impossible to confirm the optical pn junction structure. As shown in FIG. A technique is known in which an alignment marker (alignment marker) 3 having a width of 10 to 20 μm and a depth of 1 to 50 μm is formed in advance and left until after the wafer is completed (Patent Document 9).

As an end point detection technique during polishing by a CMP apparatus, the fact that a stopper film having a low polishing speed has been reached during polishing, an increase in the load current of the motor used to rotate the support base of the CMP apparatus, which appears at that time, is shown. A technique for detecting and setting a polishing end point is known (Patent Document 10).
In addition, a technique is known in which a polishing pad provided with a light-transmitting observation window is used to irradiate a wafer being polished with white or monochromatic probe light and detect the end point from the reflection spectrum (Patent Document 11). Patent Document 12).
European Patent Application No. 0053854 US Pat. No. 5,216,275 US Pat. No. 5,438,215 JP-A-9-266611 JP 2002-124474 A JP 2001-127289 A JP 2001-196573 A Japanese Patent Laid-Open No. 2004-63894 JP 2004-63894 A JP 2002-9031 A JP 2000-186918 A JP 2000-183001 A JP-A-2005-57142

However, as shown in the above-mentioned Patent Document 13, when an epitaxial layer is buried in a trench and then the oxide film is removed by etching with hydrofluoric acid and then planarized by CMP polishing, there are the following four problems. is there.
The first problem is that, as shown in FIG. 9A, the p-type epitaxial layer 2-1 protrudes upward from the oxide film 4 on the wafer surface, so that the p-type epitaxial layers are partially in contact with each other. However, since the oxide film 4 may remain without being etched, the planarization by the CMP apparatus cannot be normally performed due to the influence, and the planarization may be hindered.
The second problem is that even if the oxide film 4 is completely removed, when the protruding p-type epitaxial layer 2-1 is polished, cracks or the like occur in the p-type epitaxial layer 2-1, And remains on the surface, and the shavings cause a large amount of scratches on the wafer surface.

The third problem is that in order to polish the p-type epitaxial layer 2-1 protruding about several μm, the surface of the wafer cannot be flattened unless the wafer surface is further removed by about several μm at least due to the influence of dishing. In general, it is considered that the surface of the wafer needs to be polished by about 5 to 10 μm, which increases the polishing time, increases the cost of consumables for the slurry and polishing pad, and increases the cost.
The fourth problem is that if the wafer surface is polished excessively by about 5 to 10 μm as described above, the marker 3 disappears during polishing with the shallow alignment marker 3 of 10 μm or less, and the deep alignment marker 3 does not have the same during polishing. The scraps are taken into the recesses of the marker and cause particles, and in either case, it becomes a problem. In particular, on the surface of the alignment marker 3, the oxide film 4 is removed and the hydrophobic silicon surface is exposed. For this reason, even if the cleaning process is performed in the CMP apparatus, the dust that has entered the marker unit 3 is not sufficiently discharged and remains.

As a countermeasure against the above-mentioned problem, as shown in FIG. 10A, the oxide film 4 is used as a stopper film and is flattened by CMP, and then the oxide film 4 is removed by hydrofluoric acid as shown in FIG. 10B. Finally, a method of planarizing again with a CMP apparatus is also considered. However, this method is effective in suppressing scratches on the wafer surface and the amount of silicon polishing, but has the following two problems.
The first problem is that it is difficult to remove dust in the cleaning process because the hydrophobic silicon surface is exposed in the alignment marker portion 3 in the last CMP process, and the second problem is a thick oxidation of about 1 μm. Since it is difficult to perform the process of etching the film 4 in the CMP apparatus, it is necessary to perform the planarization process in three steps: a CMP process, an oxide film etching process, and a CMP process.

For this reason, it leads to the cost increase of semiconductor substrate manufacture. Further, when forming a deep trench 2-2 having a thickness of about 50 μm using the oxide film 4 as a hard mask, the film thickness of the oxide film after the trench etching is about 0.5 μm between the outer peripheral portion and the central portion of the wafer. It is generally known that the film has a convex film thickness distribution (thick oxide residue film distribution at the outer periphery and thin at the center). Therefore, when the oxide film polishing and the silicon layer mirror polishing are continuously performed by CMP, the height difference between the central portion and the outer peripheral portion is maintained even after polishing the silicon layer after polishing the oxide film, and the alignment marker 3 There is a problem that the distribution of the depth of the marker is also distributed, and the marker accuracy deteriorates.
Furthermore, since the polishing rate of the silicon layer is usually larger than the polishing rate of the oxide film, the difference in height after mirror polishing of the silicon layer is higher or lower than the polishing ratio by multiplying the selection ratio (silicon polishing rate / oxide polishing rate). Increased to the extent of the difference. For example, in the case of an initial oxide film thickness difference of 0.5 μm, when polished under the condition of a selection ratio of 2, the height difference of the silicon layer expands to about 1 μm. Furthermore, an end point detection technique for controlling the silicon polishing amount to a constant value has not been established.

  The present invention has been made in view of the above points, and an object of the present invention is to form a parallel trench perpendicular to the surface of a semiconductor substrate and etch the trench in order to form a drift layer of a superjunction semiconductor device. After forming a mask oxide film pattern and an alignment marker on the surface of the semiconductor substrate and filling the trench with an epitaxial layer, without reducing the accuracy of the alignment marker in a simplified process, The present invention provides a method for manufacturing a semiconductor device, including a method for polishing the surface of the semiconductor substrate with a higher degree of flatness.

  According to the first aspect of the present invention, the trench forming parallel insulating film pattern is formed on the surface of the one conductive semiconductor layer of the semiconductor substrate in which the one conductive semiconductor layer is laminated on the low resistance semiconductor substrate. Then, a parallel trench perpendicular to the semiconductor surface etched with the parallel insulating film pattern as a mask and an alignment marker are formed, and another parallel conductive semiconductor layer is filled in the parallel trench, and then the protruding portion A first polishing step for removing the conductive semiconductor layer and a second polishing step for simultaneously polishing the parallel insulating film pattern and the other conductive type semiconductor layer and subsequently polishing the lower semiconductor layer are continuously performed. In the method of manufacturing a semiconductor device, the first and second polishing steps use a semiconductor element that uses a polishing slurry having different polishing rates for the insulating film and the semiconductor layer, respectively. With the method of manufacturing, the object of the present invention can be achieved.

According to the second aspect of the present invention, the polishing supplies the polishing slurry while rotating the polishing pad held on the rotary table, and rotates the semiconductor substrate held by the polishing head. However, it is preferable to use a method of manufacturing a semiconductor element that is performed using a CMP apparatus that presses and polishes the upper surface of the polishing pad.
According to the third aspect of the present invention, the polishing rate distribution in the semiconductor substrate surface with respect to the parallel insulating film pattern in the second polishing step is determined in the semiconductor substrate surface of the parallel insulating layer pattern. 3. The method of manufacturing a semiconductor element according to claim 1, wherein polishing conditions are set so as to be large at the center portion of the semiconductor substrate and gradually become smaller toward the outer peripheral portion so as to be flattened by correcting the film thickness distribution. More preferably.
According to the present invention as set forth in claim 4, in the first polishing step, the selectivity expressed by the polishing rate of the semiconductor layer / the polishing rate of the insulating film is 30 or more, preferably 60 or more. 4. The method of manufacturing a semiconductor device according to claim 1, wherein a high selectivity slurry is used, and a low selectivity slurry having a selectivity of 3 or less, preferably 2 or less is used in the second polishing step. 5. Is more preferable.

According to the present invention of claim 5, the semiconductor device according to claim 2, wherein a polishing pad provided with a lattice-like groove is used in the second polishing step. A manufacturing method is also preferred.
According to the present invention as set forth in claim 6, in the second polishing step, the number of rotations of the rotary table in the CMP apparatus is performed at 42 or more rotations. The manufacturing method of the semiconductor device described is preferable.
The semiconductor device according to claim 1, wherein the insulating film is a thermal oxide film or an oxide film formed by thermal CVD or plasma CVD. It is more preferable to use a manufacturing method.
According to the present invention as set forth in claim 8, it is more preferable that the oxide film formed by thermal CVD or plasma CVD is a BPSG oxide film.

According to the present invention of claim 9, in the second polishing step, the polishing is performed with such a pressure distribution that the pressing force received by the central portion of the semiconductor substrate is higher than that of the outer peripheral portion. It is also preferable to adopt the method for manufacturing a semiconductor device according to any one of Items 3 to 8.
According to the tenth aspect of the present invention, the change in load current of the polishing head or the rotary table is used for detecting the polishing end point in the second polishing step. It is desirable to use the method for manufacturing the semiconductor device.
According to the present invention of claim 11, in the second polishing step, in order to monitor the film thickness of the insulating film being polished, an optical reflection spectrum by monochromatic or white light with respect to the insulating film is measured. It is also desirable to adopt a method for manufacturing a semiconductor device according to any one of claims 1 to 10.

According to the twelfth aspect of the present invention, it is also possible to use the semiconductor device manufacturing method according to the eleventh aspect in which the polishing end point detection of the insulating film is detected by comparison with a reference reflection spectrum.
According to the present invention as set forth in claim 13, the method of manufacturing a semiconductor device according to claim 11 or 12, wherein the film thickness of the insulating film is derived from the optical fitting of the thin film.
According to the present invention of claim 14, after the insulating film is completely removed, the semiconductor layer is further polished in a thickness range of 0.2 to 2 μm. It is more desirable to use the method for manufacturing a semiconductor device according to any one of the above.
According to the present invention as set forth in claim 15, the depth of the concave portion of the alignment marker is in the range of 0.5 μm to 8 μm based on the polished surface after the second polishing step. It is recommended to use the method for manufacturing a semiconductor device according to any one of 14 above.

According to the sixteenth aspect of the present invention, it is even more desirable to provide a method for manufacturing a semiconductor device in which the alignment marker after the second polishing step is covered with an insulating film.
Further, in summary, the present invention divides CMP polishing into two steps, and sequentially performs a first polishing step using a high selection ratio slurry and a second polishing step using a low selection ratio slurry. In the first polishing step, the surface of the semiconductor substrate is flattened using the oxide film as a stopper, and in the second polishing step, the oxide film and the p-type semiconductor layer are simultaneously polished and removed, and the lower semiconductor layer is about 0.5 to 2 μm. Further, when the surface is further polished to obtain a flat mirror surface, the polishing process is finished.
In these two steps, the selection ratio in the first polishing step is preferably 30 or more, more preferably 60 or more, and the selection ratio in the second polishing step is preferably 3 or less, more preferably 2 or less. In addition, the first polishing step and the second polishing step can be substantially one step when continuous processing is performed with one CMP apparatus. Further, in order to prevent generation of dust from the alignment marker, the alignment marker surface is covered with an oxide film after the second polishing step, in which the depth of the alignment marker is 10 μm or less including during the polishing process. is necessary.

Polishing rate distribution in the second polishing process to correspond to the distribution in the semiconductor substrate of the convex oxide film thickness generated by the trench etching (the distribution of the oxide film in the central part in the semiconductor substrate is larger than the oxide film thickness in the outer peripheral part) Is corrected so that the convex film thickness distribution of the oxide film is flattened so as to be convex (the polishing rate distribution in the central portion of the semiconductor substrate is larger than the outer peripheral portion). For this purpose, it is effective to use a polishing pad with a lattice groove and to set the number of rotations of the polishing table to 42 rpm or more. Furthermore, it is effective to use a BPSG film as the oxide film, and to have a pressure distribution such that the pressing force of the polishing pad at the center of the semiconductor substrate is higher than that of the outer periphery during CMP polishing.
In the second polishing step, it is effective to use one of the following two end point detection techniques in order to appropriately determine the polishing end point. First, as a first method, a motor load current of a polishing table or a polishing head is used. In the second polishing step, after the oxide film is completely removed, the motor load current is stabilized, so the polishing time of the semiconductor layer is determined from the length. As a second method, there is a method of measuring a reflection spectrum of a wafer being polished. As the method, there are a method of comparing with a bare silicon wafer as a reference, and a method of deriving an oxide film thickness during polishing from optical fitting with a calculated reflection spectrum.

  According to the present invention, since a series of polishing steps can be performed without deteriorating alignment marker recognizability, the steps can be simplified, and the surface of a semiconductor substrate necessary for manufacturing a superjunction semiconductor element can be planarized. Thus, it is possible to provide a method for manufacturing a semiconductor device in which the variation in film thickness in the polishing step is small and there is no generation of scratches or dust from alignment marks, and a high yield rate can be obtained.

Embodiments of a method for manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the drawings. However, the present invention is not limited to the description of the following examples unless it exceeds the gist.
FIGS. 1-1 to 1-4 are cross-sectional views of main parts of a semiconductor substrate shown for each manufacturing process described in the first embodiment according to the method for manufacturing a semiconductor device of the present invention, and FIG. FIG. 3 is a cross-sectional view of the semiconductor substrate after the oxide film surface polishing according to the present invention, and FIG. 4 is a graph in which the rotational speeds of the polishing pad and the polishing table according to the present invention are used as parameters. FIG. 5 is a relationship diagram between the motor load current and the polishing time in the second polishing step according to the present invention, and FIG. 6 shows three types of oxide films (heats) according to the present invention. FIG. 7 is a schematic diagram of an optical measurement system for evaluating a reflection spectrum during polishing according to the present invention, and FIG. Invention Is a reflection spectrum diagram during the polishing of the conductive substrate.

FIG. 1 is a cross-sectional view of a principal part for each manufacturing process of a semiconductor substrate for explaining a method of manufacturing a superjunction structure portion of a vertical superjunction MOSFET. First, an n ⁺⁺ type high-impurity concentration low-resistance silicon substrate 1 prepared by antimony doping, arsenic doping, or the like is prepared. The crystal plane orientation is (100) on the principal plane and (100) on the orientation flat. The impurity concentration of the n ⁺⁺ type low resistance substrate 1 is about 2 × 10 ¹⁸ cm ⁻³ . An epitaxial silicon layer 2 having a thickness of about 50 μm and an impurity concentration of about 6 × 10 ¹⁵ cm ^{−3 is} grown on the low-resistance substrate 1 (FIG. 1A).
After that, the alignment marker 3 is formed on the surface of the phosphorus-doped n-type epitaxial growth layer 2. At this time, the depth of the alignment marker 3 is about 1 to 10 μm. In Example 1, the depth of the alignment marker 3 was 3 μm (FIG. 1B). The alignment marker is used to increase mask alignment accuracy in the photolithography process. This alignment marker 3 is formed by dry etching, and any of anisotropic and isotropic etching may be used.

In the case of anisotropic etching, it is necessary to increase the thickness of the insulating film serving as a hard mask when forming a trench, which will be described later, but it is possible to ensure alignment accuracy in mask alignment. In the case of isotropic etching, the alignment accuracy is worse than that in the case of anisotropic etching, but the thickness of the insulating film serving as a hard mask during trench formation can be reduced.
Below, the example which formed the target by anisotropic etching is demonstrated. After the alignment marker 3 is formed by dry etching, an insulating film 4 serving as a hard mask when forming the trench is formed. In Example 1, the thermal oxide film 4 having a thickness of about 2.4 μm was formed on the semiconductor substrate after the alignment marker 3 was formed. This insulating film may be other than the thermal oxide film, and may be an oxide film such as HTO (High Temperature Oxide) or TEOS (Tetra Ethyl Ortho Silicate) by thermal CVD or plasma CVD.

Thereafter, an opening 4-1 is selectively formed at a portion where trench etching is performed on the oxide film 4 by patterning (FIG. 1C). In Example 1, the width of the opening 4-1 formed in the oxide film 4 is about 5 μm, and the width of the portion where the oxide film 4 is left is about 5 μm. As a result, trenches having a width of 5 μm can be formed at intervals of 5 μm. Next, the trench 5 is formed using the selectively opened oxide film 4 as a hard mask. In Example 1, the trench 5 having a depth of about 50 μm was formed. At this time, the oxide film 4 serving as a mask when forming the trench 5 is also etched by about 1.4 μm, and the remaining film thickness of the oxide film 4 becomes about 1 μm (FIG. 1D).
FIG. 2 shows the remaining film thickness distribution in the semiconductor substrate for the oxide film 4 after trench etching. The horizontal axis represents the position of the semiconductor substrate having a diameter of 150 mm, and the vertical axis represents the remaining film thickness (unit of angstrom) of the oxide film 4 after the trench etching. As shown in FIG. 2, the oxide film 4 after the trench etching has a convex distribution with a thick oxide film in the central portion having a width of about 0.4 μm between the outer peripheral portion and the central portion of the semiconductor substrate. ing.

Next, boron-doped p-type epitaxial growth is performed in the trench 5 having a depth of 50 μm to fill the p-type silicon epitaxial layer 2-1. Epitaxial growth in the trench 5 is performed at normal pressure, but it is preferable to remove the natural oxide film in a hydrogen atmosphere at normal pressure prior to that. When the p-type epitaxial layer 2-1 is grown in the trench 5, the surface of the central portion of the p-type epitaxial layer 2-1 has a concave shape as shown in FIG. It is necessary to grow the epitaxial layer so that the height of the bottom becomes higher than the surface of the remaining oxide film 4 of the hard mask.
Although not shown, when two types of trenches having different widths are formed, the epitaxial growth layer is formed so that the bottom of the concave portion in which the widest trench is buried is higher than the surface of the remaining oxide film. It is good to fill. At this time, the impurity concentration of the epitaxial growth layer 2-1 is about 6 × 10 ¹⁵ cm ^{−3 by} boron doping. The impurity concentration is the same as the impurity concentration although the conductivity type is opposite to that of the n-type epitaxial growth layer 2 formed on the low-resistance substrate 1.

By doing so, a parallel pn layer having the same impurity concentration as the superjunction structure can be formed in the drift layer of the superjunction semiconductor element. Since the alignment marker 3 is covered with the oxide film 4, the n-type epitaxial layer 2-1 hardly grows on the alignment marker portion 3 (FIG. 1 (e)). This semiconductor substrate is carried into a CMP (Chemical Mechanical Polish) apparatus, and a p-type epitaxial layer protruding above the trench 5 by using a polishing liquid (slurry) having a higher etching rate with respect to silicon than the oxide film using the thermal oxide film 4 as a stopper. The layer 2-1 is polished to the surface of the oxide film indicated by the arrow 2-4 and flattened (this is the first polishing step after being loaded into the CMP apparatus) (FIG. 1 (f)).
Next, simultaneous polishing of the p-type epitaxial layer 2-1 located between the oxide film 4 and the oxide film 4, and after that, polishing for the purpose of mirror finishing is continuously performed up to the dotted line 2-5. Then, as shown in FIG. 1 (g), the surface of the parallel pn layer can be mirror-finished while the recesses of the alignment marker 3 remain properly (this is the second polishing step). Here, EPO-113D manufactured by Ebara Seisakusho as a CMP apparatus was used. The polishing pressure control system of this apparatus is a backing film type. Table 1 below shows each polishing condition in the first and second polishing steps.

まず、ＣＭＰ装置において、エッチング選択比（シリコン研磨レート／酸化膜研磨レート）が３０以上の高選択比スラリーを供給しながら、研磨ヘッドを研磨パッドに押し当て第一研磨工程を行った。研磨スラリーには代表的な高選択比スラリーであるフジミ社製のＰｌａｎｅｒｌｉｔｅ ６１０１を用い、研磨パッドにはロデール社製のＩＣ１０００／ｓｕｂａ４００複合パッドを用いた。なお、研磨パッドには、通常、研磨スラリーの供給や排出を促進するために、穴や格子状あるいは同心円上の溝が設けられている。これらの形状により研磨レート分布に若干の相違が見られるが、第一研磨工程では酸化膜４が良好なストッパーになるため、どの研磨パッドを用いてもよい。ここでは、後述の穴と格子状の溝の双方を設けた研磨パッドを用いた。前記表１に示すように、第一研磨工程におけるエッチング選択比は１２０と高いため、突出したｐ型エピタキシャル層２−１を選択的に除去し、平坦になった時点で研磨を止めることは容易にできる。

First, in the CMP apparatus, the first polishing step was performed by pressing the polishing head against the polishing pad while supplying a high selection ratio slurry having an etching selection ratio (silicon polishing rate / oxide polishing rate) of 30 or more. As the polishing slurry, Planlite 6101 manufactured by Fujimi, which is a typical high selectivity slurry, was used. As the polishing pad, an IC1000 / suba400 composite pad manufactured by Rodel was used. Note that the polishing pad is usually provided with holes, grids or concentric grooves in order to promote the supply and discharge of the polishing slurry. Although the polishing rate distribution is slightly different depending on these shapes, any polishing pad may be used because the oxide film 4 serves as a good stopper in the first polishing step. Here, a polishing pad provided with both holes and lattice-like grooves described later was used. As shown in Table 1, since the etching selectivity in the first polishing step is as high as 120, it is easy to selectively remove the protruding p-type epitaxial layer 2-1 and stop polishing when it becomes flat. Can be.

As for the polishing time, a method using polishing for a fixed time or an end point signal is effective. As the former fixed time polishing method, a good shape is obtained by polishing for a fixed time based on the time until the p-type epitaxial layer 2-1 is completely removed and multiplied by a coefficient of about 1.1 to 1.3. can get. As the latter end point signal method, it is effective to use a change in the load current of the polishing head or the polishing table for end point detection (in the case of a polishing table, it means a combination of a rotary table and a polishing pad). When the p-type epitaxial layer 2-1 is removed and the oxide film 4 appears, the load current changes and can be detected as an end point.
After the first polishing step was completed, the second polishing step was performed with the same polishing pad. In addition, the pure water substitution for about 5 to 30 seconds was performed between the 1st grinding | polishing process and the 2nd grinding | polishing process so that polishing slurry might not mix. In the second polishing step, a low selection ratio slurry having a selection ratio of 3 or less is used, and the polishing removal of the layer having the oxide film and the mirror (mirror surface) polishing of the parallel epitaxial growth layer of the underlying p layer and n layer are continuously performed. went.

  An image of an ideal semiconductor substrate in the second polishing step is schematically shown in FIG. The oxide film 4 immediately before the second polishing step has a convex film thickness distribution in the semiconductor substrate due to the above-described formation of the trench 5 (the film thickness distribution in which the oxide film thickness in the central portion of the semiconductor substrate is larger than the outer peripheral portion). When the oxide film 4 is polished as it is, the convex film thickness distribution maintains the convex shape as shown by a chain line 6-1 even after the oxide film 4 is completely polished and removed. (FIG. 3A). Therefore, as shown in FIG. 3B, polishing is performed at a convex polishing rate (a convex polishing rate is a polishing rate in which the polishing rate at the center is higher than that at the outer periphery) so as to correct this. Ideally, it is ideal to stop when the polishing is continued until the polishing end line of the p-type and n-type parallel silicon epitaxial layers is flattened as indicated by the chain line 6-2. In order to realize this, the following two conditions are necessary.

The first condition is to make the polishing rate of the oxide film 4 and the silicon epitaxial layer as close to 1 as possible. The second condition is to polish the oxide film at a convex polishing rate in which the polishing rate on the outer periphery of the semiconductor substrate is 15 to 30% lower than the central portion. First, the first condition will be described. In general, the polishing rate of silicon is larger than that of an oxide film, and the selection ratio is larger than 1. This time, Cabot SS-25E was used as a polishing slurry as close to 1 as possible. The selection ratio under the current polishing conditions is about 2.3. Next, with regard to the second condition, as a result of intensive studies on conditions for realizing a convex polishing rate distribution, it was found that selection of the shape of the polishing pad and the number of rotations of the rotary table is important.
FIG. 4 shows polishing rate distributions by three types of polishing pads (FIGS. 4A, 4B, and 4C). The three types of polishing pads are (a) hole pad, (b) XY (grating) groove pad, and (c) XY (grating) groove + hole pad. The number of rotations of the rotary table (21 rpm for ♦, 42 rpm for □, 63 rpm for Δ, 84 rpm for x, 120 rpm for *) was used as a parameter. The normalized polishing rate is the vertical axis, the horizontal axis is the distance (mm) from the wafer center, and the polishing rate is 49-point circle scan (the distance from the origin (wafer center) in 12 directions is 12.5, 25.27. The film thickness at points of 5, 52.5, and 70 mm was derived from measurement), averaged for each concentric circle, and plotted as a relative value. From this result, as shown in FIGS. 4 (b) and 4 (c), the rotational speed of the rotary table is increased as much as possible by using a polishing pad provided with lattice grooves (XY grooves) or both lattice grooves and holes. It was found that a convex polishing rate distribution can be realized by polishing at a rotational speed (63 rpm or more). FIG. 4 (a) has a strong tendency to show a concave polishing rate with a low polishing rate at the center except for high-speed rotation of 120 rpm. FIG. 4 (b) and FIG. This indicates that the center polishing rate is not necessarily the highest.

The polishing pad has only a lattice groove (groove pitch of 15 mm) (FIG. 4B) and one provided with both lattice grooves and holes (groove pitch 40 mm, hole diameter 1.5 mm) (FIG. 4C). Either is acceptable, but the former is slightly better. Therefore, as shown in Table 1, a lattice groove pad was used, and the rotation speed of the rotary table was 120 rpm. There are three possible reasons why a convex polishing rate distribution (the polishing rate at the center of the wafer is larger than the outer peripheral portion) can be realized under these polishing conditions.
(Reason 1) When a hole pad is used, the flow of the polishing slurry from the outer periphery of the wafer to the center is poor, and as a result, a concave distribution tends to occur. When the groove pad is used, the polishing slurry flows in more, so that it works in the convex direction. (Reason 2) Increasing the rotational speed of the rotary table further improves the inflow of the polishing slurry. (Reason 3) The average temperature of the wafer surface increases when the number of rotations of the rotary table is increased. Further, since the outer peripheral portion of the polishing head is cooled by polishing slurry, air, or the like, a convex temperature distribution is obtained. As a result, when the rotational speed is increased, the temperature difference between the central portion and the outer peripheral portion is increased, and a convex polishing rate distribution is obtained.

As the second polishing time, either a fixed time polishing or a polishing time determination method by detecting an end point signal may be used as in the first polishing step. However, since there is no stopper film (oxide film) as a reference for determining the polishing end point as in the first polishing step in the second polishing step, more precise control is required, and any end point signal is output. It is desirable to use it. As an example, it is effective to use a motor load current of a polishing table, a polishing head, or a rotary table.
FIG. 5 shows a conceptual diagram of the time change of the motor load current during polishing of the semiconductor substrate. The load current continuously changes such as A region: oxide film covering, B region: oxide film partial removal, and C region: oxide film complete removal. Since the load current becomes a substantially constant value when the oxide film is completely removed, the end point in the case of polishing only the silicon layer is determined by setting the product of the time in region C and the polishing rate of silicon to a predetermined value. Thus, silicon polishing can be stopped at a predetermined position. The polishing film thickness of the silicon layer is effectively 0.5 to 5 μm, but here it is 1 μm.

As shown in FIG. 1G, the process is completed with the oxide film 4 remaining in the alignment marker portion 3. In order to examine the level difference of silicon in the alignment marker portion 3, the oxide film 4 remaining on the alignment marker portion 3 was etched with hydrofluoric acid and then evaluated with a surface roughness meter. It was found that the step difference of 50 markers formed on the 6-inch wafer surface was as small as 3.0 ± 0.12 μm. Since the oxide film thickness distribution after the trench etching was as large as ± 0.2 to 0.25, it was confirmed that the step was halved by the intended effect. Through the above steps, the manufacturing process of the semiconductor crystal substrate for forming the superjunction structure for the superjunction semiconductor device having the flat surface shape while leaving the stable and highly accurate alignment marker portion 3 is completed.
In Example 1, the first polishing step and the second polishing step were continuously performed with one set of polishing head and polishing pad. However, when polishing with a CMP apparatus having two or more polishing heads and polishing pads, These may be carried out using different polishing heads or polishing pads. Further, although the backing film type polishing head is used in Embodiment 1, an air bag type or air flow type apparatus capable of more uniform pressure control may be used. Furthermore, it is preferable to use a polishing head that can have a pressure distribution that makes the pressure at the outer peripheral portion smaller than the central portion.

  Example 2 is a method using an oxide film so-called BPSG (borophosphosilicate glass) film added with several percent of boron and phosphorus as a hard mask for trench formation. In this case, the oxide film formation step in the first embodiment may be replaced with BPSG film formation. The film forming method of BPSG may be either thermal CVD or plasma CVD. When BPSG is used, the etching selectivity at the time of trench etching is about 10 to 20% lower than that of the thermal oxide film of the first embodiment. In consideration of this point, it is necessary to set the BPSG film thickness slightly thicker than that in the case of the thermal oxide film. The BPSG film thickness in Example 2 was 2.6 μm. Table 2 shows the polishing conditions according to Example 2.

ＢＰＳＧ膜を用いると、二つのメリットが得られる。まず、図６に３種類の酸化膜（熱酸化膜◆印、ＬＰ−ＴＥＯＳ膜□印、ＢＰＳＧ膜△印）を用いたときの、ウエハの半径方向の研磨レート分布を示す。図６の縦軸は規格化された研磨レート、横軸はウエハ中心からの距離である。この結果から、ＢＰＳＧ膜を用いると研磨レート分布が熱酸化膜やＬＰ−ＴＥＯＳ膜に比べ凸型化（中央部の研磨レートが大きい）がさらに進んでいることが分かる。このときの外周部の研磨レートは中心部よりも約２６％低く、トレンチエッチング工程で生じる酸化膜厚分布を打ち消すような理想的な形状が得られることが分かった。
次に、前記表２に示すように、ＢＰＳＧ膜を用いると第一研磨工程における選択比が前記表１の熱酸化膜より若干低下（１２０が７５に低下）するものの、第二研磨工程における選択比も低下（２．３から１．１に低下）して、ほぼ１に近い１．１になることが分かった。第二研磨工程は、酸化膜の研磨除去とその後の下層のシリコン層の鏡面研磨が連続的であるため、選択比が大きいと最終的な研磨量バラツキを増大させてしまう。選択比が１に近いということは酸化膜研磨からシリコン層研磨へ移る際に研磨レートの変化が無いということであって非常に理想的なことであり、ＢＰＳＧ膜とシリコンとを連続体として研磨でき、研磨量バラツキの抑制が容易になる。

The use of a BPSG film provides two advantages. First, FIG. 6 shows the polishing rate distribution in the radial direction of the wafer when three types of oxide films (thermal oxide film ◆, LP-TEOS film □, and BPSG film Δ) are used. The vertical axis in FIG. 6 is a normalized polishing rate, and the horizontal axis is the distance from the wafer center. From this result, it can be seen that when the BPSG film is used, the polishing rate distribution is more convex (the polishing rate at the center is larger) than the thermal oxide film or the LP-TEOS film. At this time, the polishing rate of the outer peripheral portion is about 26% lower than that of the central portion, and it has been found that an ideal shape can be obtained that cancels the oxide film thickness distribution generated in the trench etching process.
Next, as shown in Table 2, when the BPSG film is used, the selection ratio in the first polishing process is slightly lower than the thermal oxide film in Table 1 (120 is reduced to 75), but the selection in the second polishing process is performed. It was also found that the ratio also decreased (from 2.3 to 1.1) to 1.1 close to 1. In the second polishing step, the removal of the oxide film and the subsequent mirror polishing of the lower silicon layer are continuous. Therefore, if the selection ratio is large, the final polishing amount variation is increased. The selection ratio close to 1 means that there is no change in the polishing rate when shifting from oxide film polishing to silicon layer polishing, which is very ideal. Polishing with a BPSG film and silicon as a continuum This makes it easy to suppress variations in the polishing amount.

  Finally, the steps of 50 markers formed on the 6-inch wafer surface were examined in the same manner as in Example 1. As a result, the step was 3.0 ± 0.07 μm, and it was confirmed that the step variation was suppressed more than in Example 1.

Example 3 is a method using optical reflectance measurement as a method for monitoring the remaining thickness of the oxide film in the second polishing step. In this method, an optical measurement system as shown in FIG. 7 in which an optical measurement system is added to the CMP apparatus is used. Wafer 7 that is polished by slurry 15 while white light 12-1 is held by polishing head 8 and rotated through lamp 12 through quartz window 11 provided in rotary table 9, polishing pad 10, and holes provided in the rotary table. The reflection spectrum is measured in synchronization with the rotation of the rotary table 9, and the data is stored in the computer 14 via the light detection device 13. FIG. 8 shows a typical reflection spectrum waveform measured during surface polishing of the semiconductor substrate (wafer) according to the present invention using this optical measurement system.
The reflection spectrum diagram shown in FIG. 8 shows a state after the oxide film 4 other than the marker portion 3 is completely removed by polishing (for example, after polishing to the dotted line 2-5 shown in FIG. 1 (f)). 1 (g)), as shown by the chain line in FIG. 8, fringes due to multiple interference as seen in the initial and intermediate spectra (thick and thin solid lines) disappear, and the reflectance of the reflection spectrum changes with time. Is not seen, indicating that the reflectance is constant. The following two methods are conceivable as methods for detecting the end point using this reflection spectrum measurement.

The first end point detection method is a method for comparison with a reference reflection spectrum. The reflection spectrum when the silicon mirror surface is polished is previously input to the computer 14 as a reference, and the reflection spectrum during the second polishing process is sequentially compared. When the reflection spectrum in the second polishing process matches the reference spectrum, it is determined that the oxide film is completely removed, and the second polishing process is terminated by extra polishing of a predetermined amount of the semiconductor layer.
The second end point detection method is a method in which the reflection spectrum is optically fitted by an optical model, and the remaining film thickness of the oxide film is sequentially derived by calculation. In the case of Example 3, it can be considered that the optical layer configuration of the semiconductor substrate is divided into two regions of the oxide film 4 and the silicon 2 as can be seen from FIG. For the oxide film 4 and the silicon layer 2, the ratio of the thickness (about 1 μm) of the target portion whose reflection spectrum is to be measured is about 1: 1. In consideration of this point, the remaining film thickness of the oxide film can be sequentially monitored by optical fitting of the reflection spectrum. This method is particularly effective when the time change of the motor load current is small and cannot be used for end point detection. A method of monitoring the remaining thickness of the oxide film by optical fitting of the optical model is described in detail in Japanese Patent Application Laid-Open No. 2001-21317.

According to the first, second, and third embodiments, it is possible to simplify the polishing process such that the recognition process of the alignment marker is not deteriorated, and the parallel strips necessary for manufacturing the superjunction semiconductor device can be simplified. In the polishing process for flattening the surface of a semiconductor substrate having a superjunction structure in which a p-type semiconductor layer and an n-type semiconductor layer are provided in a direction perpendicular to the main surface of the semiconductor substrate, the film thickness variation can be reduced and the yield rate is high. be able to.
In the first, second, and third embodiments described above, the semiconductor device manufacturing method of the present invention has been described in detail assuming a superjunction semiconductor device using silicon. However, other semiconductor crystals such as SiC are used. The present invention can also be applied to a superjunction semiconductor device. Further, in the first, second, and third embodiments, the case where the p-type silicon epitaxial layer is buried in the trench formed in the n-type silicon epitaxial region has been described. However, the trench of the p-type epitaxial layer can be changed by appropriately changing the conductivity type. Needless to say, the present invention can also be applied to the case where an n-type epitaxial layer is embedded.

Sectional drawing of process of semiconductor substrate of Example 1 according to manufacturing method of semiconductor device of the present invention (Part 1) Sectional drawing of process of semiconductor substrate of Example 1 according to manufacturing method of semiconductor device of the present invention (Part 2) Sectional view of semiconductor substrate of Example 1 according to manufacturing method of semiconductor device of the present invention (No. 3) Sectional drawing of the semiconductor substrate of Example 1 concerning the manufacturing method of the semiconductor device of this invention (the 4) Oxide film thickness distribution diagram after trench etching according to the present invention, Sectional drawing of the semiconductor substrate after the oxide film surface grinding | polishing concerning this invention, Polishing pad and polishing table according to the present invention when the rotational speed of the polishing table as a parameter is a radial polishing rate distribution diagram of the semiconductor substrate, Relationship diagram between motor load current and polishing time in the second polishing step according to the present invention, Semiconductor substrate radial direction polishing rate distribution diagram for three types of oxide films (thermal oxide film, LP-TEOS film, BPSG film) according to the present invention, Schematic diagram of an optical measurement system for evaluating the reflection spectrum during polishing according to the present invention, Reflection spectrum diagram during polishing of a semiconductor substrate according to the present invention, Sectional drawing of the principal part of the semiconductor substrate for demonstrating the conventional manufacturing method, It is principal part sectional drawing of the semiconductor substrate for demonstrating the conventional different manufacturing method.

Explanation of symbols

1: n ⁺⁺ low resistance substrate,
2: n-type epitaxial growth layer,
2-1: p-type epitaxial growth layer,
2-2: Trench,
2-3: Polishing end position,
2-4: Polishing end position,
2-5: Polishing end position,
3: Alignment marker,
4: Mask oxide film for trench formation,
5: Trench,
6: Polishing end line in the second polishing step,
7: Wafer,
8: Polishing head,
9: Rotary table,
10: Polishing pad,
11: Quartz window 12: Optical head,
13: Spectral reflectance measuring device,
14: Computer.

Claims (16)

The semiconductor surface etched by using the parallel insulating film pattern for trench formation and the parallel insulating film pattern as a mask on the surface of the one conductive semiconductor layer of the semiconductor substrate in which the one conductive semiconductor layer is laminated on the low resistance semiconductor substrate A first polishing step of forming parallel trenches perpendicular to each other and alignment markers, filling the parallel trenches with other conductivity type semiconductor layers, and then removing the other conductivity type semiconductor layers in the protruding portions; In the method for manufacturing a semiconductor element, the parallel polishing film pattern and the other conductive type semiconductor layer are simultaneously polished, and then the second polishing step of polishing the lower semiconductor layer is performed continuously. A method for manufacturing a semiconductor device, wherein polishing slurries having different polishing rates for the insulating film and the semiconductor layer are used in the two polishing steps, respectively. The polishing is performed using a CMP apparatus that supplies polishing slurry while rotating a polishing pad held on a rotary table, and presses and polishes the upper surface of the polishing pad while rotating a semiconductor substrate held by a polishing head. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed. The semiconductor substrate so that the polishing rate distribution in the semiconductor substrate surface with respect to the parallel insulating film pattern in the second polishing step is flattened by correcting the film thickness distribution in the semiconductor substrate surface of the parallel insulating layer pattern. The method for manufacturing a semiconductor device according to claim 1, wherein the polishing conditions are set so as to be large at the center portion and gradually smaller toward the outer peripheral portion. In the first polishing step, a high selectivity slurry having a selectivity expressed by the polishing rate of the semiconductor layer / the polishing rate of the insulating film is 30 or more, preferably 60 or more, and the selection is used in the second polishing step. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein a low selective ratio slurry having a ratio of 3 or less, preferably 2 or less is used. 5. The method of manufacturing a semiconductor device according to claim 2, wherein a polishing pad provided with a lattice-like groove is used in the second polishing step. 6. 6. The method of manufacturing a semiconductor device according to claim 2, wherein in the second polishing step, the number of rotations of the rotary table in the CMP apparatus is 42 or more. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film is a thermal oxide film or an oxide film formed by thermal CVD or plasma CVD. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the oxide film formed by thermal CVD or plasma CVD is a BPSG oxide film. 9. The polishing according to claim 3, wherein, in the second polishing step, polishing is performed with a pressure distribution such that the pressing force received by the central portion of the semiconductor substrate is higher than that of the outer peripheral portion. Semiconductor device manufacturing method. 10. The method of manufacturing a semiconductor device according to claim 2, wherein a change in load current of a polishing head or a rotary table is used for detecting a polishing end point in the second polishing step. 11. 11. The optical reflection spectrum by monochromatic or white light with respect to the insulating film is measured in the second polishing step in order to monitor the film thickness of the insulating film being polished. 11. The manufacturing method of the semiconductor device of description. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the polishing end point detection of the insulating film is detected by comparison with a reference reflection spectrum. 13. The method of manufacturing a semiconductor device according to claim 11, wherein the thickness of the insulating film is derived from optical fitting of the thin film. The method for manufacturing a semiconductor device according to claim 1, wherein after the insulating film is completely removed, the semiconductor layer is further polished in a thickness range of 0.2 to 2 μm. . 15. The semiconductor device according to claim 1, wherein a depth of the concave portion of the alignment marker is in a range of 0.5 μm to 8 μm with reference to the polished surface after the second polishing step. Manufacturing method. A method of manufacturing a semiconductor device, wherein the alignment marker after the second polishing step is covered with an insulating film.

Images