200837806 九、發明說明· 【發明所屬之技術領域】 本發明是有關於一種磊晶晶圓的製造 由在η型半導體基板所形成的溝渠内，蠢 體，來製造η型半導體區域與ρ型半導體 重複接合而成之具有ρη接合結構的並列矣 〇 【先前技術】 通常的縱型功率型 MOSFET(絕緣F 體；平面型）是按照其耐壓而理論性地決定 限值。亦即，若提高元件的電壓時，開啟 變高，所以無法避免開關損失變大。這是 時流動的漂移電流的方向是與在關閉狀態 時空乏層（depletion layer)擴大的方向相同之 為了提高元件的耐壓，必須提高漂移層的 如此的情況，在IGBT(絕緣閘雙極電， t . θ 亦疋相同。 針對如此的問題，有提案（例如，參考 開第0 0 5 3 8 5 4號說明書）揭示一種縱型功： 連接MOSFET)，是具有使提高不純物濃度 層區域及ρ型分隔區域並列且交替地重複 構，正實用化中。因為此種結構的功率型 接合重複且並列地形成，由於在關閉狀態 都能夠形成空乏區域，所以能夠使漂移層 方法，特別是藉 晶成長P型半導 區域是條紋狀地 舍構之蟲晶晶圓。 号電場效果電晶 其開啟電阻的下 電阻的下限值亦 因為在開啟狀態 (反向偏壓狀態） 緣故。換言之， 電阻。 昆體）或二極體等 歐洲專利申請公 率型MOSFET(超 而成的η型漂移 而成之ρη接合結 MOSFET 是使 ρη 時，橫向、縱向 整體廣泛地空乏 5 200837806 化，能夠確保高耐壓。又，若是此種構成時，因為能夠提 高漂移層的不純物濃度，所以能夠減少開啟電阻。 為了得到使ρ η接合結構並列且重複地形成之半導體 基板，雖然亦有對半導體基板重複進行離子注入步驟與磊 晶層的成長步驟來形成之方法，但是因為容易增加步驟數 且操作麻煩，在成本方面亦會產生問題（例如，參照曰本特 開2 0 0 1 - 1 3 9 3 9 9號公報）。對此，有揭示一種技術（例如參 0 照日本特開2 0 〇 〇 - 3 4 0 5 7 8平號公報、特開2 0 0 1 - 1 9 6 5 7 3號 公報）’疋在第1導電型的碎早結晶基板的表面，先藉由钱 刻形成溝渠，並使用第2導電型的填充磊晶層填埋該溝 渠，來形成具有並列且交替地重複而成的構成之ρη接合結 構。 耩由蠢晶成長法而利用蠢晶層來填埋上述溝渠時，為 了使開啟電阻更為降低，必須增大溝渠的深度相對於溝渠 的開口部的寬度之深度與寬度比（aspect ratio)。但是增加 深度與寬度比時，因為相對於基板的表面，溝渠的形狀在 〇 法線方向成為細長的長方形，所以被指出在藉由磊晶成長 法使用磊晶膜來填埋溝渠時會有溝渠開口部分容易阻塞、 或是在内部殘留空隙（孔洞）之情形。作為解決該問題的對 策，有揭示一種方法（例如，參照日本特開2001 - 1 96573號 公報），是在填埋溝渠的步驟的途中，暫時停止磊晶層的成 長，並重新導入HC1氣體，來蝕刻除去使開口狹窄之磊晶 層部分後，恢復磊晶層的成長之方法，或是一邊導入HC1 氣體一邊進行磊晶成長之方法。但是，此等方法，因為必 6 200837806 須重複進行蠢晶成長及使用HC1氣體蝕刻，所以非常 夫且麻煩’且會使成本提高許多。 因此’在日本特開2 0 0 5 - 1 1 8 8 0 8 0號公報中，揭示 .方法’疋將使石夕單結晶基板的法線向量α以最小的旋 • 度來重璺於溝渠的長度方向内侧面的法線向量冷之角 間’定義為遷移面法線角度區域，並將構成溝渠長度 的開口邊緣之區域’認定為在該遷移面法線角度區域 ^ 線向量連續變化之遷移面區域時，以{ 1 1 1 }面的法線向 存在於遷移面法線角度區域以外的方式，將基板主表 密勒指數（1^ kl h)規定為（100)，又，將溝渠的長度方 側面的密勒指數（h2 k2丨2)規定為與構成[100]軸之晶； 個{HO}面中任一個以V以上、以下的角度交差者 具備如此結晶方位條件之矽單結晶基板，在利 、埋廣渠時’管理溝渠底面及溝渠長度方向内側 的猫日日膜的成長速度，來抑制空隙的發生。 又’例如先在n型矽基板的表面形成溝渠，並藉 Β曰成長利用ρ变半導體來填埋該溝渠内部之方法，是 10圖（b)所示，Ρ蜇半導體的磊晶成長結束時，在η型 品―、的表面會形成數微米的ρ型矽單結晶的段差或 €大起物）。因此，必須藉由研磨基板表面等來除去突 或多晶矽，來加以平坦化。 關於平垣化處理’在上述日本特開2〇〇〇-34〇578 中 y to ^ 尋示一種藉由化學機械研磨法來研磨磊晶成長 板表面。又，在上述日本特開2〇〇1-196573號公報 費工 一種 轉角 度區 方向 ，法 量是 面的 向内 的4 ，藉 用蠢 面等 由蠢 如第 半導 隆起 起部 號公 後的 揭示 7 200837806 一種方法，是將形成溝時所利用的罩幕氧化膜在研磨時使 用作為中止膜，來進行研磨基板表面。又，在日本特開 2005-57142號公報中，揭示一種研磨方法，其特徵是管理 矽單結晶的隆起等的磨削厚度。 如上述，有提案揭示各式各樣的手法，藉由磊晶成長 法，將第2導電型的磊晶層，埋入形成於第1導電型的矽 基板上之條紋狀溝渠時，在該溝渠開口部或罩幕氧化膜所 生成的矽隆起或多晶矽，是藉由研磨等加以平坦化。但是 由於在該溝渠開口部所生成之矽隆起等的形狀不相同，所 以在除去該矽隆起及平坦化步驟中，除去量的管理容易變 為複雜化且步驟變為麻類，會有造成生產力降低之問題。 【發明内容】 本發明是鑒於以上情形而開發出來，本發明之目的是 提供一種製造方法，是將藉由磊晶成長法而使第2導電型 的矽單結晶填埋已形成於第1導電型的矽基板上之條紋狀 溝渠時所生成的矽隆起等，均勻地除去，並高精確度且高 效率地進行該矽基板表面的最後研磨步驟，以優良的生產 性，製造出高品質的並列pn接合結構磊晶晶圓。 為了達成上述目的，本發明是提供一種磊晶晶圓的製 造方法，是至少在第1導電型的矽基板上形成條紋狀溝 渠，並藉由磊晶成長法在該溝渠内形成第2導電型區域， 而能夠在上述第1導電型的矽基板與形成於上述溝渠内的 第2導電型區域之界面，形成pn接合結構之磊晶晶圓的製 8 200837806 造方法，其特徵是具備以下的步驟：使用第1導電型 基板，並在上述第1導電型的矽基板的表面上，形成 溝渠形成圖案的氧化膜之步驟；以上述氧化膜作為罩 來形成溝渠之步驟；在上述溝渠内，藉由選擇性磊晶 法來形成第2導電型區域之步騍；藉由旋轉蝕刻，蝕 上述磊晶成長時於上述溝渠的開口部所生成之矽隆起 而平坦化之步驟；除去上述氧化膜之步驟；及對除去 氧化膜後之上述石夕基板的已形成有並列 ρη接合之 面，進行研磨來加以平坦化之步驟。 若是具有如此的步驟，並藉由旋轉蝕刻將生成於 的開口部之矽隆起部分加以蝕刻而平坦化，來製造具 列ρ η接合結構之蠢晶晶圓的方法時’因為旋轉钱刻方 夠管理晶圓的旋轉數、蝕刻液供給喷嘴的移動條件等 夠進行面内均勻的蝕刻，且蝕刻的終端亦能夠正確 理，所以能夠實現高精確度的蝕刻處理。因此，能夠 地得到一種蠢晶晶圓，其在最後的研磨步驟能夠減少 的除去量，並且具有平坦鏡面的已形成有並列ρη接合 表面。 此時，較佳是使上述第1導電型型的矽基板的面 為（100)，並使上述溝渠側壁的面方位為{100}。 如此，使用面方位為（100)者，作為第1導電型的 板，且使溝渠側壁的面方位為{1 00}時，藉由選擇性磊 長法，利用第2導電型的矽單結晶來填埋已製作於第 電型的矽基板表面之條紋狀的溝渠時，能夠使生成於 的矽 具有 幕， 成長 刻在 部分 上述 主表 溝渠 有並 式能 ，能 地管 安定 研磨 之主 方位 砍基 晶成 1導 該溝 9 200837806 渠開口部之第 2導電型的矽單結晶的隆起或多晶 狀，一定地成為大約梯形，又，在填埋溝渠的過程 夠防止發生空隙（孔洞）。該矽隆起等的形狀為大 時，因為在除去該矽隆起等而加以平坦化時，能夠 蝕刻以同一條件進行蝕刻處理，所以能夠謀求高效 又，前述旋轉蝕刻時，較佳是使用以氫氟酸或 為主成分，且在15°C〜40°C具有相對於Si02之Si 比為 2 0以上的蝕刻特性之蝕刻液，來旋轉蝕刻上 板。 · 如此，藉由以氫氟酸或硝酸作為主成分，因為 易地使矽結晶與氧化膜的蝕刻選擇比（速度比）為 上，所以在旋轉蝕刻時，若在上述第1導電型的矽 形成溝渠時所使用的氧化膜為〇. 2微米以上時，便 用作為中止膜，能夠只蝕刻除去溝渠開口部的隆起 又，上述旋轉蝕刻，是先測定在上述溝渠開口 成的上述矽隆起部分的高度，並按照該高度來決定 刻條件為佳。 如此，在旋轉餘刻時，先測定在溝渠開口部所 矽隆起部分的高度，並按照該高度來決定旋轉蝕 時，因為能夠適當地除去該矽隆起等，所以不會產 殘餘或是相反地造成過蚀刻，能夠謀求製造高品質 成長晶圓。 又，在藉由選擇性磊晶成長法形成上述第2導 域之步驟，較佳是一邊供給二氯矽烷或三氣矽烷及 矽的形 中，能 略相同 使旋轉 率化。 硝酸作 的選擇 述矽基 能夠容 2 0 以 基板上 能夠利 部分。 部所生 旋轉# 生成的 刻條件 生蝕刻 的蠢晶 電型區 HC1氣 10200837806 IX. INSTRUCTIONS OF THE INVENTION · Technical Field of the Invention The present invention relates to the manufacture of an epitaxial wafer. The n-type semiconductor region and the p-type semiconductor are fabricated by a dummy in a trench formed by an n-type semiconductor substrate. Parallel joint with ρη joint structure [Prior Art] A normal vertical power type MOSFET (insulated F body; planar type) is theoretically determined in accordance with its withstand voltage. That is, when the voltage of the element is raised, the turn-on becomes high, so that the switching loss cannot be prevented from becoming large. This is when the direction of the drift current flowing is the same as the direction in which the depletion layer is expanded in the off state. In order to increase the withstand voltage of the component, it is necessary to increase the drift layer. In the IGBT (insulated gate bipolar , t. θ is also the same. For such a problem, there is a proposal (for example, refer to the specification of No. 0 0 5 3 8 5 4) to disclose a vertical work: connecting MOSFET), which has an area for increasing the concentration of impurities and The p-type separation regions are juxtaposed and alternately repeated, and are in practical use. Since the power type bonding of such a structure is repeated and formed in parallel, since the depletion region can be formed in the off state, the drift layer method, in particular, the P-type semiconducting region grown by the crystal growth is a stripe-like structure. Wafer. The electric field effect electric crystal The lower limit of the lower resistance of the opening resistance is also due to the open state (reverse bias state). In other words, resistance. European patent application metric MOSFETs such as quintessence or diodes (the η-type drift-type ρη junction-junction MOSFET is such that when ρη, the lateral and vertical overalls are widely depleted. In addition, in the case of such a configuration, since the impurity concentration of the drift layer can be increased, the on-resistance can be reduced. In order to obtain a semiconductor substrate in which the ρ 接合 junction structure is formed in parallel and repeatedly formed, the semiconductor substrate is repeatedly subjected to ions. The method of forming the implantation step and the growth step of the epitaxial layer, but since it is easy to increase the number of steps and the operation is troublesome, there is a problem in terms of cost (for example, refer to 曰本特开2 0 0 1 - 1 3 9 3 9 9 Bulletin). In this regard, a technique has been disclosed (for example, Japanese Patent Laid-Open No. 2 0 〇〇 - 3 4 0 5 7 8 ping No., and JP-A-200- 1 9 6 5 7 3) '疋 On the surface of the first conductivity type broken early crystal substrate, the trench is first formed by money, and the trench is filled with the second conductivity type filled epitaxial layer to form a parallel and alternately formed In the ρη joint structure of 成 时 耩 耩 耩 耩 耩 耩 耩 耩 耩 耩 耩 耩 耩 耩 耩 耩 耩 耩 耩 耩 耩 耩 蠢 蠢 蠢 蠢 蠢 蠢 蠢 蠢 蠢 蠢 蠢 蠢 蠢 蠢 蠢 蠢 蠢 蠢 蠢 蠢 蠢 蠢 蠢 蠢 蠢Aspect ratio. However, when the depth to width ratio is increased, the shape of the trench becomes an elongated rectangle in the normal direction of the crucible with respect to the surface of the substrate, so it is pointed out that the epitaxial film is used for filling by the epitaxial growth method. When the trench is buried, there is a case where the opening portion of the trench is easily blocked or a void (hole) is left in the inside. As a countermeasure against this problem, a method is disclosed (for example, refer to Japanese Laid-Open Patent Publication No. 2001-1796573). In the middle of the step of filling the trench, the growth of the epitaxial layer is temporarily stopped, and the HC1 gas is re-introduced to remove the epitaxial layer portion which narrows the opening, and the growth of the epitaxial layer is resumed, or HC1 is introduced. The method of epitaxial growth of gas is carried out. However, these methods must be repeated for stupid crystal growth and etching with HC1 gas because of the necessity of 2008. Therefore, it is very troublesome and troublesome and will increase the cost a lot. Therefore, in the Japanese Patent Laid-Open Publication No. 2 0 0 5 - 1 1 8 8 0 0 0, the method '疋' will make the normal of the Shixi single crystal substrate. The vector α is focused on the inner side of the longitudinal direction of the trench with a minimum degree of rotation. The cold angle is defined as the normal angle of the migration plane, and the area of the opening edge that constitutes the length of the trench is identified as When the normal angle of the migration plane is normal, the migration surface area of the line vector continuously changes, and the base of the { 1 1 1 } plane is outside the normal angle area of the migration surface. Kl h) is defined as (100), and the Miller index (h2 k2 丨 2) of the length side of the trench is defined as the crystal constituting the [100] axis; any one of the {HO} faces is V or more. The following angled person has a single crystal substrate having such a crystal orientation condition, and manages the growth rate of the cat day film on the bottom surface of the trench and the inner side in the longitudinal direction of the trench when the buried channel is buried, thereby suppressing the occurrence of voids. Further, for example, a method of forming a trench on the surface of the n-type germanium substrate and filling the inside of the trench by using a p-transistor semiconductor is shown in FIG. 10(b), and the epitaxial growth of the germanium semiconductor is completed. On the surface of the η-type, a step of a few micrometers of p-type 矽 single crystal or a large amount of material is formed. Therefore, it is necessary to planarize by removing the surface of the substrate or the like to remove the protrusions or polysilicon. Regarding the flattening treatment, in the above-mentioned Japanese Patent Laid-Open No. Hei 2-34〇578, y to ^ is found to polish a surface of an epitaxial growth plate by a chemical mechanical polishing method. Further, in the above-mentioned Japanese Patent Laid-Open Publication No. Hei 1-196573, the direction of the angle of the area is the same, and the amount of the method is the inward direction of the face 4, borrowing the stupid surface, etc. by the stupid as the first half of the bulge Disclosure 7 200837806 A method of polishing a surface of a substrate by using a mask oxide film used for forming a trench as a stop film during polishing. Further, Japanese Laid-Open Patent Publication No. 2005-57142 discloses a polishing method which is characterized in that a grinding thickness such as a ridge of a single crystal is managed. As described above, it has been proposed to disclose various methods of embedding a second conductivity type epitaxial layer in a stripe-shaped trench formed on a first conductivity type germanium substrate by an epitaxial growth method. The dome or polysilicon generated by the opening of the trench or the oxide film of the mask is planarized by polishing or the like. However, since the shape of the dome or the like generated in the opening of the trench is not the same, in the step of removing the dome and the flattening, the management of the removal amount is easily complicated and the step becomes hemp, which may cause productivity. Reduce the problem. SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a manufacturing method in which a single conductivity type single crystal is buried in a first conductive layer by an epitaxial growth method. The ridges and the like generated when the stripe-shaped grooves on the ruthenium substrate are uniformly removed, and the final polishing step of the ruthenium substrate surface is performed with high precision and high efficiency, and high quality is produced with excellent productivity. Parallel pn junction structure epitaxial wafer. In order to achieve the above object, the present invention provides a method for producing an epitaxial wafer in which a stripe-shaped trench is formed on at least a first conductivity type germanium substrate, and a second conductivity type is formed in the trench by an epitaxial growth method. And a method for forming an epitaxial wafer of a pn junction structure at the interface between the first conductivity type germanium substrate and the second conductivity type region formed in the trench, and characterized in that the method includes the following a step of forming an oxide film of a trench formation pattern on a surface of the first conductivity type germanium substrate by using a first conductivity type substrate; and forming a trench by using the oxide film as a cover; and in the trench a step of forming a second conductivity type region by a selective epitaxial method; a step of planarizing the ridges formed in the opening portion of the trench during the epitaxial growth by spin etching; and removing the oxide film And a step of polishing and planarizing the surface of the stone substrate after the oxide film is removed. If there is such a step, and the ridge portion of the opening portion formed by etching is planarized by spin etching, the method of manufacturing the dummy wafer having the column η junction structure is The in-plane uniform etching can be performed by managing the number of rotations of the wafer, the movement conditions of the etching liquid supply nozzle, and the like, and the end of the etching can be correctly handled, so that a highly precise etching process can be realized. Therefore, it is possible to obtain a stupid crystal wafer which can be reduced in the final grinding step and which has a flat mirror surface which has been formed with the parallel ρη bonding surface. In this case, it is preferable that the surface of the first conductivity type germanium substrate is (100), and the plane orientation of the trench sidewall is {100}. In the case where the plane orientation is (100), the first conductivity type plate is used, and when the plane orientation of the trench sidewall is {1 00}, the second conductivity type single crystal is used by the selective lengthening method. When the stripe-shaped trenches which have been formed on the surface of the ruthenium substrate of the electric type are filled, the ruthenium which is formed on the ruthenium can be formed, and the sputum which is formed in the shovel can be grown in some of the main table trenches, and the main direction of the tube can be stabilized and polished. The base crystal is formed into a guide groove 9 200837806 The ridge or polymorph of the second conductivity type single crystal of the opening portion of the channel is approximately trapezoidal, and the gap (hole) is prevented in the process of filling the trench. . When the shape of the dome is large, and the flattening is performed by removing the dome or the like, etching can be performed under the same conditions. Therefore, it is possible to achieve high efficiency. In the above-described spin etching, it is preferable to use hydrogen fluoride. An acid or a main component, and an etching liquid having an etching characteristic of 20 or more with respect to Si of SiO 2 at 15 ° C to 40 ° C is used to spin-etch the upper plate. In this way, by using hydrofluoric acid or nitric acid as a main component, since the etching selectivity (speed ratio) of the cerium crystal and the oxide film is easily made higher, in the case of spin etching, the ruthenium in the first conductivity type is When the oxide film used for forming the trench is 〇. 2 μm or more, it is used as a stop film, and only the ridges of the opening of the trench can be etched and removed. The spin etching is performed by first measuring the ridge portion of the trench opening. The height, and according to the height to determine the engraving conditions is better. As described above, in the case of the remnant of the rotation, the height of the ridge portion of the opening of the trench is measured, and when the eclipse is determined according to the height, since the ridge is lifted or the like, the residual or the opposite is not produced. By over-etching, it is possible to manufacture high-quality wafers. Further, in the step of forming the second domain by the selective epitaxial growth method, it is preferable to supply the dichlorosilane or the trioxane and the ruthenium in a shape which can slightly rotate the same. The choice of nitric acid can be used to accommodate 20% of the substrate. Part of the rotation of the generation of the engraved conditions of the etching of the stupid crystal electric zone HC1 gas 10
ϋ 200837806 體，一邊形成第2導電型區域。 如此’在藉由選擇性磊晶成長 ^ ^ A 贫去來填埋溝渠時，若供 、、、口 HCI氣體，能夠抑制多晶矽在 ^ ^ ^ ^ 隹虱化模上的成長，同時能 夠使填埋溝渠的過程不容易產生 々（孔洞）。 又，對除去上述氧化膜後之上 ^ > A 迷矽基板的已形成有並 列pn接5之主表面，進行研磨來 刀以平坦化之步驟，是先 測疋該基板的厚度並管理規定的 幻所磨量，且藉由化學機械 研磨，而能夠使該矽基板上的溝準 辟木開口部的微小凹凸平坦 化。 如此’藉由使用非接觸晶圓厚度測定器等’測定研磨 …基板的厚度，能夠確實地管理必要的研磨量，能夠 謀求有效率地將該基板的表面加以平垣化、鏡面化。 、又，較佳是在形成上述溝渠的步驟前，形成對準標記， 用以在磊晶晶圓的表面上形成圖案。 如此，藉由在梦晶圓上預先準備對準標記 連續地進行蝕刻及研磨步驟，從污染管理而言 的0 因為能夠 亦是合理 在本發明，因為藉由旋轉 高精確度地將石夕隆起等平坦化 過度姓刻，又，幾乎不會在石夕 在最後的研磨步驟，能夠以幸交 面。因此，若依照本發明之為 高生產性製造出高品質的並歹,j 钱刻來進行蝕刻處理，能夠 ，所以能夠避免蝕刻不足或 基板上產生傷痕等。因此， 少研磨量來得到高品質的鏡 晶晶圓的製造方法，能夠以 Pn接合磊晶晶圓。 11 200837806 【實施方式】 為了提高不純物濃度，超連接 MOSFET( super-junction MOSFET，以下稱為SJ-MOSFET)，是由並列pn接合結構所構成， 該並列pn接合結構是在低電阻的η型矽基板上，使同程度 低電阻的ρ型分隔區域並列且交替地重複而成。如上述， 該構成能夠大幅度地改善處於對立關係（trade-off)之開啟 電阻與耐壓。亦即，能夠降低開啟電阻，同時能確保高耐 壓。 在η型矽基板上製造上述並列pn接合結構時，通常的 方法是先在該矽基板上形成條紋狀的溝渠，然後藉由選擇 性磊晶成長法，利用ρ型矽單結晶的磊晶層來填埋該溝渠。 但是，使用磊晶層藉由選擇性磊晶成長法填埋溝渠 時，因為會在該溝渠的開口部或罩幕氧化膜上，生成矽隆 起或多晶矽，所以除去該矽隆起等而加以平坦化之步驟是 必要的。 先前，此種矽隆起等的形狀是無法忽視的偏差，因為 在將該矽隆起等除去及平坦化步驟時，無法設定同樣的蝕 刻條件，所以步驟變為麻煩，而有產生蝕刻不足或過度蝕 刻，致使磊晶晶圓的特性變差及生產力降低之問題。例如 有提案揭示一種方法，是藉由使用HC1等之氣體蝕刻，並 以氧化膜作為中止膜來蝕刻除去矽突起之方法。但是，因 為無法控制矽突起的高度，在溝渠填埋磊晶成長後，實際 上無法連續地進行氣體蝕刻。在溝渠填埋磊晶成長後，從 磊晶裝置取出並測定突起高度，然後再次在磊晶裝置進行 12 200837806 氣體姓刻之製程，麻煩且成本上亦是不實際 因此’本發明者發現藉由選擇性磊晶成 上設置並列pn接合’並藉由使用最適化的條 . 刻’來除去矽隆起及平坦化，能夠解決上述 了本發明。 以下，一邊參照圖示一邊具體地說明本 態，但是本發明未限定於此等記載。 〇 第1圖是本發明中的磊晶晶圓的製造步 第2〜9圖是本發明中的磊晶晶圓的製法的各 的概略剖面圖。 首先，在η型矽單結晶基板1上，藉由 1Ω cm左右的電阻率之磊晶層2成長，來準 晶基板3 (參照第1圖a、第2圖）。該基板3 (100)為佳。又，定向平面方位或凹口方位沒 可以是{1〇〇}。在基板3的表面，先形成光阻） 並藉由光微影法’使用乾式蝕刻來形成對 (J 4(參照第1圖B、第3圖）。 又，製造此對準標記用溝渠4，只要是 渠6前的階段，基本上是何時都可以，而沒 在本方式中’即便在最初形成對準標記用溝 夠使隨後的溝渠6圖案形成用的罩幕氧化膜 較薄之1 · 5微米以下，並能夠使對準標記用 保持較為銳利的形狀，在對準認識方面，不^ 接著，除去上述步驟中所使用的膜，並 的。 長法在矽基板 件進行旋轉蝕 問題，而完成 發明的實施形 驟的流程圖。 步驟中的晶圓 蠢晶成長法使 備η / η +型石夕蠢 的面方位是以 .有特別限定， 模等（未圖示）， 準標記用溝渠 在隨後形成溝 有特別限定。 渠 4 ’因為能 5的膜厚度為 溝渠4的形狀 Γ造成誤動作。 氧化洗淨後的 13 200837806 基板3的表面（參照第1圖C)。如此進行，在基板3的表 面上形成約1.2〜1 .5微米厚度的氧化膜5,並使用上述對準 標記用溝渠4，再次藉由光微影技術來除去氧化膜5上的 溝渠形成區域（參照第1圖D、第4圖）。接著，以殘留的 氧化膜5作為罩幕並藉由電漿蝕刻或RIE(反應性離子蝕刻） 等異方向性蝕刻，來形成用以形成條紋狀並列pn接合結構 之規定深度的溝渠6(參照第1圖E、第5圖）。基於後述的 理由，溝渠侧壁的面方位是以{ 1 0 0 }為佳。 而且，溝渠深度是因所要求的元件耐壓而變化，必須 為耐壓（V)的15分之1(微米）左右。 又，因為進行電漿蝕刻或RIE等的時候，會在溝渠6 的内壁殘留反應生成物或損傷，必要時需藉由濕式蝕刻等 來除去（參照第1圖F)。例如，洗淨溝渠的内壁後，在不 會使溝渠形狀產生變化的範圍内，亦可利用進行犧牲氧化 來除去損傷、以及對溝渠内面進行平滑化。 接著，例如以三氣矽烷或二氣矽烷作為源氣體（source gas)並與HC1 —同供給，藉由選擇性磊晶成長法，一面防 止多晶石夕在氧化膜5上成長，一面進行具有與η型蟲晶層 2大致同程度的電阻率之ρ型蠢晶層8的蠢晶成長’用以 填埋溝渠内部（參照第1圖G、第6圖）。 而且，在開始蠢晶成長之前，可充分地進行氫烘烤、 或以必要最低限度的量進行氣體蝕刻，來進行除去污染及 損傷。 又，為了使溝渠6不會形成空隙（孔洞），磊晶成長以 14 200837806 在控制反應速度的條件下進行為佳。具體上，成長 設定為1 〇 〇 〇 °c左右’並增加三氯矽烷的供給量。 行’能夠以較低的速度進行磊晶成長。又，為了使 板3)面内的成長速度為一定，以使用單片式的成長 佳。 以上述條件進行蠢晶成長時，能夠在溝渠開口 產生大致相同尺寸的梯形矽隆起9 (參照第6圖）。 另外，使溝渠側壁的面方位為{ 1 1 〇 }而形成溝穿 述矽隆起9的形狀及大小之偏差變大（參照第丨〇 s 使用主面的面方位為（1 〇 〇)矽磊晶基板，並使溝渠側 方位為{ 1 0 0 }的方式來形成溝渠時，能夠生成形狀及 大致一樣的梯形矽隆起（參照第10圖（&))。 接著，在殘留氧化膜5的狀態下，使用旋轉姓 除去上述矽隆起9 ’來加以平坦化（參照第1圖H、第 此時，因為該矽隆起9的高度為約3微米以下，中 膜（罩幕氧化膜5)的厚度為〇· 3〜0.5微米，所以若控 的偏差為±5%以下時，能夠在氧化膜的厚度範圍内 珍隆起 。又，此時，若矽隆起的形狀是如第丨〇圖 的女定的梯形時，由於能夠以同樣的旋轉蝕刻條件 ^處理，所以能夠更有效率地除去矽隆起9。 另外，所使用之旋轉蝕刻機，是例如具有第i i ^的結構，基板3固定在平台10上，並一邊旋轉一邊 3的上部，由可動性噴嘴12供給蝕刻液1丨來進行 此時，在進行旋轉蝕刻之前，通常是對鏡面晶 x'w ώ： e /皿度疋 如此進 晶圓（基 裝置為 部 7， ^時，上 函（b))。 壁的面 大小都 刻機來 7圖）。 止氧化 制#刻 ，除去 (a)所示 來進行 圖所示 從基板 餘刻。 圓進行 15 200837806 姓刻’預先對蝕刻速度及面内除去量的偏差進行預 來加以確認為佳。如此進行，能夠使旋轉蝕刻的條 適化’能夠進行高精確度的蝕刻。例如將30°C的氟 * 钱刻液（例如’氫氟酸：硝酸：硫酸：水=1 0 : 6 〇 : 的組成），以每分鐘4升的流量供給60秒，並使晶圓 或15〇〇rpm旋轉來進行蝕刻時，能夠得到如第12 的結果。又，測定固定晶圓旋轉速為15〇〇rpm並變 〇 液流量時之噴嘴擺動幅度與蝕刻不均的關係，是女 圖所示。得知此時蝕刻液流量每分鐘4升、喷嘴擺鸯 35微米的條件是適合的。 如此’若預先檢討旋轉姓刻的條件，能夠避免 足或過度#刻，所以能夠正確地管理蝕刻深度，能 於提升元件的反向耐壓及開啟電壓的特性精確度。 又，該蝕刻液之對矽及對氧化祺的蝕刻速度t! 比），在30°C時為35以上’幾乎不會蝕刻中止氧化 藉由旋轉蚀刻除去石夕隆起9後，利用氫氟酸除 U 作中止膜之氧化膜5(參照第1圖I、m β闻、士 # 於基板3的表面殘留有約0.5微米以下左右的凹凸 化學機械研磨將該狀態的基板3的表層研磨至成為 坦的表面為佳（參照第1圖J、第9圖）。因為夢由前 的旋轉蝕刻，該基板3的表面已經平垣化至某種程 以在該研磨步驟至少能夠以較少的研磨量來得到平 面。實際上，使用厚度計測定研磨前後的該基板3 ^ 結果研磨量大部分的情況為1 ·5微米左右。 備實驗 件最合 峭酸系 5 : 33 以 12〇〇 圖所示 化蝕刻 1第13 &幅度± 蝕刻不 夠有助 二（選擇 膜。 去使用 階段， 。藉由 完全平 面步驟 度，所 坦的鏡 I厚度， 16 200837806 並且’在本研磨步驟，以使用研磨量的面 良的單片式研磨機為佳；又，在研磨時，能夠 (dial gauge)等，一邊測定晶圓厚度或是一邊測 的深度，一邊研磨，來管理規定的研磨量。 如此’若依照本發明之磊晶晶圓的製造方 轉蝕刻’能夠高精確度且高效率地將矽隆起除^ 〇 以下’藉由實施例來更具體地說明本發明 明未限定於此等實施例。 (實施例、比較例） 首先’在n型矽單結晶基板1上，藉由磊 使1 Ω cm左右的電阻率之磊晶層2成長，來準 凹口（notch)方位都是{丨〇〇}的n/n +型矽磊晶基 10 A第2圖）。在基板；3的表面，先形成光 光微影法並使用乾式蝕刻來形成對準標記用的 微米的溝渠4 (參照第J圖B、第3圖）。 U 接著，除去上述步驟所使用的膜，並在洗 3的表面，形成厚度為1 · 3微米之氧化膜(參照 如此進行，在基板3的表面上形成氧化膜5, 料標記用Μ 4, #次藉由光微影技術來除 上的溝渠形成區域（參照第1圖]〇、第4圖）。 化膜5作為罩幕並藉由RIE(反應性離子蝕刻） 以形成條紋狀並列ρη接合結構之深度為4〇微 4·0微米的溝渠6(參照第1圖Ε、第5圖）。此 内均勻性優 使用度盤規 量對準標記 法，藉由旋 i*及平坦化。 ，但是本發 晶成長法， 備面方位及 卜反3 (參照第 阻膜，藉由 深度為 2.2 淨後的基板 第1圖C)。 並使用上述 去氧化膜5 以殘留的氧 ，來形成用 米、寬度為 時，氧化膜 17 200837806 亦某種私度被钱刻，而成為〇 · 4微米厚度。 為了除去由於前述RIE而在溝渠6的内壁所 應生成物或損•，施行犧牲氧化，且隨後藉 留的反 氧化膜，進而進行洗淨來除去溝渠6的内壁污染、除去 照第1圖F)。 木或損傷（參 Ο i) 接著以三氣秒烷作為源氣體並與HC1 —同 選擇性蠢晶成長法，-面防止多晶碎在氧化祺;、、°，藉由 一面進行具有“型蠢晶層2大致同程度的電亡成長， 磊晶層8的磊晶成長’用以填埋溝渠内部(參照且率之 第6圖）。而且，該磊晶成長是在成長溫度1。 並設定為使三氣矽烷的供給量多一必，且使〇C進行， 長裝置來進行。 —式的成 在此，使溝渠側壁的面方位為{ 1 10}來形 晶成長時所產生的矽隆起9的形狀及大小 冑渠時’磊 是使溝渠側壁的面方位為{1〇〇}來形成溝渠時I變大’但 狀及大小都大致-樣的梯料隆起（高度3施夠生成形 圖（a)(b))。 儆米）（參照第 接者，為了除去上述矽隆起9,是藉由 照第11圖)來加以平坦化(參照第i圖Hi蝕I 上’是將3(TC的銳破酸系姓刻液（氫氣酸7圖）。具體 水=1〇: 6〇: 5: 33的組成），以每分鐘4 酸：硬酸： 秒’並使晶圓,Χ 15術㈣旋轉來進行姓刻（失：量供給32 如此進行’能鈞進行面内同樣高精確度的麵；‘'第14圖-) 刻機（參 在此’作為上述藉由旋轉㈣來進行上起 18 200837806 除去及平坦化之比較例，是使用浸潰式的濕式蝕刻來進行 上述矽隆起9的除去及平坦化。此時，是使用與上述旋轉 蝕刻時同樣的蝕刻液，又，同樣是進行蝕刻處理3 2秒時， 浸潰式蝕刻，其研磨除去量在晶圓面内有大的偏差，且在 中心部之矽隆起9無法完全除去。ϋ 200837806 The body forms a second conductivity type region. In this way, when the trench is filled by selective epitaxial growth ^ ^ A lean, if the HCI gas is supplied, the HCI gas can suppress the growth of the polycrystalline silicon on the ^ ^ ^ ^ morphing mold, and at the same time enable filling The process of burying the trench is not prone to enthalpy (hole). Further, after removing the oxide film, the main surface on which the parallel pn junction 5 has been formed is polished, and the step of planarizing the blade is performed by first measuring the thickness of the substrate and managing the regulation. By the amount of the magical amount, the fine unevenness of the groove opening portion on the ruthenium substrate can be flattened by chemical mechanical polishing. By measuring the thickness of the polishing substrate by using a non-contact wafer thickness measuring device or the like, it is possible to reliably manage the necessary polishing amount, and it is possible to efficiently planarize and mirror the surface of the substrate. Further, preferably, an alignment mark is formed to form a pattern on the surface of the epitaxial wafer before the step of forming the trench. Thus, by continuously preparing the alignment marks on the dream wafer, the etching and polishing steps are continuously performed, and 0 from the pollution management can be also reasonable in the present invention because the Shi Xi uplift is highly accurate by rotation. If the flattening is excessively surnamed, it will hardly be in the final grinding step in Shi Xi. Therefore, according to the present invention, it is possible to produce a high-quality joint for high productivity, and it is possible to carry out an etching treatment. Therefore, it is possible to avoid insufficient etching or scratches on the substrate. Therefore, a method of manufacturing a high-quality lenticular wafer can be obtained with a small amount of polishing, and the epitaxial wafer can be bonded by Pn. 11 200837806 [Embodiment] In order to increase the impurity concentration, a super-junction MOSFET (hereinafter referred to as SJ-MOSFET) is composed of a parallel pn junction structure, which is a low-resistance n-type 矽. On the substrate, the p-type separation regions of the same low resistance are arranged in parallel and alternately. As described above, this configuration can greatly improve the opening resistance and withstand voltage in a trade-off relationship. That is, the opening resistance can be lowered while ensuring high withstand voltage. When manufacturing the parallel pn junction structure on the n-type germanium substrate, the usual method is to form a stripe-shaped trench on the germanium substrate, and then use a p-type germanium single crystal epitaxial layer by selective epitaxial growth method. To fill the ditch. However, when the trench is filled by the selective epitaxial growth method using the epitaxial layer, since the ridge or polysilicon is formed on the opening of the trench or the oxide film of the mask, the dome is removed and planarized. The steps are necessary. Conventionally, the shape of such a dome or the like is a variation that cannot be ignored. Since the same etching condition cannot be set when the dome is lifted or the like and the planarization step is performed, the step becomes troublesome, and there is an underetch or overetch. The problem that the characteristics of the epitaxial wafer deteriorate and the productivity is lowered. For example, it has been proposed to disclose a method of etching and removing the ruthenium protrusion by using a gas etching of HC1 or the like and using an oxide film as a stopper film. However, since the height of the protrusions cannot be controlled, after the trench is filled and epitaxial growth, gas etching cannot be continuously performed. After the epitaxial growth of the trench is filled, the height of the protrusion is taken out from the epitaxial device, and then the process of 12 200837806 gas surname is performed again in the epitaxial device, which is troublesome and costly. Therefore, the inventor discovered that The present invention can be solved by selectively epitaxially forming a parallel pn junction 'and removing the dome and flattening by using an optimized strip." Hereinafter, the present state will be specifically described with reference to the drawings, but the present invention is not limited to the description. Fig. 1 is a schematic cross-sectional view showing the steps of manufacturing the epitaxial wafer in the present invention. Figs. 2 to 9 are schematic cross-sectional views showing the steps of manufacturing the epitaxial wafer in the present invention. First, on the n-type tantalum single crystal substrate 1, the epitaxial layer 2 is grown by a resistivity of about 1 Ωcm, and the substrate 3 is aligned (see Fig. 1a and Fig. 2). The substrate 3 (100) is preferred. Also, the orientation plane orientation or the notch orientation may not be {1〇〇}. On the surface of the substrate 3, a photoresist is formed first, and a pair of dry etching is used to form a pair by photolithography (J 4 (refer to FIG. 1B and FIG. 3). Further, the alignment mark trench 4 is manufactured. As long as it is the stage before the canal 6, it is basically possible at any time, and in this mode, even if the groove for the alignment mark is initially formed, the mask oxide film for forming the subsequent groove 6 pattern is thinner. · 5 micron or less, and can make the alignment mark maintain a sharp shape. In terms of alignment, the film used in the above step is removed, and the long method is used to perform the rotational etching problem on the substrate. And the flow chart of the implementation of the invention is completed. The wafer growth method in the step makes the surface orientation of the η / η + type stone abundance. There are special limits, molds, etc. (not shown), The groove for marking is particularly limited in the subsequent formation of the groove. The channel 4' is malfunctioning because the film thickness of the energy 5 is the shape of the groove 4. The surface of the substrate 3 after oxidation cleaning 13 200837806 (see Fig. 1C). Forming about 1.2 on the surface of the substrate 3 The oxide film 5 having a thickness of 1.5 μm is used to remove the trench formation region on the oxide film 5 by the photolithography technique using the above-described alignment mark trench 4 (see FIGS. 1D and 4). Next, the residual oxide film 5 is used as a mask, and isotropic etching such as plasma etching or RIE (reactive ion etching) forms a trench 6 for forming a predetermined depth of the stripe parallel pn junction structure (refer to Fig. 1E and Fig. 5). For the reasons described later, the surface orientation of the side wall of the trench is preferably {1 0 0 }. Moreover, the depth of the trench varies depending on the required component withstand voltage, and must be withstand voltage. In the case of plasma etching, RIE, etc., the reaction product or damage remains on the inner wall of the trench 6, and if necessary, it is removed by wet etching or the like. (Refer to Fig. 1F.) For example, after cleaning the inner wall of the ditch, it is also possible to remove the damage by sacrificial oxidation and smooth the inner surface of the ditch without changing the shape of the ditch. Using trioxane or dioxane as a source The source gas is supplied in the same manner as the HC1, and the polycrystalline stone is prevented from growing on the oxide film 5 by the selective epitaxial growth method, and the resistivity is substantially the same as that of the n-type crystal layer 2. The stupid crystal growth of the p-type stray layer 8 is used to fill the inside of the trench (see Fig. 1G and Fig. 6). Further, before starting the stray crystal growth, the hydrogen baking can be sufficiently performed or necessary. At the minimum amount, gas etching is performed to remove contamination and damage. In order to prevent voids (holes) from being formed in the trench 6, epitaxial growth is preferably carried out under the conditions of controlling the reaction rate in 14 200837806. Specifically, growth is performed. Set to around 1 〇〇〇 °c and increase the supply of chloroform. The row ' can be epitaxially grown at a lower speed. Further, in order to make the growth rate in the plane of the panel 3) constant, it is preferable to use a single-piece growth. When the stray crystal growth is carried out under the above conditions, trapezoidal domes 9 having substantially the same size can be produced in the trench opening (see Fig. 6). Further, the surface orientation of the side wall of the trench is {1 1 〇}, and the variation in the shape and size of the ridge ridge 9 is formed. (Refer to the surface orientation of the main surface using the first 丨〇s (1 〇〇) 矽 Lei When the crystal substrate is formed so that the ditch side direction is {1 0 0 }, the trapezoidal ridges having the same shape and substantially the same shape can be formed (refer to FIG. 10 (&)). Next, the oxide film 5 remains. In the state, the above-mentioned domes 9' are removed by using the rotation name (see Fig. 1H, the first time, because the height of the dome 9 is about 3 μm or less, the middle film (the mask oxide film 5) The thickness is 〇·3~0.5 μm, so if the deviation of the control is ±5% or less, it can be raised in the thickness range of the oxide film. Also, at this time, if the shape of the ridge is like the female figure of the third figure In the case of a predetermined trapezoidal shape, the dome can be removed more efficiently by the same spin etching conditions. Further, the rotary etching machine used has, for example, a structure having a ii ^, and the substrate 3 is fixed on the platform. 10, and while rotating the upper part of the side 3, by The movable nozzle 12 supplies the etching liquid 1 丨 to perform at this time, and before the spin etching, it is usually performed on the mirror crystal x'w ώ: e / 疋 疋 into the wafer (the base device is the portion 7, ^, on Letter (b)). The surface size of the wall is engraved to 7). Stop the oxidation system #刻, remove (a) as shown in the figure to show the remaining from the substrate. Round proceeds 15 200837806 Surname engraved 'pre-etched The deviation between the speed and the amount of in-plane removal is preferably determined in advance. In this way, the strip of the spin etching can be adapted to enable high-accuracy etching. For example, a fluorine gas engraving solution of 30 ° C (for example, Hydrofluoric acid: nitric acid: sulfuric acid: water = 10: 6 〇: composition), supplied at a flow rate of 4 liters per minute for 60 seconds, and rotated by wafer or 15 rpm to obtain the same The result of 12. In addition, the relationship between the nozzle swing amplitude and the etching unevenness when the rotational speed of the fixed wafer is 15 rpm and the turbulent flow rate is measured is shown in the female figure. The condition that the nozzle and the nozzle are placed at 35 micrometers is suitable. The condition of changing the surname can avoid the foot or excessive engraving, so the etch depth can be correctly managed, and the reverse voltage withstand voltage and the characteristic accuracy of the turn-on voltage can be improved. Moreover, the etching solution and the oxidation of the etching solution蚀刻 etch rate t! ratio) is 35 or more at 30 ° C. 'Almost no etching is stopped. Oxidation is removed by spin etching. After removing the oxide film 5 by using hydrofluoric acid, U is used as a retardation film. In the first embodiment, it is preferable that the surface of the substrate 3 in this state is polished to the surface of the substrate 3 (see Fig. 1). , Figure 9). Because of the pre-dream rotary etching, the surface of the substrate 3 has been flattened to a certain extent to at least obtain a flat surface with a small amount of polishing in the grinding step. Actually, the thickness of the substrate before and after the polishing was measured using a thickness gauge. As a result, most of the polishing amount was about 1. 5 μm. Prepare the test piece for the most acid-based acid system 5: 33 etched as shown in Fig. 1 13th & amplitude ± etch is not enough to help two (select the film. To use the stage, by the full planar step degree, Mirror I thickness, 16 200837806 and 'in this grinding step, it is preferable to use a one-piece grinding machine with a good grinding amount; and, in the case of grinding, a wafer gauge or the like, the thickness of the wafer is measured or The grinding is performed while the depth is measured to manage the specified amount of polishing. Thus, if the epitaxial wafer is etched in accordance with the present invention, the dome can be removed with high precision and high efficiency. In the embodiment, the present invention is not limited to the examples. (Examples, Comparative Examples) First, on the n-type 矽 single crystal substrate 1, the resistivity of about 1 Ω cm is made by stretching. The crystal layer 2 is grown, and the orientation of the notch is n/n + type 矽 epitaxial base 10 A (Fig. 2). On the surface of the substrate 3, a photo-lithography method is first formed, and dry etching is used to form a micron trench 4 for alignment marks (see Fig. J, Fig. 3). U, the film used in the above step is removed, and an oxide film having a thickness of 1.3 μm is formed on the surface of the cleaning 3 (refer to this, an oxide film 5 is formed on the surface of the substrate 3, and the material is marked with Μ 4, The trench formation region (refer to FIG. 1 and FIG. 4) which is removed by the photolithography technique. The film 5 is used as a mask and RIE (reactive ion etching) is used to form a stripe-like juxtaposition ρη. The depth of the joint structure is 4 〇 micro 4·0 μm of the trench 6 (refer to FIG. 1 and FIG. 5). This internal uniformity is excellent in the use of the gauge gauge alignment method by the rotation i* and the planarization. However, the present crystal growth method, the surface orientation and the anti-reflection 3 (refer to the first resistive film, the substrate having a depth of 2.2 after the net is shown in Figure 1C), and using the above-mentioned deoxidation film 5 to residual oxygen, When the meter is formed and the width is used, the oxide film 17 200837806 is also engraved with a certain degree of privacy, and becomes a thickness of 〇·4 μm. In order to remove the product or damage on the inner wall of the trench 6 due to the aforementioned RIE, sacrifice is performed. Oxidation, and subsequent retention of the anti-oxidation film, followed by washing to remove the trench 6 Pollution of the inner wall is removed first to Fig. 1 F). Wood or damage (see Ο i) followed by three gas sec alkane as the source gas and HC1 - the same selective stupid crystal growth method, - surface to prevent polycrystalline ash in yttrium oxide;, °, by one side with "type The stupid layer 2 has approximately the same degree of electrical growth, and the epitaxial growth of the epitaxial layer 8 is used to fill the inside of the trench (see Figure 6 of the ratio). Moreover, the epitaxial growth is at the growth temperature of 1. It is set such that the supply amount of trioxane is more than necessary, and 〇C is carried out, and the device is carried out by a long device. Here, the surface orientation of the side wall of the trench is {1 10}, and the crystal growth occurs. The shape and size of the ridges 9 are the same as the surface orientation of the side walls of the trenches when the trenches are {1〇〇} to form a trench, and I become larger, but the shape and size are roughly the same. Generating the shape (a) (b)). 儆米) (refer to the first, in order to remove the above-mentioned ridges 9, by the 11th figure) to flatten (refer to the i-th etch I on the ' 3 (TC's sharp acid-depleted engraving solution (hydrogen acid 7 diagram). Specific water = 1 〇: 6 〇: 5: 33 composition), with 4 acids per minute: hard acid: seconds' Make the wafer, Χ 15 (4) rotate to carry the last name (missing: the amount of supply 32 to do so 'can perform the same high-precision surface in the face; ''fifteenth figure-) engraving machine (as in this 'as above In the comparative example in which the upper portion 18 200837806 is removed and planarized by the rotation (four), the ridge ridge 9 is removed and planarized by wet etching using a dipping type. In this case, the same as in the above-described spin etching. In the same manner, in the etching treatment, the etching treatment was carried out for 3 seconds, and the amount of polishing removal was largely deviated in the wafer surface, and the dome 9 at the center portion could not be completely removed.
藉由旋轉蝕刻除去矽隆起9後，利用氫氟酸除去作為 中止膜使用之氧化膜5 (參照第1圖I、第8圖）。在該階段， 於基板3的表面殘留有約0.5微米以下的凹凸。使用研磨 量的面内均勻性優良的單片式研磨機，並藉由化學機械研 磨將該狀態的基板 3的表層研磨至成為完全平坦的表面 (參照第1圖J、第9圖）。此時，使用厚度計測定研磨前後 的該基板3的厚度，求出研磨量。其結果，研磨量為1.5 微米而能夠得到大略完全平坦的表面。 另一方面，比較例之藉由浸潰式除去隆起後的晶圓， 亦在除去氧化膜後，與上述同樣地進行研磨時，即便研磨 3微米亦無法得到平坦的表面。 根據上述結果，若是依照本發明之並列pn接合磊晶晶 圓的製造方法，能夠以設成同一條件的旋轉蝕刻來進行矽 隆起等的除去及平坦化處理，且藉由使該旋轉蝕刻條件最 適合化，能使在蝕刻後能夠使基板上的内分布均勻，所以 可清楚得知，在隨後的最後研磨步驟，能夠以較少的研磨 量來得到平坦的鏡面。其結果，清楚得知能夠高精確度且 高效率地製造磊晶晶圓。 又，本發明未限定於上述實施形態。上述實施形態是 19 200837806 例示性，凡是具有與本發明之申請專利範圍所記載之技術 思想實質上相同構成、且達成相同作用效果之物，無論如 何都包含在本發明的技術範圍内。 例如，在本實施形態是使用η型矽單結晶基板，來說 明利用ρ型區域填埋已形成於基板上的溝渠，但是，其相 反的情況亦可。 【圖式簡單說明】 第1圖是本發明的步驟流程圖。 第2圖是第1圖的Α步驟中的晶圓的概略剖面圖。 第3圖是第1圖的B步驟中的晶圓的概略剖面圖。 第4圖是第1圖的D步驟中的晶圓的概略剖面圖。 第5圖是第1圖的E步驟中的晶圓的概略剖面圖。 第6圖是第1圖的G步驟中的晶圓的概略剖面圖。 第7圖是第1圖的Η步驟中的晶圓的概略剖面圖。 第8圖是第1圖的I步驟中的晶圓的概略剖面圖。 第9圖是第1圖的J步驟中的晶圓的概略剖面圖。 第1 0圖是顯示溝渠的側壁的結晶方位是U 0 0丨的情況 (a)時與{ 1 1 0 }的情況（b)時，溝渠開口部的矽隆起形狀的差 異之剖面圖。 第1 1圖是顯示本發明所使用的旋轉蝕刻機的一個例 子之概略圖。 第1 2圖是顯示進行本發明的旋轉蝕刻後之晶圓厚度 的變化量的圖（實施形態）。 20 200837806 第1 3圖是顯示蝕刻液量、噴嘴擺動幅度與晶圓内蝕刻 不均之關係圖。 第1 4圖是顯示蝕刻時間與蝕刻量之關係圖。 【主要元件符號說明】 ϋ 1 η型矽單結晶基板 2 蠢晶層 3 η/η +型石夕磊晶基板 4 對準標記用溝渠 5 罩幕氧化膜 6 溝渠 7 溝渠開口部 8 Ρ型磊晶層 9 矽隆起 10 平台 11 蝕刻液 12 可動性噴嘴 21After the dome 9 is removed by spin etching, the oxide film 5 used as the stopper film is removed by hydrofluoric acid (see Figs. 1 and 8). At this stage, irregularities of about 0.5 μm or less remain on the surface of the substrate 3. The surface layer of the substrate 3 in this state is polished to a completely flat surface by a chemical mechanical polishing using a monolithic polishing machine having an excellent in-plane uniformity of the polishing amount (see Figs. J and 9). At this time, the thickness of the substrate 3 before and after the polishing was measured using a thickness gauge to determine the amount of polishing. As a result, the amount of polishing was 1.5 μm, and a substantially completely flat surface could be obtained. On the other hand, in the comparative example, the wafer after the embossing was removed by the dipping method, and after the oxide film was removed, the polishing was carried out in the same manner as described above, and even if it was polished by 3 μm, a flat surface could not be obtained. According to the above results, according to the method for manufacturing a parallel pn-bonded epitaxial wafer according to the present invention, it is possible to perform lift removal and planarization treatment by spin etching under the same conditions, and to maximize the spin etching condition. By being suitable, it is possible to make the inner distribution on the substrate uniform after etching, so that it is clear that a flat mirror surface can be obtained with a small amount of polishing in the subsequent final polishing step. As a result, it is clear that the epitaxial wafer can be manufactured with high precision and high efficiency. Further, the present invention is not limited to the above embodiment. The above-described embodiment is exemplified in the above-mentioned embodiment of the present invention. Any object having substantially the same configuration as the technical idea described in the patent application scope of the present invention and achieving the same operational effects is included in the technical scope of the present invention. For example, in the present embodiment, an n-type germanium single crystal substrate is used, and the trench formed on the substrate is buried in the p-type region. However, the case may be reversed. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flow chart showing the steps of the present invention. Fig. 2 is a schematic cross-sectional view of the wafer in the step of Fig. 1 . Fig. 3 is a schematic cross-sectional view showing the wafer in the step B of Fig. 1. Fig. 4 is a schematic cross-sectional view showing the wafer in the step D of Fig. 1. Fig. 5 is a schematic cross-sectional view showing the wafer in the step E of Fig. 1. Fig. 6 is a schematic cross-sectional view showing the wafer in the G step of Fig. 1. Fig. 7 is a schematic cross-sectional view showing the wafer in the step of Fig. 1 . Fig. 8 is a schematic cross-sectional view showing the wafer in the first step of Fig. 1. Fig. 9 is a schematic cross-sectional view showing the wafer in the J step of Fig. 1. Fig. 10 is a cross-sectional view showing the difference in the shape of the dome of the trench opening when the crystal orientation of the side wall of the trench is U 0 0 ( (a) and the case (b) of { 1 1 0 }. Fig. 1 is a schematic view showing an example of a rotary etching machine used in the present invention. Fig. 1 is a view showing the amount of change in the thickness of the wafer after the spin etching of the present invention (embodiment). 20 200837806 Figure 1 3 is a graph showing the relationship between the amount of etchant, the amplitude of the nozzle swing, and the uneven etching in the wafer. Figure 14 is a graph showing the relationship between etching time and etching amount. [Main component symbol description] ϋ 1 η type 矽 single crystal substrate 2 stupid layer 3 η / η + type Shi Xi epitaxial substrate 4 Alignment mark trench 5 Shield oxide film 6 Ditch 7 Ditch opening 8 Ρ type Lei Crystal layer 9 矽 10 10 Platform 11 Etching liquid 12 Movable nozzle 21