JP5397402B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device manufacturing method for manufacturing a semiconductor device having a high breakdown voltage and a large current capacity, such as a MOSFET (insulated gate field effect transistor), an IGBT (insulated gate bipolar transistor) and a bipolar transistor.

In general, semiconductor elements are classified into a horizontal element having electrodes formed on one side and a vertical element having electrodes on both sides. In the vertical semiconductor element, the direction in which the drift current flows in the on state is the same as the direction in which the depletion layer due to the reverse bias voltage extends in the off state. In a normal planar type n-channel vertical MOSFET, the portion of the high resistance n ⁻ drift layer functions as a region in which a drift current flows in the vertical direction when it is in the ON state. Therefore, if the current path of the n ⁻ drift layer is shortened, the drift resistance is lowered, so that the effect of reducing the substantial on-resistance of the MOSFET can be obtained.

On the other hand, the portion of the high resistance n ⁻ drift layer is depleted in the off state to increase the breakdown voltage. Accordingly, when the n ⁻ drift layer is thinned, the width of the drain-base depletion layer proceeding from the pn junction between the P base region and the drift region is narrowed, and the critical electric field strength of silicon is reached quickly. It will decline. On the other hand, in a semiconductor device with a high breakdown voltage, since the n ⁻ drift layer is thick, the on-resistance increases and the loss increases. Thus, there is a trade-off relationship between on-resistance and breakdown voltage.

  This trade-off relationship is also known to hold in semiconductor devices such as IGBTs, bipolar transistors, and diodes. This trade-off relationship is also common to lateral semiconductor elements in which the direction in which the drift current flows in the on state and the direction in which the depletion layer extends in the off state are different.

  As a solution to the above-described problem due to the trade-off relationship, a super junction semiconductor element having a parallel pn junction structure in which a drift layer is formed by alternately and repeatedly joining n-type drift regions and p-type partition regions with an increased impurity concentration is disclosed. Known (for example, see Patent Document 1, Patent Document 2, Patent Document 3, and Patent Document 4). In the semiconductor element having such a structure, even when the impurity concentration of the parallel pn junction structure is high, the depletion layer extends in the lateral direction from each pn junction extending in the vertical direction of the parallel pn junction structure and drifts in the off state. Since the entire region is depleted, a high breakdown voltage can be achieved.

  In manufacturing the super junction semiconductor element, the semiconductor substrate having the parallel pn junction structure described above is used. As a method for mass-producing such a semiconductor substrate at a low cost and a high yield rate, a method is known in which a trench is formed in an n-type semiconductor substrate and the inside of the trench is filled with an epitaxial growth layer made of a p-type semiconductor ( For example, see Patent Document 5, Patent Document 6, Patent Document 7, Patent Document 8, and Patent Document 9.) In this method, when the epitaxial growth of the p-type semiconductor is completed, a step of 1 to several μm, an oxide film, and polysilicon remain on the surface of the semiconductor substrate. Therefore, the substrate surface is polished to remove the oxide film and polysilicon. The substrate surface needs to be flattened.

  Regarding this planarization treatment, Patent Document 5 describes that the substrate surface after epitaxial growth is polished by a CMP (Chemical Mechanical Polishing) method. Further, Patent Document 6 describes that the surface of the substrate is polished by a CMP method using a mask oxide film for forming a trench as a polishing stopper film. In addition to the CMP method, a method of silicon etching the substrate surface by a dry etching method is known. Patent Document 6 or Patent Document 7 describes performing silicon etching using a mask oxide film for forming a trench as a polishing stopper film.

  By the way, when a semiconductor element such as a MOSFET is formed on a semiconductor substrate having a parallel pn junction structure, it is necessary to align the pattern of the MOSFET and the pattern of the parallel pn junction structure. In order to facilitate this alignment, it is necessary to leave an alignment mark serving as a mask alignment target on the substrate surface after the substrate surface is polished and planarized. Patent Document 8 describes that an alignment trench is formed in a part of a semiconductor substrate as a mask alignment target before or after the trench etching step, and a film such as polysilicon is embedded in the trench. Yes.

  However, in Patent Documents 5 to 8 described above, the epitaxial growth technique of the semiconductor in the trench and the polishing technique for flattening the surface are described in detail, but whether or not the alignment mark remains when polishing is performed. Is unknown. That is, the alignment mark may be lost due to the polishing of the substrate surface. When the alignment mark disappears, alignment cannot be performed when an element surface structure such as a MOSFET is formed on the substrate surface, and thus the element surface structure cannot be manufactured. Even if the alignment mark remains after polishing, it is difficult to perform high-precision alignment if there is not a large difference in level between the substrate surface and the bottom of the alignment trench, which may cause mask displacement.

  Due to the above circumstances, it is necessary that the step of the alignment mark remains clearly after the substrate surface is polished and flattened. Therefore, the present inventors form a second alignment mark by forming a trench using the first alignment mark, performing an oxidation process after filling the trench by epitaxial growth, and patterning the generated oxide film. The method to do is proposed previously (for example, refer patent document 9).

European Patent Application No. 0053854 US Pat. No. 5,216,275 US Pat. No. 5,438,215 JP-A-9-266611 JP 2000-340578 A JP 2001-196573 A JP 2001-168327 A Japanese Patent No. 3424667 JP 2004-063894 A

  However, in the method disclosed in Patent Document 9 described above, when embedded trench growth is performed by forming trenches having different widths in a semiconductor substrate, unevenness on the surface of the substrate increases, and thus resist unevenness occurs when patterning an oxide film. Likely to happen. For this reason, processing cannot be performed according to the design dimensions, and the depth of the alignment mark may change. If the alignment mark is shallower than the design dimension, there is a problem that the alignment mark cannot be clearly left when the substrate surface is polished.

  In order to eliminate the above-described problems caused by the prior art, the present invention forms a trench in a semiconductor substrate and epitaxially grows the semiconductor in the trench to form a parallel pn junction structure. It is an object of the present invention to provide a method for manufacturing a semiconductor element that can clearly leave an alignment mark for mask alignment. Another object of the present invention is to provide a method for manufacturing a semiconductor element that can prevent resist unevenness in order to solve the above-described problems caused by the conventional technology.

  In order to solve the above-described problems and achieve the object, a method for manufacturing a semiconductor device according to the present invention includes a parallel pn having a configuration in which n-type semiconductor regions and p-type semiconductor regions are alternately and repeatedly joined on a low resistance layer. In manufacturing a semiconductor element having a junction structure, a first step of epitaxially growing a first conductivity type semiconductor layer on a surface of a low resistance semiconductor substrate, and a first step of etching a part of the first conductivity type semiconductor layer are performed. A second step of forming the alignment mark, a third step of forming an insulating film having a trench pattern on the surface of the first alignment mark and the first conductive semiconductor layer, and masking the insulating film A fourth step of etching the first conductive semiconductor layer to form a trench deeper than the first alignment mark, and in the trench and the A fifth step of epitaxially growing the second conductive semiconductor layer on the surface of the edge film; and polishing a portion of the second conductive semiconductor layer above the surface of the insulating film using the insulating film as a polishing stopper. A sixth step, a seventh step of etching the second conductive semiconductor layer using the insulating film used as a polishing stopper in the sixth step as a mask, and a new surface of the second conductive semiconductor layer An eighth step of forming a second alignment mark by etching a portion of the first conductivity type semiconductor layer different from the first alignment mark in a state protected by the formed insulating film; Between the ninth step, the seventh step, and the eighth step, where the surfaces of the first conductive type semiconductor layer and the second conductive type semiconductor layer on which the alignment mark is formed are mirror-polished. In And a tenth step of removing the insulating film used as a mask in the seventh step, wherein the seventh step has an etching depth of the second conductivity type semiconductor layer in the sixth step. The second conductive type semiconductor layer is etched until it becomes the same as the thickness of the insulating film remaining after polishing, and the eighth step newly adds the insulating film on the surface of the second conductive type semiconductor layer. Forming a part of the insulating film, exposing the formation region of the second alignment mark of the first conductive semiconductor layer, and removing the insulating film from which the part has been removed. Etching the first conductive semiconductor layer by anisotropic etching as a mask to form the second alignment mark.

  In order to solve the above-described problems and achieve the object, a method for manufacturing a semiconductor device according to the present invention includes a parallel pn having a configuration in which n-type semiconductor regions and p-type semiconductor regions are alternately and repeatedly joined on a low resistance layer. In manufacturing a semiconductor element having a junction structure, a first step of epitaxially growing a first conductivity type semiconductor layer on a surface of a low resistance semiconductor substrate, and a first step of etching a part of the first conductivity type semiconductor layer are performed. A second step of forming the alignment mark, a third step of forming an insulating film having a trench pattern on the surface of the first alignment mark and the first conductive semiconductor layer, and masking the insulating film A fourth step of etching the first conductive semiconductor layer to form a trench deeper than the first alignment mark, and in the trench and the A fifth step of epitaxially growing the second conductive semiconductor layer on the surface of the edge film; and polishing a portion of the second conductive semiconductor layer above the surface of the insulating film using the insulating film as a polishing stopper. A sixth step, a seventh step of etching the second conductive semiconductor layer using the insulating film used as a polishing stopper in the sixth step as a mask, and a new surface of the second conductive semiconductor layer An eighth step of forming a second alignment mark by etching a portion of the first conductivity type semiconductor layer different from the first alignment mark in a state protected by the formed insulating film; A ninth step of polishing the surfaces of the first conductive type semiconductor layer and the second conductive type semiconductor layer on which the alignment mark is formed in a mirror shape, and the seventh step includes the second conductive type. Etching the second conductivity type semiconductor layer until the etching depth of the conductor layer is the same as the film thickness of the insulating film remaining after polishing in the sixth step, the eighth step includes the step of A step of newly forming the insulating film on the surface of the second conductive type semiconductor layer, a part of the insulating film is removed, and the formation region of the second alignment mark of the first conductive type semiconductor layer is exposed. And a step of forming the second alignment mark by etching the first conductive semiconductor layer by anisotropic etching using the insulating film from which a part has been removed as a mask.

  In the method of manufacturing a semiconductor element according to the present invention, in the above-described invention, the eighth step includes the steps of forming a resist on the surface, selectively opening the resist, and anisotropic etching. A step of etching the one-conductivity-type semiconductor layer to form the second alignment mark. In the semiconductor device manufacturing method according to the present invention, in the above-described invention, the plane orientation of the main surface of the low-resistance semiconductor substrate is a plane equivalent to the (100) plane, and the plane orientation of the orientation flat plane is (100). ) Surface equivalent to the surface.

  In the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, the fourth step is to form the trench so that the surface orientation of the trench sidewall is parallel to a plane equivalent to the (100) plane. Features. In the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, the fifth step includes a step of performing a heat treatment in a hydrogen atmosphere at normal pressure, and the second conductive semiconductor layer at normal pressure after the heat treatment step. Including the step of epitaxial growth.

  In the method of manufacturing a semiconductor element according to the present invention, in the above-described invention, the fifth step is a mask for forming a trench in the bottom of the recess of the second conductivity type semiconductor layer epitaxially grown in the fourth step. The second conductivity type semiconductor layer is epitaxially grown until it becomes higher than the surface of the insulating film. In the method of manufacturing a semiconductor element according to the present invention, in the above-described invention, the fourth step forms a trench having a different width as the trench.

  In the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, the fifth step includes a step of performing a heat treatment in a hydrogen atmosphere at normal pressure, and the second conductive semiconductor layer at normal pressure after the heat treatment step. Including the step of epitaxial growth. In the semiconductor device manufacturing method according to the present invention, in the above-described invention, the fifth step is the step in which the bottom of the concave portion of the second conductivity type semiconductor layer epitaxially grown in the narrowest trench is formed in the fourth step. The second conductivity type semiconductor layer is epitaxially grown until it becomes higher than the surface of the insulating film used as a mask for forming a trench.

  In the semiconductor device manufacturing method according to the present invention, in the above-described invention, the eighth step forms the second alignment mark so as to be deeper than the first alignment mark. The method for manufacturing a semiconductor element according to the present invention is characterized in that, in the above-described invention, the seventh step is to etch the second conductivity type semiconductor layer by anisotropic etching.

  In the method of manufacturing a semiconductor element according to the present invention, in the above-described invention, in the seventh step, the second conductive type semiconductor layer is etched by isotropic etching, and the surface of the second conductive type semiconductor layer is etched. The protrusion is exposed and overetching is performed in this state.

  The method of manufacturing a semiconductor device according to the present invention is characterized in that, in the above-described invention, the ninth step is polished to the extent that the second alignment mark remains. The method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above-described invention, the ninth step is polishing until the first alignment mark disappears. The method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above-described invention, the ninth step is performed so that the first alignment mark remains.

  According to the present invention, since the second alignment mark remains after the mirror polishing by forming the second alignment mark before the mirror polishing of the semiconductor surface, the semiconductor for manufacturing a superjunction semiconductor element having the alignment mark A substrate can be obtained. In addition, according to the present invention, the step of the semiconductor surface before mirror polishing is reduced by performing etch back of the second conductive type semiconductor layer epitaxially grown in the trench. Thereby, the amount of polishing at the time of mirror polishing can be reduced, so that the mirror polishing time can be shortened and the manufacturing cost can be reduced. Further, since the amount of polishing during mirror polishing is small, polishing can be performed at a low polishing rate, so that the in-plane uniformity of the mirror polishing surface is also improved.

  Further, according to the present invention, after the second conductive type semiconductor layer is etched back, the second alignment mark is formed in a state in which the surface of the second conductive type semiconductor layer is protected. The depth can be changed freely. As a result, the range in which the variation in the polishing amount during mirror polishing can be tolerated is widened. That is, when the variation in the polishing amount during mirror polishing increases, the depth of the second alignment mark also varies, but even in that case, mask alignment can be performed in the subsequent process of manufacturing the semiconductor element. An alignment mark can be left. Even if the polishing conditions are constant in each batch of mirror polishing, a difference in the polishing amount occurs between the batches. However, since the allowable range of the difference becomes wide, the difference in the polishing amount between the batches is allowed. be able to.

  In addition, according to the present invention, the final depth of the alignment mark depends on the amount of mirror polishing performed after the second alignment mark is formed. Therefore, an arbitrary depth can be obtained by adjusting the amount of polishing. The alignment mark can be left. Further, according to the present invention, since the surface is flattened by polishing using the insulating film as a mask when forming the trench as a polishing stopper, it is possible to prevent resist unevenness from occurring in the subsequent photolithography process. it can.

  Further, according to the present invention, by performing etch back of the second conductivity type semiconductor layer by isotropic etching, the protrusion formed during the epitaxial growth of the second conductivity type semiconductor layer is reduced, so that anisotropic etching is performed. The protrusion can be made smaller than when etching back is performed. As a result, the amount of polishing during mirror polishing is reduced and the mirror polishing time can be shortened, so that the manufacturing cost is reduced and polishing can be performed at a low polishing rate, so that the mirror polishing surface is uniform in the surface. Improves. Furthermore, according to the present invention, since the first alignment mark can be used as an index of the polishing end timing during mirror polishing, the mirror polishing can be finished with an appropriate polishing amount.

In order to solve the above-described problems and achieve the object, a method of manufacturing a semiconductor device according to the present invention has a configuration in which n-type semiconductor regions and p-type semiconductor regions are alternately and repeatedly joined on a low resistance layer. In manufacturing a semiconductor device having a parallel pn junction structure, a first step of epitaxially growing a first conductivity type semiconductor layer on a surface of a low resistance semiconductor substrate, and a part of the first conductivity type semiconductor layer are etched. A second step of forming a first alignment mark; a third step of forming an insulating film having a trench pattern on the surfaces of the first alignment mark and the first conductive semiconductor layer; and the insulating film. a fourth step of etching the first conductive semiconductor layer as a mask to form deep trenches than the first alignment mark, Oyo in the trench A fifth step of epitaxially growing a second conductivity type semiconductor layer on the surface of the insulating film until it becomes higher than the surface of the insulating film; and the insulation of the second conductivity type semiconductor layer using the insulating film as a polishing stopper. A sixth step of polishing a portion above the surface of the film, and an epitaxial growth in the trench in the fifth step by the thickness remaining after polishing the insulating film used as a polishing stopper in the sixth step A seventh step of etching the exposed surface of the second conductive type semiconductor layer, an eighth step of removing the insulating film used as a polishing stopper in the sixth step, and a heat treatment to perform the eighth step. Including a ninth step of oxidizing the semiconductor surface exposed by removing the insulating film in the step, and a tenth step of removing the oxide film formed on the semiconductor surface in the ninth step, Ninth process , Between the tenth step, removing a portion of the oxide film formed on the semiconductor surface at the ninth step, of the first conductivity type semiconductor layer, the formation region of the second alignment mark A second alignment mark is newly formed by etching a part of the first conductive type semiconductor layer using the eleventh step to be exposed and the oxide film partially removed in the eleventh step as a mask. And a twelfth step.

In order to solve the above-described problems and achieve the object, a method of manufacturing a semiconductor device according to the present invention has a configuration in which n-type semiconductor regions and p-type semiconductor regions are alternately and repeatedly joined on a low resistance layer. In manufacturing a semiconductor device having a parallel pn junction structure, a first step of epitaxially growing a first conductivity type semiconductor layer on a surface of a low resistance semiconductor substrate, and a part of the first conductivity type semiconductor layer are etched. A second step of forming a first alignment mark; a third step of forming an insulating film having a trench pattern on the surfaces of the first alignment mark and the first conductive semiconductor layer; and the insulating film. a fourth step of etching the first conductive semiconductor layer as a mask to form deep trenches than the first alignment mark, Oyo in the trench A fifth step of epitaxially growing a second conductivity type semiconductor layer on the surface of the insulating film until it becomes higher than the surface of the insulating film; the insulating film as a polishing stopper; A sixth step of polishing the insulating film and the second conductive type semiconductor layer on the insulating film so as to remain with a thickness smaller than the thickness at the time of forming the insulating film in the third step; A seventh step of removing the insulating film used as a polishing stopper in the step, and a semiconductor exposed by performing a heat treatment after the seventh step and removing the insulating film in the seventh step an eighth step of oxidizing the surface, seen including a ninth step, the removing the oxide film formed on the semiconductor surface at the eighth step, the steps of the eighth, and the ninth step In the meantime, the oxidation generated on the semiconductor surface in the eighth step A part of the first conductive type semiconductor layer to expose a second alignment mark formation region, and an oxide film partially removed in the tenth process as a mask And an eleventh step of newly forming a second alignment mark by etching a part of the first conductivity type semiconductor layer .

  According to this invention, since the semiconductor under the insulating film is not polished after removing the insulating film used as the polishing stopper when polishing the second conductive type semiconductor layer, the alignment formed before forming the deep trench is formed. Mark steps are not reduced. Therefore, it is not necessary to newly form an alignment mark after removing the insulating film as the polishing stopper, so that the manufacturing process can be simplified and the manufacturing cost can be reduced. Further, according to the present invention, since the semiconductor under the insulating film used as the polishing stopper is not polished, the thickness of the semiconductor substrate for manufacturing the superjunction semiconductor element does not vary. In addition, variation in breakdown voltage of the semiconductor element can be reduced. In addition, since the polishing surface is completely removed by etching after polishing using the insulating film as a polishing stopper, contamination of the substrate due to polishing can be eliminated.

  According to the method for manufacturing a semiconductor device of the present invention, a deep trench is formed in the first conductivity type semiconductor layer using the first alignment mark, the second conductivity type semiconductor layer is epitaxially grown in the trench, and polishing is performed. By forming the second alignment mark after the planarization, the alignment mark for mask alignment can be clearly left on the semiconductor substrate having the parallel pn junction structure. Moreover, according to the manufacturing method of the semiconductor element concerning this invention, there exists an effect that it can prevent that resist nonuniformity generate | occur | produces.

It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 3 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 3 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 3 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 3 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 3 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 3 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 3 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 3 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 3 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 3 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 3 of this invention. It is a top view which expands and shows a part of 1st alignment mark formed by Embodiment 3 of this invention. It is principal part sectional drawing which shows the shape before insulating film formation of the 1st alignment mark formed by isotropic etching. It is principal part sectional drawing which shows the shape after insulating film formation of the 1st alignment mark formed by isotropic etching. It is principal part sectional drawing which shows the shape before the insulating film formation of the 1st alignment mark formed by anisotropic etching. It is principal part sectional drawing which shows the shape after insulating film formation of the 1st alignment mark formed by anisotropic etching. It is principal part sectional drawing which expands and shows the shape before the insulating film removal of the buried epitaxial growth layer at the time of forming a 2nd alignment mark by isotropic etching. It is principal part sectional drawing which expands and shows the shape after the insulating film removal of the buried epitaxial growth layer at the time of forming a 2nd alignment mark by isotropic etching. It is principal part sectional drawing which expands and shows the shape before the insulating film removal of the buried epitaxial growth layer at the time of forming a 2nd alignment mark by anisotropic etching. It is principal part sectional drawing which expands and shows the shape after the insulating film removal of the buried epitaxial growth layer at the time of forming a 2nd alignment mark by anisotropic etching. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 4 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 4 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 4 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 4 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 4 of this invention. It is a longitudinal cross-sectional view which expands and shows a part of semiconductor element in the middle of manufacture by Embodiment 5 of this invention. It is a longitudinal cross-sectional view which expands and shows a part of semiconductor element in the middle of manufacture by Embodiment 5 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 5 of this invention. It is a longitudinal cross-sectional view which expands and shows a part of semiconductor element in the middle of manufacture by Embodiment 5 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 5 of this invention. It is a longitudinal cross-sectional view which expands and shows a part of semiconductor element in the middle of manufacture by Embodiment 5 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 6 of this invention. It is a longitudinal cross-sectional view which expands and shows a part of semiconductor element in the middle of manufacture by Embodiment 6 of this invention. It is a longitudinal cross-sectional view which expands and shows a part of semiconductor element in the middle of manufacture by Embodiment 6 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 6 of this invention. It is a longitudinal cross-sectional view which expands and shows a part of semiconductor element in the middle of manufacture by Embodiment 6 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 6 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 7 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 7 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 7 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 7 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 7 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 7 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 7 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 7 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 7 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 7 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 8 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 8 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 8 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 8 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 8 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 8 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 8 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 9 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 9 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 9 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 9 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 9 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 10 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 10 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 11 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 11 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 12 of this invention. It is a longitudinal cross-sectional view which expands and shows a part of semiconductor element in the middle of manufacture by Embodiment 12 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 12 of this invention. It is a longitudinal cross-sectional view which expands and shows a part of semiconductor element in the middle of manufacture by Embodiment 12 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 12 of this invention. It is a longitudinal cross-sectional view which expands and shows a part of semiconductor element in the middle of manufacture by Embodiment 12 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 12 of this invention. It is a longitudinal cross-sectional view which expands and shows a part of semiconductor element in the middle of manufacture by Embodiment 12 of this invention. It is a longitudinal cross-sectional view which shows the result of having simulated the shape of the semiconductor surface before sacrificial oxidation. It is a longitudinal cross-sectional view which shows the result of having simulated the shape of the semiconductor surface after sacrificial oxidation. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 13 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 13 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 13 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 13 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 14 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 14 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 14 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 14 of this invention.

  Exemplary embodiments of a method for manufacturing a semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the following description of each embodiment and the accompanying drawings, the same reference numerals are assigned to the same components, and duplicate descriptions are omitted.

Embodiment 1 FIG.
FIGS. 1-12 is a longitudinal cross-sectional view which shows the outline of the semiconductor element in the middle of manufacture by Embodiment 1 of this invention. First, as shown in FIG. 1, a low-resistance semiconductor substrate 11 made of an n-type silicon semiconductor doped with an n-type impurity such as antimony or arsenic is prepared. The plane orientation of the main surface of the low resistance semiconductor substrate 11 is a plane equivalent to, for example, the (100) plane. Further, the plane orientation of the orientation flat surface is, for example, a surface equivalent to the (100) plane.

The concentration of the low-resistance semiconductor substrate 11 is, for example, about 2 × 10 ¹⁸ cm ⁻³ . For example, a phosphorus-doped n-type semiconductor layer 12 is epitaxially grown on the main surface of the low-resistance semiconductor substrate 11. The thickness of the n-type semiconductor layer 12 is, for example, about 50 μm. The concentration of the n-type semiconductor layer 12 is, for example, about 6 × 10 ¹⁵ cm ⁻³ when the dopant is phosphorus.

  Next, as shown in FIG. 2, for example, anisotropic dry etching is performed to form the first alignment mark 1 in the n-type semiconductor layer 12. The depth of the first alignment mark 1 is, for example, about 0.5 to 1.0 μm. Here, description will be made assuming that the depth of the first alignment mark 1 is 0.5 μm. The first alignment mark 1 may be formed by performing isotropic dry etching instead of anisotropic etching.

  In the case of performing anisotropic etching, there is an advantage that alignment accuracy can be ensured when performing mask alignment with reference to the first alignment mark 1 in the subsequent steps. However, as will be described in detail in a third embodiment, which will be described later, when forming a deep trench later, it is necessary to increase the thickness of the insulating film serving as a hard mask.

  On the other hand, when performing isotropic etching, there is an advantage that the insulating film serving as a hard mask for forming a deep trench can be thinned. On the other hand, the alignment accuracy is anisotropic etching. Worse than the case. The first alignment mark 1 may be formed by RIE (reactive ion etching) using a resist mask, or may be formed by forming an oxide film and performing trench etching. .

  Next, as shown in FIG. 3, an insulating film 13 is provided on the n-type semiconductor layer 12 and the first alignment mark 1. The insulating film 13 is an oxide film, a nitride film, or a film having a two-layer structure of a nitride film and an oxide film. Although there is no particular limitation, the n-type semiconductor layer 12 is oxidized here, and an oxide film having a thickness of, for example, about 2.5 μm is formed as the insulating film 13.

  Then, the insulating film 13 is patterned to selectively open portions of the insulating film 13 where trench etching is to be performed, thereby forming a hard mask for forming the trench. At this time, the first alignment mark 1 remains covered with the insulating film 13. The width of the opening portion of the hard mask is, for example, about 5 μm. The width of the portion of the hard mask where the oxide film remains is, for example, about 5 μm. In this case, trenches having a width of about 5 μm are formed at intervals of about 5 μm.

  Next, as shown in FIG. 4, a deep trench 2 is formed in the n-type semiconductor layer 12 using the insulating film 13 as a hard mask. The depth of the trench 2 is, for example, about 50 μm. Further, the plane orientation of the side wall of the trench 2 is a plane parallel to a plane equivalent to the (100) plane. When the n-type semiconductor layer 12 is etched, the insulating film 13 is also etched by about 1 μm, for example, so that the thickness of the insulating film 13 after the trench formation is about 1.5 μm, for example. Next, heat treatment is performed in a normal-pressure hydrogen atmosphere to remove the natural oxide film (not shown in FIG. 4) covering the side walls and bottom surface of the trench 2.

  Subsequently, as shown in FIG. 5, for example, a boron-doped p-type semiconductor layer 14 is epitaxially grown at normal pressure to selectively fill the trench 2 with the p-type semiconductor layer 14. At this time, a recess is formed in the central portion of the p-type semiconductor layer 14 in the width direction of the trench 2 (the left-right direction in FIG. 5). Epitaxial growth is performed until the bottom 15 of the recess, that is, the lowest portion of the p-type semiconductor layer 14 is higher than the surface 16 of the insulating film 13 serving as a hard mask.

When the trenches 2 having different widths are formed in the n-type semiconductor layer 12, the bottom 15 of the recess of the p-type semiconductor layer 14 filling the narrowest trench 2 is higher than the surface 16 of the insulating film 13. To do. The concentration of the p-type semiconductor layer 14 is, for example, about 6 × 10 ¹⁵ cm ⁻³ when the dopant is boron. This concentration is the same as the concentration of the n-type semiconductor layer 12 on the low-resistance semiconductor substrate 11 although the conductivity type is opposite. Thereby, a parallel pn junction structure in which the n-type semiconductor region and the p-type semiconductor region have the same concentration is formed.

  Next, as shown in FIG. 6, polishing is performed using the insulating film 13 as a hard mask when forming the trench as a stopper, and the portion of the p-type semiconductor layer 14 selectively epitaxially grown on the surface of the insulating film 13 is removed. As described above, since the p-type semiconductor layer 14 is epitaxially grown so that the bottom 15 of the recess is higher than the surface 16 of the insulating film 13, the polished surface becomes the first alignment mark by polishing here. Except for the upper part of 1, it becomes a flat surface without unevenness. Since the first alignment mark 1 is formed in a concave shape in the n-type semiconductor layer 12 and is covered with the insulating film 13, it remains even after the polishing here is completed.

  Next, as shown in FIG. 7, a resist 17 is applied to the surfaces of the insulating film 13 and the p-type semiconductor layer 14 while leaving the insulating film 13. Then, photolithography and etching are performed to remove a part of the insulating film 13 so that only the second alignment mark formation region of the n-type semiconductor layer 12 is exposed. The p-type semiconductor layer 14 remains covered with the resist 17. In the photolithography process, the first alignment mark 1 is used for alignment (alignment) of the mask during exposure.

  Next, as shown in FIG. 8, the second alignment mark 3 is formed by performing anisotropic dry etching such as trench etching using the insulating film 13 as a mask. At the same time, the p-type semiconductor layer 14 in the trench 2 is etched to reduce the level difference of the surface to be polished in the subsequent mirror polishing. The etching depth at this time is, for example, about 1.5 to 2 μm.

  When the etching depth is 1.5 μm, as described above, since the thickness of the insulating film 13 remaining after forming the deep trench 2 is about 1.5 μm, the exposed surface of the p-type semiconductor layer 14 Is approximately the same height as the interface between the n-type semiconductor layer 12 and the insulating film 13 thereon. When the etching depth is deeper than 1.5 μm, the exposed surface of the p-type semiconductor layer 14 is lower than the interface between the n-type semiconductor layer 12 and the insulating film 13 thereon. When the etching depth is 2 μm, the exposed surface of the p-type semiconductor layer 14 is almost the same height as the bottom surface of the first alignment mark 1. Here, the description will be made assuming that the depth of the second alignment mark 3 is about 2 μm.

  Next, as shown in FIG. 9, all the insulating film 13 remaining on the surface is removed. Then, as shown in FIG. 10, FIG. 11 or FIG. 12, the surface is mirror-polished so that the second alignment mark 3 is not lost. Here, since the depth of the second alignment mark 3 is about 2 μm, the polishing amount at the time of mirror polishing may be about 0.5 to 1.5 μm, for example. As a result, a step having a depth of about 0.5 to 1.5 μm remains as the second alignment mark 3. When the surface structure of the element is manufactured thereafter, mask alignment is performed using this step as a reference. Just do it.

  10, FIG. 11, and FIG. 12 correspond to the cases where the polishing depths during mirror polishing are the AA, BB, and CC lines in FIG. 9, respectively. As shown in these drawings, the first alignment mark 1 may be lost by mirror polishing (FIGS. 11 and 12) or may remain without being lost (FIG. 10). When the first alignment mark 1 is lost by mirror polishing, the first alignment mark 1 can be used as a polishing monitor.

  In other words, the polishing may be terminated when the first alignment mark 1 disappears during polishing. In this way, mirror polishing can be completed with an appropriate polishing amount. Instead of using the first alignment mark 1 as a polishing monitor, a polishing monitor may be formed in the n-type semiconductor layer 12 at the same depth as the first alignment mark 1.

  According to the first embodiment, the following effects can be obtained. Since the second alignment mark 3 remains after mirror polishing, a semiconductor substrate for manufacturing a superjunction semiconductor element having the alignment mark can be obtained. In particular, since the first and second alignment marks 1 and 3 are formed by anisotropic etching, the accuracy of the alignment mark can be improved. Further, when the second alignment mark 3 is formed, it is not necessary to newly provide an oxidation step to form a mask, so that the manufacturing cost can be reduced.

  Further, since the surface is flattened by polishing before the second alignment mark 3 is formed, it is possible to prevent the occurrence of resist unevenness in the subsequent photolithography process. Further, the step between the surface of the p-type semiconductor layer 14 and the surface of the n-type semiconductor layer 12 can be reduced by etching back the p-type semiconductor layer 14 in the trench 2, so that the amount of polishing during mirror polishing is reduced. can do. Accordingly, the mirror polishing time can be shortened, and the manufacturing cost can be reduced. Further, since the polishing amount at the time of mirror polishing is small, polishing can be performed at a low polishing rate, so that the in-plane uniformity of the mirror polishing surface can be improved.

Embodiment 2. FIG.
13 to 17 are longitudinal sectional views showing an outline of a semiconductor element being manufactured according to the second embodiment of the present invention. The second embodiment is different from the first embodiment in the etching depth when the second alignment mark 3 is formed. In the following description, description of the same configuration as that of the first embodiment will be omitted, and only a configuration different from that of the first embodiment will be described.

  First, according to the steps shown in FIGS. 1 to 7, only the second alignment mark formation region of the n-type semiconductor layer 12 is exposed. Thereafter, as shown in FIG. 13, anisotropic dry etching such as trench etching is performed using the insulating film 13 as a mask. The etching depth at this time is about 1.5 μm. Therefore, the exposed surface of the p-type semiconductor layer 14 has substantially the same height as the interface between the n-type semiconductor layer 12 and the insulating film 13 thereon. Then, as shown in FIG. 14, after all of the insulating film 13 remaining on the surface is removed, the second alignment mark 3 is not lost as shown in FIG. 15, FIG. 16, or FIG. Mirror polishing is performed.

  Here, although not described in the first embodiment, a notch is formed at the interface between the insulating film 13 and the n-type semiconductor layer 12 by the heat treatment in the hydrogen atmosphere before the p-type semiconductor layer 14 is epitaxially grown in the trench 2. It is formed. Therefore, when the p-type semiconductor layer 14 is epitaxially grown, the p-type semiconductor layer 14 is filled in this notch, so that a protrusion of the p-type semiconductor layer 14 is formed. As in the second embodiment, by etching back the p-type semiconductor layer 14, the exposed surface of the p-type semiconductor layer 14 and the interface between the n-type semiconductor layer 12 and the insulating film 13 thereon are almost the same height. In this case, only this protrusion may be removed during mirror polishing.

  Therefore, the polishing amount at the time of mirror polishing may be about 0.1 μm, for example. The polishing depth at this time corresponds to the line DD in FIG. As shown in FIG. 15, the depth of the second alignment mark 3 after mirror polishing is about 1.4 μm. Further, the polishing amount during mirror polishing may be increased to, for example, about 0.4 μm. The polishing depth at this time corresponds to the line EE in FIG. 14, and as shown in FIG. 16, the second alignment mark 3 having a depth of about 1.1 μm remains after mirror polishing.

  Furthermore, when the first alignment mark 1 is used as a polishing monitor and the mirror polishing is terminated when the first alignment mark 1 disappears, the polishing amount is about 0.7 μm. The polishing depth at this time corresponds to the FF line in FIG. 14, and as shown in FIG. 17, the second alignment mark 3 having a depth of about 0.8 μm remains after mirror polishing. Thereafter, when the surface structure of the element is manufactured, mask alignment is performed using the second alignment mark 3 as a reference. According to the second embodiment, the same effect as in the first embodiment can be obtained.

Embodiment 3 FIG.
18 to 28 are longitudinal sectional views showing an outline of a semiconductor element being manufactured according to the third embodiment of the present invention. In the third embodiment, the first and second alignment marks 1 and 3 in the first embodiment are formed by isotropic dry etching. In the following description, description of the same configuration as that of the first embodiment will be omitted, and only a configuration different from that of the first embodiment will be described.

  First, according to the process shown in FIG. 1, the n-type semiconductor layer 12 is epitaxially grown on the low resistance semiconductor substrate 11. Thereafter, as shown in FIG. 18, isotropic dry etching is performed to form the first alignment mark 1 in the n-type semiconductor layer 12. Specifically, for example, the first alignment mark 1 can be formed by forming a resist mask on the surface of the n-type semiconductor layer 12 and performing CDE (chemical dry etching). The depth of the first alignment mark 1 is, for example, about 0.5 to 1.0 μm. Here, description will be made assuming that the depth of the first alignment mark 1 is 0.5 μm.

  Next, as shown in FIG. 19, an insulating film 13 is provided on the n-type semiconductor layer 12 and the first alignment mark 1. The insulating film 13 is an oxide film, a nitride film, or a film having a two-layer structure of a nitride film and an oxide film. Although not particularly limited, here, the substrate on which the first alignment mark 1 is formed is oxidized, and an oxide film having a thickness of, for example, about 2 μm is formed as the insulating film 13. Then, the insulating film 13 is patterned to selectively open portions of the insulating film 13 where trench etching is to be performed, thereby forming a hard mask for forming the trench.

  Next, the steps shown in FIGS. 20 to 23 are performed. The steps shown in FIGS. 20, 21, 22, and 23 correspond to the steps shown in FIGS. 4, 5, 6, and 7, respectively. However, in FIGS. 20, 21, 22 and 23, the first alignment mark 1 has a shape formed by isotropic etching. In the third embodiment, the thickness of the insulating film 13 after the trench formation is, for example, about 1 μm.

  Next, as shown in FIG. 24, isotropic dry etching such as CDE is performed using the insulating film 13 as a mask to form the second alignment mark 3. At the same time, the p-type semiconductor layer 14 in the trench 2 is etched to reduce the level difference of the surface to be polished in the subsequent mirror polishing. The etching depth at this time is, for example, about 1 to 1.5 μm.

  When the etching depth is 1 μm, since the thickness of the insulating film 13 after the trench formation is about 1 μm, the exposed surface of the p-type semiconductor layer 14 is the n-type semiconductor layer 12 and the insulating film 13 thereon. It becomes almost the same height as the interface. When the etching depth is deeper than 1 μm, the exposed surface of the p-type semiconductor layer 14 is lower than the interface between the n-type semiconductor layer 12 and the insulating film 13 thereon. When the etching depth is 1.5 μm, the exposed surface of the p-type semiconductor layer 14 is almost the same height as the bottom surface of the first alignment mark 1. Here, description will be made assuming that the depth of the second alignment mark 3 is about 1.5 μm.

  Next, as shown in FIG. 25, the insulating film 13 is removed, and then, as shown in FIG. 26, FIG. 27, or FIG. 28, the surface is mirror-polished so as not to lose the second alignment mark 3. . Here, since the depth of the second alignment mark 3 is about 1.5 μm, the polishing amount at the time of mirror polishing may be, for example, about 0.5 to 1 μm. As a result, a step having a depth of about 0.5 to 1 μm remains as the second alignment mark 3, and thereafter, when the surface structure of the element is manufactured, mask alignment is performed using this step as a reference. Just do it.

  26, 27, and 28 correspond to the cases where the polishing depth during mirror polishing is the GG line, the HH line, and the II line in FIG. 25, respectively. As in the first embodiment, the first alignment mark 1 may disappear by mirror polishing (FIGS. 27 and 28), or may remain without disappearing (FIG. 26). When the first alignment mark 1 is lost by mirror polishing, the first alignment mark 1 can be used as a polishing monitor.

  Here, advantages of forming the first alignment mark 1 by performing isotropic etching will be described with reference to FIG. 29 to FIG. 33 using the insulating film 13 as an oxide film. FIG. 29 is a plan view showing a part of the first alignment mark 1, and FIGS. 30 to 33 are cross-sectional views of relevant parts showing a cross-sectional configuration taken along the line ZZ of FIG. FIGS. 30 and 31 show a state where the first alignment mark 1 is formed by isotropic etching and a state where the first alignment mark 1 is oxidized thereafter. 32 and 33 show a state in which the first alignment mark 1 is formed by anisotropic etching and a state in which the first alignment mark 1 is subsequently oxidized.

  As shown in FIG. 31, the thicknesses of the oxide film (insulating film 13) around the first alignment mark 1 formed by isotropic etching and at the rounded corners are t1 and t2, respectively. Further, as shown in FIG. 33, the thicknesses of the oxide film (insulating film 13) around the first alignment mark 1 formed by anisotropic etching and at the corners are t3 and t4, respectively. The magnitude relationship among t1, t2, t3, and t4 is t4 <t1 = t2 = t3. That is, when isotropic etching is performed, the insulating film 13 is thicker at the corners of the first alignment mark 1 than when anisotropic etching is performed.

  Therefore, when isotropic etching is performed, the insulating film 13 can be made thinner overall than when anisotropic etching is performed. Even if the insulating film 13 is thinned, the insulating film 13 may be broken at the corners of the first alignment mark 1 while performing trench etching to form the deep trench 2 in a later step. Absent. As described above, when the insulating film 13 is formed by a CVD (chemical vapor deposition) method or the like, the coverage of the insulating film 13 is improved, so that the insulating film 13 can be thinned. Further, when the hard mask of the trench 2 is formed by a thermal oxidation method or the like, it is possible to prevent a local film thickness decrease due to a three-dimensional shape effect, and thus the hard mask can be thinned.

  Advantages of forming the second alignment mark 3 by performing isotropic etching will be described with reference to FIGS. 34 and 35 show the cross-sectional shapes before and after removing the insulating film 13 of the p-type semiconductor layer 14 when the second alignment mark 3 is formed by isotropic etching. . 36 and 37 show the cross-sectional shapes of the p-type semiconductor layer 14 before and after removing the insulating film 13 when the second alignment mark 3 is formed by anisotropic etching. Has been.

  As described in the first embodiment, normally, before the p-type semiconductor layer 14 is epitaxially grown in the trench 2, heat treatment is performed in a hydrogen atmosphere to remove the natural oxide film on the surface of the trench 2. During this heat treatment, the exposed interface portion of the insulating film 13 between the insulating film 13 and the n-type semiconductor layer 12 is etched to form a notch. Therefore, when the p-type semiconductor layer 14 is epitaxially grown, the p-type semiconductor layer 14 is also filled in this notch.

  When the second alignment mark 3 is formed by isotropic etching, a sufficient selection ratio between the insulating film 13 and the p-type semiconductor layer 14 is ensured, and the etching is advanced to the protrusion 18 that fills the notch. The film 13 is not etched, but the protrusions 18 are etched away or become smaller. Therefore, even if there is no protrusion 18 on the surface after the insulating film 13 is removed, even if the protrusion is small, the amount of polishing during mirror polishing can be reduced.

  On the other hand, when the second alignment mark 3 is formed by anisotropic etching, the protrusion 18 filling the notch remains without being etched. Accordingly, since the protrusion 18 remains large on the surface after the insulating film is removed, the polishing amount during mirror polishing cannot be reduced. According to the third embodiment, in addition to the effects described above, the same effects as in the first embodiment can be obtained. However, the effect of improving the accuracy of the alignment mark obtained when the first and second alignment marks 1 and 3 are formed by anisotropic etching is excluded.

Embodiment 4 FIG.
38 to 42 are longitudinal sectional views showing an outline of a semiconductor element being manufactured according to the fourth embodiment of the present invention. The fourth embodiment is different from the third embodiment in the etching depth when the second alignment mark 3 is formed. In the following description, the description of the same configuration as that of the third embodiment will be omitted, and only the configuration different from that of the third embodiment will be described.

  First, according to the steps shown in FIGS. 1 and 18 to 23, only the second alignment mark formation region of the n-type semiconductor layer 12 is exposed. Thereafter, as shown in FIG. 38, isotropic dry etching such as CDE is performed using the insulating film 13 as a mask. The etching depth at this time is about 1 μm. Therefore, the exposed surface of the p-type semiconductor layer 14 has substantially the same height as the interface between the n-type semiconductor layer 12 and the insulating film 13 thereon. Then, as shown in FIG. 39, after all the insulating film 13 remaining on the surface is removed, as shown in FIG. 40, FIG. 41, or FIG. Mirror polishing is performed.

  Here, as described in the third embodiment, when the p-type semiconductor layer 14 is epitaxially grown in the trench 2, the p-type semiconductor layer 14 is filled in the notch at the interface between the insulating film 13 and the n-type semiconductor layer 12. Thus, the protrusion 18 of the p-type semiconductor layer 14 is formed. As in the fourth embodiment, the etched surface of the p-type semiconductor layer 14 causes the exposed surface of the p-type semiconductor layer 14 and the interface between the n-type semiconductor layer 12 and the insulating film 13 thereon to have substantially the same height. In this case, only the protrusion 18 may be removed during mirror polishing.

  Therefore, the polishing amount at the time of mirror polishing may be about 0.1 μm, for example. The polishing depth at this time corresponds to the line JJ in FIG. As shown in FIG. 40, the depth of the second alignment mark 3 after mirror polishing is about 0.9 μm. Further, the polishing amount during mirror polishing may be about 0.2 μm, for example. The polishing depth at this time corresponds to the line KK in FIG. 39, and as shown in FIG. 41, the second alignment mark 3 having a depth of about 0.8 μm remains after mirror polishing. Further, the polishing amount during mirror polishing may be increased to, for example, about 0.4 μm. The polishing depth at this time corresponds to the line LL in FIG. 39, and as shown in FIG. 42, the second alignment mark 3 having a depth of about 0.6 μm remains after mirror polishing.

  Furthermore, when the first alignment mark 1 is used as a polishing monitor and the mirror polishing is terminated when the first alignment mark 1 disappears, the polishing amount is about 0.5 μm. The polishing depth at this time is not particularly shown in FIG. 39, but is the depth to the bottom of the first alignment mark 1. The depth of the second alignment mark 3 after mirror polishing is about 0.5 μm. Thereafter, when the surface structure of the element is manufactured, mask alignment is performed using the second alignment mark 3 as a reference. According to the fourth embodiment, the same effect as in the third embodiment can be obtained.

Embodiment 5 FIG.
43 to 48 are longitudinal sectional views showing an outline of a semiconductor element being manufactured according to the fifth embodiment of the present invention. In the fifth embodiment, the protrusions of the p-type semiconductor layer 14 formed by epitaxial growth of the p-type semiconductor layer 14 in the first or second embodiment are formed and removed without performing mirror polishing. Is to be removed. In the following description, description of the same configuration as in the first or second embodiment will be omitted, and only a configuration different from the first or second embodiment will be described.

  First, according to the steps shown in FIGS. 1 to 7, only the second alignment mark formation region of the n-type semiconductor layer 12 is exposed. The thickness of the insulating film 13 at this time is set to tox1 (see FIG. 43). Thereafter, as shown in FIG. 8 or FIG. 13, anisotropic dry etching such as trench etching is performed using the insulating film 13 as a mask. Depending on the etching depth at this time, the subsequent steps from the formation of the second alignment mark 3 to the removal of the insulating film 13 are the same as those of the first and second embodiments. If the etching depth is deeper than tox1, it is the same as in the first embodiment, and if the etching depth is approximately tox1, it is the same as in the second embodiment. Here, it is assumed that the etching depth is approximately tox1.

  Since the p-type semiconductor layer 14 is also etched back at an etching depth of approximately tox1, as shown in an enlarged view in FIG. 43, the exposed surface of the p-type semiconductor layer 14 is the n-type semiconductor layer 12 and the insulating film thereon. 13 and almost the same height as the interface. However, when the p-type semiconductor layer 14 is epitaxially grown, since the p-type semiconductor layer 14 is filled in the notch formed at the interface between the insulating film 13 and the n-type semiconductor layer 12, the insulating film 13 remaining on the surface is removed. When all are removed to expose the surfaces of the n-type semiconductor layer 12 and the p-type semiconductor layer 14 (see FIG. 14), the protrusions 18 of the p-type semiconductor layer 14 remain on the surface as shown in an enlarged view in FIG. .

  In this state, as shown in FIG. 45, oxidation treatment is performed again to form a sacrificial oxide film 19 on the surfaces of the n-type semiconductor layer 12, the p-type semiconductor layer 14, the first alignment mark 1 and the second alignment mark 3. Form. By this sacrificial oxidation treatment, as shown in an enlarged view in FIG. 46, the sacrificial oxide film 19 is formed with an oxide film projection 20 reflecting the projection 18 of the p-type semiconductor layer 14. Since the size of the protrusion 18 of the p-type semiconductor layer 14 is about 0.2 μm, the sacrificial oxide film 19 may be oxidized so as to have a thickness of about 0.5 μm, for example. Then, all the protrusions 18 of the p-type semiconductor layer 14 become oxide films, and oxidation further proceeds in the depth direction of the n-type semiconductor layer 12 and the p-type semiconductor layer 14. As a result, there is almost no step at the interface between the sacrificial oxide film 19 and the semiconductor layers 12 and 14.

  Next, as shown in FIG. 47, the sacrificial oxide film 19 is removed. By doing so, as shown in an enlarged view in FIG. 48, the surfaces of the n-type semiconductor layer 12 and the p-type semiconductor layer 14 become substantially flat surfaces without irregularities. However, although the shape of the second alignment mark 3 is dulled by this sacrificial oxidation treatment, the depth of the second alignment mark 3 is about 1 to 1.5 μm if tox1 is about 1 to 1.5 μm, for example. Therefore, when the surface structure of the element is manufactured thereafter, the mask alignment may be performed with the second alignment mark 3 as a reference.

  According to the fifth embodiment, since the second alignment mark 3 remains after the sacrificial oxide film is removed, the surface is flat and the superjunction semiconductor device having the alignment mark is prepared without performing mirror polishing. A semiconductor substrate can be obtained. In addition, since the first and second alignment marks 1 and 3 are formed by anisotropic etching, the accuracy of the alignment marks can be improved. Further, when the second alignment mark 3 is formed, it is not necessary to newly provide an oxidation step to form a mask, so that the manufacturing cost can be reduced. Furthermore, since the surface is planarized before the second alignment mark 3 is formed, it is possible to prevent resist unevenness from occurring in the subsequent photolithography process.

Embodiment 6 FIG.
49 to 54 are longitudinal sectional views schematically showing a semiconductor element in the middle of manufacture according to the sixth embodiment of the present invention. In the sixth embodiment, the second alignment mark 3 is formed by isotropic etching in the fifth embodiment. In the following description, description of the same configuration as that of the fifth embodiment will be omitted, and only a configuration different from that of the fifth embodiment will be described.

  First, according to the steps shown in FIGS. 1 to 7, only the second alignment mark formation region of the n-type semiconductor layer 12 is exposed. The thickness of the insulating film 13 at this time is set to tox2 (see FIG. 50). Thereafter, as shown in FIG. 49, isotropic dry etching such as CDE is performed using the insulating film 13 as a mask. The etching depth at this time is approximately tox2, for example. Therefore, since the p-type semiconductor layer 14 is also etched back to the etching depth of approximately tox2, as shown in an enlarged view in FIG. 50, the exposed surface of the p-type semiconductor layer 14 is the n-type semiconductor layer 12 and the upper surface thereof. The height is almost the same as the interface with the insulating film 13.

  Further, the protrusion 18 of the p-type semiconductor layer 14 that fills the notch formed at the interface between the insulating film 13 and the n-type semiconductor layer 12 is also etched. Therefore, when all of the insulating film 13 remaining on the surface is removed and the surfaces of the n-type semiconductor layer 12 and the p-type semiconductor layer 14 are exposed, as shown in an enlarged view in FIG. Although the protrusion 18 remains, the size thereof is smaller than that in the fifth embodiment. The size of the protrusion 18 is, for example, about 0.1 μm.

  In this state, as shown in FIG. 52, the oxidation process is performed again to form the sacrificial oxide film 19 on the surfaces of the n-type semiconductor layer 12, the p-type semiconductor layer 14, the first alignment mark 1 and the second alignment mark 3. Form. By this sacrificial oxidation treatment, as shown in an enlarged view in FIG. 53, the sacrificial oxide film 19 is formed with an oxide film projection 20 reflecting the projection 18 of the p-type semiconductor layer 14. At this time, if the oxidation process is performed so that the sacrificial oxide film 19 has a thickness of, for example, about 0.2 μm, all the protrusions 18 of the p-type semiconductor layer 14 become oxide films. Further, the oxidation further proceeds in the depth direction of the n-type semiconductor layer 12 and the p-type semiconductor layer 14, so that there is almost no step at the interface between the sacrificial oxide film 19 and the semiconductor layers 12 and 14.

  Next, as shown in FIG. 54, the sacrificial oxide film 19 is removed. By doing in this way, the surface of the n-type semiconductor layer 12 and the p-type semiconductor layer 14 becomes a substantially flat surface without unevenness (see FIG. 48). However, although the shape of the second alignment mark 3 is dulled by this sacrificial oxidation treatment, the sacrificial oxide film 19 can be made thin, so that the mask alignment can be performed as the second alignment mark 3. A step remains. Therefore, after that, when the surface structure of the element is manufactured, the mask alignment may be performed using the second alignment mark 3 as a reference. Actually, when the inventors made a prototype with the thickness of the sacrificial oxide film 19 set to 0.4 μm according to the method of the sixth embodiment, the mask alignment is performed without any problem with the second alignment mark 3 as a reference. I was able to.

  According to the sixth embodiment, since the second alignment mark 3 remains after the sacrificial oxide film is removed, the surface is flat and a superjunction semiconductor element having an alignment mark is prepared without performing mirror polishing. A semiconductor substrate can be obtained. Further, when the second alignment mark 3 is formed, it is not necessary to newly provide an oxidation step to form a mask, so that the manufacturing cost can be reduced. Furthermore, since the surface is planarized before the second alignment mark 3 is formed, it is possible to prevent resist unevenness from occurring in the subsequent photolithography process.

Embodiment 7 FIG.
55 to 64 are longitudinal sectional views schematically showing a semiconductor element in the middle of manufacture according to the seventh embodiment of the present invention. In the following description, description of the same configuration as that of the first embodiment will be omitted, and only a configuration different from that of the first embodiment will be described.

  From preparation of the low-resistance semiconductor substrate 11 to polishing using the insulating film 13 as a hard mask at the time of trench formation as a stopper to remove the portion of the p-type semiconductor layer 14 on the surface of the insulating film 13, FIG. ~ Same process as shown in FIG. However, the description here assumes that the depth of the first alignment mark 1 is 1 μm. Note that the first alignment mark 1 may be formed by performing isotropic dry etching instead of anisotropic etching.

  Next, as shown in FIG. 55, all the insulating film 13 remaining on the surface is removed. Then, as shown in FIG. 56, the insulating film 21 is formed again on the surfaces of the n-type semiconductor layer 12, the p-type semiconductor layer 14, and the first alignment mark 1. The insulating film 21 is an oxide film, a nitride film, or a film having a two-layer structure of a nitride film and an oxide film. Although not particularly limited here, the n-type semiconductor layer 12 and the p-type semiconductor layer 14 are oxidized to form an oxide film as the insulating film 21. The thickness of the oxide film is set such that a second alignment mark having a target depth can be obtained in a later step according to the selection ratio between the oxide film and the semiconductor layer. The thickness of the oxide film (insulating film 21) is set to about 0.4 μm, for example.

  Next, as shown in FIG. 57, photolithography and etching are performed to remove a part of the insulating film 21 so that only the second alignment mark formation region of the n-type semiconductor layer 12 is exposed. The p-type semiconductor layer 14 remains covered with the insulating film 21. In the photolithography process, the first alignment mark 1 is used for alignment (alignment) of the mask during exposure. Next, as shown in FIG. 58, anisotropic dry etching is performed using the insulating film 21 as a mask to form the second alignment mark 3. At this time, the p-type semiconductor layer 14 is not etched back. Here, the depth of the second alignment mark 3 is, for example, 5 μm. Note that the second alignment mark 3 may be formed by performing isotropic dry etching instead of anisotropic etching.

  Next, as shown in FIG. 59, all the insulating film 21 remaining on the surface is removed. Then, the surface is mirror-polished so that the second alignment mark 3 is not lost. By this mirror polishing, the first alignment mark 1 may disappear (FIGS. 63 and 64) or may remain without disappearing (FIGS. 61 and 62). FIG. 60 shows four different polishing amounts at the time of mirror polishing. At the polishing depths indicated by the MM line and the NN line, the first alignment mark 1 remains as shown in FIGS. 61 and 62, respectively.

  At the polishing depth indicated by the OO line and the PP line, the first alignment mark 1 does not remain as shown in FIGS. 63 and 64, respectively. When the polishing depth indicated by the OO line is used, the first alignment mark 1 can be used as a polishing monitor. Therefore, mirror polishing is finished when the first alignment mark 1 disappears during polishing. Let Thereafter, when the surface structure of the element is fabricated, mask alignment may be performed using the second alignment mark 3 as a reference.

  According to the seventh embodiment, since second alignment mark 3 remains after mirror polishing, a semiconductor substrate for manufacturing a superjunction semiconductor element having an alignment mark can be obtained. In particular, since the p-type semiconductor layer 14 is not etched back when the second alignment mark 3 is formed, the second alignment mark 3 having an arbitrary depth can be formed. Moreover, when forming the 1st and 2nd alignment marks 1 and 3 by anisotropic etching, the precision of an alignment mark can be improved. Further, the amount (polishing depth) to be removed by mirror polishing can be set between the exposed surface of the n-type semiconductor layer 12 and immediately before the second alignment mark 3 disappears. I can afford it. This corresponds to the fact that it is possible to make a design that provides a margin for in-plane variation.

Embodiment 8 FIG.
65 to 71 are longitudinal sectional views showing an outline of a semiconductor element being manufactured according to the eighth embodiment of the present invention. In the eighth embodiment, the p-type semiconductor layer 14 is etched back after polishing using the insulating film 13 as a stopper in the seventh embodiment. In the following description, the description of the same configuration as that of the seventh embodiment will be omitted, and only the configuration different from that of the seventh embodiment will be described.

  First, according to the steps shown in FIGS. 1 to 6, polishing is performed using the insulating film 13 as a stopper, and a portion of the p-type semiconductor layer 14 on the surface of the insulating film 13 is removed. Next, as shown in FIG. 65, anisotropic or isotropic etching is performed using the remaining insulating film 13 as a mask to recede the upper end surface of the p-type semiconductor layer 14 in the trench 2. The retreat amount of the p-type semiconductor layer 14 at this time is almost the same as the thickness of the insulating film 13 used as a mask. Therefore, the exposed surface of the p-type semiconductor layer 14 has substantially the same height as the interface between the n-type semiconductor layer 12 and the insulating film 13 thereon.

  Next, as shown in FIG. 66, all the insulating film 13 remaining on the surface is removed. The surfaces of the n-type semiconductor layer 12 and the p-type semiconductor layer 14 are generally flat. As shown in FIG. 67, an oxide film, a nitride film, or a film having a two-layer structure of a nitride film and an oxide film is formed on the surface of the n-type semiconductor layer 12, the p-type semiconductor layer 14, and the first alignment mark 1. An insulating film 21 made of is formed. The subsequent steps are the same as in the seventh embodiment. That is, as shown in FIG. 68, a part of the insulating film 21 is removed. Then, as shown in FIG. 69, anisotropic etching is performed with the p-type semiconductor layer 14 covered with the insulating film 21 to form the second alignment mark 3 having a depth of, for example, 5 μm.

  The second alignment mark 3 may be formed deeper than 5 μm. However, when the second alignment mark 3 is formed deeply, for example, when the depth of the second alignment mark 3 is 10 μm, a polishing amount of about 9 μm can be afforded by subsequent mirror polishing, but 9 μm When polishing is performed with the machining allowance, the length in the depth direction of the parallel pn junction structure is 41 μm, and the breakdown voltage is lowered. Since such a problem may occur, it is necessary to appropriately determine the depth of the second alignment mark 3.

  Next, as shown in FIG. 70, the entire insulating film 21 is removed. Thereafter, the surface is mirror-polished so as not to lose the second alignment mark 3. FIG. 71 shows four different polishing amounts at the time of mirror polishing. At the polishing depth indicated by the QQ line and the RR line, the first alignment mark 1 remains (see FIGS. 61 and 62). When the polishing depth indicated by the QQ line is used, the amount of polishing is very small, and the protrusion formed by filling the p-type semiconductor layer 14 into the notch formed at the interface between the n-type semiconductor layer 12 and the insulating film 13. This corresponds to polishing for removing the portion 18.

  Further, the first alignment mark 1 does not remain at the polishing depth indicated by the SS line and the TT line (see FIGS. 63 and 64). When the polishing depth indicated by the SS line is used, the first alignment mark 1 can be used as a polishing monitor. Thereafter, when the surface structure of the element is fabricated, mask alignment may be performed using the second alignment mark 3 as a reference. According to the eighth embodiment, the same effect as in the seventh embodiment can be obtained. Further, the etch-back of the p-type semiconductor layer 14 causes the surface of the n-type semiconductor layer 12 and the surface of the p-type semiconductor layer 14 to have almost the same height, so that the insulating film 21 is formed in order to form the second alignment mark 3. Since the resist unevenness can be suppressed when patterning is performed, the opening size can be controlled with high accuracy.

Embodiment 9 FIG.
72 to 76 are longitudinal sectional views showing an outline of a semiconductor element being manufactured according to the ninth embodiment of the present invention. In the ninth embodiment, after the p-type semiconductor layer 14 is etched back in the eighth embodiment, an insulating film 21 is further formed without removing the insulating film 13. It is. In the following description, description of the same configuration as that of the eighth embodiment is omitted, and only a configuration different from that of the eighth embodiment will be described.

  First, according to the steps shown in FIGS. 1 to 6 and 65, anisotropic or isotropic etching is performed using the insulating film 13 as a mask to recede the upper end surface of the p-type semiconductor layer 14 in the trench 2. Next, as shown in FIG. 72, oxidation is performed to form the insulating film 21. This oxidation is intended to prevent the p-type semiconductor layer 14 from being etched when the second alignment mark 3 is formed later. Therefore, the insulating film 21 may be formed by depositing an insulating film such as an oxide film or a nitride film by CVD or the like. The same applies to the above-described seventh or eighth embodiment.

  The subsequent steps are the same as in the eighth embodiment. That is, a part of the insulating film 21 is removed, and anisotropic etching is performed with the p-type semiconductor layer 14 covered with the insulating film 21 as shown in FIG. The alignment mark 3 is formed. The second alignment mark 3 may be formed deeper than 5 μm. Next, as shown in FIG. 74, the entire insulating film 21 is removed. Thereafter, the surface is mirror-polished so as not to lose the second alignment mark 3.

  FIG. 75 shows four different polishing amounts at the time of mirror polishing. At the polishing depth indicated by the line U-U, as shown in FIG. 76, the polishing amount is as small as about 0.2 μm, and the level difference in the p-type semiconductor layer 14 is eliminated. Therefore, the first alignment mark 1 remains. Further, the first alignment mark 1 remains even at the polishing depth indicated by the line VV (see FIG. 62). Further, the first alignment mark 1 does not remain at the polishing depth indicated by the WW line and the XX line (see FIGS. 63 and 64). When the polishing depth indicated by the WW line is used, the first alignment mark 1 can be used as a polishing monitor. Thereafter, when the surface structure of the element is fabricated, mask alignment may be performed using the second alignment mark 3 as a reference. According to the ninth embodiment, the same effect as in the eighth embodiment can be obtained.

Embodiment 10 FIG.
77 and 78 are longitudinal sectional views schematically showing a semiconductor element in the middle of manufacture according to the tenth embodiment of the present invention. In the tenth embodiment, the p-type semiconductor layer 14 is protected by a resist instead of the insulating film 21 when the second alignment mark 3 is formed in the seventh embodiment. In the following description, the description of the same configuration as that of the seventh embodiment will be omitted, and only the configuration different from that of the seventh embodiment will be described.

  First, after polishing using the insulating film 13 as a stopper according to the steps shown in FIGS. 1 to 6 and 55, the entire insulating film 13 is removed. Next, as shown in FIG. 77, a resist 22 is applied to the surfaces of the n-type semiconductor layer 12, the p-type semiconductor layer 14, and the first alignment mark 1, and a part of the resist 22 is removed by photolithography. . Then, as shown in FIG. 78, anisotropic etching such as RIE is performed while the n-type semiconductor layer 12, the p-type semiconductor layer 14, and the first alignment mark 1 are covered with the resist 22, for example, 5 μm. A second alignment mark 3 having a depth is formed. The second alignment mark 3 may be formed deeper than 5 μm.

  Next, the resist 22 is ashed and removed. Then, the surface is mirror-polished so that the second alignment mark 3 is not lost. By this mirror polishing, the first alignment mark 1 may be lost or left. According to the tenth embodiment, the same effect as in the seventh embodiment can be obtained. Further, since it is not necessary to form the insulating film 21 for protecting the p-type semiconductor layer 14 before forming the second alignment mark 3, the manufacturing cost can be reduced.

Embodiment 11 FIG.
79 and 80 are longitudinal sectional views schematically showing a semiconductor element in the middle of manufacture according to the eleventh embodiment of the present invention. In the eleventh embodiment, the p-type semiconductor layer 14 is protected by a resist in place of the insulating film 21 when the second alignment mark 3 is formed in the eighth embodiment. In the following description, description of the same configuration as that of the eighth embodiment is omitted, and only a configuration different from that of the eighth embodiment will be described.

  First, according to the steps shown in FIGS. 1 to 6, 65 and 66, the p-type semiconductor layer 14 is etched back using the insulating film 13 as a mask, and then the insulating film 13 is entirely removed. Next, as shown in FIG. 79, a resist 22 is applied to the surfaces of the n-type semiconductor layer 12, the p-type semiconductor layer 14, and the first alignment mark 1, and a part of the resist 22 is removed by photolithography. . Then, as shown in FIG. 80, anisotropic etching such as RIE is performed with the n-type semiconductor layer 12, the p-type semiconductor layer 14, and the first alignment mark 1 covered with the resist 22. A second alignment mark 3 having a depth is formed. The second alignment mark 3 may be formed deeper than 5 μm.

  Next, the resist 22 is ashed and removed. Then, the surface is mirror-polished so that the second alignment mark 3 is not lost. By this mirror polishing, the first alignment mark 1 may be lost or left. According to the eleventh embodiment, the same effect as in the eighth embodiment can be obtained. Further, since it is not necessary to form the insulating film 21 for protecting the p-type semiconductor layer 14 before forming the second alignment mark 3, the manufacturing cost can be reduced.

Embodiment 12 FIG.
81 to 88 are longitudinal sectional views schematically showing a semiconductor element in the middle of manufacture according to the twelfth embodiment of the present invention. In the following description, description of the same configuration as that of the first embodiment will be omitted, and only a configuration different from that of the first embodiment will be described. However, in the twelfth embodiment, the first alignment mark 1 is read as the alignment mark 1.

  First, according to the steps shown in FIGS. 1 to 6, polishing is performed using the insulating film 13 as a stopper, and a portion of the p-type semiconductor layer 14 on the surface of the insulating film 13 is removed. Next, as shown in FIG. 81, etching is performed using the remaining insulating film 13 as a mask to retreat the upper end surface of the p-type semiconductor layer 14 in the trench 2. The retreat amount of the p-type semiconductor layer 14 at this time is almost the same as the thickness of the insulating film 13 used as a mask. A step may be formed between the n-type semiconductor layer 12 and the p-type semiconductor layer 14 after the etching.

  The reason why the step is formed is that the thickness of the insulating film 13 when the p-type semiconductor layer 14 is etched back varies and the etching amount varies. When the present inventors confirmed with the actual process, the height of this level | step difference was 0.1 micrometer or less. As shown in FIG. 82, when the p-type semiconductor layer 14 is epitaxially grown in the trench 2, the p-type semiconductor layer 14 is filled in the notch at the interface between the insulating film 13 and the n-type semiconductor layer 12. The reason why this notch can be made is as described in the third embodiment.

  Next, as shown in FIG. 83, the insulating film 13 is removed by peeling with HF (hydrogen fluoride) or dry etching. On the exposed semiconductor surface, in addition to the step between the n-type semiconductor layer 12 and the p-type semiconductor layer 14, as shown in FIG. 84, a protrusion 18 is formed by the p-type semiconductor layer 14 filled in the notch. . The width and height of the protrusion 18 are both about 0.14 μm, for example. Next, as shown in FIG. 85, heat treatment is performed to form a sacrificial oxide film 19 on the surfaces of the n-type semiconductor layer 12, the p-type semiconductor layer 14 and the alignment mark 1. By this sacrificial oxidation treatment, as shown in an enlarged view in FIG. 86, the sacrificial oxide film 19 is formed with an oxide film projection 20 reflecting the projection 18 of the p-type semiconductor layer 14.

  Next, as shown in FIG. 87, the sacrificial oxide film 19 is removed. By doing so, as shown in an enlarged view in FIG. 88, the protruding portion 18 of the p-type semiconductor layer 14 disappears, and a substantially flattened semiconductor surface is obtained. FIG. 89 and FIG. 90 show the results of simulations performed to verify that the protrusions 18 of the p-type semiconductor layer 14 disappear and the semiconductor surface is planarized by sacrificial oxidation. 89 shows the shape of the semiconductor surface before sacrificial oxidation, and FIG. 90 shows the shape of the semiconductor surface after sacrificial oxidation.

  Comparing the two figures, by forming the sacrificial oxide film 19 having a thickness of 0.8 μm, the protrusion 18 disappears and the step difference between the n-type semiconductor layer 12 and the p-type semiconductor layer 14 changes gently. You can see that With such a step, there is no influence on the subsequent processes. Further, since the height of the step is about 0.1 μm, there is no influence on the element characteristics. Therefore, the surface structure of the element can be fabricated without polishing the semiconductor surface thereafter.

  According to the twelfth embodiment, since the polishing is not performed after the insulating film 13 used as a mask for forming the trench 2 is removed, the semiconductor under the insulating film 13 is not polished. Does not decrease. Therefore, a semiconductor substrate for manufacturing a superjunction semiconductor element having an alignment mark can be obtained without newly forming a second alignment mark. Further, since the polishing step and the step for forming the second alignment mark can be omitted, the manufacturing cost can be reduced. Furthermore, since the semiconductor under the insulating film 13 is not polished, the thickness of the semiconductor substrate for manufacturing the superjunction semiconductor element does not vary due to the polishing, so that the variation in breakdown voltage can be reduced. Further, after polishing using the insulating film 13 as a stopper, the polished surface is completely removed by etching, so that contamination of the substrate due to polishing can be eliminated.

Embodiment 13 FIG.
91 to 94 are longitudinal sectional views schematically showing a semiconductor element in the middle of manufacture according to the thirteenth embodiment of the present invention. In the thirteenth embodiment, the sacrificial oxide film 19 is patterned to form the second alignment mark 3 in the twelfth embodiment. In the following description, description of the same configuration as that of the twelfth embodiment is omitted, and only a configuration different from that of the twelfth embodiment is described. However, in the thirteenth embodiment, the alignment mark 1 read in the twelfth embodiment is read as the first alignment mark 1 again.

  First, a sacrificial oxide film 19 is formed on the surfaces of the n-type semiconductor layer 12, the p-type semiconductor layer 14, and the first alignment mark 1 in accordance with the steps shown in FIGS. 1 to 6 and 81 to 86. Next, as shown in FIG. 91, a part of the sacrificial oxide film 19 is removed, and only the second alignment mark formation region of the n-type semiconductor layer 12 is exposed. The first alignment mark 1 is used for mask alignment (alignment) at this time. Next, as shown in FIG. 92, etching is performed using the sacrificial oxide film 19 as a mask to form the second alignment mark 3.

  Next, as shown in FIG. 93, the sacrificial oxide film 19 is removed by etching. Thereby, a flat semiconductor surface having the second alignment mark 3 is obtained. Then, as shown in FIG. 94, mirror polishing of the surface is performed so that the second alignment mark 3 is not lost. 93 indicates the polishing depth when the first alignment mark 1 is used as a polishing monitor. Thereafter, when the surface structure of the element is fabricated, mask alignment may be performed using the second alignment mark 3 as a reference.

  According to the thirteenth embodiment, since the second alignment mark 3 remains after mirror polishing, a semiconductor substrate for manufacturing a superjunction semiconductor element having an alignment mark can be obtained. Further, since the surface is flattened by polishing before the second alignment mark 3 is formed, it is possible to prevent the occurrence of resist unevenness in the subsequent photolithography process. In addition, since the protruding portion 18 of the p-type semiconductor layer 14 is eliminated due to sacrificial oxidation, the amount of polishing during mirror polishing can be reduced. Accordingly, the mirror polishing time can be shortened, and the manufacturing cost can be reduced. Further, since the polishing amount at the time of mirror polishing is small, polishing can be performed at a low polishing rate, so that the in-plane uniformity of the mirror polishing surface can be improved.

Embodiment 14 FIG.
95 to 98 are longitudinal sectional views showing the outline of a semiconductor element in the middle of manufacture according to the fourteenth embodiment of the present invention. In the fourteenth embodiment, in the twelfth embodiment, the insulating film 13 serving as a mask when forming the trench 2 is hardly left at the end of the polishing process using the insulating film 13 as a stopper. . In the following description, description of the same configuration as that of the twelfth embodiment is omitted, and only a configuration different from that of the twelfth embodiment is described. However, in the fourteenth embodiment, the alignment mark 1 that has been read in the twelfth embodiment is replaced with the first alignment mark 1 again.

  First, the first alignment mark 1 is formed on the n-type semiconductor layer 12 according to the steps shown in FIGS. Next, as shown in FIG. 95, an insulating film 13 is provided on the n-type semiconductor layer 12 and the first alignment mark 1. The insulating film 13 is an oxide film, a nitride film, or a film having a two-layer structure of a nitride film and an oxide film. Then, the insulating film 13 is patterned to selectively open portions of the insulating film 13 where trench etching is to be performed, thereby forming a hard mask for forming the trench. The thickness of the insulating film 13 is slightly thicker than the amount that is reduced until the polishing process is completed when the insulating film 13 is polished later as a stopper.

  Next, as shown in FIG. 96, a deep trench 2 is formed in the n-type semiconductor layer 12 using the insulating film 13 as a hard mask. At this time, the insulating film 13 is also etched and thinned. Next, as in the other embodiments, the natural oxide film (not shown in FIG. 96) covering the side walls and the bottom surface of the trench 2 is removed. Subsequently, as shown in FIG. 97, for example, a boron-doped p-type semiconductor layer 14 is epitaxially grown at normal pressure to selectively fill the trench 2 with the p-type semiconductor layer 14. At that time, until the bottom 15 of the recess that can be formed in the central portion of the p-type semiconductor layer 14 in the width direction of the trench 2 (the horizontal direction in FIG. 97) is higher than the surface 16 of the insulating film 13 as a hard mask. Epitaxial growth is performed.

  Next, as shown in FIG. 98, polishing is performed using the insulating film 13 as a stopper, and the portion of the p-type semiconductor layer 14 on the surface of the insulating film 13 is removed. The thickness of the insulating film 13 remaining when this polishing process is completed is, for example, about 0.05 μm. As described above, since the insulating film 13 hardly remains, in the present embodiment 14, the second alignment mark cannot be formed using the insulating film 13 as a mask oxide film.

  Next, as shown in FIGS. 85 and 87, after sacrificial oxidation, the sacrificial oxide film 19 is peeled off to planarize the semiconductor surface. In this way, the surface structure of the element can be produced without polishing the semiconductor surface. Since the insulating film 13 remaining after the polishing is very thin, there is almost no step between the n-type semiconductor layer 12 and the p-type semiconductor layer 14. Therefore, it is not necessary to perform sacrificial oxidation. When performing sacrificial oxidation, the sacrificial oxide film 19 can be patterned and the second alignment mark can be formed using the sacrificial oxide film 19 as a mask, as in the thirteenth embodiment. Further, if the second alignment mark is formed sufficiently deep, mirror polishing can be performed thereafter to completely flatten the semiconductor surface.

  According to the fourteenth embodiment, a semiconductor substrate for manufacturing a superjunction semiconductor element having an alignment mark can be obtained. In addition, since it is not necessary to etch back the p-type semiconductor layer 14, the manufacturing cost can be reduced. Furthermore, when sacrificial oxidation and mirror polishing are omitted, or when the second alignment mark is not formed, the manufacturing cost can be further reduced.

  In each of the above-described embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the reverse is also true. Further, the present invention is not limited to a silicon semiconductor, and can be applied to a compound semiconductor such as SiC. Further, the semiconductor substrate manufactured by the method of the present invention is used not only for MOSFETs but also for manufacturing devices having a parallel pn junction structure withstand voltage structure such as IGBTs, bipolar transistors, GTO thyristors, or diodes.

  As described above, the method for manufacturing a semiconductor device according to the present invention is useful for manufacturing a device having a breakdown voltage structure with a parallel pn junction structure. Particularly, a high breakdown voltage and a large current capacity can be achieved by the parallel pn junction structure. Suitable for the manufacture of MOSFETs, IGBTs, bipolar transistors, GTO thyristors or diodes.

DESCRIPTION OF SYMBOLS 1 1st alignment mark 2 Trench 3 2nd alignment mark 11 Low resistance semiconductor substrate 12 N type semiconductor layer (1st conductivity type semiconductor layer)
13 Insulating film 14 p-type semiconductor layer (second conductivity type semiconductor layer)
15 Bottom of recess of second conductive type semiconductor layer 16 Surface of insulating film 18 Protrusion 19 Sacrificial oxide film 21 Insulating film 22 Resist

Claims (18)

In manufacturing a semiconductor element having a parallel pn junction structure in which an n-type semiconductor region and a p-type semiconductor region are alternately and repeatedly joined on a low resistance layer,
A first step of epitaxially growing a first conductivity type semiconductor layer on a surface of a low-resistance semiconductor substrate;
A second step of etching a part of the first conductivity type semiconductor layer to form a first alignment mark;
A third step of forming an insulating film having a trench pattern on the surfaces of the first alignment mark and the first conductive semiconductor layer;
A fourth step of etching the first conductive semiconductor layer using the insulating film as a mask to form a trench deeper than the first alignment mark;
A fifth step of epitaxially growing a second conductivity type semiconductor layer in the trench and on the surface of the insulating film;
A sixth step of polishing a portion of the second conductivity type semiconductor layer above the surface of the insulating film using the insulating film as a polishing stopper;
A seventh step of etching the second conductivity type semiconductor layer using the insulating film as a polishing stopper in the sixth step as a mask;
In a state where the surface of the second conductivity type semiconductor layer is protected by a newly formed insulating film, a portion of the first conductivity type semiconductor layer different from the first alignment mark is etched to form a second alignment mark. An eighth step of forming;
A ninth step of polishing the surfaces of the first conductive semiconductor layer and the second conductive semiconductor layer on which the second alignment mark is formed in a mirror shape;
A tenth step of removing the insulating film used as a mask in the seventh step between the seventh step and the eighth step;
Including
In the seventh step, until the etching depth of the second conductive type semiconductor layer becomes the same as the film thickness of the insulating film remaining after polishing in the sixth step, the second conductive type semiconductor layer Etch the
The eighth step includes a step of newly forming the insulating film on the surface of the second conductive type semiconductor layer, a part of the insulating film is removed, and the second conductive type semiconductor layer includes the second conductive type layer. Exposing the formation region of the alignment mark, and forming the second alignment mark by etching the first conductive semiconductor layer by anisotropic etching using the insulating film from which a portion has been removed as a mask The manufacturing method of the semiconductor element characterized by the above-mentioned. In manufacturing a semiconductor element having a parallel pn junction structure in which an n-type semiconductor region and a p-type semiconductor region are alternately and repeatedly joined on a low resistance layer,
A first step of epitaxially growing a first conductivity type semiconductor layer on a surface of a low-resistance semiconductor substrate;
A second step of etching a part of the first conductivity type semiconductor layer to form a first alignment mark;
A third step of forming an insulating film having a trench pattern on the surfaces of the first alignment mark and the first conductive semiconductor layer;
A fourth step of etching the first conductive semiconductor layer using the insulating film as a mask to form a trench deeper than the first alignment mark;
A fifth step of epitaxially growing a second conductivity type semiconductor layer in the trench and on the surface of the insulating film;
A sixth step of polishing a portion of the second conductivity type semiconductor layer above the surface of the insulating film using the insulating film as a polishing stopper;
A seventh step of etching the second conductivity type semiconductor layer using the insulating film as a polishing stopper in the sixth step as a mask;
In a state where the surface of the second conductivity type semiconductor layer is protected by a newly formed insulating film, a portion of the first conductivity type semiconductor layer different from the first alignment mark is etched to form a second alignment mark. An eighth step of forming;
A ninth step of polishing the surfaces of the first conductive semiconductor layer and the second conductive semiconductor layer on which the second alignment mark is formed in a mirror shape;
Including
In the seventh step, until the etching depth of the second conductive type semiconductor layer becomes the same as the film thickness of the insulating film remaining after polishing in the sixth step, the second conductive type semiconductor layer Etch the
The eighth step includes a step of newly forming the insulating film on the surface of the second conductive type semiconductor layer, a part of the insulating film is removed, and the second conductive type semiconductor layer includes the second conductive type layer. Exposing the formation region of the alignment mark, and forming the second alignment mark by etching the first conductive semiconductor layer by anisotropic etching using the insulating film from which a portion has been removed as a mask The manufacturing method of the semiconductor element characterized by the above-mentioned.   The eighth step includes a step of forming a resist on the surface, a step of selectively opening the resist, and etching the first conductive semiconductor layer by anisotropic etching to form the second alignment mark. The method for manufacturing a semiconductor device according to claim 1, further comprising a forming step.   2. The plane orientation of the main surface of the low-resistance semiconductor substrate is a plane equivalent to the (100) plane, and the plane orientation of the orientation flat plane is a plane equivalent to the (100) plane. The manufacturing method of the semiconductor element as described in any one of -3.   The said 4th process forms the said trench so that the surface orientation of a trench side wall may become in parallel with a surface equivalent to a (100) plane, The Claim 1 characterized by the above-mentioned. A method for manufacturing a semiconductor device.   6. The fifth step includes a step of performing a heat treatment in a hydrogen atmosphere at normal pressure, and a step of epitaxially growing the second conductivity type semiconductor layer at normal pressure after the heat treatment step. The manufacturing method of the semiconductor element as described in any one of these.   In the fifth step, the second step is performed until the bottom of the recess of the second conductivity type semiconductor layer epitaxially grown is higher than the surface of the insulating film used as a mask for forming a trench in the fourth step. The method of manufacturing a semiconductor device according to claim 6, wherein the conductive semiconductor layer is epitaxially grown.   6. The method of manufacturing a semiconductor device according to claim 5, wherein in the fourth step, trenches having different widths are formed as the trenches.   9. The fifth step includes a step of performing a heat treatment in a hydrogen atmosphere at normal pressure and a step of epitaxially growing the second conductivity type semiconductor layer at normal pressure after the heat treatment step. A method for manufacturing a semiconductor device.   In the fifth step, the bottom of the recess of the second conductivity type semiconductor layer epitaxially grown in the narrowest trench is more than the surface of the insulating film used as a mask for forming the trench in the fourth step. 10. The method of manufacturing a semiconductor device according to claim 8, wherein the second conductive semiconductor layer is epitaxially grown until it becomes higher.   11. The semiconductor device manufacturing method according to claim 1, wherein in the eighth step, the second alignment mark is formed so as to be deeper than the first alignment mark. Method.   12. The method of manufacturing a semiconductor device according to claim 1, wherein in the seventh step, the second conductive semiconductor layer is etched by anisotropic etching.   In the seventh step, the second conductive semiconductor layer is etched by isotropic etching to expose a protrusion on the surface of the second conductive semiconductor layer, and overetching is performed in that state. The manufacturing method of the semiconductor element as described in any one of Claims 1-11.   The method of manufacturing a semiconductor device according to claim 1, wherein the ninth step is polished to such an extent that the second alignment mark remains.   15. The method of manufacturing a semiconductor device according to claim 14, wherein in the ninth step, polishing is performed until the first alignment mark disappears.   15. The method of manufacturing a semiconductor device according to claim 14, wherein the ninth step is polished to such an extent that the first alignment mark remains. In manufacturing a semiconductor element having a parallel pn junction structure in which an n-type semiconductor region and a p-type semiconductor region are alternately and repeatedly joined on a low resistance layer,
A first step of epitaxially growing a first conductivity type semiconductor layer on a surface of a low-resistance semiconductor substrate;
A second step of forming a first alignment mark by etching a portion of the first conductive type semiconductor layer,
A third step of forming an insulating film having a trench pattern on a surface of the first alignment mark and the first conductive semiconductor layer,
A fourth step of etching the first conductive semiconductor layer using the insulating film as a mask to form a trench deeper than the first alignment mark;
A fifth step of epitaxially growing the second conductivity type semiconductor layer in the trench and on the surface of the insulating film until it becomes higher than the surface of the insulating film;
A sixth step of polishing a portion of the second conductivity type semiconductor layer above the surface of the insulating film using the insulating film as a polishing stopper;
A seventh step of etching the exposed surface of the second conductive type semiconductor layer epitaxially grown in the trench in the fifth step by the thickness remaining after polishing the insulating film used as a polishing stopper in the sixth step When,
An eighth step of removing the insulating film used as a polishing stopper in the sixth step;
Performing a heat treatment to oxidize the exposed semiconductor surface by removing the insulating film in the eighth step;
A tenth step of removing the oxide film formed on the semiconductor surface in the ninth step;
Including
Between the ninth step and the tenth step, a part of the oxide film generated on the semiconductor surface in the ninth step is removed, and the second conductivity of the first conductivity type semiconductor layer is reduced . An eleventh step of exposing the formation region of the alignment mark;
A twelfth step of newly forming a second alignment mark by etching a part of the first conductive semiconductor layer using the oxide film partially removed in the eleventh step as a mask;
A method for manufacturing a semiconductor device, further comprising: In manufacturing a semiconductor element having a parallel pn junction structure in which an n-type semiconductor region and a p-type semiconductor region are alternately and repeatedly joined on a low resistance layer,
A first step of epitaxially growing a first conductivity type semiconductor layer on a surface of a low-resistance semiconductor substrate;
A second step of forming a first alignment mark by etching a portion of the first conductive type semiconductor layer,
A third step of forming an insulating film having a trench pattern on a surface of the first alignment mark and the first conductive semiconductor layer,
A fourth step of etching the first conductive semiconductor layer using the insulating film as a mask to form a trench deeper than the first alignment mark;
A fifth step of epitaxially growing the second conductivity type semiconductor layer in the trench and on the surface of the insulating film until it becomes higher than the surface of the insulating film;
The insulating film and the insulating film on the insulating film are used as a polishing stopper, and the insulating film remains at a thickness thinner than the thickness at the time of forming the insulating film in the third step at the end of polishing. A sixth step of polishing the second conductivity type semiconductor layer;
A seventh step of removing the insulating film used as a polishing stopper in the sixth step;
An eighth step of oxidizing the semiconductor surface exposed by performing a heat treatment after the seventh step and removing the insulating film in the seventh step;
A ninth step of removing the oxide film formed on the semiconductor surface in the eighth step;
Only including,
Between the eighth step and the ninth step, a part of the oxide film generated on the semiconductor surface in the eighth step is removed, and the second alignment of the first conductivity type semiconductor layer is performed. A tenth step of exposing a mark formation region;
An eleventh step of newly forming a second alignment mark by etching a portion of the first conductive semiconductor layer using the oxide film partially removed in the tenth step as a mask;
A method for manufacturing a semiconductor device, further comprising:

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