CN112086354B - Flattening method of IGBT device - Google Patents
Flattening method of IGBT device Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 238000001514 detection method Methods 0.000 claims abstract description 49
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 49
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000003153 chemical reaction reagent Substances 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention provides a planarization method of an IGBT device, which comprises the steps of firstly removing part of polysilicon through first grinding to expose a first insulating layer, then mainly removing part of the first insulating layer through second grinding to enable the first insulating layer to be flush with the upper surface of the second insulating layer, and then mainly removing polysilicon on the upper surface of the second insulating layer through third grinding to expose the second insulating layer, namely, each grinding process is subjected to targeted grinding, simultaneously, each grinding process is matched with an online endpoint detection method to realize control of each grinding endpoint, the situation of over-polishing and insufficient grinding is avoided, and therefore the first insulating layer and the upper surface of the second insulating layer obtained after planarization are flush, and the accurate control of the uniformity of the surface morphology of a wafer is realized.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a planarization method of an IGBT device.
Background
IGBT (Insulated Gate Bipolar Transistor), also known as insulated gate bipolar transistor, is currently the most representative power electronic device. The IGBT is a composite fully controlled-voltage driven-power semiconductor device composed of a BJT (bipolar junction transistor) and a MOS (insulated gate field effect transistor), and has the characteristic of self-turn-off, so that the IGBT has the advantages of both the BJT device and the MOS device, such as a voltage controlled switch, a high operating frequency, a simple driving control circuit, bipolar conduction, and the like. The IGBT device has a self-turn-off feature that can be seen as a wire when on and as an open circuit when off. The control region of an IGBT device is a gate region, and the electrode attached thereto is referred to as a gate (i.e., gate G). The switching function of the IGBT is to turn on the IGBT by applying a forward gate voltage to form a channel. And otherwise, the reverse gate voltage is applied to eliminate the channel, and the base current is cut off, so that the IGBT is turned off.
In the preparation process of the IGBT device gate electrode, firstly, a silicon nitride layer is formed on the surface of a substrate (1); then removing part of the silicon nitride to expose part of the substrate, forming a first groove (2) on the exposed substrate by photoetching, and performing thermal oxidation on the first groove (2) to form a first insulating layer (4), wherein the thickness of the first insulating layer (4) is higher than the depth of the first groove (2); subsequently removing the remaining silicon nitride to expose another part of the substrate, forming a second groove (3) on the exposed substrate by photoetching, wherein the depth of the second groove (3) is larger than that of the first groove (2), performing thermal oxidation on the second groove (3) to form a second insulating layer (5), wherein the second insulating layer (5) is only positioned at the bottom and the side wall of the first groove (2), and the first insulating layer (4) is communicated with the second insulating layer (5); and finally, depositing a polysilicon layer, and grinding the structure obtained in the steps through a grinding process to planarize the IGBT device. That is, the substance to be ground in this grinding step includes polysilicon and a part of the substance of the insulating layer.
The grinding process is generally performed by chemical mechanical polishing (Chemical Mechanical Planarization, abbreviated as CMP). The basic principle of chemical mechanical polishing is that a workpiece to be polished is rotated relative to a polishing pad under a certain pressure and in the presence of polishing liquid, and the material on the surface of the workpiece is removed by means of mechanical grinding of abrasive particles and corrosion of chemical oxidizing agents, so that a smooth surface is obtained. However, when polishing a wafer by chemical mechanical polishing, the polishing effect is commonly affected by various factors, such as different materials to be polished are suitable for different polishing solutions, polishing head rotation speeds and pressures, etc., so that conventional chemical mechanical polishing is not suitable for removing various materials with a large thickness at the same time in the same polishing process. In the planarization process of the IGBT device, the conventional chemical mechanical polishing causes larger topography difference of the surface of the wafer, and the situation that partial areas are over polished and the partial areas are not sufficiently ground exists, so that the uniformity and the performance of the IGBT device in the wafer are affected.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the defect that the surface of the wafer has larger morphology difference caused by the planarization process of the traditional IGBT device and has adverse effect on the uniformity and performance of the IGBT device in the wafer, thereby providing a planarization method of the IGBT device.
For this purpose, the invention provides a planarization method of an IGBT device, comprising the following steps:
carrying out first grinding on the wafer at a first rotating speed and a first pressure by using a first grinding fluid, wherein the selection ratio of the first grinding fluid to the first insulating layer to the polysilicon layer is (0.9-1): 1, detecting the grinding process through online end point detection, and stopping grinding after the first insulating layer is exposed;
performing second grinding on the wafer at a second rotating speed and a second pressure by using a second grinding liquid, wherein the selection ratio of the second grinding liquid to the first insulating layer to the polysilicon layer is 1 (0-0.02), detecting the grinding process through online end point detection, and stopping grinding after the upper surfaces of the first insulating layer and the second insulating layer are level;
carrying out third grinding on the wafer at a third rotating speed and a third pressure by using a third grinding liquid, wherein the selection ratio of the third grinding liquid to the first insulating layer to the polysilicon layer is (0-0.02): 1, the grinding process is detected by online end point detection, and polysilicon is filled in only the second groove (3) when the grinding is stopped;
wherein the second rotation speed is more than or equal to the first rotation speed and is more than or equal to the third rotation speed, and the second pressure is more than or equal to the third pressure and is more than or equal to the first pressure.
Further, the second rotation speed=first rotation speed > third rotation speed.
Further, the first rotating speed is 70-108 revolutions per minute, and the first pressure is 1-2 Psi;
the second rotating speed is 70-108 revolutions per minute, and the second pressure is 3-4 Psi;
the third rotating speed is 30-60 revolutions per minute, and the third pressure is 2-3 Psi.
Further, in the polishing liquid used for the first polishing, the polishing particles are SiO 2 The PH of the grinding fluid is 3-6;
in the grinding liquid used for the second grinding, the grinding particles are CeO 2 ；
In the polishing liquid used for the third polishing, the polishing particles are polysilicon.
Further, the online end point detection method is one of motor current end point detection, optical end point detection, eddy current end point detection and comprehensive end point detection methods.
Further, the diameter of the wafer is smaller than 200mm.
Further, the first insulating layer is made of silicon dioxide, the second insulating layer is made of silicon dioxide, and the substrate is made of silicon.
The technical scheme of the invention has the following advantages:
according to the planarization method of the IGBT device, part of polysilicon is removed through first grinding to expose the first insulating layer, then part of the first insulating layer is mainly removed through second grinding to enable the first insulating layer to be flush with the upper surface of the second insulating layer, and then polysilicon on the upper surface of the second insulating layer is mainly removed through third grinding to expose the second insulating layer, namely, each grinding process is subjected to targeted grinding, and meanwhile, each grinding process is matched with an online endpoint detection method to control each grinding endpoint, the situation of over-polishing and insufficient grinding is avoided, so that the first insulating layer obtained after planarization treatment is flush with the upper surface of the second insulating layer, and the accurate control of the uniformity of the surface morphology of a wafer is realized;
specifically, the rotation speed, pressure and grinding fluid in each grinding process are adapted to the property and precision of the material to be ground, namely, first grinding is carried out at a relatively moderate rotation speed and a relatively small pressure, polysilicon is mainly removed to expose the first insulating layer, and the selection of the first grinding fluid can avoid overgrinding the local polysilicon layer during global planarization; then the first insulating layer which is difficult to grind and has high thickness and a small amount of polysilicon which is easy to remove are removed by relatively high rotating speed and relatively high pressure and matching with the second grinding liquid, so that the grinding degree is high, and the grinding precision of the polysilicon is more accurate; finally, third grinding is carried out through third grinding liquid so as to achieve the purpose of removing polysilicon on the upper surface of the second insulating layer only, and the grinding end point is convenient to accurately control due to relatively low rotating speed and relatively moderate pressure, so that the first insulating layer obtained after planarization treatment is flush with the upper surface of the second insulating layer, and the grinding precision is high.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of an IGBT device before lapping in an embodiment of the present invention;
fig. 2 is a schematic structural diagram of the IGBT device of fig. 1 after a first polish;
fig. 3 is a schematic structural diagram of the IGBT device of fig. 1 after a second lapping;
fig. 4 is a schematic structural diagram of the IGBT device of fig. 1 after a third lapping;
reference numerals:
1-a substrate; 2-a first trench; 3-a second trench; 4-a first insulating layer; 5-a second insulating layer; 6-polysilicon layer.
Detailed Description
The following examples are provided for a better understanding of the present invention and are not limited to the preferred embodiments described herein, but are not intended to limit the scope of the invention, any product which is the same or similar to the present invention, whether in light of the present teachings or in combination with other prior art features, falls within the scope of the present invention.
The specific experimental procedures or conditions are not noted in the examples and may be followed by the operations or conditions of conventional experimental procedures described in the literature in this field. The reagents or apparatus used were conventional reagent products commercially available without the manufacturer's knowledge.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "upper", "lower", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Example 1
The embodiment provides a planarization method for an IGBT device, where before performing planarization processing on a gate of the IGBT device, a structure of the gate of the IGBT device is as shown in fig. 1: the substrate 1 comprises a first groove 2 and a plurality of second grooves 3, the depth of the second grooves 3 is larger than that of the first grooves 2, a first insulating layer 4 is formed in the first grooves 2, the thickness of the first insulating layer 4 is higher than that of the first grooves 2, second insulating layers 5 are formed on the bottom and the side walls of the first grooves 2, and the first insulating layer 4 is communicated with the second insulating layers 5; a polysilicon layer 6 is formed on the first insulating layer 4 and the second insulating layer 5, the polysilicon layer 6 on the second insulating layer 5 extends to the outlet of the second trench 3, the materials of the first insulating layer 4 and the second insulating layer 5 are silicon dioxide, and the material of the substrate 1 is silicon. The planarization method of the IGBT device provided by the embodiment adopts a chemical mechanical polishing method, and comprises the following steps:
firstly, placing a wafer on a first polishing disk and fixing the wafer under a polishing head, enabling a surface to be polished to face the polishing pad, then rotating the polishing head relative to the polishing pad at a first rotating speed to conduct first polishing, applying first pressure on the wafer in the polishing process, and introducing first polishing liquid, wherein the selection ratio of the first polishing liquid to the first insulating layer 4 to the polysilicon layer 6 is (0.9-1): 1, detecting the grinding process through online end point detection until the first insulating layer 4 is exposed, and stopping grinding to obtain a structure shown in fig. 2; specifically, the first rotation speed is 108 revolutions per minute, the first pressure is 1Psi, the PH of the first grinding fluid is 3, and the grinding particles are SiO 2 ；
Secondly, placing the wafer on a second polishing disk and fixing the wafer under a polishing head, enabling the surface to be polished to face the polishing pad, then rotating the polishing head relative to the polishing pad at a second rotating speed to conduct second polishing, applying second pressure to the wafer in the polishing process, and introducing second polishing liquid, wherein the selection ratio of the second polishing liquid to the first insulating layer 4 to the polysilicon layer 6 is 1 (0-0.02), detecting the polishing process through online end point detection, and stopping polishing after the upper surfaces of the first insulating layer 4 and the second insulating layer 5 are flush, so that the structure shown in fig. 3 is obtained; specifically, the second rotation speed is 108 revolutions per minute, the second pressure is 3Psi, and the grinding particles in the second grinding fluid are CeO 2 ；
Finally, placing the wafer on a third polishing disk and fixing the wafer under a polishing head, enabling the surface to be polished to face the polishing pad, then rotating the polishing head relative to the polishing pad at a third rotating speed to conduct third polishing, applying third pressure on the wafer in the polishing process, and introducing third polishing liquid, wherein the selection ratio of the third polishing liquid to the first insulating layer 4 and the polysilicon layer 6 is (0-0.02): 1, detecting the polishing process through online end point detection, and filling polysilicon into only the second groove 3 when the polishing is stopped, so as to obtain the structure shown in fig. 4; specifically, the third rotation speed is 60 revolutions per minute, the third pressure is 2Psi, and the grinding particles in the third grinding liquid are polysilicon.
It should be understood that the above-mentioned on-line endpoint detection method is one of motor current endpoint detection, optical endpoint detection, eddy current endpoint detection, and comprehensive endpoint detection, and those skilled in the art can select according to needs, which are not specifically limited herein; in addition, the online end point detection method is suitable for wafer wafers with diameters smaller than 200mm, so that the planarization method of the IGBT device is also suitable for wafer wafers with diameters smaller than 200mm.
It should be understood that, due to the difference in pattern density of the chip design, the morphology and thickness of the different positions after the material is filled are different, so that the polishing rate of the different positions in the polishing process is different. The selection ratio is the ratio of the grinding rates of two different substances, so that the selection ratio given in the application is not an accurate numerical value, but a numerical range, and the difference of the grinding rates of different positions of the same grinding liquid in the grinding process is expressed strictly; furthermore, the purpose of the first polishing is to remove polysilicon over all regions of silicon dioxide on the wafer, the difference in polishing rates at different locations results in some regions of polysilicon being removed earlier and some regions being removed later, resulting in some regions being overpolished, using a selectivity of (0.9-1): 1, the difference of the flat grinding rates can be coordinated, so that a larger height difference between different materials in the overgrinding area is avoided.
Example 2
The embodiment provides a planarization method for an IGBT device, where before performing planarization processing on a gate of the IGBT device, a structure of the gate of the IGBT device is as shown in fig. 1: the substrate 1 comprises a first groove 2 and a plurality of second grooves 3, the depth of the second grooves 3 is larger than that of the first grooves 2, a first insulating layer 4 is formed in the first grooves 2, the thickness of the first insulating layer 4 is higher than that of the first grooves 2, second insulating layers 5 are formed on the bottom and the side walls of the first grooves 2, and the first insulating layer 4 is communicated with the second insulating layers 5; a polysilicon layer 6 is formed on the first insulating layer 4 and the second insulating layer 5, the polysilicon layer 6 on the second insulating layer 5 extends to the outlet of the second trench 3, the materials of the first insulating layer 4 and the second insulating layer 5 are silicon dioxide, and the material of the substrate 1 is silicon. The planarization method of the IGBT device provided by the embodiment adopts a chemical mechanical polishing method, and comprises the following steps:
firstly, placing a wafer on a first polishing disk and fixing the wafer under a polishing head, enabling a surface to be polished to face the polishing pad, then rotating the polishing head relative to the polishing pad at a first rotating speed to conduct first polishing, applying first pressure on the wafer in the polishing process, and introducing first polishing liquid, wherein the selection ratio of the first polishing liquid to the first insulating layer 4 to the polysilicon layer 6 is (0.9-1): 1, detecting the grinding process through online end point detection until the first insulating layer 4 is exposed, and stopping grinding to obtain a structure shown in fig. 2; specifically, the first rotation speed is 70 rpm, the first pressure is 2Psi, the PH of the first grinding fluid is 6, and the grinding particles are SiO 2 ；
Secondly, placing the wafer on a second polishing disk and fixing the wafer under a polishing head, enabling the surface to be polished to face the polishing pad, then rotating the polishing head relative to the polishing pad at a second rotating speed to conduct second polishing, applying second pressure to the wafer in the polishing process, and introducing second polishing liquid, wherein the selection ratio of the second polishing liquid to the first insulating layer 4 to the polysilicon layer 6 is 1 (0-0.02), detecting the polishing process through online end point detection, and stopping polishing after the upper surfaces of the first insulating layer 4 and the second insulating layer 5 are flush, so that the structure shown in fig. 3 is obtained; specifically, the second rotation speed is 70 revolutions per minute, the second pressure is 4Psi, and the grinding particles in the second grinding fluid are CeO 2 ；
Finally, placing the wafer on a third polishing disk and fixing the wafer under a polishing head, enabling the surface to be polished to face the polishing pad, then rotating the polishing head relative to the polishing pad at a third rotating speed to conduct third polishing, applying third pressure on the wafer in the polishing process, and introducing third polishing liquid, wherein the selection ratio of the third polishing liquid to the first insulating layer 4 and the polysilicon layer 6 is (0-0.02): 1, detecting the polishing process through online end point detection, and filling polysilicon into only the second groove 3 when the polishing is stopped, so as to obtain the structure shown in fig. 4; specifically, the third rotation speed is 30 revolutions per minute, the third pressure is 3Psi, and the grinding particles in the third grinding fluid are polysilicon.
It should be understood that the above-mentioned on-line endpoint detection method is one of motor current endpoint detection, optical endpoint detection, eddy current endpoint detection, and comprehensive endpoint detection, and those skilled in the art can select according to needs, which are not specifically limited herein; in addition, the online end point detection method is suitable for wafer wafers with diameters smaller than 200mm, so that the planarization method of the IGBT device is also suitable for wafer wafers with diameters smaller than 200mm.
It should be understood that, due to the difference in pattern density of the chip design, the morphology and thickness of the different positions after the material is filled are different, so that the polishing rate of the different positions in the polishing process is different. The selection ratio is the ratio of the grinding rates of two different substances, so that the selection ratio given in the application is not an accurate numerical value, but a numerical range, and the difference of the grinding rates of different positions of the same grinding liquid in the grinding process is expressed strictly; furthermore, the purpose of the first polishing is to remove polysilicon over all regions of silicon dioxide on the wafer, the difference in polishing rates at different locations results in some regions of polysilicon being removed earlier and some regions being removed later, resulting in some regions being overpolished, using a selectivity of (0.9-1): 1, the difference of the flat grinding rates can be coordinated, so that a larger height difference between different materials in the overgrinding area is avoided.
Example 3
The embodiment provides a planarization method for an IGBT device, where before performing planarization processing on a gate of the IGBT device, a structure of the gate of the IGBT device is as shown in fig. 1: the substrate 1 comprises a first groove 2 and a plurality of second grooves 3, the depth of the second grooves 3 is larger than that of the first grooves 2, a first insulating layer 4 is formed in the first grooves 2, the thickness of the first insulating layer 4 is higher than that of the first grooves 2, second insulating layers 5 are formed on the bottom and the side walls of the first grooves 2, and the first insulating layer 4 is communicated with the second insulating layers 5; a polysilicon layer 6 is formed on the first insulating layer 4 and the second insulating layer 5, the polysilicon layer 6 on the second insulating layer 5 extends to the outlet of the second trench 3, the materials of the first insulating layer 4 and the second insulating layer 5 are silicon dioxide, and the material of the substrate 1 is silicon. The planarization method of the IGBT device provided by the embodiment adopts a chemical mechanical polishing method, and comprises the following steps:
firstly, placing a wafer on a first polishing disk and fixing the wafer under a polishing head, enabling a surface to be polished to face the polishing pad, then rotating the polishing head relative to the polishing pad at a first rotating speed to conduct first polishing, applying first pressure on the wafer in the polishing process, and introducing first polishing liquid, wherein the selection ratio of the first polishing liquid to the first insulating layer 4 to the polysilicon layer 6 is (0.9-1): 1, detecting the grinding process through online end point detection until the first insulating layer 4 is exposed, and stopping grinding to obtain a structure shown in fig. 2; specifically, the first rotation speed is 80 revolutions per minute, the first pressure is 1.5Psi, the PH of the first grinding fluid is 5, and the grinding particles are SiO 2 ；
Secondly, placing the wafer on a second polishing disk and fixing the wafer under a polishing head, enabling the surface to be polished to face the polishing pad, then rotating the polishing head relative to the polishing pad at a second rotating speed to conduct second polishing, applying second pressure to the wafer in the polishing process, and introducing second polishing liquid, wherein the selection ratio of the second polishing liquid to the first insulating layer 4 to the polysilicon layer 6 is 1 (0-0.02), detecting the polishing process through online end point detection, and stopping polishing after the upper surfaces of the first insulating layer 4 and the second insulating layer 5 are flush, so that the structure shown in fig. 3 is obtained; specifically, the second rotation speed is 90 rpm, and the second pressure is3.5Psi, the grinding particles in the second grinding liquid are CeO 2 ；
Finally, placing the wafer on a third polishing disk and fixing the wafer under a polishing head, enabling the surface to be polished to face the polishing pad, then rotating the polishing head relative to the polishing pad at a third rotating speed to conduct third polishing, applying third pressure on the wafer in the polishing process, and introducing third polishing liquid, wherein the selection ratio of the third polishing liquid to the first insulating layer 4 and the polysilicon layer 6 is (0-0.02): 1, detecting the polishing process through online end point detection, and filling polysilicon into only the second groove 3 when the polishing is stopped, so as to obtain the structure shown in fig. 4; specifically, the third rotation speed is 45 revolutions per minute, the third pressure is 2.5Psi, and the grinding particles in the third grinding liquid are polysilicon.
It should be understood that the above-mentioned on-line endpoint detection method is one of motor current endpoint detection, optical endpoint detection, eddy current endpoint detection, and comprehensive endpoint detection, and those skilled in the art can select according to needs, which are not specifically limited herein; in addition, the online end point detection method is suitable for wafer wafers with diameters smaller than 200mm, so that the planarization method of the IGBT device is also suitable for wafer wafers with diameters smaller than 200mm.
It should be understood that, due to the difference in pattern density of the chip design, the morphology and thickness of the different positions after the material is filled are different, so that the polishing rate of the different positions in the polishing process is different. The selection ratio is the ratio of the grinding rates of two different substances, so that the selection ratio given in the application is not an accurate numerical value, but a numerical range, and the difference of the grinding rates of different positions of the same grinding liquid in the grinding process is expressed strictly; furthermore, the purpose of the first polishing is to remove polysilicon over all regions of silicon dioxide on the wafer, the difference in polishing rates at different locations results in some regions of polysilicon being removed earlier and some regions being removed later, resulting in some regions being overpolished, using a selectivity of (0.9-1): 1, the difference of the flat grinding rates can be coordinated, so that a larger height difference between different materials in the overgrinding area is avoided.
Comparative example 1
The present comparative example provides a planarization method of an IGBT device, which differs from the planarization method of an IGBT device provided in embodiment 1 only in that: only the first grinding was performed and no in-line endpoint detection was coordinated.
Comparative example 2
The present comparative example provides a planarization method of an IGBT device, which differs from the planarization method of an IGBT device provided in embodiment 1 only in that: only the second grinding was performed and no in-line endpoint detection was coordinated.
Comparative example 3
The present comparative example provides a planarization method of an IGBT device, which differs from the planarization method of an IGBT device provided in embodiment 1 only in that: only the third grinding was performed and no in-line endpoint detection was coordinated.
Comparative example 4
The present comparative example provides a planarization method of an IGBT device, which differs from the planarization method of an IGBT device provided in embodiment 1 only in that: does not coordinate on-line endpoint detection.
Test examples
The wafers obtained in examples 1 to 3 and comparative examples 1 to 4 were subjected to uniformity test by a thickness test method using an F5X machine of KLA company. Taking 9 points positioned at the edge, the center and the middle area of the wafer, measuring the thickness value of the wafer, and differencing the maximum value and the minimum value of the thickness value to obtain the uniform value to reflect the uniformity, wherein the smaller the uniform value is, the higher the flatness of each area in the wafer is, and the smaller the morphology difference is. The results are shown in Table 1.
TABLE 1
| Index (I) | Homogeneous value (A) |
| Example 1 | 143 |
| Example 2 | 151 |
| Example 3 | 157 |
| Comparative example 1 | 176 |
| Comparative example 2 | 171 |
| Comparative example 3 | 169 |
| Comparative example 4 | 172 |
As is clear from Table 1, examples 1 to 3 produced wafer crystals excellent in uniformity by three polishing and limiting the rotation speed, pressure and polishing liquid of polishing.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (7)
1. A planarization method of an IGBT device is characterized by comprising the following steps:
carrying out first grinding on the wafer at a first rotating speed and a first pressure by using a first grinding fluid, wherein the selection ratio of the first grinding fluid to the first insulating layer (4) to the polysilicon layer (6) is (0.9-1): 1, detecting the grinding process through online end point detection until the first insulating layer (4) is exposed, and stopping grinding;
carrying out second grinding on the wafer at a second rotating speed and a second pressure by using a second grinding liquid, wherein the selection ratio of the second grinding liquid to the first insulating layer (4) to the polysilicon layer (6) is 1 (0-0.02), detecting the grinding process through online end point detection, and stopping grinding after the upper surfaces of the first insulating layer (4) and the second insulating layer (5) are level;
carrying out third grinding on the wafer at a third rotating speed and a third pressure by using a third grinding liquid, wherein the selection ratio of the third grinding liquid to the first insulating layer (4) to the polysilicon layer (6) is (0-0.02): 1, the grinding process is detected by online end point detection, and polysilicon is filled in only the second groove (3) when the grinding is stopped;
wherein the second rotation speed is more than or equal to the first rotation speed and is more than or equal to the third rotation speed, and the second pressure is more than or equal to the third pressure and is more than or equal to the first pressure.
2. The method of planarizing an IGBT device according to claim 1, characterized in that the second rotation speed = first rotation speed > third rotation speed.
3. The method for planarizing an IGBT device according to claim 1 or 2, characterized in that,
the first rotating speed is 70-108 revolutions per minute, and the first pressure is 1-2 Psi;
the second rotating speed is 70-108 revolutions per minute, and the second pressure is 3-4 Psi;
the third rotating speed is 30-60 revolutions per minute, and the third pressure is 2-3 Psi.
4. A planarization method of an IGBT device as claimed in any one of claims 1-3, wherein,
in the first grinding liquid, the grinding particles are SiO 2 The PH of the grinding fluid is 3-6;
the second grindingIn the grinding liquid, the grinding particles are CeO 2 ；
In the third grinding liquid, the grinding particles are polysilicon.
5. The method of planarizing an IGBT device of any of claims 1-4 wherein the in-line endpoint detection method is one of a motor current endpoint detection, an optical endpoint detection, an eddy current endpoint detection, a comprehensive endpoint detection method.
6. The method for planarizing the IGBT device according to any one of claims 1 to 5, characterized in that the diameter of the wafer is 200mm or less.
7. The method for planarizing an IGBT device according to any of claims 1 to 6, characterized in that the material of the first insulating layer (4) is silicon dioxide and the material of the second insulating layer (5) is silicon dioxide.
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|---|---|---|---|---|
| JP2002231662A (en) * | 2001-01-22 | 2002-08-16 | Promos Technol Inc | Method for chemical and mechanical planarization |
| JP2007129115A (en) * | 2005-11-07 | 2007-05-24 | Fuji Electric Holdings Co Ltd | Manufacturing method for semiconductor device |
| CN102339741A (en) * | 2010-07-22 | 2012-02-01 | 中芯国际集成电路制造(上海)有限公司 | Groove structure filled with metal and forming method thereof, and chemical mechanical polishing method |
| CN106558529A (en) * | 2015-09-30 | 2017-04-05 | 无锡华润微电子有限公司 | Shallow trench isolation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002231662A (en) * | 2001-01-22 | 2002-08-16 | Promos Technol Inc | Method for chemical and mechanical planarization |
| JP2007129115A (en) * | 2005-11-07 | 2007-05-24 | Fuji Electric Holdings Co Ltd | Manufacturing method for semiconductor device |
| CN102339741A (en) * | 2010-07-22 | 2012-02-01 | 中芯国际集成电路制造(上海)有限公司 | Groove structure filled with metal and forming method thereof, and chemical mechanical polishing method |
| CN106558529A (en) * | 2015-09-30 | 2017-04-05 | 无锡华润微电子有限公司 | Shallow trench isolation method |
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