JP2005072191A - Method for manufacturing semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To terminate polish of a surface of the substrate in the amount of appropriate polishing by forming a polish stopper film used as a target of polish end when a trench is formed on a semiconductor substrate, epitaxial growth of semiconductor is performed in the trench, and parallel pn junction structure is formed. <P>SOLUTION: A target trench 14 is formed in the n-type semiconductor substrate 11 and filled with an HTO oxide film 15. The HTO oxide film 15 is subjected to etch back and left only on a bottom of the target trench 14. A trench 17 for super junction which is used for forming the parallel pn junction structure is formed on the semiconductor substrate 11, epitaxial growth of p-type semiconductor is performed to the trench 17, and a p-type semiconductor region 18 is formed. The surface of the semiconductor substrate 11 is polished. Polishing is stopped when the HTO oxide film 15 positioned on the bottom of the target trench 14 appears to the polishing surface, and the surface of the substrate is planarized. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor substrate, and in particular, an n-type semiconductor region and a p-type semiconductor region are alternately formed by epitaxially growing a second conductivity type semiconductor in a trench formed in the first conductivity type semiconductor substrate. The present invention relates to a method for manufacturing a semiconductor substrate having a parallel pn junction structure that is repeatedly bonded to each other.

In general, semiconductor elements are classified into a horizontal element having electrodes formed on one side and a vertical element having electrodes on both sides. In the vertical semiconductor element, the direction in which the drift current flows in the on state is the same as the direction in which the depletion layer due to the reverse bias voltage extends in the off state. In a normal planar type n-channel vertical MOSFET (insulated gate field effect transistor), the high-resistance n ⁻ drift layer portion functions as a region in which a drift current flows in the vertical direction when in the ON state. Therefore, if the current path of the n ⁻ drift layer is shortened, the drift resistance is lowered, so that the effect of reducing the substantial on-resistance of the MOSFET can be obtained.

On the other hand, the portion of the high resistance n ⁻ drift layer is depleted in the off state to increase the breakdown voltage. Therefore, when the n ⁻ drift layer is thinned, the width of the drain-base depletion layer proceeding from the pn junction between the P base region and the drift region is narrowed, and the critical electric field strength of silicon is reached quickly. It will decline. On the other hand, in a semiconductor device with a high breakdown voltage, since the n ⁻ drift layer is thick, the on-resistance increases and the loss increases. Thus, there is a trade-off relationship between on-resistance and breakdown voltage.

  This trade-off relationship is also known to hold in semiconductor devices such as IGBTs (insulated gate bipolar transistors), bipolar transistors, and diodes. This trade-off relationship is also common to lateral semiconductor elements in which the direction in which the drift current flows in the on state and the direction in which the depletion layer extends in the off state are different.

  As a solution to the above-described problem due to the trade-off relationship, a superjunction semiconductor element having a parallel pn structure in which a drift layer is formed by alternately and repeatedly joining n-type drift regions and p-type partition regions having a high impurity concentration is known. It is. In the semiconductor element having such a structure, even when the impurity concentration of the parallel pn structure is high, the depletion layer extends laterally from each pn junction extending in the vertical direction of the parallel pn structure in the off state, and the entire drift region Therefore, a high breakdown voltage can be achieved.

  In manufacturing the super junction semiconductor element, the semiconductor substrate having the parallel pn junction structure described above is used. As a method for mass-producing such a semiconductor substrate at a low cost and at a high yield rate, a method is known in which a trench is formed in an n-type semiconductor substrate and the inside of the trench is filled with an epitaxial growth layer made of a p-type semiconductor. In this method, as shown in FIG. 16, when the epitaxial growth of the p-type semiconductor 2 is completed, a step of 1 to several μm, an oxide film 3 and polysilicon 4 remain on the surface of the semiconductor substrate 1, so that the substrate surface is polished. Then, it is necessary to remove the oxide film 3 and the polysilicon 4 and planarize it.

  Meanwhile, a trench (hereinafter referred to as a target trench) is formed as a mask alignment target in forming a semiconductor element such as a MOSFET in a semiconductor substrate used for manufacturing a superjunction semiconductor element. Usually, since the depth of the target trench is 1 μm or less, if the above-described planarization process is performed on a semiconductor substrate having a conventional parallel pn junction structure, the target trench disappears due to polishing. As a result, when forming a MOSFET or the like on the substrate surface, there is a problem that it is difficult to match the pattern of the MOSFET and the pattern of the parallel pn junction structure.

  In order to prevent the target trench from disappearing by the planarization polishing, it is conceivable to form a target trench deeper than the thickness of the surface layer removed by the polishing. However, in this case, there is a problem that resist unevenness and resist residue due to the target pattern are likely to occur in the photolithography process.

  In addition, when forming a trench for forming a parallel pn junction structure, that is, an original trench and a target trench at the same time, before the epitaxial growth is performed, in order to prevent the target trench from being buried by the epitaxial growth layer, It is necessary to coat the inner wall with an oxide film. For this purpose, once the inner walls of both the original trench and the target trench are covered with an oxide film, the oxide film in the original trench may be selectively removed. However, in this case, there is a problem that the resist unevenness and the resist residue are likely to occur because the number of photolithography processes increases.

  As measures against the above problems, the present inventors formed a target trench deeper than the substrate surface portion to be removed by polishing during the planarization process, and finished polishing when the substrate surface was removed by a predetermined thickness. Thus, a method of leaving a target trench on the polished substrate surface was proposed (Japanese Patent Application No. 2002-221778). However, after that, when mass production of semiconductor substrates is performed by this method, it has been found that there are the following problems, which cause a decrease in yield and process throughput.

  That is, when forming a target by applying this method, there is no target for finishing the polishing, so an optimum polishing time is obtained in advance by a preliminary experiment or the like, and polishing is performed only for that time. Become. Therefore, it has been found that when the amount of slurry supplied and the temperature of the polishing pad deviate from the conditions of the preliminary experiment or the like during polishing, the polishing amount is not constant and the depth of the target trench remaining after polishing varies.

  Actually, the target trench was formed and polished using 500 semiconductor substrates by the method according to the prior application. As a result, since the polishing amount was too large for 27 substrates, the target disappeared and could not be regenerated. Further, in another 59 substrates, the depth of the target trench was 1.5 μm or more, and additional polishing was necessary. Further, in another 55 substrates, the depth of the target trench is 1 to 1.5 μm, which is inappropriate for automatic mask alignment. Matching has to be done, and the process capacity is greatly reduced.

  In order to solve the above-mentioned problems, the present invention makes it possible to finish polishing with an appropriate polishing amount by forming a polishing stopper film that is a target for polishing completion, and thereby a semiconductor substrate having high process throughput An object of the present invention is to provide a method of manufacturing a semiconductor substrate that can be manufactured at a high yield.

  In order to solve the above-described problems and achieve the object, a semiconductor substrate manufacturing method according to the invention of claim 1 is a parallel pn junction structure in which n-type semiconductor regions and p-type semiconductor regions are alternately and repeatedly joined. Forming a first trench serving as a mask alignment target in a first conductivity type semiconductor substrate, filling the first trench with an insulating film, and the insulating film Leaving the insulating film only at the bottom of the first trench, forming a second trench deeper than the first trench in the semiconductor substrate, and in the second trench And a step of epitaxially growing a second conductivity type semiconductor.

  According to the first aspect of the present invention, the insulating film remains as a polishing stopper film in the first trench. Moreover, since the target is made of an insulating film made of a material different from that of the semiconductor substrate, the target can be easily recognized by the stepper.

  According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor substrate according to the first aspect, wherein after the epitaxial growth of the second conductivity type semiconductor, the surface of the semiconductor substrate is polished to form the first trench. The method further includes the step of planarizing the substrate surface by stopping polishing when the insulating film at the bottom appears on the polishing surface.

  According to the second aspect of the invention, by adjusting the thickness of the insulating film remaining as the polishing stopper film in the first trench, the polishing can be completed with an appropriate polishing amount.

  According to a third aspect of the present invention, there is provided the method for manufacturing a semiconductor substrate according to the first or second aspect, wherein the thickness of the insulating film is ½ or more of the opening width of the first trench. It is characterized by that.

  According to the third aspect of the present invention, the first trench can be completely filled with the insulating film by depositing the insulating film with a thickness of ½ or more of the opening width of the first trench.

  In order to solve the above-described problems and achieve the object, a semiconductor substrate manufacturing method according to the invention of claim 4 is a parallel pn having a configuration in which n-type semiconductor regions and p-type semiconductor regions are alternately and repeatedly joined. In manufacturing a semiconductor substrate having a junction structure, a step of forming a first trench serving as a first target for mask alignment in a semiconductor substrate of a first conductivity type, and a step of forming a first trench in the semiconductor substrate than the first trench. A step of forming a deep second trench; a step of epitaxially growing a second conductivity type semiconductor in the second trench; and a second target for mask alignment on the semiconductor substrate, from the first trench. Forming a third trench that is deeper and shallower than the second trench, filling the third trench with an insulating film, and etching the insulating film. Ring to characterized in that it comprises a a step of leaving the insulating film only on the bottom of the third trench.

  According to the invention of claim 4, the insulating film remains as a polishing stopper film in the third trench. Moreover, since the target is made of an insulating film made of a material different from that of the semiconductor substrate, the target can be easily recognized by the stepper.

  According to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor substrate according to the fourth aspect of the invention, wherein after the insulating film is etched, the surface of the semiconductor substrate is polished and located at the bottom of the third trench. The method further includes a step of planarizing the substrate surface by stopping polishing when the insulating film appears on the polished surface.

  According to the fifth aspect of the present invention, the polishing can be completed with an appropriate polishing amount by adjusting the thickness of the insulating film remaining as the polishing stopper film in the third trench.

  According to a sixth aspect of the present invention, in the semiconductor substrate manufacturing method according to the fourth or fifth aspect, the thickness of the insulating film is ½ or more of the opening width of the third trench. It is characterized by that.

  According to the sixth aspect of the present invention, the third trench can be completely filled with the insulating film by depositing the insulating film with a thickness of ½ or more of the opening width of the third trench.

  According to a seventh aspect of the present invention, in the semiconductor substrate manufacturing method according to the fifth aspect, the first trench is eliminated by surface polishing of the semiconductor substrate.

  According to the seventh aspect of the present invention, even if the first trench disappears, the insulating film in the third trench remains as a mask alignment target. You can make adjustments.

  According to the semiconductor substrate manufacturing method of the present invention, since the insulating film remains as a polishing stopper film in the target trench, the polishing can be completed with an appropriate polishing amount. Therefore, it is possible to prevent the yield and the process throughput from being lowered due to the variation of the process. Further, since the target is made of a material different from that of the semiconductor substrate, the target can be easily recognized as compared with the conventional technique in which the stepper recognizes the target using a step on the substrate surface. Therefore, there is an effect that a semiconductor substrate having a high process throughput can be manufactured with a high yield.

  Exemplary embodiments of a method for producing a semiconductor substrate according to the present invention will be explained below in detail with reference to the accompanying drawings.

Embodiment 1 FIG.
1 to 7 are longitudinal sectional views schematically showing a semiconductor substrate being manufactured according to the first embodiment of the present invention. First, as shown in FIG. 1, a low-resistance n-type silicon semiconductor substrate 11 is prepared, and an oxide film 12 for trench etching is formed on the surface thereof. The mask is not limited to the oxide film, but may be an insulating film such as a nitride film. Then, as shown in FIG. 2, a part of the oxide film 12 is removed by a photolithography technique using a mask (not shown), and the target trench formation region 13 of the semiconductor substrate 11 is exposed.

  Next, as shown in FIG. 3, anisotropic etching such as plasma etching, RIE (reactive ion etching) or anisotropic wet etching is performed using the patterned oxide film 12 as a mask, and the target trench which is the first trench is formed. 14 is formed. The depth of the target trench 14 is not particularly limited. For example, the depth may be about 1 μm deeper than the thickness (that is, the polishing amount) of the substrate surface portion to be removed by polishing in the subsequent planarization process. Then, an HTO oxide film 15 that is an insulating film is deposited on the surface of the oxide film 12 and in the target trench 14 so as to have a thickness that is half or more of the opening width of the target trench 14. Completely fill with.

  Next, as shown in FIG. 4, the HTO oxide film 15 is etched back using an oxide film etcher or the like. If the HTO oxide film 15 and the oxide film 12 on the substrate surface disappear and the semiconductor substrate 11 is exposed during the etch back process, the plasma emission that is constantly monitored changes. By detecting this change, it can be known that the oxide films 12 and 15 on the surface of the semiconductor substrate 11 have disappeared.

  The HTO oxide film 15 remaining in the target trench 14 is removed by over-etching for a predetermined time from when the plasma emission changes, that is, when the oxide films 12 and 15 on the substrate surface disappear. Only the HTO oxide film 15 is left with a thickness of about 1 μm. As described above, this over-etching process is controlled by time management. However, the etching amount is controlled by the passage of time from the time when the oxide films 12 and 15 on the surface of the substrate are eliminated. Can do.

  Next, as shown in FIG. 5, an oxide film (which may be an insulating film such as a nitride film) 16 is formed again on the surface of the semiconductor substrate 11 and in the target trench 14. Next, using a mask (not shown) in FIG. 5, a part of the oxide film 16 is removed by a photolithography technique to expose a formation region of a superjunction trench for forming a parallel pn junction structure of the semiconductor substrate 11. . Then, anisotropic etching such as plasma etching, RIE, or anisotropic wet etching is performed to form a superjunction trench 17 that is a second trench.

  Next, as shown in FIG. 6, the p-type semiconductor is epitaxially grown by a low pressure epitaxial method or the like, and the superjunction trench 17 is filled with the p-type semiconductor to form a p-type semiconductor region 18. At this time, since the reduced pressure epitaxial method is used, the epitaxial film does not grow on the oxide film 16. Next, the oxide film 16 is removed by wet etching to expose the surface of the semiconductor substrate 11.

  At that time, since the oxide film has a two-layer structure of the HTO oxide film 15 and the oxide film 16 in the target trench 14, the total thickness of the oxide film in the target trench 14 is the same as that of the HTO oxide film 15 and the oxide film 16. The combined thickness is thicker than the oxide film 16 covering the surface of the semiconductor substrate 11. Therefore, if the etching is stopped when the surface of the semiconductor substrate 11 is exposed during wet etching, that is, when the oxide film 16 on the substrate surface disappears, the oxide film 15 or a part of the HTO oxide film 15 and the oxide film 16 is removed. Remains at the bottom of the target trench 14.

  Next, as shown in FIG. 7, the substrate surface is polished and planarized by, for example, a CMP (chemical mechanical polishing) method. In general, polishing of a silicon semiconductor substrate by a CMP method uses a slurry made of an organic alkali or the like to perform polishing mainly by a chemical action, so that the selection ratio between silicon and an oxide film is high and the oxide film is hardly polished. Using this characteristic, as shown in FIG. 7, the polishing is stopped when the HTO oxide film 15 in the target trench 14 appears on the polishing surface. In this way, the polishing during the planarization process can be stopped at any position simply by adjusting the thickness of the oxide film 15 remaining at the bottom in the target trench 14.

  As described above, according to the first embodiment, since the HTO oxide film 15 is left as a polishing stopper film in the target trench 14, the polishing can be finished with an arbitrary polishing amount. It is possible to prevent a decrease in yield and process capability due to variations in depth. Further, since the target is made of the HTO oxide film 15 instead of silicon, the target can be easily recognized as compared with the conventional technique in which the target is recognized using the step on the substrate surface by the stepper. Therefore, it is possible to manufacture a semiconductor substrate having a high process throughput with a high yield.

  In order to verify this, the present inventors actually applied 500 semiconductor substrates that were processed so that the HTO oxide film 15 having a thickness of 1 μm remained in the target trench 14 in accordance with the first embodiment described above. Prepared and performed mask matching as in the prior art. As a result, it was possible to automatically perform mask alignment for all 500 semiconductor substrates. Further, when the cross section of the target was observed with 50 SEMs using a scanning electron microscope (SEM), the thickness of the HTO oxide film 15 (and the oxide film 16) remaining in the target trench 14 was 0.83 to 1.12 μm. It was confirmed that polishing was stopped within this range.

  In the first embodiment described above, the epitaxial growth is performed under the condition that the epitaxial growth film is not deposited on the oxide film 16 by using the low pressure epitaxial growth method. However, the epitaxial growth is performed under the condition that the epitaxial growth film is deposited on the oxide film 16. Also good. Even in such a case, since the polishing is stopped when the oxide film 15 in the target trench 14 is exposed during the planarization process, the same effect can be obtained.

Embodiment 2. FIG.
8 to 15 are longitudinal sectional views showing an outline of a semiconductor substrate being manufactured according to the second embodiment of the present invention. First, as shown in FIG. 8, a low-resistance n-type silicon semiconductor substrate 21 is prepared, and an oxide film for trench etching (an insulating film such as a nitride film) (not shown) is formed on the surface thereof. Then, by using a mask (not shown), a part of the oxide film on the substrate surface is removed by photolithography technique, and the first target trench formation region of the semiconductor substrate 21 is exposed. Next, anisotropic etching such as plasma etching, RIE, or anisotropic wet etching is performed using the patterned oxide film as a mask to form a first target trench 22 that is a first trench, and an oxide film on the substrate surface is formed. Remove.

  Next, as shown in FIG. 9, an oxide film (or an insulating film such as a nitride film) 23 is formed on the surface of the semiconductor substrate 21 and in the first target trench 22. Then, using a mask (not shown), a part of the oxide film 23 is removed by a photolithography technique, and a formation region of a superjunction trench for forming a parallel pn junction structure of the semiconductor substrate 21 is exposed. Next, anisotropic etching such as plasma etching, RIE, or anisotropic wet etching is performed using the oxide film 23 as a mask to form a superjunction trench 24 as a second trench. Thereafter, the p-type semiconductor is epitaxially grown, and the superjunction trench 24 is filled with the p-type semiconductor to form the p-type semiconductor region 25.

  Next, as shown in FIG. 10, after removing the oxide film 23, an oxide film (which may be an insulating film such as a nitride film) 26 is formed again on the surface of the semiconductor substrate 21 and in the first target trench 22. Then, as shown in FIG. 11, a part of the oxide film 26 is removed by a photolithography technique using a mask (not shown), and the second target trench formation region 27 of the semiconductor substrate 21 is exposed.

  Then, as shown in FIG. 12, anisotropic etching such as plasma etching, RIE, or anisotropic wet etching is performed using the patterned oxide film 26 as a mask to form a second target trench 28 that is a third trench. To do. The depth of the second target trench 28 is not particularly limited. For example, the depth may be about 1 μm deeper than the thickness (that is, the polishing amount) of the substrate surface portion to be removed by polishing during the subsequent planarization process.

  Next, as shown in FIG. 13, after removing the oxide film 26, an oxide film (an insulating film such as a nitride film) is again formed on the surface of the semiconductor substrate 21, the first target trench 22, and the second target trench 28. 29) is deposited so as to have a thickness more than half of the opening width of the second target trench 28, and the second target trench 28 is completely filled with the oxide film 29. Note that an oxide film 29 may be further deposited thereon without removing the oxide film 26.

  Next, as shown in FIG. 14, the oxide film 29 (the oxide films 26 and 29 when there is the oxide film 26) is etched back using an oxide film etcher or the like. In this etch-back process, the oxide film 29 on the substrate surface (the oxide films 26 and 29 when the oxide film 26 is present) disappears for a predetermined time from the time when the semiconductor substrate 21 is exposed for a second time. The oxide film 29 remaining in the target trench 28 is removed by over-etching, and the oxide film 29 is left with a thickness of about 1 μm only at the bottom of the second target trench 28. This over-etching process is controlled by time management as described above, but the time elapses from the point when the oxide film 29 on the substrate surface (the oxide films 26 and 29 when the oxide film 26 is present) is eliminated. Since the etching amount is controlled by this, processing can be performed with high accuracy.

  Next, as shown in FIG. 15, the substrate surface is polished and planarized by, for example, a CMP method. At this time, as described in the first embodiment, since the oxide film is hardly polished by the CMP method, the polishing is stopped when the oxide film 29 in the second target trench 28 appears on the polishing surface. In this way, the polishing during the planarization process can be stopped at an arbitrary position only by adjusting the thickness of the oxide film 29 remaining at the bottom in the second target trench 28. In the example shown in FIG. 15, the first target trench 22 disappears due to polishing, but there is no problem even if the first target trench 22 remains.

  As described above, according to the second embodiment, the polishing can be finished with an arbitrary polishing amount by leaving the oxide film 29 as a polishing stopper film in the second target trench 28. Similarly, a decrease in yield and a decrease in process throughput can be prevented. Further, since the target is made of the oxide film 29, the target can be easily recognized as in the first embodiment. Therefore, it is possible to manufacture a semiconductor substrate having a high process throughput with a high yield.

  In the above, this invention is not restricted to each embodiment mentioned above, A various change is possible. For example, in each of the above-described embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the reverse is also true. Further, the present invention is not limited to a silicon semiconductor, and can be applied to a compound semiconductor such as SiC.

  As described above, the method for manufacturing a semiconductor substrate according to the present invention is useful for manufacturing a semiconductor substrate used when manufacturing a device having a breakdown voltage structure with a parallel pn junction structure. This is suitable for manufacturing MOSFETs, IGBTs, bipolar transistors, GTO thyristors, diodes, and the like that can achieve both high current capacity and high current capacity.

It is a longitudinal cross-sectional view which shows the outline of the semiconductor substrate in the middle of manufacture by Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor substrate in the middle of manufacture by Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor substrate in the middle of manufacture by Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor substrate in the middle of manufacture by Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor substrate in the middle of manufacture by Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor substrate in the middle of manufacture by Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows an example of the semiconductor substrate manufactured by Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor substrate in the middle of manufacture by Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor substrate in the middle of manufacture by Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor substrate in the middle of manufacture by Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor substrate in the middle of manufacture by Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor substrate in the middle of manufacture by Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor substrate in the middle of manufacture by Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the outline of the semiconductor substrate in the middle of manufacture by Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows an example of the semiconductor substrate manufactured by Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the mode of the substrate surface after the epitaxial growth of the semiconductor substrate which has a parallel pn junction structure.

Explanation of symbols

11, 21 First conductivity type semiconductor substrate 14 First trench (target trench)
15 Insulating film (HTO oxide film)
17, 24 Second trench (super junction trench)
18, 25 Second conductivity type semiconductor (p-type semiconductor region)
22 First trench (first target trench)
28 Third trench (second target trench)
29 Insulating film (oxide film)

Claims (7)

In manufacturing a semiconductor substrate having a parallel pn junction structure in which an n-type semiconductor region and a p-type semiconductor region are alternately and repeatedly joined,
Forming a first trench serving as a target for mask alignment on a semiconductor substrate of a first conductivity type;
Filling the first trench with an insulating film;
Etching the insulating film to leave the insulating film only at the bottom of the first trench;
Forming a second trench deeper than the first trench in the semiconductor substrate;
Epitaxially growing a second conductivity type semiconductor in the second trench;
A method for manufacturing a semiconductor substrate, comprising:   After the epitaxial growth of the second conductivity type semiconductor, the surface of the semiconductor substrate is polished, and when the insulating film at the bottom of the first trench appears on the polished surface, the polishing is stopped and the substrate surface is flattened. The method for manufacturing a semiconductor substrate according to claim 1, further comprising a step.   3. The method of manufacturing a semiconductor substrate according to claim 1, wherein a thickness of the insulating film is not less than ½ of an opening width of the first trench. In manufacturing a semiconductor substrate having a parallel pn junction structure in which an n-type semiconductor region and a p-type semiconductor region are alternately and repeatedly joined,
Forming a first trench serving as a first target for mask alignment in a first conductivity type semiconductor substrate;
Forming a second trench deeper than the first trench in the semiconductor substrate;
Epitaxially growing a second conductivity type semiconductor in the second trench;
Forming a third trench deeper than the first trench and shallower than the second trench as a second target for mask alignment on the semiconductor substrate;
Filling the third trench with an insulating film;
Etching the insulating film to leave the insulating film only at the bottom of the third trench;
A method for manufacturing a semiconductor substrate, comprising:   Polishing the surface of the semiconductor substrate after the etching of the insulating film, and further stopping the polishing when the insulating film at the bottom of the third trench appears on the polished surface to planarize the substrate surface. The method of manufacturing a semiconductor substrate according to claim 4, comprising:   6. The method of manufacturing a semiconductor substrate according to claim 4, wherein the thickness of the insulating film is not less than 1/2 of the opening width of the third trench. 6. The method of manufacturing a semiconductor substrate according to claim 5, wherein the first trench is eliminated by surface polishing of the semiconductor substrate.

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