JP5458608B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a high power semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of forming a trench in a semiconductor substrate.

  2. Description of the Related Art Conventionally, semiconductor devices are broadly classified into horizontal semiconductor devices in which electrode portions are provided on one side of a substrate and vertical semiconductor devices in which electrode portions are provided on both sides of a substrate. In the vertical semiconductor device, the direction in which the drift current flows when turned on is the same as the direction in which the depletion layer extends due to the reverse bias voltage when turned off.

Note that in this specification, a semiconductor having n or p means that electrons and holes are majority carriers, respectively. Further, “ ⁺ ” or “ ⁻ ” attached to n or p, such as n ⁺ or n ^−, is relatively higher or lower than the impurity concentration of the semiconductor to which they are not attached. Represents that.

As an example of the vertical semiconductor device, a planar n-channel vertical MOSFET (insulated gate field effect transistor) will be described. FIG. 20 is a cross-sectional view showing a cross-sectional structure of a planar n-channel vertical MOSFET. As shown in FIG. 20, the vertical semiconductor device 200 is provided with a high resistance n ⁻ drift layer 202 on the front surface side of a low resistance n ⁺ drain layer 201. A p base region 203 is selectively provided in a part of the surface layer of the n ⁻ drift layer 202. A part of the surface layer of the p base region 203 is provided with an n ⁺ source region 204 having a high impurity concentration and a p ⁺ pickup region 205 which are selectively in contact with each other.

A gate electrode 207 is provided on the surface of the p base region 203 sandwiched between the n ⁻ drift layer 202 and the n ⁺ source region 204 via a gate oxide film 206, and the gate electrode 207 and the source electrode are separated by the insulating film 208. 209 is separated. The source electrode 209 is provided in contact with the n ⁺ source region 204 and the p ⁺ pickup region 205. A drain electrode 210 is provided on the back side of the n ⁺ drain layer 201.

In the vertical semiconductor device 200 shown in FIG. 20, the n ⁻ drift layer 202 functions as a region for flowing a drift current in the vertical direction when the MOSFET is in the on state, and is depleted in the off state to increase the breakdown voltage. Plays a function. Therefore, if the n ⁻ drift layer 202 through which the drift current flows is made thinner, the current path of the drift current is shortened, so that the on-resistance (drain-source resistance) is lowered, but the breakdown voltage is lowered. The reason is that the current path of the drift current is shortened and the drift resistance is lowered, while the drain-source depletion layer progresses from the pn junction between the n ⁻ drift layer 202 and the p base region 203. This is because the width becomes narrow and the structure reaches the maximum (critical) electric field strength of silicon quickly. Conversely, when the n ⁻ drift layer 202 is thickened, the breakdown voltage increases, but the on-resistance increases. Thus, in these semiconductor devices, there is a trade-off relationship between on-resistance (current capacity) and breakdown voltage.

  Such a trade-off relationship is the same for semiconductor devices such as IGBTs (insulated gate bipolar transistors), bipolar transistors, or diodes. Further, the same applies to a lateral semiconductor device in which a direction in which a drift current flows when turned on and a direction in which a depletion layer extends due to a reverse bias voltage when turned off.

  A super-junction structure is known as a technique for improving the trade-off described above. FIG. 21 is a cross-sectional view showing a cross-sectional structure of a superjunction semiconductor device. In the vertical semiconductor device 220 shown in FIG. 21, the superjunction structure means that the drift layer 222 is not a single semiconductor layer but an n drift region 222a and a p drift region 222b with increased impurity concentration are alternately and repeatedly joined. (Hereinafter, referred to as Patent Documents 1 to 4 below).

  As a method of forming a parallel pn structure, a method of forming an n drift region and a p drift region in stages by repeating patterning and ion implantation and performing epitaxial growth in several steps is known. However, this method has a problem that it takes time and effort to manufacture, and the cost increases.

As a method for solving such a problem, for example, a trench buried epi method is known. In the trench buried epi method, first, a high-resistance n-type semiconductor layer is formed on the surface of an n ⁺ drain layer 201 as a substrate by an epitaxial method. Next, the n drift region 222a is formed by selectively etching the trench reaching the n ⁺ drain layer 201. A p-type drift region 222b is formed in this trench by growing a p-type semiconductor by an epitaxial method.

Here, in manufacturing a semiconductor device having a superjunction structure with a breakdown voltage of about 800 V, for example, the impurity concentration of the drift layer 222 is 1.9 × 10 ¹⁶ cm ⁻³ , and the widths of the n drift region 222 a and the p drift region 222 b. When both are 5 μm, the thickness of the drift layer 222 needs to be approximately 73 μm. Therefore, in order to form the p drift region 222b in the n-type substrate, a deep trench of about 73 μm must be formed. The deep trench etching for forming a deep trench in this way is a process necessary for forming a superjunction structure.

For deep trench etching, a method of continuously supplying an etching gas such as SF ₆ or HBr while holding the wafer in a chamber depressurized to several Pa, or protecting the etching gas and the trench sidewall There is a BOSCH (Bosch) process in which switching to a protective film forming gas for forming a film is performed every few seconds.

In the Bosch process, for example, a protective film forming gas such as C ₄ F ₈ is first supplied, and then the gas is switched at a high speed to supply an etching gas such as SF ₆ . The trench is formed by repeating the supply of the protective film forming gas and the etching gas. Then, after cleaning the trench, a p-type semiconductor is grown by an epitaxial method. Next, the surface of the parallel pn structure is planarized by a CMP (Chemical Mechanical Polishing) method. Thereafter, a surface structure is formed on the drift layer 222 formed as described above by, for example, a process similar to that for manufacturing a normal planar type MOSFET, and a vertical semiconductor device having a super junction structure is formed. Complete.

Here, when forming the trench, a silicon oxide (SiO ₂ ) film having a high selectivity to silicon as a hard mask and relatively easy to form thicker than other types of films is used. . The hard mask is formed by patterning the SiO ₂ film. At this time, an edge rinse process is performed to remove the SiO ₂ film on the outer peripheral portion of the wafer where the pattern is not formed.

FIG. 22 is a cross-sectional view showing a problem of conventional trench etching. As shown in FIG. 22, when the hard mask is formed, a region where silicon is widely exposed is formed on the outer peripheral portion of the wafer 101 in order to remove the SiO ₂ film 102 in the region where the pattern is not formed. In the outer peripheral portion 111 of the wafer where silicon is widely exposed, when the trench 105 is formed, there is a high probability that the Si product generated by the Si etching is redeposited. If etching is continued with the Si product attached, the Si product acts as a mask material for trench etching, and a columnar silicon etching residue called black silicon 120 is generated. The black silicon 120 has a problem of becoming a particle source when it is broken in a process after the trench etching.

As a method for preventing the generation of the black silicon 120, there is a method of adjusting the conditions of trench etching. Further, there is a method of leaving the SiO ₂ film 102 provided on the outer peripheral portion 111 of the wafer 101 without etching when patterning the hard mask (see, for example, Patent Document 5 below).

European Patent Application No. 0053854 US Pat. No. 5,216,275 US Pat. No. 5,438,215 JP-A-9-266611 Japanese Patent No. 3267199

  However, there is a problem that it is difficult to adjust the conditions of trench etching because black silicon 120 is generated if the condition of the chamber holding the wafer changes even a little during trench etching.

Next, problems when trench etching is performed with the SiO ₂ film 102 provided on the outer peripheral portion 111 of the wafer being left will be described. FIG. 23 is a cross-sectional view showing problems of the conventional epitaxial method. As shown in FIG. 23, in order to form a parallel pn structure, it is necessary to form a semiconductor in the trench by an epitaxial method after the trench etching. At this time, if the SiO ₂ film 102 remains on the outer peripheral portion 111 or the back surface side of the wafer, Si 121 abnormally grows due to the gas that has entered the outer peripheral portion 111 or the back surface side of the wafer.

  Then, when Si 121 grows abnormally, it becomes particles in a later process, causing a device defect, resulting in a decrease in yield. Further, there is a problem that the flatness of the wafer is deteriorated by foreign matters such as particles, the accuracy in the patterning process is lowered, and a device defect is caused.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing a device failure in order to solve the above-described problems caused by the prior art.

To solve the above problems and achieve an object, a method of manufacturing a semiconductor device according to this invention, the entire surface of the semiconductor substrate excluding the trench formation region of the front surface side of a semiconductor substrate of a first conductivity type A mask step of covering with a mask; a trench forming step of etching a semiconductor portion exposed in the opening portion of the mask to form a trench in the semiconductor substrate; and at least an outer peripheral portion of the semiconductor substrate after the trench forming step; A mask removing step of removing the mask coated on the back surface side, and a burying step of filling the trench with a second conductivity type semiconductor in a state where the mask is not coated on the outer peripheral portion and the back surface side of the semiconductor substrate; said semiconductor substrate surface, seen including a grinding step, the grinding of the second conductivity type semiconductor run-off portions from the trench, the mask Engineering In the method, a silicon oxide film is formed on the entire surface of the semiconductor substrate, and an opening is formed in the trench formation region of the silicon oxide film. In the mask removing step, In the grinding step, the inner peripheral portion of the semiconductor substrate is removed by removing the outer peripheral portion and the rear surface portion of the semiconductor substrate, leaving a portion covering the inner peripheral portion on the surface side. Using the mask remaining on the periphery as a stopper, the second conductivity type semiconductor of the surface of the semiconductor substrate protruding from the trench is ground .

A method of manufacturing a semiconductor device according to this invention is the invention described above, in the mask removing step, characterized in that all removing the mask covering the semiconductor substrate.

To solve the above problems and achieve an object, a method of manufacturing a semiconductor device according to this invention, the entire surface of the semiconductor substrate excluding the trench formation region of the front surface side of a semiconductor substrate of a first conductivity type A mask step of covering with a mask; a trench forming step of etching a semiconductor portion exposed in the opening portion of the mask to form a trench in the semiconductor substrate; and at least an outer peripheral portion of the semiconductor substrate after the trench forming step; A mask removing step of removing the mask coated on the back surface side, and a burying step of filling the trench with a second conductivity type semiconductor in a state where the mask is not coated on the outer peripheral portion and the back surface side of the semiconductor substrate; wherein the surface of the semiconductor substrate, anda grinding step of grinding the second conductivity type semiconductor run-off portions from the trench, the mask Engineering In this embodiment, after forming a silicon nitride film on the inner peripheral portion on the front surface side of the semiconductor substrate, a silicon oxide film is formed on the entire surface of the semiconductor substrate, and the silicon nitride film and a laminated film of the silicon oxide film An opening is formed in the trench formation region, and in the mask removing step, the silicon nitride film formed on the inner peripheral portion on the front surface side of the semiconductor substrate is left, and the silicon oxide film is entirely removed. In the grinding step, the second portion of the surface of the semiconductor substrate that protrudes from the trench is formed using the silicon nitride film remaining on the inner peripheral portion on the front surface side of the semiconductor substrate as a stopper. A conductive semiconductor is ground .

To solve the above problems and achieve an object, a method of manufacturing a semiconductor device according to this invention, the entire surface of the semiconductor substrate excluding the trench formation region of the front surface side of a semiconductor substrate of a first conductivity type A mask step of covering with a mask; a trench forming step of etching a semiconductor portion exposed in the opening portion of the mask to form a trench in the semiconductor substrate; and at least an outer peripheral portion of the semiconductor substrate after the trench forming step; A mask removing step of removing the mask coated on the back surface side, and a burying step of filling the trench with a second conductivity type semiconductor in a state where the mask is not coated on the outer peripheral portion and the back surface side of the semiconductor substrate; wherein the surface of the semiconductor substrate, anda grinding step of grinding the second conductivity type semiconductor run-off portions from the trench, the mask Engineering The step of coating the entire surface of the semiconductor substrate with a silicon oxide film, etching the silicon oxide film coated on the inner peripheral portion of the front surface side of the semiconductor substrate, Forming a silicon oxide film on the entire surface of the semiconductor substrate with the step of exposing the semiconductor portion of the inner peripheral portion on the front surface side, and the silicon oxide film being coated on the outer peripheral portion and the back surface side of the semiconductor substrate. The step of making the silicon oxide film coated on the outer peripheral portion and the back surface side of the semiconductor substrate thicker than the silicon oxide film coated on the inner peripheral portion on the front surface side of the semiconductor substrate, An opening is formed in the trench formation region on the inner peripheral portion of the front surface side of the semiconductor substrate, and an edge rinse treatment is performed so that the silicon oxide film covered on the outer peripheral portion of the semiconductor substrate remains. Cormorants a step, characterized in that it comprises a.

According to inventions described above, it is possible to the outer peripheral portion and the mask on the back side of the first conductivity type semiconductor substrate in a remaining state, to form a trench in the inner peripheral portion of the front surface side of the semiconductor substrate . For this reason, it is possible to prevent formation of a region where the semiconductor substrate is widely exposed and to prevent generation of black silicon. In addition, the trench can be filled with the second conductivity type semiconductor in a state where the outer peripheral portion and the back surface side of the semiconductor substrate are not covered with the mask. For this reason, even if the gas for growing the semiconductor wraps around the outer peripheral portion 111 or the back surface side of the wafer, it is possible to prevent the semiconductor from being abnormally generated. Therefore, the generation of particles can be prevented, so that device failure can be prevented.

According to the above-described invention, the trench can be filled with the second conductivity type semiconductor with the mask or the silicon nitride film left in the inner peripheral portion on the front surface side of the semiconductor substrate. For this reason, when the portion of the second conductivity type semiconductor protruding from the trench is ground, it can be ground using the mask or the silicon nitride film as a stopper. Therefore, the thickness of the semiconductor substrate can be set to a desired thickness, and a semiconductor device having a desired breakdown voltage can be formed. Further, since the excess second conductivity type semiconductor on the surface of the semiconductor substrate is surely removed, the semiconductor substrate can be surely exposed, so that a current path can be secured.

  According to the method for manufacturing a semiconductor device of the present invention, it is possible to prevent a device failure.

6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment; FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment; FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment; FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment; FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment; FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment; 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment; FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment; FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment; FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment; FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment; FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment; FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment; FIG. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a fourth embodiment; FIG. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a fourth embodiment; It is sectional drawing which shows the cross-section of a planar type n channel vertical MOSFET. It is sectional drawing which shows the cross-section of the semiconductor device of a super junction structure. It is sectional drawing shown about the problem of the conventional trench etching. It is sectional drawing shown about the problem of the conventional epitaxial method.

  Exemplary embodiments of a method for manufacturing a semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. Note that, in the following description of the embodiments and all the attached drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment 1)
First, a method for manufacturing a semiconductor device according to the first embodiment will be described. 1 to 4 are cross-sectional views sequentially showing the method for manufacturing the semiconductor device according to the first embodiment. First, as shown in FIG. 1, an n-type semiconductor layer having a thickness of, for example, 73 μm and an impurity concentration of 1.9 × 10 ¹⁶ cm ⁻³ is epitaxially grown on a low-resistivity n-type semiconductor substrate having a thickness of, for example, 625 μm. Prepared wafer 1 is prepared. Then, a mask oxide film 2 having a thickness of, for example, 1.5 μm is formed on the surface layer of the wafer 1. Here, the mask oxide film 2 may be formed by thermal oxidation or by a CVD method.

  Next, a resist 3 is applied on the mask oxide film 2 and a trench pattern is patterned on the resist 3 by photolithography or the like. At this time, the edge rinse process is not performed on the outer peripheral portion 11 of the wafer 1, and the resist 3 is left on the outer peripheral portion 11 of the wafer 1.

Next, as shown in FIG. 2, the oxide film is etched, and the mask oxide film 2 is selectively removed using the trench pattern formed in the resist 3 as a mask to form an opening. Therefore, the wafer 1 is exposed only in the region of the opening, and the outer peripheral portion 11 of the wafer 1 remains covered with the mask oxide film 2. Next, using the mask oxide film 2 in which the opening is formed as a mask, trench etching is performed by, for example, a BOSCH process to form a trench 4 having a depth of, for example, 73 μm. Here, since the BOSCH process has a high Si / SiO ₂ selection ratio, the mask oxide film 2 is hardly etched and the wafer 1 in the region covered with the mask oxide film 2 is not exposed. As described above, since the mask oxide film 2 remains in the outer peripheral portion 11 of the wafer 1, Si in the outer peripheral portion 11 of the wafer 1 is not etched, so that generation of black silicon can be suppressed. .

  Next, as shown in FIG. 3, an HF process is performed to remove the mask oxide film on the entire surface of the wafer 1. The inside of the trench 4 is cleaned by removing the polymer inside the trench 4 by this HF treatment.

  Further, the hydrogen annealing process is performed for about 30 seconds to 200 seconds, for example, in a reducing atmosphere having a temperature of about 950 ° C. to 1100 ° C. and a pressure of about 10 Torr to 760 Torr, for example. As a result, irregularities and scallops on the side walls of the trench 4 are smoothed, and the corners of the bottom of the trench 4 are rounded (not shown).

  Next, as shown in FIG. 4, a p-type semiconductor 5 is grown by an epitaxial method to fill the trench 4. Here, for example, the p-type semiconductor 5 is grown more than the height of the surface of the wafer 1 so that all the trenches are completely filled. At this time, since the mask oxide film does not remain on the outer peripheral portion 11 or the back surface side of the wafer 1, even if the reaction gas used for the epitaxial method wraps around the outer peripheral portion 11 or the back surface side of the wafer 1, it depends on the surface orientation of Si. Since the film grows faceted, it does not become a foreign substance. Therefore, silicon does not grow abnormally on the outer peripheral portion 11 or the back surface side of the wafer 1 and no foreign matter is generated.

  Next, although not shown in the figure, the p-type semiconductor 5 on the surface of the wafer 1 is ground by a CMP method or the like to form a parallel pn structure, and a device structure such as a MOS structure is formed by a normal process. A junction type vertical semiconductor device is completed.

  According to the first embodiment described above, generation of black silicon can be prevented because the mask oxide film remains on the surface side of the outer peripheral portion of the wafer during trench etching. Further, since no mask oxide film remains on the outer peripheral portion and the back surface of the wafer during epitaxial growth, abnormal growth of silicon can be prevented. Therefore, the generation of particles can be suppressed, so that device failure can be prevented and the yield is increased. In addition, since the flatness of the wafer is maintained and the patterning accuracy in forming the device structure can be suppressed from decreasing, device defects can be prevented.

(Embodiment 2)
Next, a method for manufacturing the semiconductor device according to the second embodiment will be described. 5 to 10 are cross-sectional views sequentially illustrating the method for manufacturing the semiconductor device according to the second embodiment. In the second embodiment, a mask oxide film is formed after a silicon nitride (SiN) film is formed on the entire surface of the wafer.

  First, as shown in FIG. 5, for example, a wafer 1 similar to that of the first embodiment is prepared. Then, a SiN film 6 having a thickness of, for example, 100 nm is deposited on the surface of the wafer 1 by, for example, a low pressure CVD method. Next, a resist 7 is applied to the entire surface of the SiN film 6, and then an edge rinse process is performed. By this edge rinse treatment, the outer peripheral portion 11 and the resist 7 on the back surface side of the wafer 1 are removed.

  Next, as shown in FIG. 6, the region of the SiN film 6 where the resist 7 is not applied is removed by CDE (Chemical Dry Etching). As a result, the outer peripheral portion 11 and the SiN film 6 on the back surface side of the wafer 1 are removed, and Si is exposed.

  Next, as shown in FIG. 7, after removing the resist, a mask oxide film having a thickness of, for example, 1.5 μm is formed by, eg, CVD. Specifically, the LP-TEOS film 8 is formed as a mask oxide film by, for example, a low pressure CVD method.

  Next, as shown in FIG. 8, a resist is applied on the LP-TEOS film 8, and the LP-TEOS film 8 and the SiN film 6 are selected by a photolithography process or the like using, for example, a resist in which a trench pattern is formed as a mask. Are removed to form an opening. Therefore, the wafer 1 is exposed only in the region of the opening. At this time, the edge rinse process is not performed on the outer peripheral portion 11 of the wafer 1, and the LP-TEOS film 8 is left on the outer peripheral portion 11 and the back surface side of the wafer 1.

Next, using the LP-TEOS film 8 in which the opening is formed as a mask, for example, trench etching is performed by a BOSCH process to form a trench 9 having a depth of, for example, 73 μm. At this time, the LP-TEOS film 8 remains in the outer peripheral portion 11 of the wafer 1, and the BOSCH process has a high Si / SiO ₂ selection ratio, so the LP-TEOS film 8 is hardly scraped and the wafer 1 is exposed. do not do. Therefore, since the Si in the outer peripheral portion 11 of the wafer 1 does not need to be etched, the generation of black silicon can be suppressed.

  Next, as shown in FIG. 9, HF treatment is performed to remove the LP-TEOS film 8. By this HF treatment, the polymer inside the trench 9 is removed and the inside of the trench 9 is cleaned. At this time, the SiN film 6 has a slower etch rate for HF than the LP-TEOS film 8. Therefore, the etching time is adjusted so that the entire LP-TEOS film 8 is removed and the SiN film 6 remains. Further, for example, the hydrogen annealing process is performed under the same conditions as in the first embodiment. As a result, the unevenness and scallops on the side walls of the trench 9 are smoothed, and the bottom corners of the trench 9 are rounded.

  Next, as shown in FIG. 10, a p-type semiconductor 10 is grown by an epitaxial method to fill the trench 9. At this time, since the mask oxide film does not remain on the outer peripheral portion 11 or the back surface side of the wafer 1, silicon does not grow abnormally and no foreign matter is generated.

  Next, although not shown in the drawing, the parallel pn structure is formed by grinding the excess p-type semiconductor 10 on the surface of the wafer 1 using the SiN film 6 as a stopper by CMP or the like. Next, by forming a device structure such as a MOS structure by a normal process, a superjunction type vertical semiconductor device is completed.

  According to the second embodiment, the same effect as in the first embodiment can be obtained. Further, according to the second embodiment, the p-type semiconductor grown epitaxially in excess of the height of the wafer surface can be ground using the SiN film as a grinding stopper. For this reason, the thickness of the parallel pn structure can be set to a desired thickness, and a semiconductor device having a desired breakdown voltage can be formed. Furthermore, since the excess p-type semiconductor on the surface of the wafer is surely removed, the n-type layer can be reliably exposed on the surface of the wafer by removing the SiN film, so that a current path can be secured. it can.

(Embodiment 3)
In the third embodiment, a method will be described in which edge rinsing is performed when patterning a mask oxide film, and trench etching is performed while leaving the mask oxide film on the outer peripheral portion and back surface of the wafer.

11 to 17 are cross-sectional views sequentially illustrating the method for manufacturing the semiconductor device according to the third embodiment. Note that Embodiment 3 shows an example in which the present invention is applied to a vertical semiconductor device having a withstand voltage of 600V. First, as shown in FIG. 11, an n-type semiconductor layer having a thickness of, for example, 55 μm and an impurity concentration of 4.0 × 10 ¹⁵ cm ⁻³ is epitaxially grown on a low-resistivity n-type semiconductor substrate having a thickness of, for example, 625 μm. Prepared wafer 21 is prepared. Next, a first oxide film 22a having a thickness of, for example, 0.8 μm is formed on the surface of the wafer 21 by thermal oxidation.

  Next, as shown in FIG. 12, the first oxide film 22 a formed on the inner peripheral portion 32 of the wafer 21 is etched using an oxide film etcher having a shelter so that the outer peripheral portion 31 of the wafer 21 is not etched. . As a result, the wafer 21 is exposed at the inner peripheral portion 32 of the wafer 21.

  Next, as shown in FIG. 13, the second oxide film 22 b is formed in the inner peripheral portion 32 of the wafer 21 so that the thickness becomes, for example, 0.8 μm. At this time, in the outer peripheral portion 31 of the wafer 21, the second oxide film 22b is formed on the surface of the first oxide film 22a. Therefore, in the outer peripheral portion 31 of the wafer 21, the thickness of the mask oxide film 22 including the first oxide film 22a and the second oxide film 22b is, for example, 1.2 μm. In the inner peripheral portion 32 of the wafer 21, only the second oxide film 22b is formed on the surface of the wafer 21, so that the thickness x of the mask oxide film 22 is, for example, 0.8 μm.

  Next, as shown in FIG. 14, a resist 13 is applied to the surface of the mask oxide film 22 and exposed to form a stripe-shaped trench pattern having a width of 6 mm, for example. At this time, the resist 13 on the surface of the mask oxide film 22 formed on the outer peripheral portion 31 of the wafer 21 is removed.

  Next, as shown in FIG. 15, the mask oxide film 22 is selectively removed using the resist in which the trench pattern is formed as a mask to form an opening. Therefore, the wafer 21 is exposed at the opening. At this time, the thickness of the mask oxide film 22 remaining on the inner peripheral portion 32 of the wafer 21 is, for example, 0.8 μm, and the thickness of the mask oxide film 22 remaining on the outer peripheral portion 31 of the wafer 21 is, for example, 0. 4 μm. Then, the resist is removed.

  Next, as shown in FIG. 16, using the mask oxide film 22 having the opening as a mask, trench etching is performed by, for example, a BOSCH process to form a trench 25 having a depth of, for example, 45 μm. At this time, since the mask oxide film 22 is also etched, the thickness of the mask oxide film 22 remaining on the inner peripheral portion 32 of the wafer 21 becomes, for example, 0.45 μm, and the mask oxide film remaining on the outer peripheral portion 31 of the wafer 21. The thickness of 22 is, for example, 0.05 μm.

  Next, as shown in FIG. 17, wet etching with hydrofluoric acid is performed to remove the mask oxide film 22 remaining on the outer peripheral portion 31 of the wafer 21, and the wafer 21 is exposed at the outer peripheral portion 31 of the wafer 21. Then, a p-type semiconductor is grown by an epitaxial method to fill the trench 25. In FIG. 17, the mask oxide film is removed only on the surface of the outer peripheral portion 31 of the wafer 21, but all mask oxide films 22 including the back surface side may be removed. By doing so, since the mask oxide film 22 does not remain on the back surface side of the wafer 21, it is possible to prevent silicon from growing abnormally on the mask oxide film 22 during the epitaxial growth and to prevent foreign matters from being generated. .

  When epitaxial growth is performed while leaving the mask oxide film 22 on the inner peripheral portion 32 of the wafer 21, after the epitaxial growth, an extra epitaxial film on the surface of the wafer 21 is masked remaining on the inner peripheral portion 32 of the wafer 21. The film 22 can be removed by CMP polishing using the stopper. In the case where the mask oxide film 22 is not left on the inner peripheral portion 32 of the wafer 21, time etching may be performed after CMP polishing to some extent after epitaxial growth. By doing so, since the n-type layer is exposed on the surface of the wafer 21, a current path can be secured. Next, by forming a device structure such as a MOS structure by a normal process, a superjunction type vertical semiconductor device is completed.

  According to the third embodiment, the same effect as in the first embodiment can be obtained.

(Embodiment 4)
Next, a fourth embodiment will be described. 18 and 19 are cross-sectional views sequentially illustrating the method for manufacturing the semiconductor device according to the fourth embodiment. Note that the fourth embodiment shows an example in which the present invention is applied to a vertical semiconductor device having a withstand voltage of 600V. First, as shown in FIG. 18, for example, a wafer 21 similar to that of the third embodiment is prepared. Then, an oxide film 26 having a thickness of, for example, 0.4 μm is formed on the surface of the wafer 21 by thermal oxidation. Further, a SiN film 27 is deposited on the surface of the oxide film 26.

  Next, as shown in FIG. 19, a resist 28 is applied to the surface of the SiN film 27 and an edge rinse process is performed. As a result, the outer peripheral portion 31 of the wafer 21 and the resist 28 on the back surface side are removed, leaving only the resist 28 on the inner peripheral portion on the front surface side of the wafer 21. Further, the SiN film 27 is removed using the resist 28 remaining on the inner peripheral portion on the front surface side of the wafer 21 as a mask. As a result, the SiN film 27 is removed from the outer peripheral portion 31 of the wafer 21, and the wafer 21 is exposed.

Next, the resist 28 remaining on the inner peripheral portion on the front surface side of the wafer 21 is removed and thermally oxidized. As a result, a thermal oxide film thicker than the inner peripheral portion is formed on the outer peripheral portion 31 of the wafer 21 that is not covered with the SiN film 27. At this time, the thickness of the first oxide film formed on the outer peripheral portion of the wafer is set to 0.8 μm, for example. Then, by removing the SiN film 27, the cross section shown in FIG. 13 is obtained. Subsequently, after performing the same processing as in FIGS. 14 to 17, a device structure such as a MOS structure is formed by a normal process. Thus, a super junction type vertical semiconductor device is completed. In the BOSCH process, since the selectivity ratio between Si and SiO ₂ is high, if a mask oxide film having a thickness of about 0.4 μm remains on the inner periphery of the wafer, it functions sufficiently as a mask for BOSCH trench etching. Therefore, the peripheral oxide film becomes thick even when, for example, the selectivity around the wafer is lowered during trench etching (the oxide film is easily etched) or when the edge rinsing process of the resist is performed during photo etching of the oxide film. ing. Therefore, even if etching is performed with reference to the wafer central portion of the oxide film mask having a thickness of 0.4 μm, the peripheral oxide film remains reliably and black silicon is not generated.

  According to the fourth embodiment, the same effect as in the second embodiment can be obtained.

  As described above, the method for manufacturing a semiconductor device according to the present invention is useful for manufacturing a high-power semiconductor element, and in particular, has a semiconductor substrate having a parallel pn structure, and has improved breakdown voltage and improved on-resistance characteristics. It is suitable for the manufacture of a semiconductor device that can achieve both of these.

1 Wafer 4 Trench 5 P-type Semiconductor 11 Outer Periphery

Claims (4)

A masking step for coating with a mask over the entire surface of the semiconductor substrate excluding the trench formation region of the front surface side of the first conductivity type semiconductor substrate,
Forming a trench in the semiconductor substrate by etching a semiconductor portion exposed in the opening of the mask; and
After the trench formation step, at least a mask removal step of removing the mask coated on the outer peripheral portion and the back surface side of the semiconductor substrate;
A burying step of filling the trench with a second conductivity type semiconductor in a state where the outer peripheral portion and the back surface side of the semiconductor substrate are not covered with the mask;
A grinding step of grinding the second conductivity type semiconductor in a portion of the surface of the semiconductor substrate that protrudes from the trench;
Only including,
In the mask process, a silicon oxide film is formed on the entire surface of the semiconductor substrate, an opening is formed in the trench formation region of the silicon oxide film,
In the mask removing step, the outer peripheral portion of the mask and the back surface portion of the mask are removed while leaving a portion of the mask covering the inner peripheral portion of the front surface side of the semiconductor substrate. ,
In the grinding step, the second conductive semiconductor on the surface of the semiconductor substrate protruding from the trench is ground using the mask remaining on the inner peripheral portion on the front surface side of the semiconductor substrate as a stopper. A method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 1 , wherein in the mask removing step, all the mask covering the semiconductor substrate is removed. A mask step of covering the entire surface of the semiconductor substrate except for the trench formation region on the front surface side of the first conductivity type semiconductor substrate with a mask;
Forming a trench in the semiconductor substrate by etching a semiconductor portion exposed in the opening of the mask; and
After the trench formation step, at least a mask removal step of removing the mask coated on the outer peripheral portion and the back surface side of the semiconductor substrate;
A burying step of filling the trench with a second conductivity type semiconductor in a state where the outer peripheral portion and the back surface side of the semiconductor substrate are not covered with the mask;
A grinding step of grinding the second conductivity type semiconductor in a portion of the surface of the semiconductor substrate that protrudes from the trench;
Including
In the mask process, after forming a silicon nitride film on the inner peripheral portion on the front surface side of the semiconductor substrate, a silicon oxide film is formed on the entire surface of the semiconductor substrate, and the silicon nitride film and the silicon oxide film are formed. Forming an opening in the trench formation region of the laminated film ,
In the mask removing step, all the silicon oxide film is removed, leaving the silicon nitride film formed on the inner peripheral portion on the front surface side of the semiconductor substrate,
In the grinding step, using the silicon nitride film remaining on the inner peripheral portion on the front surface side of the semiconductor substrate as a stopper, the portion of the surface of the semiconductor substrate that protrudes from the trench is the second conductive semiconductor. method of manufacturing a semi-conductor device characterized by grinding. A mask step of covering the entire surface of the semiconductor substrate except for the trench formation region on the front surface side of the first conductivity type semiconductor substrate with a mask;
Forming a trench in the semiconductor substrate by etching a semiconductor portion exposed in the opening of the mask; and
After the trench formation step, at least a mask removal step of removing the mask coated on the outer peripheral portion and the back surface side of the semiconductor substrate;
A burying step of filling the trench with a second conductivity type semiconductor in a state where the outer peripheral portion and the back surface side of the semiconductor substrate are not covered with the mask;
A grinding step of grinding the second conductivity type semiconductor in a portion of the surface of the semiconductor substrate that protrudes from the trench;
Including
In the mask process,
Coating the entire surface of the semiconductor substrate with a silicon oxide film;
Etching the silicon oxide film coated on the inner peripheral portion on the front surface side of the semiconductor substrate to expose a semiconductor portion on the inner peripheral portion on the front surface side of the semiconductor substrate;
By forming the silicon oxide film on the entire surface of the semiconductor substrate in a state where the outer peripheral portion and the back surface side of the semiconductor substrate are coated, the outer peripheral portion and the back surface side of the semiconductor substrate are covered. And making the silicon oxide film thicker than the silicon oxide film coated on the inner peripheral portion of the front surface side of the semiconductor substrate;
Forming an opening in the trench formation region on the inner peripheral portion of the front surface side of the semiconductor substrate, and performing an edge rinse process so that the silicon oxide film covered on the outer peripheral portion of the semiconductor substrate remains; ,
Method of manufacturing a semi-conductor device, which comprises a.

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