JP4923414B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device that can be applied to a MOSFET (insulated gate field effect transistor), an IGBT (insulated gate bipolar transistor), a bipolar transistor, or the like and achieves both high breakdown voltage and large current capacity.

In general, semiconductor elements can be broadly classified into horizontal elements having electrode portions only on one side and vertical elements having electrode portions on both sides. In the vertical element, the direction in which the drift current flows when turned on and the direction in which the depletion layer is extended by the reverse bias voltage when turned off are both in the thickness direction (vertical direction) of the substrate. For example, in a normal planar type n-channel vertical MOSFET, the portion of the high resistance n ⁻ drift layer functions as a region for flowing a drift current in the vertical direction when the MOSFET is in the on state, and is depleted when in the off state. It works to increase pressure resistance.

Reducing the thickness of the high-resistance n ⁻ drift layer, that is, shortening the current path length lowers the drift resistance in the on state, so that the substantial on-resistance (drain-source resistance) of the MOSFET is reduced. It has a lowering effect. However, since the extension width of the drain-base depletion layer extending from the pn junction between the p base region and the n ⁻ drift layer becomes narrow in the off state, the depletion electric field strength is faster than the maximum (critical) electric field strength of silicon. Will reach. That is, breakdown occurs before the drain-source voltage reaches the design value of the device breakdown voltage, and the breakdown voltage (drain-source voltage) is lowered.

On the contrary, when the n ⁻ drift layer is formed thick, it is possible to increase the breakdown voltage, but the on-resistance is inevitably increased, so that the on-loss increases. Thus, there is a trade-off relationship between on-resistance (current capacity) and breakdown voltage. This relationship is also known to hold in semiconductor devices such as IGBTs having a drift layer, bipolar transistors, and diodes. The same applies to a lateral element in which the direction in which the drift current flows when turned on and the direction in which the depletion layer is extended by the reverse bias voltage when turned off. As a solution to this problem, a semiconductor element (hereinafter referred to as a superjunction semiconductor element) in which a drift layer has a parallel pn structure in which n-type regions and p-type regions with an increased impurity concentration are alternately arranged is known. It is.

  The difference in structure between a superjunction semiconductor element and a normal planar type n-channel vertical MOSFET is that the drift portion is not a uniform / single conductive type layer (impurity diffusion layer), but a vertical layer-like n-type. That is, it is constituted by a parallel pn structure in which a drift region and a vertical layered p-type partition region are joined alternately. In this structure, even if the impurity concentration of the parallel pn structure is high, the depletion layer extends in both the lateral directions from each pn junction oriented in the vertical direction of the parallel pn structure in the off state, and the entire drift portion is depleted. High breakdown voltage can be achieved.

  In such a superjunction semiconductor element, one in which a part of the surface of the parallel pn structure is covered with an oxide film is known (see, for example, Patent Document 1 and Patent Document 2). Further, as a method of manufacturing the above-described parallel pn structure on a low resistance substrate, a trench is formed by forming a trench in an n-type semiconductor layer, filling the trench with an epitaxial growth layer of a p-type semiconductor, and polishing and planarizing the surface. The method is known (see, for example, Patent Document 3).

JP 2002-134748 A JP 2001-298190 A JP 2001-196573 A

  In a superjunction semiconductor device, in order to obtain a low on-resistance while ensuring a breakdown voltage, the total impurity amount of the n-type region and the p-type region of the parallel pn structure is made substantially the same, and the depth direction of the n-type region and the p-type region is It is necessary to make the impurity concentration of the substrate approximately uniform. When the widths of the n-type region and the p-type region are the same, the impurity concentrations of the n-type region and the p-type region may be made substantially the same. By doing so, a withstand voltage can be ensured in the active region where current flows in the on state.

  However, when the parallel pn structure of the active region and the parallel pn structure of the surrounding inactive region are formed by one trench formation step and one trench buried epitaxial growth step according to the method disclosed in Patent Document 3, the active region The parallel pn structure is directly extended to the withstand voltage structure portion of the inactive region. In this structure, since the depletion layer from the pn junction in the outermost p base region does not extend outward or in the depth direction of the device, the depletion electric field strength quickly reaches the critical electric field strength of silicon, and the breakdown voltage decreases. Resulting in.

  Further, in the method disclosed in Patent Document 3, when the polishing of the surface is completed, the n-type region and the p-type region of the parallel pn structure are exposed on the surface. When the oxide film is formed, boron, which is a dopant in the p-type region, is taken into the thermal oxide film, and the concentration of the p-type region is lowered on the surface side. On the other hand, in the n-type region, phosphorus, which is a dopant, is not taken into the thermal oxide film, but accumulates at the interface between the thermal oxide film and silicon. For this reason, the concentration of the n-type region is higher than the concentration of the p-type region on the surface side of the parallel pn structure disposed immediately below the thermal oxide film.

That is, as shown in FIG. 39, in the parallel pn structure 7 immediately below the thermal oxide film to be the field oxide film 11, the low level passes through the interface between the p-type region 6 and the field oxide film 11 and the p-type region 6. The portions of the surface of the resistance substrate (n ⁺ substrate) 1 that reach the drain electrode 15 are denoted by A1 and A2, respectively. The drain electrode 15 passes through the interface between the n-type region 5 and the field oxide film 11 and the n-type region 5. Assuming that the locations leading to are B1 and B2, respectively, the concentration in the vicinity of B1 is higher than the concentration in the vicinity of A1, as in the concentration profiles of A1-A2 and B1-B2 shown in FIG. Therefore, the depletion layer is difficult to spread in the parallel pn structure immediately below the field oxide film 11, and the breakdown voltage is reduced.

  The present invention provides a method for manufacturing a semiconductor device capable of securing the withstand voltage of a semiconductor device having a parallel pn structure manufactured by a trench embedding method as a drift portion in order to eliminate the above-described problems caused by the prior art. With the goal.

To solve the above problems and achieve an object, a method of manufacturing a semiconductor device according to this invention, over non-active area surrounding the active region and the active region in which a current flows when the on-state, the low-resistance layer A first step of epitaxially growing a first conductive type semiconductor on a low resistance layer in manufacturing a semiconductor element having a parallel pn structure in which first conductive type semiconductor regions and second conductive type semiconductor regions are alternately arranged A second step of forming a plurality of trenches in the epitaxial growth layer of the first conductive type semiconductor at predetermined intervals, a third step of filling the trenches by epitaxial growth of the second conductive type semiconductor, and the trench The surface of the parallel pn structure composed of the first conductive type semiconductor region remaining in between and the second conductive type semiconductor region buried in the trench is flattened by polishing. A fourth step of ion implantation, a fifth step of ion-implanting a second conductivity type impurity into a flat region of the parallel pn structure that becomes the inactive region, and a second conductivity implanted into the parallel pn structure. A sixth step of activating the type impurities by heat treatment in a non-oxidizing atmosphere, and a seventh step of covering part of the surface of the parallel pn structure with a field oxide film by thermal oxidation. And

The method of manufacturing a semiconductor device according to this invention is the invention described above, wherein the first conductive type semiconductor region second conductivity type semiconductor regions are alternately arranged so that the planar shape forms a stripe, In the fifth step, the parallel pn structure disposed in the region that becomes the inactive region includes the first conductive type semiconductor region and the second conductive type semiconductor region that do not pass through the region that becomes the active region. An impurity of the second conductivity type is selectively ion-implanted only in the stripe portion.

The method of manufacturing a semiconductor device according to this invention, over non-active area surrounding the active region and the active region in which a current flows when the ON state, the first conductivity type semiconductor region and the second conductivity type on the low-resistance layer In manufacturing a semiconductor element having a parallel pn structure in which semiconductor regions are alternately arranged so as to form a stripe-like planar shape, a first step of epitaxially growing a first conductivity type semiconductor on a low resistance layer; A second step of forming a plurality of trenches in the epitaxial growth layer of one conductivity type semiconductor at predetermined intervals; a third step of filling the trench by epitaxial growth of the second conductivity type semiconductor; The surface of the parallel pn structure composed of the first conductive type semiconductor region and the second conductive type semiconductor region embedded in the trench is flattened by polishing. And a stripe-shaped portion made of the first conductive semiconductor region and the second conductive semiconductor region that do not pass through the region serving as the active region of the parallel pn structure flattened in the region serving as the non-active region. A second conductivity type impurity is ion-implanted into both the first conductivity type semiconductor region and the second conductivity type semiconductor region extending from the active region to the inactive region. A step of activating a second conductivity type impurity implanted into the parallel pn structure by a heat treatment in a non-oxidizing atmosphere; and a field oxidation of a part of the surface of the parallel pn structure by thermal oxidation And a seventh step of covering with a film.

The method of manufacturing a semiconductor device according to this invention is the invention described above, in the fifth step, the parallel pn first conductivity type in the partial region of the non-active region and a region of the structure the semiconductor region and the second A second conductivity type impurity is selectively ion-implanted only in the conductivity type semiconductor region.

The method of manufacturing a semiconductor device according to this invention is the invention described above, in the fifth step, the second conductive only selectively to the second conductivity type semiconductor region of the non-active region and a region of the parallel pn structure It is characterized by ion-implanting a type impurity.

The method of manufacturing a semiconductor device according to the invention this is, in the invention described above, in the fifth step, selecting only the second conductivity type semiconductor region of the partial region of the region to be the non-active region of the parallel pn structure In particular, the second conductivity type impurity is ion-implanted.

The method of manufacturing a semiconductor device according to this invention is the invention described above, in the fifth step, the second conductive only selectively a first conductivity type semiconductor region of the non-active region and a region of the parallel pn structure It is characterized by ion-implanting a type impurity.

The method of manufacturing a semiconductor device according to the invention this is, in the invention described above, in the fifth step, selecting only the first conductivity type semiconductor region of the partial region of the region to be the non-active region of the parallel pn structure In particular, the second conductivity type impurity is ion-implanted.

The method of manufacturing a semiconductor device according to the present invention is the above-described invention. The method further includes an eighth step of forming a channel stopper electrode that covers the end portion. In the fifth step, the field plate electrode side end portion directly below the channel stopper electrode side end portion of the field plate electrode. The second conductivity type impurity is selectively ion-implanted only in a region excluding the portion located between the region immediately below and the region covered with the channel stopper electrode.

The method of manufacturing a semiconductor device according to the present invention includes a first conductive type semiconductor region and a second conductive type semiconductor on a low resistance layer over an active region where current flows in an on state and an inactive region around the active region. In manufacturing a semiconductor device having a parallel pn structure in which regions are alternately arranged, a first step of epitaxially growing a first conductivity type semiconductor on a low resistance layer, and a surface of the epitaxial growth layer of the first conductivity type semiconductor A second step of forming a trench forming mask, and using the mask to form a plurality of trenches in the epitaxial growth layer of the first conductive type semiconductor at predetermined intervals; and the second conductive type semiconductor in the trench A third step of burying by epitaxial growth of the second conductive type half-mask embedded in the trench and the mask formed in the second step A fourth step of flattening the surface of the body region by polishing, and a parallel pn structure comprising a first conductive type semiconductor region remaining between the trenches and a second conductive type semiconductor region embedded in the trenches A fifth step of ion-implanting a second conductivity type impurity into a part or all of the surface, and a first conductivity type semiconductor on the surface of the parallel pn structure including a region where the second conductivity type impurity is ion-implanted. A sixth step of epitaxial growth, and in the fifth step, the second conductive type semiconductor region embedded in the trench in the third step is etched by approximately the thickness of the mask. The second conductivity type impurity is ion-implanted in a self-aligning manner using the mask.

The method for manufacturing a semiconductor device according to the present invention is the semiconductor device manufacturing method according to the above-described invention, wherein the first conductivity type semiconductor region remaining between the trenches and the trench are buried between the fourth step and the sixth step. A seventh step of ion-implanting a first conductivity type impurity into a part or all of the surface of the parallel pn structure made of the second conductivity type semiconductor region, and the first step of ion implantation in the seventh step; The dose amount of the conductivity type impurity is approximately ½ of the dose amount of the second conductivity type impurity ion-implanted in the fifth step.

In the semiconductor device manufacturing method according to the present invention, in the above-described invention, in the fifth step, the first conductive semiconductor region remaining between the trenches and the second conductive semiconductor region buried in the trenches are used. A second conductivity type impurity is selectively ion-implanted only into the surface of the second conductivity type semiconductor region of the parallel pn structure.

The method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above-described invention, the seventh step is performed immediately before the fifth step.

The method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above-described invention, the seventh step is performed immediately after the fifth step.

In the semiconductor device manufacturing method according to the present invention, in the above-described invention, in the seventh step, the first conductivity type impurity is selectively ion-implanted only on the surface of the first conductivity type semiconductor region having a parallel pn structure. It is characterized by doing.

In the semiconductor device manufacturing method according to the present invention, in the above-described invention, in the sixth step, the first conductive type semiconductor region and the second conductive type semiconductor region of the parallel pn structure are formed on the surface of the parallel pn structure. A first conductivity type semiconductor having a thickness of about 1/2 of the repetitive pitch is epitaxially grown.

According to the above-described invention, before the thermal oxide film is formed on the surface of the parallel pn structure, the second conductive type impurity is ion-implanted in the region that becomes the inactive region in advance, thereby becoming the inactive region. In the parallel pn structure of regions, the total impurity amount of the second conductivity type is larger than the total impurity amount of the first conductivity type on the surface side. In this state, when the thermal oxide film is formed on the surface of the parallel pn structure, the second conductivity type impurity is taken into the thermal oxide film, and the first conductivity type impurity is accumulated at the interface between the thermal oxide film and the silicon. However, in the region that becomes the inactive region, the impurity amount of the first conductivity type semiconductor region is smaller than the impurity amount of the second conductivity type semiconductor region. Therefore, the depletion layer easily spreads in the breakdown voltage structure portion in the inactive region, and the breakdown voltage is improved.

According to the above-described invention, before forming the thermal oxide film on the surface of the parallel pn structure, the stripe-shaped portion and the active region that do not pass through the region that becomes the active region in the parallel pn structure that becomes the inactive region in advance. In the parallel pn structure of the ion implantation region, the second conductivity type is formed on the surface side by ion-implanting the second conductivity type impurity into both of the stripe-shaped portions extending through the region to the inactive region. The total amount of impurities is larger than the total amount of impurities of the first conductivity type. In this state, when the thermal oxide film is formed on the surface of the parallel pn structure, the second conductivity type impurity is taken into the thermal oxide film, and the first conductivity type impurity is accumulated at the interface between the thermal oxide film and the silicon. However, in the parallel pn structure, the amount of impurities in the first conductivity type semiconductor region is smaller than the amount of impurities in the second conductivity type semiconductor region in the stripe portion that does not pass through the region that becomes the active region. As a result, the depletion layer easily spreads and the breakdown voltage is improved. In addition, in the parallel pn structure of the region that becomes the inactive region, the charge imbalance on the surface side is alleviated and the charge balance is secured in the stripe-like portion that extends from the region that becomes the active region to the inactive region. Therefore, local electric field concentration is eliminated, the breakdown voltage as the lateral superjunction structure is secured, and the breakdown voltage is improved.

According to the above-described invention, the region located between the position immediately below the channel stopper electrode side end portion of the field plate electrode and the field stopper electrode side end portion of the channel stopper electrode to the region immediately below the channel stopper electrode. The second conductivity type impurity is not ion-implanted. In the region where the second conductivity type impurity is not implanted on the channel stopper side, the impurity concentration of the first conductivity type semiconductor region is higher than the impurity concentration of the second conductivity type semiconductor region on the surface side of the parallel pn structure. Elongation of the depletion layer is suppressed. Accordingly, it is possible to prevent a decrease in breakdown voltage particularly when a negative charge disturbance is applied to the surface of the field oxide film. In addition, since the electric field is strongest in the vicinity of the end portion of the field plate electrode, a sufficient breakdown voltage can be ensured even if the second conductivity type impurity is not ion-implanted up to just below the channel stopper electrode.

According to the above-described invention, after the second conductivity type impurity is ion-implanted into the surface of the parallel pn structure, the first conductivity type semiconductor is epitaxially grown on the surface of the parallel pn structure, thereby forming a thermal oxidation that becomes a subsequent field oxide film. Even if the second conductivity type impurity is diffused in the oxidation step for generating the film, only the first conductivity type dopant is present on the surface of the parallel pn structure. Dopants are not incorporated. Therefore, no charge imbalance occurs on the surface side of the parallel pn structure that exists directly under the field oxide film. Thereby, since the spread of the depletion layer at the edge portion is not hindered, the depletion layer immediately below the oxide film, that is, immediately below the edge portion is easily spread, and the concentration of the electric field is suppressed, so that the breakdown voltage is improved.

According to the above-described invention, by performing ion implantation of the second conductivity type impurity and ion implantation of the first conductivity type impurity, in the parallel pn structure immediately below the thermal oxide film that becomes the field oxide film, Charge balance can be easily secured. Further, in the parallel pn structure immediately below the thermal oxide film that becomes the field oxide film, the concentration on the surface side can be easily controlled. Furthermore, since the concentration of the p-type region of the parallel pn structure can be increased by controlling the respective ion implantation amounts, the spread of the depletion layer can be further promoted.

  According to the method for manufacturing a semiconductor element according to the present invention, there is an effect that the breakdown voltage of the semiconductor element having the parallel pn structure manufactured by the trench embedding method as a drift portion can be secured.

Exemplary embodiments of a method for manufacturing a semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, “ ⁺ ” attached to n or p means that the impurity concentration is higher than that of a layer or region where it is not attached. Note that the same reference numerals are given to the same components in all the attached drawings, and redundant description is omitted.

Embodiment 1 FIG.
1 to 9 sequentially show the cross-sectional configurations of MOSFETs being manufactured according to the manufacturing method according to the first embodiment. First, as shown in FIG. 1, an n-type low-resistance silicon substrate (n ⁺⁺ substrate) 1 having an impurity concentration of, for example, antimony or the like of about 2 × 10 ¹⁸ cm ⁻³ is prepared. Then, an n-type semiconductor 2 having, for example, a phosphorus impurity concentration of about 6 × 10 ¹⁵ cm ⁻³ is epitaxially grown on the n-type low-resistance substrate 1 to a thickness of, for example, about 50 μm.

  Next, as shown in FIG. 2, an insulating film having a thickness of 1.6 μm or more, for example, 2.4 μm, for example, an oxide film (or a nitride film or the like) is formed on the surface of the n-type semiconductor 2. The thickness of the oxide film (or nitride film or the like) is determined even after a trench having a depth of, for example, 50 μm is formed based on the selectivity between the oxide film (or nitride film or the like) and silicon. , Nitride film, etc.) are left. Subsequently, the oxide film (or nitride film or the like) is patterned by lithography to form a hard mask 3 for forming trenches.

  The width of the oxide film (or nitride film or the like) portion and the opening portion of the hard mask 3 is, for example, 5 μm. That is, for example, hard masks 3 having a width of 5 μm are arranged at intervals of 5 μm. Subsequently, the trench 4 having a depth of, for example, about 50 μm is formed in the n-type semiconductor 2 by dry etching, for example, so that the surface orientation of the trench side wall is, for example, the (010) plane or a plane equivalent thereto. The hard mask 3 is patterned so that the trench 4 having such a plane orientation is formed. The portion of the n-type semiconductor 2 remaining after the trench formation becomes the n-type region 5 having a parallel pn structure.

Next, as shown in FIG. 3, a boron-doped p-type semiconductor is epitaxially grown in the trench 4, and the trench 4 is filled with a p-type semiconductor having a concentration of, for example, about 6 × 10 ¹⁵ cm ⁻³ . At this time, an epitaxial growth layer of the p-type semiconductor is grown until it becomes higher than the upper surface of the hard mask 3. Since the surface orientation of the trench sidewall is as described above, the trench 4 can be filled with an epitaxial growth layer of a p-type semiconductor without leaving a void in the trench 4. The p-type semiconductor buried in the trench 4 becomes a p-type region 6 having a parallel pn structure.

  Next, as shown in FIG. 4, CMP (chemical mechanical polishing) or the like is performed using the oxide film or the like of the hard mask 3 as a polishing stopper, and above the upper surface of the hard mask 3 by epitaxial growth of the p-type semiconductor. The formed silicon layer is removed to flatten the surface. By using the hard mask 3 as a polishing stopper, variations during epitaxial growth can be flattened.

Next, after removing the hard mask 3, as shown in FIG. 5, polishing such as CMP is performed to planarize the exposed surface of the parallel pn structure 7. If the polishing amount at this time is about 0.5 μm, for example, the dimension in the depth direction, that is, the thickness of the parallel pn structure 7 is about 48 μm, for example. Next, as shown in FIG. 6, a screening oxide film 8 having a thickness of about 500 angstroms is formed on the surface of the parallel pn structure 7. Then, a resist mask 9 having a desired pattern is formed on the screening oxide film 8, and a p-type impurity such as boron is ion-implanted at a dose of, for example, 8 × 10 ¹² cm ⁻² to form a region that becomes an inactive region. , Boron is ion-implanted only into the p-type region 6 having the parallel pn structure. The damage to the silicon at that time is reduced by the presence of the screening oxide film 8.

  Thereafter, the resist mask 9 is removed, and heat treatment is performed to activate the implanted boron. The heat treatment atmosphere at this time is preferably a non-oxidizing atmosphere. The reason for this is that when heat treatment is performed in an oxidizing atmosphere, defects due to ion implantation and an oxidizing atmosphere, in particular, an oxygen stacking fault is induced by the combination of oxygen. This is because the induction of can be avoided. By this heat treatment, the implanted boron diffuses. As a result, as shown in FIG. 7, the width of the p-type region 6 increases in the surface region of the parallel pn structure in the region that becomes the inactive region. Thereafter, the screening oxide film 8 is removed.

  Next, as shown in FIG. 8, thermal oxidation is performed to form a thermal oxide film 10 on the entire surface of the parallel pn structure 7. At that time, boron which is a dopant of the p-type region 6 is taken into the thermal oxide film 10. On the other hand, phosphorus, which is a dopant in the n-type region 5, is not taken into the thermal oxide film 10 but accumulates at the interface between silicon and the thermal oxide film 10. As a result, in the region that becomes the active region and the region that becomes the inactive region, the width of the p-type region 6 in the surface region of the parallel pn structure becomes narrower than the state before the thermal oxide film 10 is formed.

  Next, as shown in FIG. 9, the thermal oxide film 10 is patterned to form a field oxide film 11, and an element structure 12 on the surface side of the MOSFET is formed on the surface of the region to be the active region. Further, the source electrode 13 and the channel stopper electrode 14 are formed on the front surface side of the parallel pn structure, and the drain electrode 15 is formed on the back surface of the n-type low resistance substrate 1, thereby completing the super junction MOSFET. The source electrode 13 extends from the active region to the non-active region side and covers a part of the field oxide film 11 in the non-active region as the field plate electrode 16. The channel stopper electrode 14 is provided along the outer periphery of the chip and covers a part of the field oxide film 11.

  FIG. 10 is a diagram showing the concentration profiles of the p-type region 6 (A1-A2 in FIG. 9) and the n-type region 5 (B1-B2 in FIG. 9) of the parallel pn structure 7 arranged in the region to be the inactive region. It is. As shown in FIG. 10, boron is ion-implanted only in the p-type region 6 of the parallel pn structure 7 in the region that becomes the inactive region, so that the surface of the n-type region 5 in the surface region of the region that becomes the inactive region. The impurity concentration of the p-type region 6 becomes higher than the impurity concentration of the n-type region 5 without the region becoming p-type. Since the p-type region 6 having a high concentration in this surface region acts as a guard ring, the depletion layer sufficiently spreads in the parallel pn structure 7 immediately below the breakdown voltage structure portion. Accordingly, the breakdown voltage is improved.

Note that the dose amount when boron is ion-implanted into the p-type region 6 of the parallel pn structure 7 in the region to be the inactive region may be as high as about 3 × 10 ¹³ cm ⁻² . In this case, boron diffuses laterally from the p-type region 6 of the parallel pn structure 7 in the region that becomes the inactive region and is connected to the surface region of the n-type region 5, and the surface region of the n-type region 5 is p-type. However, the effect of improving the breakdown voltage due to the extension of the depletion layer can be obtained similarly. At this time, the concentration profiles of the p-type region 6 (A1-A2 in FIG. 9) and the n-type region 5 (B1-B2 in FIG. 9) of the parallel pn structure 7 arranged in the region serving as the inactive region are shown in FIG. become that way.

Embodiment 2. FIG.
In the second embodiment, boron is ion-implanted into both the n-type region 5 and the p-type region 6 of the parallel pn structure 7 in a region to be an inactive region. FIG. 11 to FIG. 12 sequentially show cross-sectional configurations of MOSFETs being manufactured according to the manufacturing method according to the second embodiment. First, the surface of the parallel pn structure 7 is planarized according to the processes shown in FIGS. 1 to 5 as in the first embodiment.

Next, as shown in FIG. 11, a screening oxide film 8 and a resist mask 9 are sequentially formed on the surface of the parallel pn structure 7. Then, a p-type impurity, for example, boron is ion-implanted into the n-type region 5 and the p-type region 6 having a parallel pn structure in a region to be an inactive region with a dose of, for example, about 2 × 10 ¹³ cm ⁻² . The subsequent processes are the same as those in the first embodiment.

  FIG. 12 shows a state in which an activation heat treatment is performed after boron ion implantation and then the screening oxide film 8 is removed. As shown in FIG. 12, in the second embodiment, the surface of the n-type region 5 of the parallel pn structure 7 is made thin and p-type in the region that becomes the inactive region by the activation heat treatment. FIG. 13 shows a state where a field oxide film 11 made of a thermal oxide film, an element structure 12 on the surface side of the MOSFET, a source electrode 13, a channel stopper electrode 14 and a drain electrode 15 are formed, and a super junction MOSFET is completed.

  FIG. 14 is a diagram showing concentration profiles of the p-type region 6 (A1-A2 in FIG. 13) and the n-type region 5 (B1-B2 in FIG. 13) of the parallel pn structure 7 arranged in the region to be the inactive region. It is. As shown in FIG. 14, boron is ion-implanted into the n-type region 5 and the p-type region 6 of the parallel pn structure 7 in the region that becomes the inactive region, so that the n of the parallel pn structure 7 in the region that becomes the inactive region. The surface of the mold region 5 becomes thin and becomes p-type. As a result, the potential at the end of the source electrode 13 is transmitted to the surface of the p-type parallel pn structure 7 in the region serving as the inactive region via the oxide film serving as the field oxide film 11. The difference from the drain potential is directly applied in the depth direction of the parallel pn structure 7. Therefore, the depletion layer is strongly expanded in the surface region of the parallel pn structure 7 below the field oxide film 11, and the breakdown voltage is improved.

Note that the dose amount when boron is ion-implanted into the n-type region 5 and the p-type region 6 of the parallel pn structure 7 in the region to be the inactive region may be about 5 × 10 ¹² cm ⁻² . In this case, the surface of the n-type region 5 of the parallel pn structure 7 in the region to be the inactive region remains n-type without being made p-type. At this time, the concentration profiles of the p-type region 6 (A1-A2 in FIG. 13) and the n-type region 5 (B1-B2 in FIG. 13) of the parallel pn structure 7 arranged in the region serving as the inactive region are shown in FIG. become that way. Therefore, the same effect as that of the first embodiment can be obtained as an effect of improving the breakdown voltage due to the extension of the depletion layer.

Embodiment 3 FIG.
In the third embodiment, boron is ion-implanted only into the n-type region 5 having a parallel pn structure in a region to be an inactive region. FIG. 15 sequentially shows the cross-sectional configurations of MOSFETs being manufactured according to the manufacturing method according to the third embodiment. First, the surface of the parallel pn structure 7 is planarized according to the processes shown in FIGS. 1 to 5 as in the first embodiment.

Next, as shown in FIG. 15, a screening oxide film 8 and a resist mask 9 are sequentially formed on the surface of the parallel pn structure 7. Then, a p-type impurity such as boron is ion-implanted into the n-type region 5 having a parallel pn structure in a region to be an inactive region with a dose of about 5 × 10 ¹² cm ⁻² , for example. The subsequent processes are the same as those in the first embodiment. The cross-sectional configuration of the superjunction MOSFET completed according to the third embodiment is the same as the configuration shown in FIG.

  FIG. 16 is a diagram showing the concentration profiles of the p-type region 6 (A1-A2 in FIG. 9) and the n-type region 5 (B1-B2 in FIG. 9) of the parallel pn structure 7 arranged in the region to be the inactive region. It is. As shown in FIG. 16, boron is ion-implanted only in the n-type region 5 of the parallel pn structure 7 in the region that becomes the inactive region, so that the impurity in the n-type region 5 in the surface region of the region that becomes the inactive region. The concentration is lower than the impurity concentration of the p-type region 6. Therefore, the depletion layer spreads strongly in the parallel pn structure 7 below the field oxide film 11, and the breakdown voltage is improved.

Note that the dose amount when boron is ion-implanted into the n-type region 5 of the parallel pn structure 7 in the region to be the inactive region may be about 2 × 10 ¹³ cm ⁻² . In this case, the surface region of the n-type region 5 of the parallel pn structure 7 becomes p-type in the region that becomes the inactive region, but the effect of improving the breakdown voltage due to the extension of the depletion layer is obtained similarly. At this time, the concentration profiles of the p-type region 6 (A1-A2 in FIG. 9) and the n-type region 5 (B1-B2 in FIG. 9) of the parallel pn structure 7 arranged in the region serving as the inactive region are shown in FIG. become that way.

  Further, in the first to third embodiments described above, in the parallel pn structure 7 arranged in the region to be the inactive region, the boron ion implantation region is formed of the field oxide film 11 as shown by an arrow C1 in FIG. The lower region and the lower region of the channel stopper electrode 14. However, the region below the source electrode 13 may be removed from the region indicated by the arrow C1 as indicated by the arrow C2 in FIG. 9, or the channel stopper electrode 14 may be excluded from the region indicated by the arrow C1 as indicated by the arrow C3. The region below the source electrode 13 and the region below the channel stopper electrode 14 may be excluded from the region indicated by the arrow C1, as indicated by the arrow C4. In either case, the depletion layer tends to spread between the source electrode 13 and the channel stopper electrode 14 where the depletion layer is most difficult to spread.

Embodiment 4 FIG.
In the fourth embodiment, as shown in FIG. 17, the planar shape of the parallel pn structure 7 is a stripe shape. In the fourth embodiment, the n-type region that does not pass through the region that becomes the active region in the parallel pn structure 7 of the region that becomes the inactive region before forming the thermal oxide film that becomes the field oxide film in the first embodiment. P-type region 61 of stripe-shaped portion 71 composed of 51 and p-type region 61, and p-type of stripe-shaped portion 72 composed of n-type region 52 and p-type region 62 extending from the region serving as the active region to the non-active region. Boron is ion-implanted into the region 62. Other processes are the same as those in the first embodiment. In FIG. 17, the surface layer of the parallel pn structure 7 and the surface structure of the element formed thereon are omitted (the same applies to FIG. 18).

  FIG. 17 shows boron ion implantation regions 21 and 22 with hatching. As shown in FIG. 17, in the p-type region 62 that extends from the active region to the non-active region, the width of the boron ion-implanted region 22 is narrower than the width of the p-type region 62. This is because if the boron is implanted into the p-type region 62 with the same width as the p-type region 62, the impurity concentration of the p-type region 62 increases on the surface side. On the other hand, in the p-type region 61 that does not pass through the region serving as the active region, the width of the boron ion-implanted region 21 is the same as the width of the p-type region 61. In the fourth embodiment, boron ions are implanted into the breakdown voltage structure sandwiched between two large and small ¼ arcs in FIG.

For example, when the widths of the p-type regions 61 and 62 are 5 μm, the boron implantation width for the p-type region 62 extending from the active region to the non-active region is 4 μm. For example, when the boron dose is 8 × 10 ¹² cm ⁻² , the charge balance is ensured in the stripe-shaped portion 72 extending from the active region to the inactive region in the breakdown voltage structure. The breakdown voltage improved from about 450V to about 680V.

Embodiment 5 FIG.
In the fifth embodiment, as shown in FIG. 18, the planar shape of the parallel pn structure 7 is a stripe shape. In the fifth embodiment, the n-type region which does not pass through the region serving as the active region in the parallel pn structure 7 of the region serving as the non-active region before forming the thermal oxide film serving as the field oxide film in the first embodiment. N-type region 51 of stripe-shaped portion 71 composed of 51 and p-type region 61, and n-type of stripe-shaped portion 72 composed of n-type region 52 and p-type region 62 extending from the region serving as the active region to the non-active region. Boron is ion-implanted into the region 52. Other processes are the same as those in the first embodiment.

  FIG. 18 shows boron ion implantation regions 21 and 22 with hatching. As shown in FIG. 18, in the n-type region 52 extending from the active region to the non-active region, the width of the boron ion-implanted region 22 is wider than the width of the n-type region 52. This is because, when thermal oxidation is performed to form a field oxide film, the n-type region 52 expands on the surface side, so that if boron is implanted with the same width as the n-type region 52 before thermal oxidation, the impurity concentration This is because a high n-type region remains. In the n-type region 51 that does not pass through the region that becomes the active region, the width of the boron ion-implanted region 21 is the same as the width of the n-type region 51. In the fifth embodiment, boron ions are implanted into the breakdown voltage structure sandwiched between two large and small quarter arcs in FIG.

For example, when the width of the n-type regions 51 and 52 is 5 μm as the remaining width at the time of forming the trench, the boron implantation width to the n-type region 52 extending from the active region to the inactive region is 6 μm. Then, for example, when making a prototype with a boron dose of 2 × 10 ¹² cm ⁻² , in the breakdown voltage structure portion, the charge balance is ensured in the stripe-like portion 72 extending from the active region to the inactive region, The breakdown voltage improved from about 450V to about 635V.

Embodiment 6 FIG.
In the sixth embodiment, a field oxide film is formed by a CVD method. First, the silicon layer formed above the upper surface of the hard mask 3 is removed by polishing such as CMP according to the process shown in FIGS.

However, as the n-type low-resistance silicon substrate (n ⁺⁺ substrate) 1, for example, a substrate having a (100) plane or a plane equivalent thereto as a main surface is used. Further, the impurity concentration of the n-type semiconductor 2 epitaxially grown on the n-type low-resistance substrate 1 is set to about 4.5 × 10 ¹⁵ cm ^−3, for example. Further, the impurity concentration of the epitaxial growth layer of the p-type semiconductor filling the trench 4 is set to about 4.5 × 10 ¹⁵ cm ^−3, for example.

  After completion of polishing such as CMP, isotropic etching using a plasma etcher or anisotropic etching using a trench etcher is performed with the hard mask 3 left, and a p-type semiconductor that becomes the p-type region 6 is obtained. Then, the hard mask 3 remaining after the polishing such as CMP is etched and removed by an approximate thickness. By this etching, the step between the surface of the p-type region 6 and the interface between the n-type region 5 and the hard mask 3 is almost eliminated. Subsequently, the hard mask 3 is removed, and the exposed surface of the parallel pn structure 7 is mirror-polished to remove the unevenness on the surface. The polishing amount here is, for example, about 0.5 μm.

An element structure 12, a field oxide film 11 and a source electrode 13 on the surface side of the MOSFET are formed on the surface of the parallel pn structure 7 manufactured as described above. When the field oxide film 11 is formed, for example, a vertical furnace is used, the pressure in the chamber is set to 80 Pa, the flow rates of SiH ₄ (monosilane) and N ₂ O are set to 20 cc and 1000 cc, respectively, and parallel at a temperature of 800 ° C. A silicon oxide film is vapor-phase grown on the surface of the pn structure 7 at a growth rate of 2 to 20 nm per minute. In the sixth embodiment, a protective film is formed instead of the channel stopper electrode 14 in the region (see FIG. 9) where the channel stopper electrode 14 is formed in the first embodiment. Then, by forming the drain electrode 15 on the back surface of the n-type low resistance substrate 1, a super junction MOSFET is completed.

By manufacturing the super-junction MOSFET as described above, the amount of boron in the p-type region 6 and the amount of phosphorus in the n-type region 5 arranged below the field oxide film 11 can be balanced. The decrease can be suppressed. When actually manufactured as a prototype, the withstand voltage was 680 V and the on-resistance was 20.5 mΩcm ² . As a comparison, the breakdown voltage and on-resistance of the element formed by thermal oxidation of the field oxide film 11 were 430 V and 17.2 mΩcm ² , respectively, so that the breakdown voltage improved by 250 V (+ 58%) according to the sixth embodiment, The increase in on-resistance could be suppressed to 3.3 mΩcm ² (about + 20%).

Embodiment 7 FIG.
The seventh embodiment is a modification of the first embodiment. The ion implantation region of the p-type impurity after the surface of the parallel pn structure 7 is planarized is directly below the end of the field plate electrode 16 on the channel stopper electrode side. And a region located between the portion immediately below the end of the channel stopper electrode 14 on the field plate electrode side and a region covered with the channel stopper electrode 14. Hereinafter, for convenience of explanation, the parallel pn structure of the region to be the inactive region is divided into two, the region on the side where the p-type impurity is ion-implanted (region close to the active region) is set as the implantation target region, and the p-type impurity is ionized. The region on the non-injection side (region near the outer peripheral edge of the chip) is set as a non-injection target region (the same applies to the eighth and ninth embodiments).

19 to 20 sequentially show the cross-sectional configurations of MOSFETs being manufactured according to the manufacturing method according to the seventh embodiment. First, the surface of the parallel pn structure 7 is planarized according to the processes shown in FIGS. 1 to 5 as in the first embodiment. Next, as shown in FIG. 19, a screening oxide film 8 and a resist mask 9 are sequentially formed on the surface of the parallel pn structure 7. Then, a p-type impurity such as boron is ion-implanted into the p-type region 6 having a parallel pn structure in a region to be an inactive region with a dose of about 8 × 10 ¹² cm ⁻² .

  At this time, in the region to be the inactive region, the surface of the non-implantation target region and the surface of the n-type region 5 of the target region of implantation are covered with the resist mask 9, so that boron is implanted into these regions. Not. The subsequent processes are the same as those in the first embodiment. FIG. 20 shows a state in which after the ion implantation of boron, the resist mask 9 is removed and activation heat treatment is performed. In FIG. 21, a field oxide film 11 made of a thermal oxide film, an element structure 12 on the surface side of the MOSFET, a source electrode 13, a field plate electrode 16, a channel stopper electrode 14 and a drain electrode 15 are formed, thereby completing a super junction MOSFET. Indicates the state.

  Concentration profiles of the p-type region 6 (A3-A4 in FIG. 21) and the n-type region 5 (B3-B4 in FIG. 21) in the region to be implanted in the region to be the inactive region are A1, A2, The profiles are obtained by replacing B1 and B2 with A3, A4, B3, and B4, respectively. Therefore, as in the first embodiment, the depletion layer spreads strongly in the parallel pn structure 7 below the field oxide film 11, so that the breakdown voltage is improved.

  Further, the concentration profiles of the p-type region 6 (A5-A6 in FIG. 21) and the n-type region 5 (B5-B6 in FIG. 21) in the non-implantation target region among the regions that become the non-active regions are A1 in FIG. , A2, B1, and B2 are read as A5, A6, B5, and B6, respectively. That is, in the region near the outer peripheral edge of the chip in the inactive region, the impurity concentration of the n-type region 5 is higher than the impurity concentration of the p-type region 6 on the surface side of the parallel pn structure 7, so that the depletion layer is prevented from growing. Is done. Therefore, it is possible to prevent a decrease in breakdown voltage particularly when a negative charge disturbance is applied to the surface of the field oxide film 11.

  When boron is ion-implanted into the parallel pn structure 7 immediately below the channel stopper electrode 14 as in the first embodiment, the channel stopper electrode 14 particularly when a negative charge disturbance is applied to the surface of the field oxide film 11. As the depletion layer extends strongly until the electric field strength in the vicinity of the channel stopper electrode 14 increases, the breakdown voltage may decrease. The seventh embodiment is effective against this decrease in breakdown voltage. In addition, since the electric field is strongest in the vicinity of the end of the field plate electrode 16, a sufficient breakdown voltage can be ensured even if boron is not ion-implanted under the channel stopper electrode 14.

Note that the dose amount when boron is ion-implanted into the p-type region 6 of the region to be implanted in the region to be the inactive region may be as high as about 2 × 10 ¹³ cm ⁻² . In this case, the surface region of the n-type region 5 becomes p-type in the region to be implanted in the region that becomes the inactive region, but the effect of improving the breakdown voltage due to the extension of the depletion layer is obtained in the same manner. At this time, the concentration profiles of the p-type region 6 (A3-A4 in FIG. 21) and the n-type region 5 (B3-B4 in FIG. 21) in the region to be implanted out of the region that becomes the inactive region are A1 in FIG. , A2, B1, and B2 are read as A3, A4, B3, and B4, respectively.

Embodiment 8 FIG.
The eighth embodiment is a modification of the second embodiment, and an implantation target region when performing ion implantation of p-type impurities after the surface of the parallel pn structure 7 is planarized is the same as in the seventh embodiment. Of the two halves of the parallel pn structure of the region to be the non-active region, the region near the active region is used, and the region near the outer periphery of the chip is the non-implantation target region. 22 to 23 sequentially show the cross-sectional configurations of MOSFETs being manufactured according to the manufacturing method according to the eighth embodiment.

First, the surface of the parallel pn structure 7 is planarized according to the processes shown in FIGS. 1 to 5 as in the first embodiment. Next, as shown in FIG. 22, a screening oxide film 8 and a resist mask 9 are sequentially formed on the surface of the parallel pn structure 7. Then, a p-type impurity such as boron is ion-implanted into the p-type region 6 and the n-type region 5 having a parallel pn structure in a region to be an inactive region with a dose of about 2 × 10 ¹³ cm ⁻² , for example.

  At this time, since the surface of the non-implantation target region is covered with the resist mask 9 in the region to be the non-active region, boron is not implanted into this region. The subsequent processes are the same as those in the first embodiment. FIG. 23 shows a state in which after the ion implantation of boron, the resist mask 9 and the screening oxide film 8 are removed and an activation heat treatment is performed. In FIG. 24, a field oxide film 11 made of a thermal oxide film, an element structure 12 on the surface side of the MOSFET, a source electrode 13, a field plate electrode 16, a channel stopper electrode 14 and a drain electrode 15 are formed to complete a super junction MOSFET. Indicates the state.

  Concentration profiles of the p-type region 6 (A3-A4 in FIG. 24) and the n-type region 5 (B3-B4 in FIG. 24) in the region to be implanted out of the region that becomes the inactive region are A1, A2, The profiles are obtained by replacing B1 and B2 with A3, A4, B3, and B4, respectively. Accordingly, in the region to be implanted, as in the second embodiment, the depletion layer is strongly spread in the surface region of the parallel pn structure 7 below the field oxide film 11, and the breakdown voltage is improved.

  In addition, the concentration profiles of the p-type region 6 (A5-A6 in FIG. 24) and the n-type region 5 (B5-B6 in FIG. 24) in the non-implantation target region of the region that becomes the inactive region are A1 in FIG. , A2, B1, and B2 are read as A5, A6, B5, and B6, respectively. Therefore, as in the seventh embodiment, it is possible to prevent a decrease in breakdown voltage particularly when a negative charge disturbance is applied to the surface of the field oxide film 11. In addition, since the electric field is strongest in the vicinity of the end of the field plate electrode 16, a sufficient breakdown voltage can be ensured even if boron is not ion-implanted under the channel stopper electrode 14.

Note that the dose amount when boron is ion-implanted into the p-type region 6 and the n-type region 5 of the region to be implanted in the region to be the inactive region may be about 5 × 10 ¹² cm ⁻² . In this case, the surface of the n-type region 5 of the implantation target region is not p-type but remains n-type. At this time, the concentration profiles of the p-type region 6 (A3-A4 in FIG. 24) and the n-type region 5 (B3-B4 in FIG. 24) in the implantation target region are A3, A2, B1, and B2 in FIG. , A4, B3, and B4.

Embodiment 9 FIG.
The ninth embodiment is a modification of the third embodiment, and the region to be implanted when ion implantation of p-type impurities is performed after the surface of the parallel pn structure 7 is planarized, as in the seventh embodiment. Of the two halves of the parallel pn structure of the region to be the non-active region, the region near the active region is used, and the region near the outer periphery of the chip is the non-implantation target region. FIG. 25 to FIG. 26 sequentially show cross-sectional configurations of MOSFETs being manufactured according to the manufacturing method according to the ninth embodiment.

First, the surface of the parallel pn structure 7 is planarized according to the processes shown in FIGS. 1 to 5 as in the first embodiment. Next, as shown in FIG. 25, a screening oxide film 8 and a resist mask 9 are sequentially formed on the surface of the parallel pn structure 7. Then, a p-type impurity such as boron is ion-implanted into the n-type region 5 having a parallel pn structure in a region to be an inactive region with a dose of about 5 × 10 ¹² cm ⁻² , for example.

  At this time, in the region to be the inactive region, the surface of the non-implantation target region and the surface of the p-type region 6 in the target region of implantation are covered with the resist mask 9, and boron is implanted into these regions. Not. The subsequent processes are the same as those in the first embodiment. FIG. 26 shows a state in which after the ion implantation of boron, the resist mask 9 and the screening oxide film 8 are removed and an activation heat treatment is performed. In FIG. 27, a field oxide film 11 made of a thermal oxide film, an element structure 12 on the surface side of the MOSFET, a source electrode 13, a field plate electrode 16, a channel stopper electrode 14 and a drain electrode 15 are formed to complete a super junction MOSFET. Indicates the state.

  Concentration profiles of the p-type region 6 (A3-A4 in FIG. 27) and the n-type region 5 (B3-B4 in FIG. 27) in the region to be implanted among the regions to be inactive regions are shown in FIG. The profiles are obtained by replacing B1 and B2 with A3, A4, B3, and B4, respectively. Therefore, as in the third embodiment, since the depletion layer spreads strongly in the parallel pn structure 7 below the field oxide film 11, the breakdown voltage is improved.

  In addition, the concentration profiles of the p-type region 6 (A5-A6 in FIG. 27) and the n-type region 5 (B5-B6 in FIG. 27) in the non-implantation target region among the regions that become the inactive regions are A1 in FIG. , A2, B1, and B2 are read as A5, A6, B5, and B6, respectively. Therefore, as in the seventh embodiment, it is possible to prevent a decrease in breakdown voltage particularly when a negative charge disturbance is applied to the surface of the field oxide film 11. In addition, since the electric field is strongest in the vicinity of the end of the field plate electrode 16, a sufficient breakdown voltage can be ensured even if boron is not ion-implanted under the channel stopper electrode 14.

Note that the dose amount when boron is ion-implanted into the n-type region 5 of the region to be implanted in the region to be the inactive region may be as high as about 2 × 10 ¹³ cm ⁻² . In this case, the surface region of the n-type region 5 becomes p-type in the region to be implanted in the region that becomes the inactive region, but the effect of improving the breakdown voltage due to the extension of the depletion layer is obtained in the same manner. At this time, the concentration profiles of the p-type region 6 (A3-A4 in FIG. 27) and the n-type region 5 (B3-B4 in FIG. 27) in the region to be implanted in the region to be the inactive region are shown in FIG. , A2, B1, and B2 are read as A3, A4, B3, and B4, respectively.

  In Embodiments 6 to 9 described above, in the parallel pn structure 7 arranged in the region to be the inactive region, the boron ion implantation region (implantation target region) is as shown by an arrow C5 in FIG. In the non-active region, it is a region on the active region side from a position located immediately below the channel stopper electrode side end of the field plate electrode 16 and directly below the field plate electrode side end of the channel stopper electrode 14. However, as indicated by the arrow C6 in FIG. 9, a part of the active region side in the lower region of the field plate electrode 16 may be excluded from the region indicated by the arrow C5. In any case, the depletion layer tends to spread between the field plate electrode 16 and the channel stopper electrode 14 where the depletion layer is most difficult to spread, and the breakdown voltage is improved.

Embodiment 10 FIG.
In the tenth embodiment, a p-type impurity is ion-implanted into the surface of the parallel pn structure 7 and then an n-type semiconductor is epitaxially grown on the surface of the parallel pn structure 7. 28 to 32 sequentially show cross-sectional configurations of MOSFETs being manufactured according to the manufacturing method according to the tenth embodiment. First, according to the process shown in FIGS. 1 to 4, as in the first embodiment, polishing such as CMP is performed using the trench forming hard mask 3 as a polishing stopper, and the p-type is epitaxially grown above the upper surface of the hard mask 3. The semiconductor (p-type region 6) is removed, and the surface composed of the hard mask 3 and the p-type region 6 is flattened. The step of polishing the epitaxial growth layer (p-type region 6) on the hard mask 3 is defined as a first polishing step.

However, in the tenth embodiment, as the n-type low resistance silicon substrate (n ⁺⁺ substrate) 1, a substrate having, for example, a (100) plane or a plane equivalent to this is used. Alternatively, the silicon opening may be widened by isotropic etching. In the region where the opening of silicon is widened, the width of the opening is widened, making it difficult to form voids. In the tenth embodiment, even when the opening width of silicon is widened by isotropic etching, it can be filled without leaving voids.

  Next, as shown in FIG. 28, with the hard mask 3 left, silicon etching is performed by an amount (thickness) substantially equal to the thickness of the remaining hard mask 3 to substantially eliminate the level difference on the silicon surface. . This silicon etching may be isotropic etching using a plasma etcher or the like, or may be anisotropic etching using a trench etcher. When isotropic etching is performed, a side etching portion is formed. In the subsequent ion implantation step, anisotropic etching may be performed in order to avoid ion implantation into the side etching portion.

  A screening oxide film (not shown) is formed on the surface. The thickness of the screening oxide film is, for example, 50 mm. With this film thickness, the oxide film (hard mask 3) remaining on the n-type region 5 is hardly oxidized. Therefore, a difference occurs in the thickness of the surface oxide film. That is, the thickness of the oxide film is the thickness of the screen oxide film (for example, 50 nm) on the p-type region 6 and the thickness of the remaining hard mask 3 (for example, approximately 800 nm) on the n-type region 5.

Next, as shown in FIG. 29, ion implantation of a p-type impurity such as boron is performed in a self-aligning manner using the hard mask 3 on the n-type region 5 as a self-aligned mask. At this time, the acceleration voltage is, for example, 45 KeV, and the dose amount is, for example, 3 × 10 ¹³ cm ⁻² . Under this condition, since the boron range is about 100 nm, boron is implanted only into the p-type region 6 embedded in the trench. In FIG. 29, reference numeral 17 denotes a boron ion implantation region. By performing ion implantation of p-type impurities in this way, the amount of impurities in the p-type region 6 of the parallel pn structure 7 is increased, so that the depletion layer immediately below the breakdown voltage structure portion is sufficiently expanded.

  Next, as shown in FIG. 30, the hard mask 3 is peeled off and the exposed surface is mirror-polished to expose the exposed surfaces of the n-type region 5 and the p-type region 6 (boron ion implantation region 17). Is in a mirror state. The mirror polishing at this time is defined as a second polishing step. Thereafter, as shown in FIG. 31, a screening oxide film 8 of, eg, a 50 nm thickness is formed on the mirror polished surface. Then, ion implantation of an n-type impurity such as phosphorus is performed on the entire surface.

The acceleration voltage at this time is, for example, about 100 KeV, and the dose amount is, for example, 1.5 × 10 ¹³ cm ⁻² . In this case, since the dose of the boron ion implantation region 17 in the p-type region 6 is, for example, 3 × ¹³ cm ⁻² as described above, the effective boron dose after phosphorus ion implantation is, for example, 1 5 × 10 ¹³ cm ⁻² . Therefore, in the parallel pn structure 7, the dose amount in the surface region of the p-type region 6 and the dose amount in the surface region of the n-type region 5 are approximately the same.

  In this way, ion implantation of an n-type impurity (for example, phosphorus) is performed, and the dose amount at this time and the dose amount of the p-type impurity (boron in this case) performed before this are adjusted as appropriate, thereby charge balance. Alternatively, it is possible to make the total impurity amount p-rich, that is, to increase the impurity amount in the p-type region 6 more than the impurity amount in the n-type region 5. Therefore, the depletion in such a portion is promoted, and the breakdown voltage is improved.

Next, as shown in FIG. 32, after the screening oxide film 8 is removed, an n-type semiconductor is epitaxially grown on the exposed surface, so that the surface of the boron ion implantation region 17 and the surface of the phosphorus ion implantation region 18 are formed. Covered with an n-type semiconductor layer 19. Considering isotropic diffusion of the dopant, the thickness of the n-type semiconductor layer 19 is preferably about ½ of the pitch D of the parallel pn structure 7 (see FIG. 32). Further, the impurity concentration of the n-type semiconductor layer 19 may be a concentration that does not affect the variation during ion implantation. For example, in the case of the dose described above, the impurity concentration of the n-type semiconductor layer 19 may be about 5 × 10 ¹³ cm ⁻³ .

  Finally, as shown in FIG. 33, a field oxide film 11, an element structure 12 on the surface side of the MOSFET, a channel stopper region 20, a source electrode 13, a field plate electrode 16, a channel stopper electrode 14 and a drain electrode 15 are formed. A super-junction MOSFET is completed. When forming the field oxide film 11, the element structure 12 on the surface side of the MOSFET, or the channel stopper region 20, various thermal histories are generated.

  During the thermal history, for example, boron and phosphorus are supplied from ion implantation regions 17 and 18 (see FIG. 32) serving as a dopant supply source provided in the surface region of the parallel pn structure 7, and the field oxide film 11 Diffuses to the interface. Thereby, the incorporation of boron into the field oxide film 11 is suppressed. Further, accumulation of phosphorus at the interface between silicon and the field oxide film 11 is suppressed. Accordingly, it is possible to suppress a decrease in breakdown voltage in the breakdown voltage structure.

Embodiment 11 FIG.
The eleventh embodiment is a modification of the tenth embodiment, in which ion implantation of an n-type impurity such as phosphorus is selectively performed in the n-type region 5 of the parallel pn structure 7. 34 to 35 sequentially show cross-sectional configurations of MOSFETs being manufactured according to the manufacturing method according to the eleventh embodiment. First, in the same manner as in the tenth embodiment, the second polishing step is performed according to the processes shown in FIGS. 1 to 4 and FIGS. 28 to 30, and the n-type region 5 and the p-type region 6 (boron ion implantation region). 17) Set the exposed surface to a mirror state.

  Thereafter, as shown in FIG. 34, a screening oxide film 8 of, eg, a 50 nm thickness is formed on the mirror polished surface. Further, as shown in FIG. 35, a resist is applied on the screening oxide film 8, and a resist mask 9 is formed by selectively opening a portion above the n-type region 5 by photolithography. Then, ion implantation of an n-type impurity such as phosphorus is performed, and phosphorus is implanted into the surface region of the n-type region 5 through the opening of the resist mask 9.

The dose amount at this time is the same as the dose amount at the time of boron ion implantation performed before this, and is, for example, 3 × 10 ¹³ cm ⁻² . In this way, even when phosphorus ions are selectively implanted, the charge balance of the parallel pn structure 7 can be ensured. Thereafter, the resist mask 9 and the screening oxide film 8 are removed. The subsequent processes are the same as those in the tenth embodiment. According to the eleventh embodiment, the same effect as in the tenth embodiment can be obtained.

Embodiment 12 FIG.
The twelfth embodiment is a modification of the tenth embodiment, and after the second polishing process (mirror polishing process), ion implantation of p-type impurities such as boron is selectively performed in the p-type region of the parallel pn structure 7. 6 and the n-type impurity, for example, phosphorus ion implantation is selectively performed in the n-type region 5 of the parallel pn structure 7. 36 to 37 sequentially show cross-sectional configurations of the MOSFETs being manufactured according to the manufacturing method according to the twelfth embodiment. First, in the same way as in the tenth embodiment, according to the processes shown in FIGS. 1 to 4 and FIG. 28, silicon etching is carried out with the trench-forming hard mask 3 left, so that the level difference on the silicon surface is substantially eliminated. .

Thereafter, the remaining hard mask 3 is removed. Then, the exposed surface is subjected to mirror polishing as a second polishing step, and the exposed surface is brought into a mirror state. The cross-sectional configuration after mirror polishing is the same as the configuration shown in FIG. Next, as shown in FIG. 36, a screening oxide film 8 is formed on the mirror polished surface. Further, a resist is applied on the screening oxide film 8, and a resist mask 9 is formed by selectively opening portions on the p-type region 6 by photolithography. Then, ion implantation of a p-type impurity such as boron is performed, and boron is implanted into the surface region of the p-type region 6 through the opening of the resist mask 9. At this time, the acceleration voltage is, for example, 45 KeV, and the dose amount is, for example, 1.5 × 10 ¹³ cm ⁻² .

Next, as shown in FIG. 37, after removing the resist mask 9, a resist is again applied on the screening oxide film 8, and a resist in which a portion above the n-type region 5 is selectively opened by photolithography. A mask 25 is formed. Then, ion implantation of an n-type impurity such as phosphorus is performed, and phosphorus is implanted into the surface region of the n-type region 5 through the opening of the resist mask 25. The dose at this time is, for example, 1.5 × 10 ¹³ cm ⁻² . In this way, the charge balance of the parallel pn structure 7 can be ensured.

  Thereafter, the resist mask 25 and the screening oxide film 8 are removed. Then, an n-type semiconductor is epitaxially grown on the exposed surface, and the surface of the boron ion implantation region 17 and the surface of the phosphorus ion implantation region 18 are covered with an n-type semiconductor layer 19 (see FIG. 32). The subsequent processes are the same as those in the tenth embodiment. According to the twelfth embodiment, the same effect as in the tenth embodiment can be obtained. Note that the ion implantation of the p-type impurity may be performed after the ion implantation of the n-type impurity.

Embodiment 13 FIG.
The thirteenth embodiment is a modification of the twelfth embodiment, in which ion implantation of an n-type impurity such as phosphorus is performed on the entire surface of the parallel pn structure 7. FIG. 38 shows, in order, the cross-sectional configurations of MOSFETs being manufactured according to the manufacturing method according to the thirteenth embodiment. First, in the same manner as in the twelfth embodiment, ion implantation of a p-type impurity, for example, boron is performed according to the processes shown in FIGS. 1 to 4, 28 and 36. Although not particularly limited, the dose of boron is, for example, 3 × 10 ¹³ cm ⁻² .

Thereafter, the resist mask 9 is removed. The cross-sectional configuration at this time is the same as the configuration shown in FIG. Then, as shown in FIG. 38, ion implantation of an n-type impurity such as phosphorus is performed, and phosphorus is implanted into the entire surface of the parallel pn structure 7. The dose at this time is about half of the dose of the p-type impurity performed before this, for example, 1.5 × 10 ¹³ cm ⁻² . In this case, since the effective dose amounts of the boron ion implantation region 17 and the phosphorus ion implantation region 18 of the parallel pn structure 7 are substantially equal, the charge balance of the parallel pn structure 7 can be ensured.

  Thereafter, the screening oxide film 8 is removed, an n-type semiconductor is epitaxially grown on the exposed surface, and the surface of the boron ion implantation region 17 and the surface of the phosphorus ion implantation region 18 are covered with the n-type semiconductor layer 19 (FIG. 32). The subsequent processes are the same as those in the tenth embodiment. According to the thirteenth embodiment, the same effect as in the tenth embodiment can be obtained. Note that the ion implantation of the p-type impurity may be performed after the ion implantation of the n-type impurity.

  In Embodiments 10 to 13 described above, the condition of the dose amount related to the ion implantation of the p-type impurity and the n-type impurity is set as the charge balance condition. However, by adjusting these dose amounts appropriately, the total impurity amount can be reduced. It is possible to achieve p-riching or n-riching in which the amount of impurities in the n-type region 5 is larger than the amount of impurities in the p-type region 6. In particular, in the case of p enrichment, the current-voltage characteristic that becomes a negative resistance can be improved by the redistribution of the electric field caused by the accumulation of holes generated during avalanche. Thus, the avalanche resistance is improved by making the dose amount during ion implantation p-rich.

  Furthermore, in Embodiments 10 to 13 described above, when ion implantation of a p-type impurity (for example, boron) is performed as in Embodiments 6 to 9, directly below the channel stopper electrode side end of field plate electrode 16. And p-type impurities (for example, boron) may not be injected into a region from a position located between the channel stopper electrode 14 and a portion directly below the end of the field plate electrode on the field plate electrode side. Even in this case, the depletion layer is easily spread between the field plate electrode 16 and the channel stopper electrode 14 where the depletion layer is most difficult to spread, and the breakdown voltage is improved.

  As described above, the present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the widths of the n-type regions 5, 51, 52 of the parallel pn structure 7 and the p-type regions 6, 61, 62 in the region that becomes the non-active region are the n-type regions of the parallel pn structure 7 in the region that becomes the active region, respectively. 5 and 52 and the widths of the p-type regions 6 and 62 may be the same or different. Further, the widths of the n-type regions 5, 51, 52 and the p-type regions 6, 61, 62 in the region that becomes the inactive region are set so that the n-type regions 5, 52 and the p-type regions 6, 62 in the region that becomes the active region, respectively. It may be narrower than the width.

  The p-type regions 6, 61, and 62 have the same width in the region that becomes the active region and the region that becomes the inactive region, but the width of the n-type regions 5, 51, and 52 in the region that becomes the inactive region is the same. The width of the n-type regions 5 and 52 in the region to be the active region may be narrower. In addition, the dimensions, concentrations, CVD conditions, and the like described in the embodiments are examples, and the present invention is not limited to these values. Further, the first conductivity type may be p-type and the second conductivity type may be n-type. Furthermore, the present invention can be applied not only to MOSFETs but also to IGBTs, bipolar transistors, FWDs, Schottky diodes, and the like.

  As described above, the method for manufacturing a semiconductor device according to the present invention is useful for manufacturing a high-power semiconductor device. In particular, it is possible to increase the breakdown voltage of MOSFETs, IGBTs, bipolar transistors, etc. having a parallel pn structure in the drift portion. It is suitable for manufacturing a semiconductor device capable of achieving both large current capacity.

It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 1 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 1 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 1 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 1 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 1 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 1 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 1 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 1 of this invention. It is sectional drawing which shows the semiconductor element manufactured according to the manufacturing method concerning Embodiment 1 of this invention. It is a figure which shows the concentration profile of the parallel pn structure of the semiconductor element manufactured according to the manufacturing method concerning Embodiment 1 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 2 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 2 of this invention. It is sectional drawing which shows the semiconductor element manufactured according to the manufacturing method concerning Embodiment 2 of this invention. It is a figure which shows the density | concentration profile of the parallel pn structure of the semiconductor element manufactured according to the manufacturing method concerning Embodiment 2 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 3 of this invention. It is a figure which shows the concentration profile of the parallel pn structure of the semiconductor element manufactured according to the manufacturing method concerning Embodiment 3 of this invention. It is a top view for demonstrating the ion implantation area | region of the manufacturing method concerning Embodiment 4 of this invention. It is a top view for demonstrating the ion implantation area | region of the manufacturing method concerning Embodiment 5 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 7 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 7 of this invention. It is sectional drawing which shows the semiconductor element manufactured according to the manufacturing method concerning Embodiment 7 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 8 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 8 of this invention. It is sectional drawing which shows the semiconductor element manufactured according to the manufacturing method concerning Embodiment 8 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 9 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 9 of this invention. It is sectional drawing which shows the semiconductor element manufactured according to the manufacturing method concerning Embodiment 9 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 10 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 10 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 10 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 10 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 10 of this invention. It is sectional drawing which shows the semiconductor element manufactured according to the manufacturing method concerning Embodiment 10 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 11 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 11 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 12 of this invention. It is sectional drawing which shows the semiconductor element under manufacture according to the manufacturing method concerning Embodiment 12 of this invention. It is sectional drawing which shows the semiconductor element in manufacture according to the manufacturing method concerning Embodiment 13 of this invention. It is sectional drawing which shows the structure of the principal part of the conventional superjunction semiconductor element. It is a figure which shows the density | concentration profile of the parallel pn structure of the conventional superjunction semiconductor element.

Explanation of symbols

1 Low resistance layer (n-type low resistance substrate)
2 First conductivity type semiconductor (n-type semiconductor)
3 Hard mask 4 Trench 5, 51, 52 First conductivity type semiconductor region (n-type region)
6, 61, 62 Second conductivity type semiconductor region (p-type region)
7 Parallel pn structure 10 Thermal oxide film 11 Field oxide film 14 Channel stopper electrode 16 Field plate electrode 71, 72 Striped portion

Claims (16)

A parallel pn structure in which a first conductive type semiconductor region and a second conductive type semiconductor region are alternately arranged on a low resistance layer over an active region where current flows in an on state and a non-active region around the active region. In manufacturing a semiconductor device having
A first step of epitaxially growing a first conductivity type semiconductor on the low resistance layer;
A second step of forming a plurality of trenches at predetermined intervals in the epitaxial growth layer of the first conductivity type semiconductor;
A third step of filling the trench by epitaxial growth of a second conductivity type semiconductor;
A fourth step of polishing to flatten the surface of the parallel pn structure comprising the first conductive type semiconductor region remaining between the trenches and the second conductive type semiconductor region embedded in the trench;
A fifth step of ion-implanting a second conductivity type impurity into a flat region of the parallel pn structure which becomes an inactive region;
A sixth step of activating the second conductivity type impurity implanted in the parallel pn structure by heat treatment in a non-oxidizing atmosphere;
A seventh step of covering a part of the surface of the parallel pn structure with a field oxide film by thermal oxidation;
A method for manufacturing a semiconductor device, comprising:   The first conductivity type semiconductor regions and the second conductivity type semiconductor regions are alternately arranged so that a planar shape thereof forms a stripe shape. In the fifth step, the first conductivity type semiconductor regions and the second conductivity type semiconductor regions are arranged in regions that become inactive regions. In the parallel pn structure, impurities of a second conductivity type are selectively applied only to a stripe-shaped portion made of the first conductivity type semiconductor region and the second conductivity type semiconductor region that do not pass through the region that becomes the active region. The method for manufacturing a semiconductor device according to claim 1, wherein ions are implanted. The first conductivity type semiconductor region and the second conductivity type semiconductor region have a stripe-like planar shape on the low resistance layer over the active region where current flows in the on state and the inactive region around the active region. In manufacturing a semiconductor device having a parallel pn structure arranged alternately,
A first step of epitaxially growing a first conductivity type semiconductor on the low resistance layer;
A second step of forming a plurality of trenches at predetermined intervals in the epitaxial growth layer of the first conductivity type semiconductor;
A third step of filling the trench by epitaxial growth of a second conductivity type semiconductor;
A fourth step of polishing to flatten the surface of the parallel pn structure comprising the first conductive type semiconductor region remaining between the trenches and the second conductive type semiconductor region embedded in the trench;
Of the parallel pn structure flattened in a region to be an inactive region, a stripe-shaped portion made of the first conductive type semiconductor region and the second conductive type semiconductor region that do not pass through the region to be an active region, and an active region A fifth step of ion-implanting a second conductivity type impurity into both of the first conductivity type semiconductor region extending from the region to the inactive region and the stripe-shaped portion made of the second conductivity type semiconductor region;
A sixth step of activating the second conductivity type impurity implanted in the parallel pn structure by heat treatment in a non-oxidizing atmosphere;
A seventh step of covering a part of the surface of the parallel pn structure with a field oxide film by thermal oxidation;
A method for manufacturing a semiconductor device, comprising:   In the fifth step, the second conductivity type impurity is selectively ionized only in the first conductivity type semiconductor region and the second conductivity type semiconductor region in a part of the region which becomes the inactive region of the parallel pn structure. The method for manufacturing a semiconductor device according to claim 1, wherein implantation is performed.   4. In the fifth step, ions of a second conductivity type are selectively ion-implanted only into a second conductivity type semiconductor region of a region that becomes an inactive region of the parallel pn structure. The manufacturing method of the semiconductor element as described in any one of these.   In the fifth step, the second conductivity type impurity is selectively ion-implanted only into the second conductivity type semiconductor region in a part of the region which becomes the inactive region of the parallel pn structure. A method for manufacturing a semiconductor device according to claim 5.   4. In the fifth step, a second conductivity type impurity is selectively ion-implanted only in a first conductivity type semiconductor region of a region that becomes an inactive region of the parallel pn structure. The manufacturing method of the semiconductor element as described in any one of these.   In the fifth step, the second conductivity type impurity is selectively ion-implanted only in the first conductivity type semiconductor region in a part of the region which becomes the inactive region of the parallel pn structure. A method for manufacturing a semiconductor device according to claim 7. An eighth step of forming a field plate electrode covering the active region side end portion of the field oxide film on the non-active region and a channel stopper electrode covering the chip outer peripheral side end portion of the field oxide film on the non-active region; Including
  In the fifth step, the channel stopper electrode covers the portion located between the portion immediately below the channel stopper electrode side end portion of the field plate electrode and the field stopper electrode side end portion of the channel stopper electrode. 9. The method of manufacturing a semiconductor element according to claim 4, wherein the second conductivity type impurity is selectively ion-implanted only in a region excluding the region. A parallel pn structure in which a first conductive type semiconductor region and a second conductive type semiconductor region are alternately arranged on a low resistance layer over an active region where current flows in an on state and a non-active region around the active region. In manufacturing a semiconductor device having
  A first step of epitaxially growing a first conductivity type semiconductor on the low resistance layer;
  Forming a trench forming mask on the surface of the epitaxial growth layer of the first conductivity type semiconductor, and forming a plurality of trenches in the epitaxial growth layer of the first conductivity type semiconductor at predetermined intervals using the mask; Process,
  A third step of filling the trench by epitaxial growth of a second conductivity type semiconductor;
  A fourth step of flattening the surface of the mask formed in the second step and the second conductive type semiconductor region embedded in the trench by polishing;
  A second conductivity type impurity is ion-implanted into a part or all of the surface of the parallel pn structure composed of the first conductivity type semiconductor region remaining between the trenches and the second conductivity type semiconductor region buried in the trench. 5 steps,
  A sixth step of epitaxially growing a first conductivity type semiconductor on a surface of the parallel pn structure including a region into which a second conductivity type impurity is ion-implanted;
  Including
  In the fifth step, the second conductivity type semiconductor region buried in the trench in the third step is etched by approximately the thickness of the mask, and then the second conductive semiconductor region is self-aligned using the mask. A method of manufacturing a semiconductor device, characterized by ion-implanting two conductivity type impurities.   Part of a parallel pn structure comprising a first conductive type semiconductor region remaining between the trenches and a second conductive type semiconductor region embedded in the trenches between the fourth step and the sixth step, or A seventh step of ion-implanting a first conductivity type impurity into the entire surface;
  The dose amount of the first conductivity type impurity ion-implanted in the seventh step is approximately ½ of the dose amount of the second conductivity type impurity ion-implanted in the fifth step. A method for manufacturing a semiconductor device according to claim 10. In the fifth step, only the surface of the second conductive semiconductor region having a parallel pn structure composed of the first conductive semiconductor region remaining between the trenches and the second conductive semiconductor region buried in the trench is used. 12. The method of manufacturing a semiconductor device according to claim 10, wherein a second conductivity type impurity is selectively ion-implanted. The method of manufacturing a semiconductor element according to claim 11, wherein the seventh step is performed immediately before the fifth step. The method of manufacturing a semiconductor element according to claim 11, wherein the seventh step is performed immediately after the fifth step. 15. The seventh step according to claim 11, 13 or 14, wherein in the seventh step, a first conductivity type impurity is selectively ion-implanted only into a surface of the first conductivity type semiconductor region having a parallel pn structure. A method for manufacturing a semiconductor device. In the sixth step, on the surface of the parallel pn structure, a first conductivity type semiconductor having a thickness of about ½ of a repetition pitch of the first conductivity type semiconductor region and the second conductivity type semiconductor region of the parallel pn structure. The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor device is epitaxially grown.

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