JP2004128112A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of production yield degradation caused by dishing or eroding at flattening of a copper wiring, resulting in increase in variation of wiring resistances after flattening or in generation of shorting caused by the polishing residual of copper. <P>SOLUTION: With an oxidant, organic acid, anticorrosive, surfactants, polishing liquid of pure water, a polishing pad, a fixed abrasive table, and a dresser for dressing the surface of the polishing tool provided, the polishing liquid for fast polishing copper is supplied to the polishing pad for polishing in an initial process stage. In an intermediate process stage, a polishing liquid of high protrusion/recess selecting ratio is supplied to the fixed abrasive table for polishing to eliminate a residual step of the copper. In a later process stage directly below or after exposion of a barrier film, the polishing liquids are switched so that the copper and barrier films are polished almost at the same speed, and the dresser is driven for in-process conditioning. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a polishing or grinding technique for flattening a substrate surface, and more particularly to a method for manufacturing a semiconductor integrated circuit in which a thin film formed on a semiconductor substrate is polished or ground.
[0002]
[Prior art]
2. Description of the Related Art In recent years, a new fine processing technology has been developed in accordance with high integration and high performance of a semiconductor integrated circuit device (hereinafter, referred to as LSI). A chemical mechanical polishing method (Chemical Mechanical Polishing; also referred to as CMP) is one of the techniques, and is a technique frequently used in the LSI manufacturing process, particularly in the flattening of the interlayer insulating film, the formation of metal plugs, and the formation of embedded wiring in a multilayer wiring formation process. is there. This flattening technique is disclosed in, for example, Patent Document 1.
[0003]
In addition, recently, in order to achieve high-speed performance of LSI, it has been attempted to use a copper alloy having a low electric resistance from a conventional aluminum alloy as a wiring material. However, it is difficult to finely process a copper alloy by a dry etching method frequently used for forming an aluminum alloy wiring. Therefore, a tantalum, a tantalum alloy, a tantalum nitride, another tantalum compound, or the like is deposited as a barrier film on the processed insulating film having a groove to prevent copper diffusion into the insulating film. The so-called damascene method of depositing a copper or copper alloy thin film on the substrate and removing the copper or copper alloy thin film other than the portion buried in the groove formed in the insulating film by CMP to form a buried wiring is mainly used. Has been adopted. The wiring technique based on the damascene method is disclosed in, for example, Patent Document 2.
[0004]
A general method of metal CMP is to attach a polishing pad to a circular polishing platen (platen), immerse the polishing pad surface with a metal polishing solution, and press the surface of the substrate on which a metal film is formed, to form a substrate. The polishing platen is rotated while applying a predetermined pressure (hereinafter, referred to as a polishing pressure) from the back surface of the substrate, and the metal film on the convex portion is removed by mechanical friction between the polishing liquid and the convex portion of the metal film.
[0005]
Generally, an abrasive used for CMP of a metal such as a copper alloy used for wiring mainly contains solid abrasive grains and an oxidizing substance. The basic mechanism of CMP is to mechanically remove the oxide by solid abrasive grains while oxidizing the metal surface by the oxidizing action of the oxidizing substance. The mechanism of CMP is disclosed on page 299 of Non-Patent Document 1. As the solid abrasive grains, alumina abrasive grains and silica abrasive grains having a particle diameter of several tens to several hundreds of nm are known, but most of the commercially available solid abrasive grains for metal polishing are the former. Oxidizing substances include hydrogen peroxide (H ₂ O ₂ ), Ferric nitrate (Fe (NO ₃ ) ₃ ), Potassium periodate (KIO ₃ ) Are widely used in general, and these are disclosed, for example, in Non-Patent Document 1 at pages 299 to 300.
Further, the flattening of the STI layer using fixed abrasive grains is described in, for example, Patent Document 3.
[0006]
Conventional techniques using a plurality of polishing pads are disclosed in Patent Literature 4, Patent Literature 5, Patent Literature 6, Patent Literature 7, Patent Literature 8, Patent Literature 9, and the like.
[0007]
[Patent Document 1]
U.S. Pat. 4944836
[Patent Document 2]
JP-A-2-278822
[Patent Document 3]
JP 2000-49122 A
[Patent Document 4]
JP-A-2000-164595
[Patent Document 5]
JP-A-9-326392
[Patent Document 6]
JP 2001-135605 A
[Patent Document 7]
JP 2001-170858 A
[Patent Document 8]
JP 2001-332517 A
[Patent Document 9]
JP-T-2002-512894
[Non-patent document 1]
Edited by Masahiro Kashiwagi, "Science of CMP", August 20, 1997 (published by Science Forum Inc.), pp. 299 and 300.
[Non-patent document 2]
"Journal of Electrochemical Society (J. Electrochem. Soc.)", Vol. 141, No. 10, October 1994, p. 2842-2848
[Non-Patent Document 3]
"New Materials and Process Technologies for Next-Generation ULSI Multilayer Wiring", Technical Information Association, p. 242-246
[0008]
[Problems to be solved by the invention]
However, in the above-described prior art, there is a problem that the polishing rate is high but the flatness is insufficient, or the polishing rate is insufficient even though the flatness is high. Furthermore, if the step between the surface of the convex portion of the deposited Cu film and the bottom surface of the concave portion is referred to as a Cu residual step or a residual step, no consideration is given to the change and the polishing solution, and There are (1) insufficient flatness and (2) high cost.
(1) Since the polishing pad is soft (for example, a polishing pad made of polyurethane and has a compression modulus of 100 MPa or less), the polishing pad is deformed into irregularities by a force pressing the substrate surface, and the insulating film is formed. The phenomenon that the central part of the surface of the metal wiring embedded in the groove formed in the trench is excessively polished and dented (hereinafter referred to as dishing) from the peripheral part and the phenomenon that the surface of the insulating film around the wiring part is excessively polished ( (Hereinafter referred to as erosion) (FIG. 11). Further, tantalum, tantalum alloys, tantalum nitride, and other tantalum compounds used as barrier films are chemically stable and difficult to etch, and have high hardness, so that mechanical polishing is not as easy as copper and copper alloys. Therefore, when the hardness of the abrasive grains is increased, polishing scratches occur in copper or a copper alloy, which causes electrical characteristics failure. When the particle concentration of the abrasive grains is increased, the polishing rate of the insulating film is increased. And erosion is likely to occur.
[0009]
Further, it is known that in a CMP of a wafer in which a metal film is deposited on an insulating film in which a groove serving as a wiring pattern is formed, a portion which is locally excessively polished occurs. This is because unevenness reflecting grooves serving as wiring patterns is formed on the surface of the metal film on the wafer surface before CMP, and when CMP is performed, locally high pressure is applied in accordance with the pattern density, and the This is because the polishing rate increases. Therefore, dishing or erosion is a significant problem in a pad having a large metal area (area of about 0.1 mm square) or a dense wiring pattern. These are described in Journal of Electrochemical Society, Vol. 141, No. 10, October 1994 (see Non-Patent Document 2). When dishing or erosion in which the wiring surface is depressed occurs, as a result, the variation width of the wiring resistance value increases. In particular, this is an important issue in a logic device called a system LSI having a multilayer wiring structure as shown in FIG. That is, as shown in FIG. 11, when the flatness of the lower layer is low, the flatness is impaired more than the performance of CMP, and a short circuit or disconnection between wirings due to unpolished residue easily occurs, which causes a fatal defect. Become. This content is disclosed in "New Material and Process Technology for Next-Generation ULSI Multilayer Wiring" Technical Information Association (see Non-Patent Document 3).
(2) There is a problem that the cost of consumables used for CMP is high. This is because the production cost of the abrasive used as the abrasive is high, and extreme care is required to make the particle size uniform, maintain the particle size, and remove impurities. In particular, alumina abrasive grains are several times more expensive than silica abrasive grains. Further, foamed polyurethane is generally used for the polishing cloth. When the CMP is performed, abrasive grains adhere to the polishing cloth, causing a so-called "clogging" phenomenon, and the polishing rate is reduced. In order to prevent this, it was necessary to sharpen the polishing cloth surface with a grindstone (hereinafter, referred to as a conditioner) to which diamond particles were appropriately fixed. As a result, the life of the polishing cloth has been shortened, and it has become a high-cost consumable item next to abrasive grains. The cost of the CMP process is described in, for example, “Latest Trends in CMP Equipment and Related Materials and Their Problems” in May 1996, the latest technical course by Realize.
[0010]
The present invention has been made in view of the above points, and (1) suppresses the occurrence of dishing and erosion when forming embedded wiring while maintaining a high polishing rate. (2) Reduces the cost of a polishing liquid and a polishing cloth. It is an object to provide a method for manufacturing a semiconductor device which can be reduced.
[0011]
[Means for Solving the Problems]
Means for achieving the above objects (1) and (2) will be described in detail with reference to FIG. Polishing is performed by supplying a polishing agent solution onto a polishing tool fixed to a rotary platen, and moving the wafer substrate relative to the polishing tool while applying pressure to the wafer substrate. The polishing process is divided into three stages: high-speed polishing of Cu (process I), elimination of residual steps of Cu (process II), and polishing of a barrier film (process III). First, in step I, a polishing pad is used as a polishing tool, and a Cu polishing liquid 1 is supplied onto the polishing pad to polish Cu at a high polishing rate. Next, in the step II, the polishing tool is switched to the fixed abrasive disk, and the Cu polishing liquid 2 having a higher concentration of the surfactant than the polishing liquid 1 is supplied to eliminate the Cu residual step before the barrier film is exposed. Further, by switching to the barrier film polishing liquid at the stage of the process III immediately before or immediately after the exposure of the barrier film and dressing the surface of the fixed abrasive disk during the processing, the damascene flattening of the copper wiring is efficiently achieved.
[0012]
Next, the reason will be described. Assuming that the polishing rate of the Cu convex portion is R1 and the polishing speed of the Cu concave portion is R2, the ratio R1 / R2 of the polishing speed of the convex portion and the concave portion (hereinafter, referred to as the convex / concave selectivity) changes depending on the remaining step. That is, it has dependency on the remaining step. Furthermore, the residual step difference dependence of the unevenness selectivity differs depending on the combination of the polishing tool and the polishing liquid (FIG. 7A). In the conventional technique using only a polishing pad and a polishing liquid, the unevenness selectivity has a maximum value immediately after the start of polishing, and gradually approaches 1 as polishing progresses and the Cu step is eliminated. On the other hand, in the present invention, by using a fixed abrasive disc, a higher unevenness selectivity is maintained than in the prior art, so that a highly flattened shape after processing is achieved. When the unevenness selectivity reaches 1 before the Cu residual step is eliminated, it means that the residual step at the time when the unevenness selectivity becomes 1 is continuously maintained until the polishing of the copper film is completed (barrier film exposure). That is, it is understood that the remaining step cannot be eliminated by the conventional technique (FIG. 7B). Assuming that the ratio of the polishing rate of the convex portion to the concave portion, which is the minimum required for eliminating the Cu step and flattening, is n (hereinafter, referred to as a required selection ratio), the required selection ratio n is the remaining film thickness. It is expressed as a function of the ratio between the remaining step and the remaining step. That is, the necessary selection ratio n is uniquely determined from the geometrical shape of the remaining film thickness and the remaining step (FIG. 12). In general planarization of Cu damascene wiring, the relationship between the film thickness of the copper film before processing and the remaining step is the remaining film thickness / the remaining step ≒ 2, and the necessary selection ratio n ≒ 2. As the processing proceeds and the remaining step is eliminated, the ratio of remaining film thickness / remaining step tends to be smaller than 2. That is, when the value of remaining film thickness / remaining step becomes smaller than 2 (approaches 1), the necessary selection ratio n sharply increases as is apparent from FIG. Therefore, it is desirable to perform processing so that the necessary selection ratio n is made as small as possible.
[0013]
Here, if the unevenness selectivity R1 / R2 is always higher than the required selectivity n, the remaining film thickness of the copper film reaches zero (before the barrier film is exposed) (if R1 / R2 ≧ n). Means that the step existing in the copper film can be eliminated. It is desirable that the step of the copper film can be eliminated before the barrier film is exposed, because the effect of suppressing dishing and erosion that may occur during polishing of the barrier film subsequent to polishing of the copper film is remarkably improved.
[0014]
The timing at which the polishing tool 1 and the Cu polishing liquid 1 are switched to the polishing tool 2 and the Cu polishing liquid 2 is determined by the selection ratio R1 / R2 of Cu between the polishing tool 1 and the Cu polishing liquid 1 in the process I. It is desirable that the ratio be less than the required selection ratio n calculated from the film thickness and the Cu residual step, and it is more desirable that Cu residual film thickness / Cu residual step be greater than 2.
[0015]
It is preferable that the above-mentioned unevenness selectivity R1 / R2 ≧ 2 of the Cu polishing liquid 1 and the unevenness selectivity R1 / R2 ≧ 3 of the Cu polishing liquid 2 be satisfied. It is further preferable that the unevenness selectivity R1 / R2 ≧ 5 of the liquid 2 is satisfied.
[0016]
The Cu polishing liquids 1 and 2 are composed of an oxidizing agent, an organic acid, an anticorrosive, a surfactant, and pure water, and are supplied in a predetermined amount during processing.
[0017]
As an oxidizing agent for the Cu polishing liquids 1 and 2, hydrogen peroxide is particularly preferable because it does not contain a metal component and is not a strong acid.
[0018]
As the organic acid of the Cu polishing liquids 1 and 2, malic acid is desirable as the acid used in the polishing liquid of the present invention from the viewpoint of a high polishing rate and a low etching rate. Malic acid is also commonly used as a food additive, and is particularly desirable as an acid used in the polishing liquid of the present invention because of its low toxicity, low harm as a waste liquid, no odor, and high solubility in water.
[0019]
The amount of malic acid used as the organic acid in the Cu polishing liquids 1 and 2 is preferably 0.1% by weight or more from the viewpoint of the Cu polishing rate.
[0020]
As the anticorrosive for the Cu polishing liquids 1 and 2, any substance can be used as long as mixing with the polishing liquid suppresses etching and provides a sufficient polishing rate. In particular, benzotriazole (hereinafter referred to as BTA) is highly effective and desirable as an anticorrosive substance for copper alloys.
[0021]
The addition amount of BTA used as an anticorrosive for the Cu polishing liquids 1 and 2 is preferably 0.1% by weight or more from the viewpoint of the polishing rate and the anticorrosion effect.
[0022]
It goes without saying that imidazole and its derivatives can be used instead of BTA as the anticorrosive for the Cu polishing liquids 1 and 2.
[0023]
As the surfactant of the above Cu polishing liquids 1 and 2, an acrylic acid polymer and its ammonium salt are desirable as the surfactant used in the polishing liquid of the present invention from the viewpoint of a high polishing rate and a low etching rate.
[0024]
As the molecular weight of the surfactant of the Cu polishing liquids 1 and 2, a molecular weight of 5,000 or more is preferable because the dishing suppressing effect is large.
[0025]
The polishing rate characteristics of the polishing liquid for each material are as shown in FIG. 6, and the polishing rate ratio (material selection ratio) of each material can be controlled by the concentration of the oxidizing agent.
[0026]
The concentration of hydrogen peroxide in the Cu polishing liquid 1 and the Cu polishing liquid 2 is preferably 0.05 vol% or more, and 30 vol% is particularly preferable because the Cu polishing rate can be increased.
[0027]
The aqueous hydrogen peroxide concentration of the above-mentioned barrier film polishing solution is preferably 10% by volume or less, and 5% by volume is particularly preferable because the polishing rate of the barrier film can be made equal to the polishing rate of Cu.
[0028]
The object of (2) reducing the cost of the polishing liquid and the polishing cloth is achieved by using a polishing liquid containing no solid abrasive grains. If solid abrasive grains are not contained in the polishing liquid, clogging of the polishing pad is dramatically reduced, and the number of times of conditioning by the diamond dresser can be reduced, so that the life of the polishing pad can be extended, which is desirable for cost reduction. .
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
(Example 1)
Hereinafter, the device configuration of the present embodiment will be described with reference to FIGS. The present invention is not limited by these examples. In the drawings, the same function is denoted by the same reference numeral. The apparatus includes a polishing tool 1 and a polishing tool 2 for flattening a wafer, a head 3 for holding a wafer, a swing arm 4 for swinging the head, a rotating platen 10 on which the polishing tool 1 and the polishing tool 2 are bonded and rotated, It has polishing liquid supply systems 6, 7 and 8 for supplying a polishing liquid onto the polishing tool 1 and the polishing tool 2, and a dresser 5 for dressing in order to recover the polishing capability of the polishing tool. The head 3 can hold the wafer 9 and rotate in the same direction as the rotary platen 10, and also has a function of pressing the wafer surface against a polishing tool and applying a load with a predetermined force. Further, a retainer ring (not shown) is provided so that the wafer does not come off during the CMP. The polishing liquid is dropped from the supply system at a rate of 100 to 300 cc / min. As shown in FIG. 1, there are three polishing liquid supply systems in the present invention. These three types of polishing liquids can switch the respective liquids and control the flow rate. The dresser 5 can be dressed with a predetermined pressure. The dresser is equipped with a ring-type dresser to which diamond abrasive grains are fixed, and can be arbitrarily rotated up to about 200 revolutions per minute. Needless to say, this dresser is configured so that the entire surface of the polishing tool can be conditioned.
[0030]
In the present embodiment, a fixed abrasive disc, which was originally developed as a polishing tool 2, was a polishing pad IC1000 made of foamed polyurethane made by Rodale Co., Ltd. as a polishing tool 1 for these series of processing processes. This fixed abrasive disk has a laminated structure of a grindstone and an elastic pad (hereinafter, referred to as a laminated fixed abrasive disk), and can be dressed by a constant pressure dressing method of dressing at a constant pressure, similarly to the IC000. The wafer polishing load during polishing was 210 g / cm 2, and the rotation speeds of the rotating platen and the head were both 46 rpm (53 cm / sec in terms of linear velocity). The polishing load and the number of rotations are not limited to these. Generally, the polishing rate is increased by increasing the load and the number of revolutions of the platen, but scratches are likely to occur. However, in the present invention, since the concentration of free abrasive grains in the polishing liquid is low or not contained, the occurrence of polishing scratches with respect to the load is small. Before processing the wafer, the surfaces of the polishing pad and the lamination-type fixed abrasive disc are dressed by a dresser 5. The polishing pad 1 is supplied with the Cu polishing liquid 1 for polishing. At this time, the dresser 5 is stopped at a position away from the surface of the polishing pad.
[0031]
Next, the polishing liquid will be described. First, a preliminary experiment was performed using a wafer on which a wiring pattern was not formed in order to determine the proportion of hydrogen peroxide solution that is an oxidizing agent for the Cu polishing liquid and the barrier film polishing liquid. The sample is obtained by forming a 200-nm-thick silicon oxide film on a silicon wafer and then continuously forming a 50-nm-thick TaN film and an 800-nm-thick copper film as an adhesive layer in a vacuum by a sputtering method. The wafer diameter is 8 inches. Before and after the polishing, the sheet resistance was measured with a four-probe resistance meter, and the change in the sheet resistance value was converted to obtain the polishing rate. As shown in FIG. 6, the concentration of the hydrogen peroxide solution and the polishing rate characteristics of each material are as shown in FIG. 6. For both the polishing pad and the fixed abrasive disk, the characteristic that the polishing rate of copper becomes maximum when the hydrogen peroxide solution concentration is 30% by volume is obtained. Was. That is, when the hydrogen peroxide concentration is 30% by volume, a desirable effect that the processing time of one wafer can be shortened most and the throughput is improved is produced.
[0032]
Next, a sectional structure of the wafer 9 to be processed will be described with reference to FIG. In this drawing, the silicon portion of the wafer substrate is omitted, and only the configuration of the oxide film 15, the barrier film 16, and the copper film 17 is shown. It goes without saying that oxide film 15 may be a low dielectric constant material other than the silicon dioxide film, or may be a layer pair of an oxide film and a low dielectric constant material. A wiring groove is formed in the oxide film 15, a barrier film 16 for preventing copper diffusion into the oxide film is formed thereon, and a copper film 17 is further formed.
[0033]
Next, the polishing process in the present embodiment will be considered with reference to FIG. 5 by dividing into three stages of high-speed polishing of Cu (step I), elimination of residual steps of Cu (step II), and polishing of a barrier film (step III).
[0034]
In step I, a polishing pad is used as a polishing tool, and a Cu polishing liquid 1 is supplied onto the polishing pad to polish Cu at a high polishing rate. From the viewpoint of increasing the polishing rate of Cu, referring to the results of preliminary experiments, 30% by volume of hydrogen peroxide solution (commercially available 30% by volume concentration) as an oxidizing agent, 0.15% by weight of malic acid as an organic acid, As the anticorrosive, benzotriazole (BTA) was used in an amount of 0.2% by weight, and a Cu polishing liquid 1 in which a surfactant was adjusted so that the roughness selectivity R1 / R2 was about 2 was used.
[0035]
In the step II, the polishing tool is switched to the fixed abrasive disk, the Cu polishing liquid 2 is supplied, and the residual Cu step is eliminated before the barrier film is exposed. From the viewpoint of high flatness, referring to the results of the preliminary experiment, 30% by volume of aqueous hydrogen peroxide (commercially available 30% by volume concentration) as an oxidizing agent, 0.15% by weight of malic acid as an organic acid, and as an anticorrosive A Cu polishing liquid 2 in which benzotriazole (BTA) was 0.2% by weight and a surfactant was adjusted so that the roughness selectivity R1 / R2 was about 3 was used.
[0036]
In the process III, the barrier film polishing liquid is switched immediately before or immediately after the barrier film is exposed, and the damascene flattening of the copper wiring is efficiently achieved by dressing the surface of the fixed abrasive disk during the processing. From the viewpoint of preventing excessive removal of copper and oxide film such as dishing and erosion, refer to the results of preliminary experiments and adjust the oxidizing agent concentration so that the polishing rate ratio between copper and barrier film when using dressing during processing is 1: 1. Was used.
[0037]
In this embodiment, the removal of copper proceeds in step I of FIG. 5, and when the remaining film thickness of the copper film becomes about 320 nm and the remaining step becomes about 150 nm, the polishing tool is changed from the IC 1000 to a laminated fixed abrasive disc, The polishing liquid was also switched from Cu polishing liquid 1 to Cu polishing liquid 2 (Step II). When the remaining film thickness of the copper film is 320 nm and the remaining step is about 150 nm, the necessary selection ratio n is 1.88, and the unevenness selection ratio R1 / R2 between the laminated fixed abrasive disk and the Cu polishing liquid 2 is At 2.33, the required selection ratio n was exceeded, and flattening was performed while suppressing dishing. When the removal of copper further progressed and the state immediately before the barrier film was exposed was reached, the Cu polishing liquid 2 was switched to the barrier film polishing liquid (step III). In this embodiment, the polishing liquid supply system 2 may be stopped and the supply of the polishing liquid may be changed from the polishing liquid supply system 3 to the supply of the barrier film polishing liquid.
[0038]
In-process dressing in the process III means that the dresser 5 is lowered until the dresser 5 comes into contact with the surface of the lamination-type fixed abrasive disc, which is the polishing tool 2, and the diamond particles are brought into contact with the surface of the lamination-fixed abrasive disc, and the crushed resin is removed. This is a function that removes abrasive grains and exposes new abrasive grains and generates loose abrasive grains. The dressing pressure of the dresser 5 may be the same as that when the IC 1000 as the polishing tool 1 is dressed before processing, or may be further increased by about 5 kg. By increasing the dress pressure, more free abrasive grains 19 are generated, and the polishing rate of the barrier film 16 can be further improved, which is desirable.
[0039]
When the barrier film 16 is removed and the oxide film 15 is exposed, the processing ends. When removing the barrier film, if the barrier film polishing rate is not uniform in the wafer plane, the polishing may be performed with a longer time set than the processing time obtained from preliminary experiments (over polishing). If the polishing rate of the oxide film 15 is much lower than that of the barrier film 16 or the copper film 17, over-polishing can prevent the copper film or the barrier film from being left unpolished, which is desirable. Further, when the polishing rate of the oxide film 15 is much lower than that of the barrier film 16 or the copper film 17, it is possible to prevent the film from being reduced during overpolishing, which is desirable. For example, when the polishing time until most of the barrier film on the surface to be processed is removed is referred to as “just polishing time”, the total polishing time is reduced from 1.3 to 1 of the just polishing time in order to prevent remaining polishing. It is preferable to over-polish by about 0.5 times.
[0040]
As a result of processing an 8-inch diameter wafer with a pattern by applying the above flattening method, the result of FIG. 7B was obtained. The relative residual steps in FIGS. 7B and 7A are expressed as relative values with the initial step of the copper film at the start of polishing of the wafer used in FIG. The initial step height of the copper film of the wafer used in FIG. 7B is 350 nm, the initial thickness of the copper film is 750 nm, and the pattern used is a so-called line & space in which copper wiring is periodically arranged. is there. The horizontal axis in FIG. 7B is the relative remaining film thickness of the copper film of this patterned wafer, and the vertical axis is the remaining step difference of the copper film. In the conventional CMP using only the resin polishing pad, the residual step cannot be eliminated even if the residual film thickness of the copper film reaches zero, whereas in the present invention, the residual film thickness of the copper film becomes zero. Before reaching, that is, before the barrier film is exposed, the remaining step can be made zero, and it can be seen that extremely high flattening performance has been demonstrated as compared with the conventional technology. This high planarization performance is caused by switching to a polishing tool and a polishing solution that can obtain a higher selectivity in consideration of the dependency of the processing selectivity of the copper convex and concave portions on the residual step difference. This is the effect of the high processing selectivity of the copper projections and depressions due to the use of the laminated fixed abrasive disc having a compression elastic modulus of 3 to 10 times higher than that of the CMP pad in the second stage of Cu polishing ( (FIG. 7A).
[0041]
In this embodiment, a CMP apparatus having a two-platen structure is used. However, the present invention can be implemented as long as the CMP apparatus has the above-described functions. For example, a CMP apparatus MIRRRA MESA manufactured by Applied Materials is used. You can do it. In this case, the present invention can be implemented by installing a CMP pad as the polishing tool 1 on the first platen and installing a fixed abrasive disk as the polishing tool 2 on the second platen. In this embodiment, a polishing tool installed on a rotary platen was used. However, a belt-type polishing tool was used as the polishing tool 1, and a hard polishing pad on which abrasive grains were fixed was used as the polishing tool 2. Needless to say, it is good. Further, in this embodiment, a polishing tool installed on a rotary platen is used as a polishing tool, but it goes without saying that a small-diameter polishing tool smaller than the wafer diameter may be used. Further, in the present embodiment, the polishing liquid is dropped on the polishing tool surface, but it is needless to say that the polishing liquid may flow out of the polishing tool. It goes without saying that imidazole can be used instead of BTA as an anticorrosive.
[0042]
Further, since the present invention is carried out by performing a two-stage polishing in the Cu polishing step, if the selectivity between the convex portions and the concave portions of Cu can be sufficiently high, the polishing tool can be changed by changing only the polishing liquid without changing the polishing tool. Needless to say, it is good.
[0043]
(Example 2)
In the present embodiment, a method of realizing Cu damascene wiring flattening by using an ordinary fixed abrasive disc that does not have an elastic pad under a grindstone as a polishing tool 2, that is, is not a laminated type will be described. As shown in FIG. 4, when an ordinary fixed abrasive disk that is not a lamination type is used for the polishing tool 2, a method using a fixed size cut (a fixed size dressing method) can be used as the dressing of the polishing tool 2. In this fixed-size dressing system, the distance between the diamond tool and the grinding wheel is kept constant while rotating a ring or disc with a diameter of 30 to 70 mm embedded with hard abrasive grains such as diamond at a high speed of 3000 to 10000 revolutions per minute. The fixed abrasive grain surface can be dressed accurately by a method of cutting by relatively moving the inside of the grindstone surface. Specifically, it can be realized by scanning the surface of the fixed abrasive disc while controlling the absolute height position so that the surface of the fixed abrasive disc is only about 1 μm deep and only the very surface layer is removed. In such a fixed size cutting process, if the positioning accuracy of the tool height is increased, a higher flatness can be obtained in principle. Since the grinding amount of the fixed abrasive disc by dressing is usually 10 μm or less, if the thickness of the fixed abrasive disc is 10 mm, it can be expected that the fixed abrasive disc will reach the use limit at the time of processing 1000 wafers. . It is obvious that reducing the grinding amount of the fixed abrasive disc by dressing further extends the life of the fixed abrasive disc.
[0044]
Also in this example, when the removal of copper progressed and the residual step of the copper film became about 150 nm, the polishing tool was changed from the IC 1000 to a fixed abrasive disk, and the polishing liquid was changed from the Cu polishing liquid 1 to the Cu polishing liquid 2. Switch. Also in this embodiment, as already described in the first embodiment, the component composition of the Cu polishing liquid 2 is the same as that of the Cu polishing liquid 1, and the added concentration of the surfactant is different. This addition concentration is adjusted so that the ratio of the polishing rate of the convex portion to the concave portion of the copper becomes large and the polishing rate of the copper becomes as high as possible. Further, when the removal of copper proceeds and the state of step III is reached, the Cu polishing liquid 2 is switched to the barrier film polishing liquid. Also in this embodiment, the polishing liquid supply system 2 may be stopped and the supply of the polishing liquid from the polishing liquid supply system 3 may be changed. The constituent components of the barrier film polishing liquid are the same as those of the polishing liquid 2. The component ratio is adjusted by adjusting the concentration of the oxidizing agent and using dressing during processing, which will be described later, to reduce the polishing rate ratio between copper and the barrier film to 1: 1. It was made to become. This is preferable because it is possible to prevent excessive removal of copper or an oxide film such as dishing or erosion.
[0045]
The dressing in the process III means that the dresser 5 is lowered until the dresser 5 comes into contact with the surface of the fixed abrasive disc, which is the polishing tool 2, and the diamond grains are brought into contact with the fixed abrasive disc face to remove the crushed resin and to form a new abrasive grain face. And the function of generating loose abrasive grains. The positioning height position of the dresser may be the same position as the position dressed before the flattening process in step II, or may be further cut by about 1 μm. By cutting, more free abrasive grains 19 are generated, and the polishing rate of the barrier film 16 can be further improved, which is desirable.
[0046]
Next, when the barrier film 16 is removed and the oxide film 15 is exposed, the processing ends. When removing the barrier film, if the polishing rate of the barrier film is not uniform in the wafer plane, the polishing may be performed with a longer setting than the processing time obtained from preliminary experiments (over polishing). If the polishing rate of the oxide film 15 is much lower than that of the barrier film 16 or the copper film 17, over-polishing can prevent the copper film or the barrier film from being left unpolished, which is desirable. Further, when the polishing rate of the oxide film 15 is much lower than that of the barrier film 16 or the copper film 17, it is possible to prevent the film from being reduced during overpolishing, which is desirable. For example, when the polishing time until most of the barrier film on the surface to be processed is removed is referred to as “just polishing time”, the total polishing time is reduced from 1.3 to 1 of the just polishing time in order to prevent remaining polishing. It is good to make it about 5 times.
[0047]
As a result of processing the patterned wafer by applying the above-mentioned flattening method, the result of FIG. 8 was obtained over the entire surface of the wafer. The pattern used is a so-called line & space in which copper wirings are arranged periodically, and the width of one line is 20 μm and the length of the line is 1900 μm. The horizontal axis represents the distance between the patterns, and the vertical axis represents the sum of dishing and erosion. It can be seen that higher planarization performance can be demonstrated as compared to conventional CMP using only a resin polishing pad. This high flattening performance is caused by the use of a polishing solution containing no abrasive grains and a second-stage Cu polishing using a fixed abrasive disc having a compression modulus of 3 to 10 times higher than that of a conventional CMP pad. This is the effect of the high processing selection ratio between the part and the concave part (FIG. 7A).
[0048]
One of the problems when flattening with a hard fixed abrasive disc is scratching. The fixed abrasive disk of the present invention has high-purity silica fine abrasive particles dispersed and fixed uniformly. Therefore, scratches are unlikely to occur because they do not contain foreign matter or large-diameter particles that cause scratches. FIG. 9 shows the result of measuring the surface shape after processing a copper pattern of 120 μm square. The width of the irregularities on the surface was 10 nm or less, and it was confirmed that the surface had a mirror surface sufficient for semiconductor wiring.
[0049]
(Example 3)
In the first and second embodiments, the entire surface of the fixed abrasive disc serving as the polishing tool 2 was dressed by the dresser 5 before the flattening process, so that the fixed abrasive grains 18 were exposed on the surface of the fixed abrasive disc. Is also possible. This is because it is already known that the copper film 17 can be processed even without abrasive grains, so dressing before processing is not necessarily indispensable. In addition, since the life of the fixed abrasive disc is determined by the reduction in thickness due to dressing, the frequency of dressing should be reduced as much as possible, which is preferable from this viewpoint. Therefore, it is possible to perform the flattening process of the semiconductor wiring structure in which the dressing before the processing is omitted in the steps in the first and second embodiments. According to the present embodiment, in addition to flattening the damascene wiring structure using copper at low cost, high throughput, and high flattening, a great effect that a longer life of the fixed abrasive disk can be achieved can be expected.
[0050]
(Example 4)
An embodiment in which the present invention is actually applied to a semiconductor device will be described with reference to FIG. This structure is a cross section of a six-layer multilayer wiring logic device. After a shallow trench isolation trench (STI) is formed on the surface of the silicon substrate 23 by an oxide film flattening technique, a gate pattern 22 and the like are formed to form a transistor. Thereafter, a W contact plug 21 with the upper wiring layer is formed by W flattening processing technology. The barrier film 20 is formed on the interface between the W plug and the insulating film, similarly to the copper wiring structure. All layers above the W plug are copper wiring layers, and all six layers are formed using the present invention. Since the underlayer is flat, good flattening without the problem of unsatisfactory electrical shorting due to polishing residue, dishing, erosion, or scratching described with reference to FIG. 11 can be performed. In addition, it goes without saying that a flattened semiconductor device can be manufactured by applying the flattening using the fixed abrasive to the STI layer and the W plug.
[0051]
【The invention's effect】
According to the present invention, the sum of dishing and erosion during the formation of embedded wiring can be halved to less than 40 nm over the entire surface of the wafer while maintaining a high polishing rate. As a result, the yield can be improved, such as reduction in variation in wiring resistance value and reduction in disconnection failure. Further, the cost of the polishing liquid and the polishing cloth can be reduced.
[Brief description of the drawings]
FIG. 1 is a front view illustrating the configuration of an apparatus according to an embodiment.
FIG. 2 is a side view for explaining the device configuration of the present embodiment.
FIG. 3 is a side view illustrating an apparatus configuration of the present embodiment.
FIG. 4 is a side view illustrating an apparatus configuration of the present embodiment.
FIG. 5 is a diagram illustrating a processing step of the present embodiment.
FIG. 6 is a diagram illustrating the concentration of a processing chemical oxidant and a polishing rate according to the present embodiment.
FIG. 7 is a diagram illustrating the flattening performance of the present embodiment.
FIG. 8 is a diagram illustrating the flattening performance of the present embodiment.
FIG. 9 is a diagram for explaining a copper surface shape after flattening in this example.
FIG. 10 is a diagram illustrating a cross section of a semiconductor device having a multilayer wiring structure.
FIG. 11 is a diagram illustrating a problem associated with insufficient flattening performance.
FIG. 12 is a diagram illustrating the dependence of the required selectivity on the remaining step and the remaining film thickness in this embodiment.
[Explanation of symbols]
1. Polishing tools 1, 2,. Polishing tools 2, 3, 2. Head, 4. Swing arm, 5. Dresser, 6. Polishing liquid supply system 1,7. 7. Polishing liquid supply system 2,8. Polishing liquid supply system 3,9. Wafer, 10. Rotating platen, 11. Reference plane, 12. Cu polishing liquid 1, 13. 13. Cu polishing liquid 2, 14 14. barrier film polishing liquid; Oxide film, 16. Barrier film, 17. Copper film, 18. Fixed abrasive, 19. Loose abrasives, 20. 21. W plug barrier film W plug, 22. Gate, 23. Silicon substrate, 24. substrate.

Claims (18)

Forming a first conductive film and a second conductive film on an insulating film having an opening on a substrate;
Removing a part of the first conductive film and the second conductive film by processing with a polishing tool, and leaving the first conductive film and the second conductive film in the opening; With
A method for manufacturing a semiconductor device, comprising a step of using a first polishing tool for processing the second conductive film and switching to a second polishing tool during the processing of the second conductive film. Forming a first conductive film and a second conductive film on an insulating film having an opening on a substrate;
Removing a part of the first conductive film and the second conductive film by processing with a polishing tool, and leaving the first conductive film and the second conductive film in the opening; With
A method for manufacturing a semiconductor device, comprising: using a first polishing tool for processing the second conductive film; and using a second polishing tool for processing the first conductive film. The first polishing tool is provided with a material having a first compression modulus, and the second polishing tool is provided with a material having a compression modulus higher than the first compression modulus. 2. The method for manufacturing a semiconductor device according to claim 1, wherein: 2. The method according to claim 1, wherein the first polishing tool is a polishing pad, and the second polishing tool is a fixed abrasive disk. Assuming that the polishing rate of the convex portion of the second conductive film is R1 and the polishing speed of the concave portion is R2, a ratio R1 / R2 of the polishing speed of the convex portion and the concave portion of the second conductive film in the second polishing tool 2. The method of manufacturing a semiconductor device according to claim 1, wherein the ratio is larger than a ratio of a polishing rate of the convex portion to a concave portion of the second conductive film in the first polishing tool. 2. The method according to claim 1, wherein a ratio R1 / R2 of a polishing rate between the convex portion and the concave portion of the second conductive film satisfies R1 / R2> 1. 3. 2. The method according to claim 1, wherein a polishing liquid supplied to the first polishing tool and a polishing liquid supplied to the second polishing tool are different. Forming an insulating film on the substrate, forming an opening in the insulating film,
Forming a first conductive film over the opening and the insulating film;
Forming a second conductive film on the first conductive film;
Processing a part of the first conductive film and the second conductive film using a polishing tool to form the first conductive film and the second conductive film in the opening;
A first polishing tool and a first polishing liquid are used for processing the second conductive film, and the processing is switched to a second polishing tool and a second polishing liquid during the processing of the second conductive film; The method of manufacturing a semiconductor device, further comprising: a step of dressing the surface of the second polishing tool during processing before the first conductive film is exposed; and a step of switching to a third polishing liquid. Method. The method according to claim 8, wherein the first polishing tool is a polishing pad, and the second polishing tool is a fixed abrasive disk. 2. The method according to claim 1, wherein the first and second polishing liquids include an oxidizing agent, an organic acid, an anticorrosive or a surfactant, and pure water. 2. The method according to claim 1, wherein the first, second, and third polishing liquids have different amounts of surfactant added thereto. 3. 2. The method according to claim 1, wherein the first and second polishing liquids have different surfactant molecular weights. 3. 2. The method according to claim 1, wherein the first, second, and third polishing liquids have different amounts of anticorrosive added to each other. 3. The method according to claim 1, wherein the first and second polishing liquids have different anticorrosive agents. 2. The method according to claim 1, wherein the second and third polishing liquids have different amounts of an oxidizing agent. 2. The method according to claim 1, wherein the second and third polishing liquids have different amounts of organic acid added. 3. Hydrogen peroxide water as an oxidizing agent of the first and second polishing liquids, malic acid as an organic acid, benzotriazole or a derivative thereof as an anticorrosive, an acrylic acid polymer and its ammonium salt as a surfactant, and pure solvent as a solvent A method for manufacturing a semiconductor device, comprising water. 9. The method according to claim 1, wherein the first conductive film contains tantalum, a tantalum alloy, or a tantalum compound, and the second conductive film contains copper, an alloy containing copper as a main component, or a copper compound. Manufacturing method of a semiconductor device.

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