JP2007103868A - Printed circuit board for electronic component package and manufacturing method thereof - Google Patents
Printed circuit board for electronic component package and manufacturing method thereof Download PDFInfo
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- JP2007103868A JP2007103868A JP2005295344A JP2005295344A JP2007103868A JP 2007103868 A JP2007103868 A JP 2007103868A JP 2005295344 A JP2005295344 A JP 2005295344A JP 2005295344 A JP2005295344 A JP 2005295344A JP 2007103868 A JP2007103868 A JP 2007103868A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 238000007747 plating Methods 0.000 claims abstract description 118
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 96
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 68
- 239000010931 gold Substances 0.000 claims abstract description 62
- 229910052737 gold Inorganic materials 0.000 claims abstract description 62
- 238000000034 method Methods 0.000 claims abstract description 55
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 47
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910052802 copper Inorganic materials 0.000 claims abstract description 41
- 239000010949 copper Substances 0.000 claims abstract description 41
- 238000005530 etching Methods 0.000 claims abstract description 25
- 238000004381 surface treatment Methods 0.000 claims abstract description 9
- 239000007769 metal material Substances 0.000 claims description 5
- 238000009713 electroplating Methods 0.000 abstract description 8
- 239000004020 conductor Substances 0.000 abstract description 6
- 230000003628 erosive effect Effects 0.000 abstract description 3
- 238000005728 strengthening Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 21
- 229910000679 solder Inorganic materials 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 11
- 239000000463 material Substances 0.000 description 10
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 239000000654 additive Substances 0.000 description 6
- 238000011161 development Methods 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 4
- 230000000996 additive effect Effects 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000003513 alkali Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 235000011121 sodium hydroxide Nutrition 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- -1 ammonium ions Chemical class 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002343 gold Chemical class 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
本発明は電解金めっき表面処理を施し、リード配線部を除去するエッチバック工程における不具合を生じることのない電子部品パッケージ用プリント配線板及びその製造方法に関する。 The present invention relates to a printed wiring board for an electronic component package and a method for manufacturing the same, which does not cause a problem in an etch back process in which an electrolytic gold plating surface treatment is performed to remove a lead wiring portion.
情報通信端末などの内部に使用される半導体等の電子部品のパッケージ用のプリント配線板は、例えば図１０に示されるような構造体で用いられる。すなわち、図１０に示される電子部品パッケージ用のプリント配線板Ｐ１の部品実装面に、接着剤５８などを用いて電子部品５１を所望の位置に設置した後に、当該電子部品５１とプリント配線板Ｐ１のワイヤーボンディングパッド部５２とを金ワイヤー５５を使用して電気的に接続するものである。 A printed wiring board for packaging electronic components such as semiconductors used in an information communication terminal or the like is used in a structure as shown in FIG. 10, for example. That is, after the electronic component 51 is placed at a desired position using the adhesive 58 or the like on the component mounting surface of the printed wiring board P1 for the electronic component package shown in FIG. 10, the electronic component 51 and the printed wiring board P1 are mounted. The wire bonding pad portion 52 is electrically connected using a gold wire 55.
このような態様で使用されるプリント配線板Ｐ１において、前記金ワイヤー５５との接続部であるワイヤーボンディングパッド部５２には、接続のための表面処理としてニッケル／金めっき処理を施すことが必要である。 In the printed wiring board P1 used in such a manner, the wire bonding pad portion 52 which is a connection portion with the gold wire 55 needs to be subjected to nickel / gold plating treatment as a surface treatment for connection. is there.
この際に使用する、ニッケル／金めっき処理の製造方法としては、大別して無電解型のめっき処理と電解型のめっき処理方法が挙げられる。 The manufacturing method of the nickel / gold plating process used at this time is roughly classified into an electroless plating process and an electrolytic plating process.
無電解型のめっき処理方法の特徴としては、プリント配線板をめっき浴に浸漬させ、プリント配線板の表層部において開口する導体部に、めっきを析出させる方法である。この際、めっきが析出する箇所としては、めっき液に接触する導体部に、めっきが徐々に蓄積されるような状態で析出される。このような無電解型のめっき処理方法の場合は、電源供給を必要としないためリード配線が不必要となる。 The electroless plating method is characterized in that a printed wiring board is immersed in a plating bath and plating is deposited on a conductor portion that opens at the surface layer portion of the printed wiring board. At this time, the plating is deposited in such a state that the plating is gradually accumulated on the conductor portion in contact with the plating solution. In the case of such an electroless type plating method, since no power supply is required, no lead wiring is required.
しかしながら、図１０に示される電子部品パッケージ用のプリント配線板Ｐ１において、ワイヤーボンディングパッド部５２に無電解型のめっき処理方法にてニッケル／金めっき処理を施す場合には、ボンディング特性と称される金ワイヤー５５との密着力を高めるために、厚付けの金めっき処理が必要となる。そして、無電解型の厚付けの金めっき処理においては、高温めっき浴でのめっき処理が必要となり、めっき浴の管理及び調整が大変であり、加えて、置換型と還元型との併用めっき処理が必要となるために、めっき工程の管理が難しく、品質の良いプリント配線板Ｐ１を得ることが困難であった。 However, in the printed wiring board P1 for an electronic component package shown in FIG. 10, when the wire bonding pad portion 52 is subjected to nickel / gold plating by an electroless plating method, it is referred to as bonding characteristics. In order to increase the adhesion with the gold wire 55, a thick gold plating process is required. And, in electroless thick gold plating treatment, it is necessary to perform plating treatment in a high-temperature plating bath, and management and adjustment of the plating bath is difficult. In addition, combined plating treatment of substitution type and reduction type Therefore, it is difficult to manage the plating process, and it is difficult to obtain a high-quality printed wiring board P1.
これに対して、電解型のめっき処理方法は、電源供給によりめっきを所望の導体部に析出させる方法である。電源供給によりめっき析出が調整できるために、めっき終了後の表面状態はめっき粒子が均一であり、金ワイヤー５５とワイヤーボンディングパッド部５２との密着力が強いためにワイヤーボンディングパッド部５２のめっき処理方法として良好である。加えて、めっき浴の液温度は室温と同程度の温度においてめっきを析出させることが可能であり、めっき析出速度も速いことなどの理由から、厚さが要求されるめっき皮膜を形成することが可能であり、工業的な生産を背景とした場合に有用なめっき処理方法である。 In contrast, the electrolytic plating method is a method in which plating is deposited on a desired conductor portion by supplying power. Since the plating deposition can be adjusted by supplying power, the plating state of the surface after the plating is uniform and the adhesion of the gold wire 55 and the wire bonding pad portion 52 is strong. Good method. In addition, it is possible to form a plating film that requires a thickness because the plating bath can deposit at a temperature similar to room temperature and the plating deposition rate is fast. This is a plating method that is possible and useful in the context of industrial production.
しかしながら、前記電解型のめっき処理方法は前述のように電源供給を必要とするために、特に、金めっき仕上げをする電子部品パッケージ用のプリント配線板Ｐ１のワイヤーボンディングパッド部５２は、リード配線と電源供給部に接続する必要がある。また、このリード配線は高周波ではアンテナとなり悪影響を及ぼすなどの理由から、このリード配線をエッチングして除去する、いわゆるエッチバックと称される製造方法が重要となる。 However, since the electrolytic plating method requires power supply as described above, in particular, the wire bonding pad portion 52 of the printed wiring board P1 for the electronic component package to be subjected to gold plating finish has a lead wiring and Must be connected to the power supply. In addition, for the reason that this lead wiring becomes an antenna at a high frequency and has an adverse effect, a so-called etch back manufacturing method in which this lead wiring is removed by etching is important.
このような技術的な背景において、電解型のめっき処理方法を使用して、めっき終了後のリード配線の除去方法に特徴を有する前記エッチバックに関する製造方法が既に報告されている（特許文献１参照）。 In such a technical background, there has already been reported a manufacturing method relating to the etch back characterized by a method for removing a lead wiring after completion of plating using an electrolytic plating method (see Patent Document 1). ).
図１１は、図１０に示される電子部品パッケージ用プリント配線板Ｐ１の部品実装面において、主にワイヤーボンディングパッド部５２とそれに接続されるリード配線６１を模式図として示したものである。 FIG. 11 is a schematic diagram mainly showing the wire bonding pad portion 52 and the lead wiring 61 connected thereto on the component mounting surface of the electronic component package printed wiring board P1 shown in FIG.
前記特許文献１に示される従来技術によれば、始めに銅材を使用し、ワイヤーボンディングパッド部５２及び当該パッド部より延長される回路配線６２並びに当該パッド部に電源供給するためのリード配線６１を回路形成する。次いで、ソルダーレジスト５４を形成した後に、耐金めっき用フィルム（図示省略）を貼り付け、主にワイヤーボンディングパッド部５２に、ニッケル／金めっき６４処理を施す。この際に、図１１に示される電源供給部の一部にニッケル／金めっき６４処理が施されても良い。次いで、前記耐金めっき用フィルムを剥離することで、図１１に示される構造体を得る。 According to the prior art disclosed in Patent Document 1, first, a copper material is used, and a wire bonding pad portion 52, a circuit wiring 62 extended from the pad portion, and a lead wiring 61 for supplying power to the pad portion. The circuit is formed. Next, after forming the solder resist 54, a gold-resistant plating film (not shown) is attached, and the wire bonding pad portion 52 is mainly subjected to nickel / gold plating 64 treatment. At this time, nickel / gold plating 64 may be applied to a part of the power supply unit shown in FIG. Next, the structure shown in FIG. 11 is obtained by peeling off the gold-resistant plating film.
この図１１に示される構造体において特徴的な箇所としては、ワイヤーボンディングパッド部５２にリード配線６１が接続され、電解ニッケル／金めっき６４処理が安定した品質にて行なわれること、及びワイヤーボンディングパッド部５２にニッケル／金めっき６４が被覆され、リード配線６１にはニッケル／金めっき６４が被覆されていない点にある。 A characteristic place in the structure shown in FIG. 11 is that the lead wiring 61 is connected to the wire bonding pad portion 52, the electrolytic nickel / gold plating 64 is processed with stable quality, and the wire bonding pad. The part 52 is covered with the nickel / gold plating 64, and the lead wiring 61 is not covered with the nickel / gold plating 64.
これにより図１１に示される構造体に、銅材を溶出し、ニッケル／金めっきを溶出しないエッチング液にてエッチング処理をすると、銅材からなるリード配線６１が除去され、ワイヤーボンディングパッド部５２はニッケル／金めっき６４が保護マスクとして作用し、当該ワイヤーボンディングパッド部５２が残存する図１２に示される構造体が得られる。次いで、断裁線６０により切断することで、特にワイヤーボンディングパッド部５２のニッケル／金めっき品質に優れた電子部品パッケージ用プリント配線板を得ることが可能になる。 Thus, when the copper material is eluted into the structure shown in FIG. 11 and the etching process is performed with an etching solution that does not elute nickel / gold plating, the lead wiring 61 made of the copper material is removed, and the wire bonding pad portion 52 is The nickel / gold plating 64 acts as a protective mask, and the structure shown in FIG. 12 in which the wire bonding pad portion 52 remains is obtained. Next, by cutting along the cutting line 60, it is possible to obtain a printed wiring board for electronic component packages that is particularly excellent in the nickel / gold plating quality of the wire bonding pad portion 52.
しかしながら、図１２に示される構造体において、前記銅材を溶出し、ニッケル／金めっきを溶出しないエッチング液にてリード配線をエッチング除去する際に不具合を生じていた。すなわち、図１２のＣ１−Ｃ２線要部拡大断面説明図として示される図１３において、ワイヤーボンディングパッド部５２の上に被覆されるソルダーレジスト５４とニッケル／金めっき６４との界面において間隙部を生じることがある。当該間隙部においては、前記銅材を溶出し、ニッケル／金めっきを溶出しないエッチング液が侵入することがあり、その結果、銅材からなるワイヤーボンディングパッド部５２を浸食することが生じていた。加えて、当該浸食された部分においては、ワイヤーボンディングパッド部５２の銅が溶出し、ニッケル／金めっき６４の表面に付着する２次的な不具合を併発し、金ワイヤーとニッケル／金めっきの表面との密着性が低下する問題を生じていた。 However, in the structure shown in FIG. 12, the copper material is eluted and a problem occurs when the lead wiring is removed by etching with an etching solution that does not elute nickel / gold plating. That is, in FIG. 13 shown as an enlarged sectional explanatory view of the C1-C2 line of FIG. 12, a gap is generated at the interface between the solder resist 54 coated on the wire bonding pad 52 and the nickel / gold plating 64. Sometimes. In the gap portion, an etching solution that elutes the copper material and does not elute nickel / gold plating may enter, and as a result, the wire bonding pad portion 52 made of the copper material is eroded. In addition, in the eroded portion, the copper of the wire bonding pad portion 52 is eluted, causing secondary defects adhering to the surface of the nickel / gold plating 64, and the surfaces of the gold wire and the nickel / gold plating. There was a problem that the adhesiveness with the lowering.
このように、ニッケル／金めっき６４の表面に付着した銅残渣は、ボンディング特性と呼称される前記金ワイヤー５５とワイヤーボンディングパッド部５２との密着性を低下させるために、品質の良いプリント配線板を得ることが困難であった。
以上のような背景に基づき本発明が解決しようとする課題は、電解めっきの際に使用するリード配線をエッチバック工程により除去する際に、電子部品パッケージ用のプリント配線板の導体部が浸食されることがなく、ワイヤーとワイヤーボンディングパッド部との密着性を強固なものとすることができる電子部品パッケージ用プリント配線板及びその製造方法を提供することにある。 The problem to be solved by the present invention based on the above background is that when the lead wiring used in the electroplating is removed by the etch back process, the conductor portion of the printed wiring board for the electronic component package is eroded. An object of the present invention is to provide a printed wiring board for an electronic component package and a method for manufacturing the same, which can strengthen the adhesion between a wire and a wire bonding pad portion.
本発明者は上記課題を解決するために種々検討を重ねた。その結果、電子部品パッケージ用のプリント配線板のワイヤーボンディングパッド部を、当該プリント配線板の電解めっき用に使用されるリード配線とはエッチング条件の異なる金属材料で構成すれば、極めて良い結果が得られることを見出して発明を完成するに至った。 The inventor has made various studies in order to solve the above problems. As a result, if the wire bonding pad portion of the printed wiring board for the electronic component package is made of a metal material having etching conditions different from those of the lead wiring used for electrolytic plating of the printed wiring board, extremely good results can be obtained. I found out that I was able to complete the invention.
すなわち、本発明は、電源供給用のリード配線が除去され、かつワイヤーボンディングパッド部が残存している電子部品パッケージ用プリント配線板であって、当該ワイヤーボンディングパッド部が除去された電源供給用のリード配線とはエッチング条件の異なる金属材料からなることを特徴とする電子部品パッケージ用プリント配線板により上記課題を解決したものである。 That is, the present invention is a printed wiring board for an electronic component package in which the lead wiring for power supply is removed and the wire bonding pad portion remains, and the power supply for power supply with the wire bonding pad portion removed is provided. The above-mentioned problems are solved by a printed wiring board for an electronic component package, wherein the lead wiring is made of a metal material having different etching conditions.
また、本発明の電子部品パッケージ用プリント配線板は、前記ワイヤーボンディングパッド部の表面に、電解型の金めっきが施されていることを特徴とする。 The printed wiring board for an electronic component package of the present invention is characterized in that electrolytic gold plating is applied to the surface of the wire bonding pad portion.
また、本発明は、電解型の金めっきが表面処理されるワイヤーボンディングパッド部及び当該ワイヤーボンディングパッド部に接続される電源供給用のリード配線を有する電子部品パッケージ用プリント配線板であって、当該ワイヤーボンディングパッド部と当該電源供給用のリード配線とがエッチング条件の異なる金属材料からなることを特徴とする電子部品パッケージ用プリント配線板により上記課題を解決したものである。 Further, the present invention is a printed wiring board for an electronic component package having a wire bonding pad portion on which electrolytic gold plating is surface-treated and a lead wiring for power supply connected to the wire bonding pad portion, The above-described problems are solved by a printed wiring board for an electronic component package, wherein the wire bonding pad portion and the lead wiring for supplying power are made of metal materials having different etching conditions.
また、本発明の電子部品パッケージ用プリント配線板は、前記ワイヤーボンディングパッド部がニッケルからなり、かつ前記電源供給用のリード配線が銅からなることを特徴とする。 The printed wiring board for an electronic component package according to the present invention is characterized in that the wire bonding pad portion is made of nickel and the lead wiring for supplying power is made of copper.
また、本発明は、電解型の金めっきが表面処理されるワイヤーボンディングパッド部及び当該ワイヤーボンディングパッド部に接続される電源供給用のリード配線を有する電子部品パッケージ用プリント配線板の製造方法であって、ニッケルからなるワイヤーボンディングパッド部及び回路配線を形成する工程と、当該ワイヤーボンディングパッド部に接続するリード配線を銅めっきにより形成する工程と、金めっきレジストを張合せて当該リード配線を保護した後に、前記ワイヤーボンディングパッド部に電解型の金めっき表面処理をする工程と、選択的にエッチング加工により前記リード配線のみをエッチング除去し、前記ワイヤーボンディングパッド部を残存させる工程とを備えていることを特徴とする電子部品パッケージ用プリント配線板の製造方法により上記課題を解決したものである。 The present invention also relates to a method of manufacturing a printed wiring board for an electronic component package having a wire bonding pad portion on which electrolytic gold plating is surface-treated and a lead wiring for supplying power connected to the wire bonding pad portion. A step of forming a wire bonding pad portion and circuit wiring made of nickel, a step of forming a lead wiring to be connected to the wire bonding pad portion by copper plating, and a gold plating resist are bonded to protect the lead wiring. And a step of performing an electrolytic gold plating surface treatment on the wire bonding pad portion, and a step of selectively removing only the lead wiring by etching to leave the wire bonding pad portion. Print for electronic parts package characterized by It is obtained by solving the above problems by the production method of the line board.
本発明の電子部品パッケージ用プリント配線板は、電解めっきの際に使用するリード配線をエッチバック工程により除去する際に、電子部品パッケージ用のプリント配線板の導体部が浸食する不具合を生じることがないので、ワイヤーとワイヤーボンディングパット部との密着性を強固なものとすることができる。
また、本発明の電子部品パッケージ用プリント配線板の製造方法によれば、斯かる品質に優れた電子部品パッケージ用プリント配線板を効率良く製造することができる。
The printed wiring board for an electronic component package of the present invention may cause a problem that the conductor portion of the printed wiring board for an electronic component package is eroded when the lead wiring used in the electrolytic plating is removed by an etch back process. Therefore, the adhesion between the wire and the wire bonding pad portion can be strengthened.
In addition, according to the method for manufacturing an electronic component package printed wiring board of the present invention, it is possible to efficiently manufacture an electronic component package printed wiring board having excellent quality.
以下本発明の実施の形態を、図１〜図１０を使用して説明する。また、本発明におけるプリント配線板の製造方法を明確にする目的で、下記表１に示した本発明の製造工程表と合わせて説明する。 Hereinafter, embodiments of the present invention will be described with reference to FIGS. Further, for the purpose of clarifying the method for producing a printed wiring board according to the present invention, it will be described together with the production process table of the present invention shown in Table 1 below.
図１は、本発明における電子部品パッケージ用プリント配線板の主骨格構造の製造方法について示したものである。始めに、図１（ａ）に示したように絶縁材２を中心に配置し、その上下両方にニッケル１を配置した後に積層プレスにより一体化し、両面構造の積層板を作成する。表１内の製造工程としては工程（１）ニッケル両面基板の作成に該当する。 FIG. 1 shows a method for manufacturing a main skeleton structure of a printed wiring board for an electronic component package according to the present invention. First, as shown in FIG. 1A, the insulating material 2 is arranged at the center, nickel 1 is arranged on both the upper and lower sides thereof, and then integrated by a laminating press to create a double-sided laminated board. The manufacturing process in Table 1 corresponds to the process (1) creation of a nickel double-sided substrate.
ここで使用するニッケル１は箔状態のものが好適に使用でき、例えば１２μｍニッケル箔が使用できる。また、絶縁材２は従来のプリント配線板に使用されているガラスクロス含有もしくはフィラー類が多く使用されたエポキシ材料を主体とするプリプレグ材料やイミド系材料などを始めとする絶縁材が使用できる。 The nickel 1 used here can be suitably used in a foil state, for example, a 12 μm nickel foil can be used. The insulating material 2 can be an insulating material such as a prepreg material or an imide-based material mainly composed of an epoxy material containing glass cloth or used in many fillers used in conventional printed wiring boards.
次いで、前記図１（ａ）に示されるニッケル両面基板を使用して、回路形成を行ない、ニッケル１に基づく回路配線３やワイヤーボンディングパッド部４を形成する。ここでの回路形成方法としては、主にサブトラクティブ方法により回路を形成することができ、具体的にはニッケル１の表層面にドライフィルムを張り付けた後に、所望の回路形成用のマスクを設置し、露光、現像、エッチング、ドライフィルム剥離の工程順により上記回路配線３やワイヤーボンディングパッド部４を形成し、図１（ｂ）に示される回路形成終了後の構造体を得る。表１内の製造工程としては工程（２）ニッケルの回路形成に該当する。 Next, using the nickel double-sided substrate shown in FIG. 1A, circuit formation is performed to form circuit wirings 3 and wire bonding pad portions 4 based on nickel 1. As a circuit formation method here, a circuit can be formed mainly by a subtractive method. Specifically, after a dry film is pasted on the surface of nickel 1, a mask for forming a desired circuit is installed. Then, the circuit wiring 3 and the wire bonding pad portion 4 are formed in the order of steps of exposure, development, etching, and dry film peeling to obtain a structure after completion of the circuit formation shown in FIG. The manufacturing process in Table 1 corresponds to process (2) nickel circuit formation.
ここで、前記回路形成におけるエッチング液としては、ニッケル１を溶出することが必要となるために、例えば塩化第二鉄エッチング液を使用することが好適である。 Here, since it is necessary to elute nickel 1 as an etching solution in the circuit formation, it is preferable to use, for example, a ferric chloride etching solution.
次いで、図１（ｂ）に示される回路形成終了後のニッケル両面基板を使用して、層間接続用の有底孔５を形成する。この層間接続用の有底孔５はレーザによる加工により形成される。また、レーザによる加工後は、層間接続部の電気的信頼性を向上させることを目的として、デスミアなどによる洗浄を行ない有底孔５の内部を洗浄する。表１内の製造工程としては工程（３）層間接続用の有底孔形成に該当する。 Next, a bottomed hole 5 for interlayer connection is formed using the nickel double-sided substrate after the circuit formation shown in FIG. The bottomed hole 5 for interlayer connection is formed by laser processing. In addition, after the laser processing, the inside of the bottomed hole 5 is cleaned by performing desmearing or the like for the purpose of improving the electrical reliability of the interlayer connection portion. The manufacturing process in Table 1 corresponds to process (3) formation of a bottomed hole for interlayer connection.
次いで、前記図１（ｃ）に示される層間接続用の有底孔５部を、有底孔内の充填機能を有する、いわゆるフィルドビア用の銅めっき液を使用して埋設する。ここでの銅めっきによる有底孔内の充填方法は、アディティブ法もしくはセミアディティブ法により行なわれる。すなわち、始めに前記銅めっきを行なう前にあらかじめめっきレジストを貼り付け、露光及び現像工程を得て、有底孔５部以外の箇所にめっきレジストを形成する。表１内の製造工程としては工程（４）銅めっきレジストの形成に該当する。 Next, 5 parts of bottomed holes for interlayer connection shown in FIG. 1C are embedded using a so-called filled via copper plating solution having a filling function in the bottomed holes. The filling method in the bottomed hole by copper plating here is performed by an additive method or a semi-additive method. That is, first, before performing the copper plating, a plating resist is pasted in advance, exposure and development steps are obtained, and a plating resist is formed at a place other than the bottomed hole 5 part. The manufacturing process in Table 1 corresponds to the process (4) formation of a copper plating resist.
これにより有底孔５部のみが開口するめっきレジスト皮膜を形成でき、この状態においてアディティブ法もしくはセミアディティブ法によるめっき析出方法にて層間接続用の有底孔５部に銅めっきを充填し、次いでめっきレジスト皮膜を剥離することで、図１（ｄ）に示される構造体の本発明電子部品パッケージ用プリント配線板を得る。表１内の製造工程としては工程（５）銅めっきによる有底孔充填及びリード配線の形成並びに工程（６）銅めっきレジストの剥離に該当する。 As a result, a plating resist film in which only the bottomed hole 5 part is opened can be formed. In this state, the bottomed hole 5 part for interlayer connection is filled with copper plating by the plating deposition method by the additive method or the semi-additive method. By peeling the plating resist film, the printed wiring board for an electronic component package of the present invention having the structure shown in FIG. The manufacturing steps in Table 1 correspond to step (5) filling of bottomed holes by copper plating and formation of lead wiring and step (6) peeling of the copper plating resist.
ここで、表１内の製造工程の工程（５）銅めっきによる有底孔充填の形成及びリード配線の形成は、同工程において同時に図１（ｄ）に示されるリード配線７の形成も併せて行なうが、このリード配線７の形成については、図２〜図８を使用して後述する。 Here, step (5) formation of bottomed hole filling by copper plating and formation of lead wiring in the manufacturing process in Table 1 are also performed simultaneously with formation of lead wiring 7 shown in FIG. The formation of the lead wiring 7 will be described later with reference to FIGS.
このようにして得られた図１（ｄ）に示される構造体は、本発明における電子部品パッケージ用のプリント配線板の主骨格構造をなす。 The structure shown in FIG. 1D thus obtained constitutes the main skeleton structure of the printed wiring board for the electronic component package in the present invention.
次の製造工程として、前述記載のように図１（ｄ）に示されるワイヤーボンディングパッド部４に、ニッケル／金めっき処理を行なう。また、この工程においては、ワイヤーボンディングパッド部４がニッケル１により回路形成されているために、金めっきのみの表面処理を行なうだけでもワイヤーボンディングパッド部４の表面処理に対応することができる。 As the next manufacturing process, a nickel / gold plating process is performed on the wire bonding pad portion 4 shown in FIG. Further, in this process, since the wire bonding pad portion 4 is formed of a circuit with the nickel 1, it is possible to cope with the surface treatment of the wire bonding pad portion 4 only by performing the surface treatment only with gold plating.
この金めっき表面処理方法及び金めっきに必要なリード配線の形成と除去方法について、図２〜図９を使用して以下順に説明する。 This gold plating surface treatment method and the formation and removal method of lead wiring necessary for gold plating will be described in the following order using FIGS.
図２は、図１（ｄ）に示される構造体のプリント配線板において、電子部品が配置されるワイヤーボンディングパッド部４を有する面側の拡大平面説明図である。この図２の拡大平面説明図よりわかるように、図１（ｄ）に示されるワイヤーボンディングパッド部４は表面からの観察によれば、主に外周部分に配置され、各ワイヤーボンディングパッド部４は電解金めっきを行なうために、電源供給されるリード配線７と接続している。 FIG. 2 is an enlarged plan view illustrating the surface side having the wire bonding pad portion 4 on which electronic components are arranged in the printed wiring board having the structure shown in FIG. As can be seen from the enlarged plan view of FIG. 2, the wire bonding pad portion 4 shown in FIG. 1 (d) is arranged mainly on the outer peripheral portion according to observation from the surface, and each wire bonding pad portion 4 is In order to perform electrolytic gold plating, the lead wire 7 is connected to a power supply.
また、ワイヤーボンディングパッド部４は回路部８と接続しており、当該回路部８はプリント配線板に設計上で要求される回路配置となる。さらに、図面での記載は無いが、当該回路部８は図１（ｄ）に示される層間接続部６と接続することができるために、プリント配線板の表裏面部において電気的に接続されている。 Further, the wire bonding pad portion 4 is connected to the circuit portion 8, and the circuit portion 8 has a circuit arrangement required for designing a printed wiring board. Further, although not shown in the drawing, the circuit portion 8 can be connected to the interlayer connection portion 6 shown in FIG. 1D, and is therefore electrically connected to the front and back surface portions of the printed wiring board. .
ワイヤーボンディングパッド部４は、前述のように電解金めっきを行なうためには電源供給が必要となる。そのためのリード配線７と接続されていることが必要である。この接続方法について、図２に示されるＡ箇所の要部拡大説明図を図３以下に示し、プリント配線板の製造方法と共に説明する。 The wire bonding pad portion 4 needs to be supplied with power in order to perform electrolytic gold plating as described above. It is necessary to be connected to the lead wiring 7 for that purpose. This connection method will be described with reference to FIG. 3 and the following enlarged views of the main part A shown in FIG. 2 and will be described together with a method for manufacturing a printed wiring board.
図３は、回路形成により得られたワイヤーボンディングパッド部４を含む回路部８を拡大した平面説明図である。表１内の製造工程としては、工程（２）ニッケルの回路形成が終了した状態である。すなわち、前記記載の図１（ｂ）に示されるニッケルの回路配線３を表面より観察し、特にワイヤーボンディングパッド部４とその周辺の回路部８を拡大した図である。 FIG. 3 is an enlarged plan view of the circuit portion 8 including the wire bonding pad portion 4 obtained by circuit formation. As a manufacturing process in Table 1, it is in the state where process (2) nickel circuit formation was completed. That is, the nickel circuit wiring 3 shown in FIG. 1B is observed from the surface, and in particular, the wire bonding pad portion 4 and the peripheral circuit portion 8 are enlarged.
図３に示されるように、ワイヤーボンディングパッド部４は回路部８と接続しており、当該回路部８はプリント配線板に設計上で要求される回路配置となり、回路部８の延長先においては、層間接続部６と接続することができる。また、ワイヤーボンディングパッド部４はリード配線接続部９と接続されている。 As shown in FIG. 3, the wire bonding pad portion 4 is connected to the circuit portion 8, and the circuit portion 8 has a circuit arrangement required for design on the printed wiring board. The interlayer connection portion 6 can be connected. Further, the wire bonding pad portion 4 is connected to the lead wiring connecting portion 9.
このリード配線接続部９は、表１内の工程（２）ニッケルの回路形成にて、ワイヤーボンディングパッド部４を回路形成する際に同時に形成され、ワイヤーボンディングパッド部４と同じくニッケル１より構成される。当該リード配線接続部９は、ワイヤーボンディングパッド部４に金めっき処理をする際に電源供給が必要になり、その電源供給を行なうリード配線部との接続箇所として設けられている。 This lead wiring connection portion 9 is formed simultaneously with the wire bonding pad portion 4 in the step (2) nickel circuit formation in Table 1 and is composed of nickel 1 like the wire bonding pad portion 4. The The lead wiring connection portion 9 needs to be supplied with power when the gold bonding process is performed on the wire bonding pad portion 4, and is provided as a connection portion with the lead wiring portion that supplies the power.
次いで、図３に示されるリード配線接続部９に接続するように、リード配線７を銅めっきにより形成し、図４に示される構造体を得る。このリード配線７を銅めっきにより形成する方法は次のように行なう。 Next, the lead wiring 7 is formed by copper plating so as to be connected to the lead wiring connecting portion 9 shown in FIG. 3, and the structure shown in FIG. 4 is obtained. A method of forming the lead wiring 7 by copper plating is performed as follows.
図１（ｃ）から図１（ｄ）に示される構造体において、銅めっきレジストを形成した後にアディティブ法もしくはセミアディティブ法にて有底孔５の銅めっきによる充填を行なうが、この際に、前記銅めっきレジストの開口部を図４に示されるリード配線７を形成する位置に開口させる。次いで、前記有底孔５を充填する銅めっきにて、有底孔５を充填すると同時に前記リード配線７を形成するため銅めっきレジスト開口部に析出させる。 In the structure shown in FIG. 1 (c) to FIG. 1 (d), after forming the copper plating resist, the bottomed hole 5 is filled by copper plating by an additive method or a semi-additive method. The opening of the copper plating resist is opened at a position where the lead wiring 7 shown in FIG. 4 is formed. Next, in the copper plating filling the bottomed hole 5, the bottomed hole 5 is filled, and at the same time, the lead wiring 7 is deposited in the copper plating resist opening.
これにより、図４に示されるリード配線７を形成することが可能となる。表１内の製造工程としては工程（５）銅めっきによる有底孔充填の形成及びリード配線の形成に該当する。また、銅めっき付着後は、工程（６）銅めっきレジストの剥離により銅めっきレジストの剥離を行なう。 Thereby, the lead wiring 7 shown in FIG. 4 can be formed. The manufacturing process in Table 1 corresponds to process (5) formation of bottomed hole filling by copper plating and formation of lead wiring. Further, after the copper plating adheres, the copper plating resist is peeled off by the step (6) peeling of the copper plating resist.
次いで、図５に示されるように、ワイヤーボンディングパッド部４に接続する回路部８などにソルダーレジスト１１を形成する。表１内の製造工程としては、工程（７）ソルダーレジストの形成に該当する。 Next, as shown in FIG. 5, a solder resist 11 is formed on the circuit portion 8 or the like connected to the wire bonding pad portion 4. As a manufacturing process in Table 1, it corresponds to formation of a process (7) soldering resist.
次いで、図６に示されるように、金めっき処理を行なうワイヤーボンディングパッド部４以外の箇所に耐金めっきレジスト１２を形成する。表１内の製造工程としては、工程（８）耐金めっきマスクの形成に該当する。 Next, as shown in FIG. 6, a gold-resistant plating resist 12 is formed at a place other than the wire bonding pad portion 4 that performs the gold plating process. The manufacturing process in Table 1 corresponds to the step (8) formation of a gold-resistant plating mask.
次いで、電解金めっき処理によりワイヤーボンディングパッド部４の表面に金めっき１５を付着した後に、耐金めっきレジスト１２を剥離し、図７に示されるような構造体を得る。表１内の製造工程としては、工程（９）電解金めっき処理及び工程（１０）耐金めっきマスク剥離に該当する。 Next, after gold plating 15 is attached to the surface of the wire bonding pad portion 4 by electrolytic gold plating, the gold-resistant plating resist 12 is peeled off to obtain a structure as shown in FIG. The manufacturing steps in Table 1 correspond to step (9) electrolytic gold plating treatment and step (10) gold-resistant plating mask peeling.
次いで、銅めっきからなるリード配線７をエッチングにより除去し、図８に示される構造体の本発明電子部品パッケージ用のプリント配線板を得る。このエッチング加工に使用するエッチング液はアルカリエッチング液を使用する。アルカリエッチング液は、銅を溶解することが可能である。しかし、ニッケルは溶解しないため、ニッケルからなるワイヤーボンディングパッド部４は残存し、銅めっきからなるリード配線７のみを除去することができる。表１内の製造工程としては、工程（１１）リード配線のエッチングに該当する。 Next, the lead wiring 7 made of copper plating is removed by etching to obtain a printed wiring board for the electronic component package of the present invention having the structure shown in FIG. An etching solution used for this etching process is an alkaline etching solution. The alkaline etching solution can dissolve copper. However, since nickel does not melt, the wire bonding pad portion 4 made of nickel remains and only the lead wiring 7 made of copper plating can be removed. The manufacturing process in Table 1 corresponds to the process (11) etching of the lead wiring.
また、図８のＢ１−Ｂ２線要部拡大断面説明図として示される図９において、ワイヤーボンディングパッド部４の上に被覆されるソルダーレジスト１１と金めっき１５との界面において間隙部を生じた場合においても、当該間隙部においては、ワイヤーボンディングパッド部４がニッケルにより構成されているため前記アルカリエッチング液を使用した場合には図１３に示されるような従来技術のように浸食などを発生させることは無く、品質の良い電子部品パッケージ用のプリント配線板を形成することができる。 Further, in FIG. 9 shown as an enlarged sectional explanatory view of the B1-B2 line in FIG. 8, when a gap is generated at the interface between the solder resist 11 and the gold plating 15 coated on the wire bonding pad portion 4. However, in the gap portion, the wire bonding pad portion 4 is made of nickel, and therefore, when the alkaline etching solution is used, erosion or the like is generated as in the prior art as shown in FIG. It is possible to form a high-quality printed wiring board for an electronic component package.
以下、実施例を挙げ、より具体的に説明を行なう。なお、ここで記載する電子部品パッケージ用プリント配線板としては、図１０に示される部品実装面には、半導体部品と金ワイヤー接続するためのワイヤーボンディングパッド部を配置し、はんだ接続面には、マザーボードと接続するためのはんだボールパッドをペリフェラル状に配置し、各実装パッドの表面処理はリード給電による電解厚付けニッケル（５μｍ）／金めっき（０．５μｍ）仕様とした。 Hereinafter, an example is given and it demonstrates more concretely. In addition, as a printed wiring board for electronic component packages described here, a wire bonding pad portion for connecting a semiconductor component and a gold wire is arranged on the component mounting surface shown in FIG. Solder ball pads for connection to the mother board were arranged in a peripheral shape, and the surface treatment of each mounting pad was set to electrolytic thick nickel (5 μm) / gold plating (0.5 μm) by lead feeding.
始めに、まず、エポキシ樹脂を主成分とする厚さ１００μｍプリプレグ２を用意し、その両側に電解ニッケルめっきにより箔形状に生成した１２μｍのニッケル箔１を配置し、積層することで、図１（ａ）に示される両面板を作成した。 First, a 100 μm-thick prepreg 2 mainly composed of an epoxy resin is prepared, and a 12 μm nickel foil 1 formed into a foil shape by electrolytic nickel plating is disposed on both sides of the prepreg 2, and laminated. A double-sided board shown in a) was prepared.
次に、アルカリ現像型のドライフィルムレジストを図１（ａ）で得られた両面板に張り合せ、露光及び現像を行ない、次いで、第二塩化鉄液によりドライフィルムレジスト非被覆部のニッケル１をエッチングにより除去し、ニッケルからなる、ライン（Ｌ）／スペース（Ｓ）＝３０／３０μｍの回路配線３とワイヤーボンディングパッド部４とはんだボールパッドを形成し、図１（ｂ）に示される構造体を得た。 Next, an alkali development type dry film resist is laminated on the double-sided plate obtained in FIG. 1 (a), exposed and developed, and then nickel 1 in the dry film resist non-coating portion is coated with a ferric chloride solution. The structure shown in FIG. 1B is formed by forming the circuit wiring 3, the wire bonding pad portion 4, and the solder ball pad made of nickel and made of nickel and having a line (L) / space (S) = 30/30 μm. Got.
次に、炭酸ガスレーザを使用して、図１（ｂ）に示される構造体の所望の位置に穴明けを行ない、φ７０μｍの開口径を有する有底孔５を形成し、当該有底孔５を過マンガン酸デスミア処理により洗浄し、有底孔５の底部の残膜を除去し、図１（ｃ）に示される構造体を得た。 Next, a carbon dioxide laser is used to drill a desired position of the structure shown in FIG. 1B to form a bottomed hole 5 having an opening diameter of φ70 μm. Washing was performed by permanganate desmear treatment, and the remaining film at the bottom of the bottomed hole 5 was removed to obtain a structure shown in FIG.
次に、図１（ｃ）に示される構造体の全体に、無電解型の銅めっきを０．３μｍの厚みで施した後に、３０μｍ厚みの銅めっきレジストを貼り付け、当該めっきレジストを露光、現像して、所望の位置に形成した（図面説明なし）。 Next, after applying electroless copper plating to a thickness of 0.3 μm over the entire structure shown in FIG. 1 (c), a copper plating resist having a thickness of 30 μm is pasted, and the plating resist is exposed. It was developed and formed at a desired position (no drawing description).
次に、前記０．３μｍの厚みで形成した無電解層めっきを給電層として硫酸銅めっき工程を行ない、有底孔５に銅めっきを充填し、図１（ｄ）に示される層間接続部６を得た。また、同工程により、図１（ｄ）に示されるリード配線７部を形成した。このリード配線７部は、前記記載のように電源供給のためワイヤーボンディングパッド部４に重なる構造が良好であるが、ここでは５０μｍ重なる構造体を形成した。 Next, a copper sulfate plating process is performed using the electroless layer plating formed with a thickness of 0.3 μm as a power supply layer, and the bottomed hole 5 is filled with copper plating, and the interlayer connection portion 6 shown in FIG. Got. In addition, the lead wiring 7 shown in FIG. 1D was formed by the same process. As described above, the lead wiring 7 portion has a favorable structure of overlapping the wire bonding pad portion 4 for power supply, but here, a structure body of 50 μm is formed.
次に、前記銅めっきレジストを苛性ソーダで剥離し、その後、ソフトエッチング液にて０．３μｍの厚みの無電解銅めっきを除去した。これにより、まず図１（ｄ）に示される構造体の本発明電子部品パッケージ用プリント配線板を得た。 Next, the copper plating resist was stripped with caustic soda, and then the electroless copper plating with a thickness of 0.3 μm was removed with a soft etching solution. As a result, a printed wiring board for an electronic component package of the present invention having the structure shown in FIG.
次に、前記得られた図１（ｄ）に示される構造体の表面にソルダーレジスト１１を被覆し、回路部８の上が保護されるように露光及び現像を行ない、図５に示されるソルダーレジスト被膜状態を形成した。 Next, the surface of the structure shown in FIG. 1D is coated with a solder resist 11 and exposed and developed so that the top of the circuit portion 8 is protected, and the solder shown in FIG. A resist film state was formed.
次に、図６に示されるように、アルカリ現像型の耐金めっき用レジスト１２を露光及び現像によって形成した。 Next, as shown in FIG. 6, an alkali development type gold-resistant plating resist 12 was formed by exposure and development.
次に、図７に示されるように、電解型の金めっき１５を０．５μｍ行ない、その後、苛性ソーダで耐金めっき用レジスト１２を剥離した。 Next, as shown in FIG. 7, electrolytic gold plating 15 was performed by 0.5 μm, and then the gold-resistant plating resist 12 was peeled off with caustic soda.
次に、図８に示されるように、錯アンモニウムイオンを主成分とするアルカリエッチング液により、銅からなるリード配線７を除去し、図９に示される構造体を得た。 Next, as shown in FIG. 8, the lead wiring 7 made of copper was removed with an alkaline etching solution mainly composed of complex ammonium ions to obtain the structure shown in FIG. 9.
斯くして得られた構造体は、電解金めっき用のリード配線７部及び各実装パッドに浸食やシミが無く、品質に優れた電子部品パッケージ用プリント配線板であった。 The structure thus obtained was a printed wiring board for electronic component packages having no erosion and spots on the 7 parts of lead wiring for electrolytic gold plating and each mounting pad, and excellent in quality.
１：ニッケル
２：絶縁材
３：回路配線
４：ワイヤーボンディングパッド部
５：有底孔
６：層間接続部
７：リード配線
８：回路部
９：リード配線接続部
１１：ソルダーレジスト
１２：耐金めっき用レジスト
１５：金めっき
１６：銅
５１：電子部品
５２：ワイヤーボンディングパッド部
５３：層間接続部
５４：ソルダーレジスト
５５：金ワイヤー
５６：回路配線
５７：はんだ
５８：接着材
５９：封止材
６０：断裁線
６１：リード配線
６４：ニッケル／金めっき
Ｐ１：プリント配線板
1: Nickel 2: Insulating material 3: Circuit wiring 4: Wire bonding pad part 5: Bottomed hole 6: Interlayer connection part 7: Lead wiring 8: Circuit part 9: Lead wiring connection part 11: Solder resist 12: Gold-resistant plating Resist 15: Gold plating 16: Copper 51: Electronic component 52: Wire bonding pad portion 53: Interlayer connection portion 54: Solder resist 55: Gold wire 56: Circuit wiring 57: Solder 58: Adhesive material 59: Sealing material 60: Cutting line 61: Lead wiring 64: Nickel / gold plating P1: Printed wiring board
Claims (5)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8528200B2 (en) | 2009-12-18 | 2013-09-10 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing printed wiring board |
| CN103747636A (en) * | 2013-12-24 | 2014-04-23 | 广州兴森快捷电路科技有限公司 | Gold-plated circuit-board lead etch-back method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002016347A (en) * | 2000-06-27 | 2002-01-18 | Mitsui Chemicals Inc | Method for manufacturing printed circuit board |
| JP2005005409A (en) * | 2003-06-11 | 2005-01-06 | Matsushita Electric Ind Co Ltd | Semiconductor device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002016347A (en) * | 2000-06-27 | 2002-01-18 | Mitsui Chemicals Inc | Method for manufacturing printed circuit board |
| JP2005005409A (en) * | 2003-06-11 | 2005-01-06 | Matsushita Electric Ind Co Ltd | Semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8528200B2 (en) | 2009-12-18 | 2013-09-10 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing printed wiring board |
| US9161445B2 (en) | 2009-12-18 | 2015-10-13 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing printed wiring board |
| CN103747636A (en) * | 2013-12-24 | 2014-04-23 | 广州兴森快捷电路科技有限公司 | Gold-plated circuit-board lead etch-back method |
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