JP2007088369A - Manufacturing method and manufacturing apparatus of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To fully ensure a thickness on a void of an insulating film formed on front surfaces of a trench and a semiconductor substrate. <P>SOLUTION: In a trench formation process by a manufacturing method of a semiconductor device, a trench 102 is formed on a front surface of a p-type semiconductor substrate 101. In an implantation process, an n-type dopant is implanted to the trench 102 formed by the trench formation process. In an insulating film formation process, an insulating film 601 is formed in the trench 102 to which the n-type dopant is implanted by the implantation process by using a viscous insulating application material. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device manufacturing apparatus in which a trench is formed in a semiconductor substrate, and more particularly to a semiconductor device manufacturing method and a semiconductor device manufacturing apparatus such as a high breakdown voltage MOSFET used for a power IC or the like.

  Conventional trench technologies include, for example, a technology for creating a capacitance such as a DRAM (Dynamic Random Access Memory), an SOI (Silicon On Insulator) technology for element isolation, and a discrete MOSFET (Metal Oxide Semiconductor Transistor Trench technology). Various methods are being studied. In recent years, application techniques to lateral high voltage MOSFETs used in power ICs (Integrated Circuits) have been actively proposed.

  As a technique for forming an offset drain in the trench portion, for example, a technique has been proposed in which impurity ions are implanted around the trench groove and the inside of the wide trench groove is filled with an oxide or the like (for example, the following patent document) 1 and 2).

  In addition, a technique for obtaining a dielectric-separated wafer into a first section S1 that leads out the terminals of the semiconductor element from the front side and the back side and a second section S2 that leads out only from the front side has been proposed (for example, (See Patent Document 3).

JP 2003-37267 A JP 2005-19461 A JP-A-7-273187

  However, in the above-described prior art, in order to use the insulating region formed in the trench for the breakdown voltage structure of a high breakdown voltage MOSFET having a breakdown voltage of about 700 V, it is necessary to form a trench having a depth of about 20 μm. Considering the film formation speed for embedding the trench with an insulating film by a method or the like, the upper limit of the width of the trench is about 1 to 2 μm. In consideration of the oxidation time for completely thermally oxidizing the semiconductor substrate remaining between the trenches, the upper limit of the width of the semiconductor substrate between the trenches is about 1 to 2 μm.

  As described above, the shape of the trench to be formed is defined by device process limitations. In order to leave the semiconductor substrate between the trenches in a fin shape after the trench etching, the taper angle of the trench is substantially vertical (specifically, Specifically, it must be within 90 ° ± 0.5 °. When the taper angle of the trench is close to 90 °, the rate at which the insulating film is deposited near the opening of the trench when the insulating film is formed in the trench increases, so that a void is formed in the trench.

  The upper end of the void is located near the surface of the semiconductor substrate. In such a shape, in the subsequent etching or cleaning process, the thin portion of the insulating film on the void disappears and the void opens. If the void opens, the resist penetrates deep into the void during the subsequent resist coating process, and cannot be removed by the resist removal process. For this reason, the semiconductor substrate is contaminated in the course of manufacturing, and the problem that the yield of the product is deteriorated or the characteristics of the semiconductor device are remarkably deteriorated is given as an example.

  In addition, after the semiconductor substrate remaining between the trenches is thermally oxidized, the oxide film is removed by anisotropic etching to lower the void opening position, or the void is covered with a resist and taper etched. A method of protecting the insulating film and making it difficult for the voids to open is also conceivable. Even if such a method is used, the film thickness of the insulating film on the void is about 1 μm at the maximum, and the void is opened in the subsequent manufacturing process in consideration of variations in processing conditions in each manufacturing process. The problem is given as an example.

  In order to solve the above-described problems caused by the prior art, the present invention provides a method of manufacturing a semiconductor device in which an insulating film is formed in a trench, and a sufficient thickness of the insulating film on the void after forming can be secured. An object of the present invention is to provide a semiconductor device manufacturing apparatus.

  In order to solve the above-described problems and achieve the object, in the present invention, an insulating coating material having a viscosity of 0.5 mPa · s to 5 mPa · s is applied to a plurality of adjacent trenches formed on the surface of the semiconductor substrate. Then, an insulating region is formed in the trench by heat treatment.

  In order to solve the above-described problems and achieve the object, a manufacturing method of a semiconductor device according to claim 1 includes a trench forming step of forming a trench in a surface portion of a semiconductor substrate, and a viscosity of 0 inside the trench. And an insulating film forming step of forming an insulating film using an insulating coating material of 5 mPa · s to 5 mPa · s.

  According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the first aspect, wherein the trench forming step includes a concave portion formed in a rectangular shape having a long side and a short side. A trench having a length of 10 μm or more and a length of the short side of 0.5 μm to 5 μm is formed.

  According to a third aspect of the present invention, there is provided a semiconductor device manufacturing method according to the first aspect, wherein the insulating film forming step includes a coating step of coating the insulating coating material in the trench, and the coating step. And a heat treatment step of heat-treating the insulating coating material applied by the method.

  According to a fourth aspect of the present invention, there is provided a semiconductor device manufacturing apparatus comprising: a trench forming means for forming a trench in a surface portion of a semiconductor substrate; and an insulating coating having a viscosity of 0.5 mPa · s to 5 mPa · s inside the trench. And an insulating film forming means for forming an insulating film using a material.

  According to a fifth aspect of the present invention, there is provided a semiconductor device manufacturing apparatus according to the fourth aspect, wherein the trench forming means has a recess formed in a rectangular shape having a long side and a short side. A trench having a length of 10 μm or more and a length of the short side of 0.5 μm to 5 μm is formed.

  According to a sixth aspect of the present invention, in the semiconductor device manufacturing apparatus according to the fourth aspect of the present invention, the insulating film forming means includes a coating means for coating the insulating coating material in the trench, and the coating means. And heat treatment means for heat-treating the insulating coating material applied by the method.

  According to the first to third aspects of the present invention, it is possible to sufficiently secure the thickness of the insulating film on the void of the insulating film embedded in the trench. Further, by adjusting the viscosity, the thickness of the insulating film on the void can be ensured to 5 μm.

  Further, according to the inventions of claims 4 to 6, it is possible to manufacture a semiconductor device in which the thickness of the insulating film on the insulating film void buried in the trench is sufficiently secured.

  According to the semiconductor device manufacturing method and the semiconductor device manufacturing apparatus according to the present invention, it is possible to sufficiently secure the thickness of the insulating film on the void of the insulating film embedded in the trench. Therefore, the manufacturing process can be simplified and the yield of the manufactured semiconductor device can be improved.

  Exemplary embodiments of a semiconductor device manufacturing method and a semiconductor device manufacturing apparatus according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Embodiment)
In the embodiment of the present invention, a method of manufacturing a lateral trench MOSFET using a silicon semiconductor substrate is shown, and an n ⁻ offset drain region is formed along an insulating region (trench) having a depth and a base length of 20 μm, respectively. An example of the case will be described.

  First, a lateral trench MOSFET manufactured by a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described. FIG. 1 is a cross-sectional view of a principal part showing a lateral trench MOSFET manufactured by a method for manufacturing a semiconductor device according to an embodiment of the present invention.

In FIG. 1, the lateral trench MOSFET includes a p-type semiconductor substrate 101, a trench 102, an insulating region 103, an n ⁻ offset drain region 104, a p well region 105, and a p ⁺ source region. 106, an n ⁺ source region 107, an n well region 108, an n ⁺ drain region 109, a gate oxide film 110, a gate electrode 111, a source electrode 112, and a drain electrode 113.

The trench 102 is formed from the surface of the surface portion of the p-type semiconductor substrate 101. The insulating region 103 is formed by applying a viscous insulating coating material to the trench 102 and performing a heat treatment. The n ⁻ offset drain region 104 is formed so as to surround the periphery of the trench 102 (insulating region 103), specifically, the side surface and the bottom surface of the trench 102 (insulating region 103).

The p well region 105 is formed adjacent to the outside of the n ⁻ offset drain region 104 in the surface portion of the p type semiconductor substrate 101 on the source side with respect to the trench region. The p well region 105 serves to lower the base resistance. The p ⁺ source region 106 is formed on the surface portion of the p well region 105. The n ⁺ source region 107 is formed adjacent to the p ⁺ source region 106 in the surface portion of the p well region 105. The n-well region 108 is formed on the surface of the n ⁻ offset drain region 104 on the drain side (opposite the source side) with respect to the trench 102 (insulating region 103).

n ⁺ drain region 109, the surface of the n-well region 108, n ^- are formed in contact with the offset drain region 104. Gate oxide film 110 is formed on the surface from n ⁺ source region 107 to the source side portion of n ⁻ offset drain region 104. The gate electrode 111 is formed on the gate oxide film 110. Source electrode 112 is formed on p ⁺ source region 106 and n ⁺ source region 107.

Source electrode 112 is electrically connected to p ⁺ source region 106 and n ⁺ source region 107. The drain electrode 113 is formed on the n ⁺ drain region 109. The drain electrode 113 is electrically connected to the n ⁺ drain region 109. In FIG. 1, the reference numerals are omitted, but the gate electrode 111 and the trench 102 (insulating region 103) are covered with an interlayer insulating film.

  Next, a manufacturing process of the lateral trench MOSFET having the configuration shown in FIG. 1 will be described. 2 to 7-2 (excluding FIG. 6-3) are explanatory views showing an outline of a lateral trench MOSFET in the middle of manufacture according to the embodiment of the present invention. First, a p-type impurity, for example, boron (B) is ion-implanted into the surface of the p-type semiconductor substrate 101 to form a p-well region 105 (not shown).

  Further, an n-type impurity such as phosphorus (P) is ion-implanted into the surface of the p-type semiconductor substrate 101 to form an n-well region 108 (not shown). Here, the order of forming the p well region 105 and the n well region 108 may be reversed. After the p-well region 105 and the n-well region 108 are formed, next, for example, a 1.4 μm thermal oxide film 201 is formed on the surface of the p-type semiconductor substrate 101 as shown in FIG.

Next, as shown in FIG. 3A, by using a photoresist mask (not shown), the thermal oxide film 201 is formed only in the region above the region where the n ⁻ offset drain region 104 is formed and the trench 102 is formed. Remove in slit form. Here, the upper side in FIG. 2 is the upper side of the p-type semiconductor substrate 101 where the thermal oxide film 201 is formed. 3A, the thermal oxide film 201 in the region where the p-type semiconductor substrate 101 is exposed is removed. 3-2 to 3-4 show an AA ′ sectional view, a BB ′ sectional view, and a CC ′ sectional view of FIG. 3-1.

  Next, by using RIE (reactive ion etching apparatus), trench etching of the p-type semiconductor substrate 101 is performed using the thermal oxide film 201 as a mask, and as shown in FIG. Form with depth. The depth of the trench 102 is preferably 10 μm or more.

  Moreover, the mask width used when forming the trench 102 indicated by the arrow 301 in FIG. 3A is, for example, 2 μm. At this time, since the length of the short side of the trench 102 formed after the trench etching is equal to the mask width (2 μm) described above, the length of the short side of the trench 102 is similarly changed to the arrow 301 in FIG. Indicated by. The length of the short side is preferably 0.5 μm to 5 μm.

  Moreover, the mask width on the p-type semiconductor substrate 101 between the adjacent trenches 102 indicated by the arrow 302 in FIG. 3A is, for example, 2 μm. The taper angle of the trench 102 is 90 ° ± 0.5 °. Next, the p-type semiconductor substrate 101 is buffer oxidized. Next, as the n-type impurity, for example, vertical ion implantation of phosphorus (P) and oblique ion implantation in the long side direction of trench 102 (side wall 303 of trench 102) are performed.

Then, the p-type semiconductor substrate 101 is driven in a high temperature atmosphere of 1100 ° C. or higher, and implantation is performed as shown in FIGS. 4-1 (AA ′ sectional view) and FIG. 4-2 (BB ′ sectional view). The phosphorus (P) thus diffused is diffused into the side wall 303 and the bottom surface 401 of the trench 102 to form an n ⁻ offset drain region 104 having a depth of 4 μm and a peak concentration of 5 × 10 ¹⁵ cm ⁻³ , for example.

  Next, the thermal oxide film 201 is completely removed by wet etching, for example, and the p-type semiconductor substrate 103 between the trenches 102 is completely oxidized by thermal oxidation, as shown in FIG. In FIG. 5-1 (AA ′ cross-sectional view) and FIG. 5-2 (BB ′ cross-sectional view), reference numeral 501 denotes a region oxidized by heat treatment after removing the thermal oxide film 201 (oxidized region). 501). The oxidized region 501 is formed on the surface of the p-type semiconductor substrate 101 and around the trench 102.

  Then, as shown in FIG. 6A (AA ′ cross-sectional view), for example, an insulating coating material whose viscosity is adjusted to 1.5 mPa · s is applied to the trench 102, and in a steam atmosphere, for example, 1100 Heat treatment (pyrogenic oxidation) is carried out at 11 ° C. for 11 hours. Thus, the insulating film 601 is formed so as to cover the inside of the trench 102 and the top of the trench 102. The insulating coating material is applied by, for example, a spin coating method. The viscosity of the insulating coating material is preferably 0.5 mPa · s to 5 mPa · s.

  As described above, by adjusting the viscosity of the insulating coating material to a value in the range of 0.5 mPa · s to 5 mPa · s, the inside of the trench 102 as shown in FIG. 6-2 (BB ′ sectional view). The thickness (arrow 603) of the insulating film 601 formed over the void 602 formed in the insulating film 601 can be sufficiently ensured. In this embodiment, the thickness of the insulating film 601 (arrow 603) is 5 μm.

Further, when the heat treatment time is doubled under the same conditions as described above, the thickness of the insulating film 601 is about ^20.5 times. Here, FIG. 6-3 shows a SEM (Scanning Electron Microscope) photograph during the manufacturing process corresponding to the schematic diagram of FIG.

  Next, an oxide film etchback is performed, and as shown in FIGS. 7-1 (AA ′ cross-sectional view) and FIG. 7-2 (BB ′ cross-sectional view), an insulating film on the surface of the p-type semiconductor substrate 101 is formed. 601 is removed. At this time, as described with reference to FIG. 6B, since the thickness of the insulating film 601 over the void 602 is 5 μm or more, the upper surface of the void 602 is covered with a resist when the insulating film 601 is removed. , The step of protecting becomes unnecessary. For this reason, the possibility that the void 602 opens due to variations in processing conditions in each manufacturing process is reduced.

As described above, the trench 102 is formed on the surface of the p-type semiconductor substrate 101, and the n ⁻ offset drain region 104 is formed on the surface of the trench 102. Thereafter, the manufacturing process of filling the formed trench 102 with the insulating film 601 is completed. Thereafter, the lateral MOSFET as shown in FIG. 1 is formed using the same manufacturing process as that of a normal lateral MOSFET device.

  As described above, according to the semiconductor device manufacturing method and the semiconductor device manufacturing apparatus of the present invention, it is possible to sufficiently ensure the thickness of the insulating film on the void of the insulating film embedded in the trench. Therefore, simplification of the manufacturing process and improvement of the yield of the manufactured semiconductor device can be realized.

  As described above, the method for manufacturing a semiconductor device and the device for manufacturing a semiconductor device according to the present invention are useful for a lateral MOSFET, and are particularly suitable for a high voltage MOSFET used for a power IC or the like.

It is principal part sectional drawing which shows the lateral trench MOSFET manufactured by the manufacturing method of the semiconductor device concerning embodiment of this invention. It is explanatory drawing which shows the outline of the horizontal type | mold trench MOSFET in the middle of manufacture by embodiment of this invention. It is explanatory drawing which shows the outline of the horizontal type | mold trench MOSFET in the middle of manufacture by embodiment of this invention. It is A-A 'sectional drawing of FIGS. It is B-B 'sectional drawing of FIGS. FIG. 3 is a C-C ′ sectional view of FIG. It is explanatory drawing (A-A 'sectional drawing) which shows the outline of the horizontal type | mold trench MOSFET in the middle of manufacture by embodiment of this invention. It is explanatory drawing (B-B 'sectional drawing) which shows the outline of horizontal type | mold trench MOSFET in the middle of manufacture by embodiment of this invention. It is explanatory drawing (A-A 'sectional drawing) which shows the outline of the horizontal type | mold trench MOSFET in the middle of manufacture by embodiment of this invention. It is explanatory drawing (B-B 'sectional drawing) which shows the outline of horizontal type | mold trench MOSFET in the middle of manufacture by embodiment of this invention. It is explanatory drawing (A-A 'sectional drawing) which shows the outline of the horizontal type | mold trench MOSFET in the middle of manufacture by embodiment of this invention. It is explanatory drawing (B-B 'sectional drawing) which shows the outline of horizontal type | mold trench MOSFET in the middle of manufacture by embodiment of this invention. 6 is an SEM photograph showing a lateral MOSFET in the manufacturing process corresponding to the schematic diagram of FIG. It is explanatory drawing (A-A 'sectional drawing) which shows the outline of the horizontal type | mold trench MOSFET in the middle of manufacture by embodiment of this invention. It is explanatory drawing (B-B 'sectional drawing) which shows the outline of horizontal type | mold trench MOSFET in the middle of manufacture by embodiment of this invention.

Explanation of symbols

101 p-type semiconductor substrate 102 trench 103 insulating region 104 n ^- offset drain region 105 p well region 106 p ⁺ source region 107 n ⁺ source region 108 n well region 109 n ⁺ drain region 110 gate oxide film 111 gate electrode 112 source electrode 113 Drain electrode 201 Thermal oxide film 501 Oxidation region 601 Insulating film 602 Void

Claims (6)

A trench forming step of forming a trench in the surface portion of the semiconductor substrate;
An insulating film forming step of forming an insulating film inside the trench using an insulating coating material having a viscosity of 0.5 mPa · s to 5 mPa · s;
A method for manufacturing a semiconductor device, comprising:   The trench forming step includes forming a trench having a recess formed in a rectangular shape having a long side and a short side and having a depth of 10 μm or more and a length of the short side of 0.5 μm to 5 μm. A method for manufacturing a semiconductor device according to claim 1. The insulating film forming step includes
An application step of applying the insulating coating material inside the trench;
A heat treatment step of heat-treating the insulating coating material applied by the application step;
The method of manufacturing a semiconductor device according to claim 1, comprising: Trench forming means for forming a trench in the surface portion of the semiconductor substrate;
Insulating film forming means for forming an insulating film inside the trench using an insulating coating material having a viscosity of 0.5 mPa · s to 5 mPa · s;
An apparatus for manufacturing a semiconductor device, comprising:   The trench forming means forms a trench having a concave portion formed in a rectangular shape having a long side and a short side and having a depth of 10 μm or more and a length of the short side of 0.5 μm to 5 μm. The semiconductor device manufacturing apparatus according to claim 4. The insulating film forming means includes
Application means for applying the insulating coating material inside the trench;
Heat treatment means for heat-treating the insulating coating material applied by the application means;
The apparatus for manufacturing a semiconductor device according to claim 4, comprising:

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