JP2005045147A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device and the manufacturing method thereof which has in a single semiconductor layer transistors having different gate and drain withstanding voltages from each other. <P>SOLUTION: The semiconductor device includes a semiconductor layer 10, gate insulation layers 60, 62 formed on the semiconductor layer 10, offset trench insulation layers 50, 52 formed on the lateral sides of the gate insulation layers 60, 62 by a trench element separating method, offset impurity layers 30, 32 formed under the offset trench insulation layers 50, 52, and gate electrodes 70, 72 formed on the gate insulation layers 60, 62. Further, in the adjacent ends of the gate insulation layers 60, 62 to the offset trench insulation layers 50, 52, the rear surfaces of the adjacent ends are so inclined respectively as to fall toward the offset trench insulation layers 50, 52. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having transistors with different gate breakdown voltages and drain breakdown voltages in the same semiconductor layer and a method for manufacturing the same.

  Currently, high breakdown voltage transistors having a LOCOS (Local Oxidation of Silicon) offset structure are known. In a high breakdown voltage transistor having a LOCOS offset structure, a LOCOS layer for electric field relaxation is provided between a gate insulating layer and a drain region, and an offset impurity layer is formed below the LOCOS layer.

  In recent years, research and development have been conducted to reduce the size of ICs mounted on electronic devices. As such a technique, there is a method in which a low voltage operation transistor and a high voltage operation high voltage transistor are mixedly mounted on the same substrate (same chip) to reduce the chip area of the IC.

  In the case where the high breakdown voltage transistor provided with the LOCOS layer for electric field relaxation and the low voltage driving transistor are formed on the same substrate, for example, a LOCOS layer for element isolation and a LOCOS layer for electric field relaxation. Can be manufactured in the same process, so that the semiconductor device having such a mode can be manufactured.

  However, due to the recent demand for miniaturization, the element isolation region forming method is shifting from the LOCOS method to the trench element isolation method, and a method of substituting the LOCOS layer for mitigating the electric field of the high voltage transistor with a trench insulating layer. Has been proposed.

  In this case, when a thick gate insulating layer is formed in the high breakdown voltage transistor formation region, the thickness of the gate insulating layer may be partially reduced in a region adjacent to the trench insulating layer. As a result, the breakdown voltage is reduced at the thinned portion, and the reliability of the semiconductor device is impaired.

  An object of the present invention is to provide a highly reliable semiconductor device having transistors with different gate breakdown voltages and drain breakdown voltages in the same semiconductor layer and a method for manufacturing the same.

1. The semiconductor device according to the present invention is
A semiconductor layer;
A gate insulating layer formed on the semiconductor layer;
An offset trench insulating layer formed by a trench isolation method on the side of the gate insulating layer,
An offset impurity layer formed below the offset trench insulating layer;
A gate electrode formed on the gate insulating layer,
At the end portion of the gate insulating layer adjacent to the offset trench insulating layer, the lower surface of the end portion is inclined so as to be lowered toward the offset trench insulating layer.

  According to this semiconductor device, the lower surface of the end portion of the gate insulating layer adjacent to the offset trench insulating layer is inclined so as to be lowered toward the offset trench insulating layer. That is, the end portion of the gate insulating layer protrudes downward. Therefore, the thickness of the end portion of the gate insulating layer is thicker in the region adjacent to the offset trench insulating layer than when the lower surface of the end portion of the gate insulating layer is not inclined. As a result, the problem that the thickness of the gate insulating layer is partially thinned in a region adjacent to the offset trench insulating layer is solved, and the entire gate insulating layer has a desired uniform thickness. . Therefore, a highly reliable semiconductor device can be provided.

  In the semiconductor device according to the present invention, an inclination angle of the lower surface of the end portion in the gate insulating layer with respect to a horizontal direction may be 10 to 30 °.

  In the semiconductor device according to the present invention, the horizontal length of the lower surface of the end portion of the gate insulating layer may be 0.1 to 0.4 μm.

2. The semiconductor device according to the present invention is
A semiconductor layer;
An element isolation region formed by a trench element isolation method for separating the high breakdown voltage transistor formation region and the low voltage drive transistor formation region in the semiconductor layer;
A first gate insulating layer formed in the high breakdown voltage transistor formation region;
A first gate electrode formed on the first gate insulating layer;
An offset trench insulating layer formed by a trench isolation method on a side of the first gate insulating layer;
An offset impurity layer formed below the offset trench insulating layer;
A second gate insulating layer formed in the low-voltage driving transistor formation region;
A gate electrode formed on the second gate insulating layer,
At the end portion of the first gate insulating layer adjacent to the offset trench insulating layer, the lower surface of the end portion is inclined so as to be lowered toward the offset trench insulating layer.

  According to this semiconductor device, at the end portion of the first gate insulating layer adjacent to the offset trench insulating layer of the high breakdown voltage transistor, the lower surface of the end portion is lowered toward the offset trench insulating layer. Inclined. That is, the end portion of the first gate insulating layer protrudes downward. Therefore, the thickness of the end portion of the first gate insulating layer is thicker in the region adjacent to the offset trench insulating layer than when the lower surface of the end portion of the first gate insulating layer is not inclined. As a result, the problem that the film thickness of the first gate insulating layer is partially thinned in a region adjacent to the offset trench insulating layer is solved, and the entire first gate insulating layer has a desired uniform thickness. It becomes the film thickness. Therefore, a highly reliable semiconductor device can be provided.

  In the semiconductor device according to the present invention, an inclination angle of the lower surface of the end portion of the first gate insulating layer with respect to a horizontal direction may be 10 to 30 °.

  In the semiconductor device according to the present invention, the horizontal length of the lower surface of the end portion of the first gate insulating layer may be 0.1 to 0.4 μm.

3. A method for manufacturing a semiconductor device according to the present invention includes:
Forming a high breakdown voltage transistor formation region and a low voltage drive transistor formation region in a semiconductor layer, and forming an offset trench insulating layer in the high breakdown voltage transistor formation region by a trench element isolation method;
Forming an offset impurity layer below the offset trench insulating layer;
Etching the semiconductor layer adjacent to the offset trench insulating layer to form a surface inclined with respect to the upper surface of the semiconductor layer;
Forming a gate insulating layer in the high breakdown voltage transistor formation region;
Forming a gate electrode on the gate insulating layer,
The inclined surface is lowered toward the offset trench insulating layer.

  According to this method of manufacturing a semiconductor device, the thickness of the gate insulating layer is included in the region adjacent to the offset trench insulating layer only by adding the step of forming the inclined surface. It can be formed thicker than when there is no step of forming a trench (hereinafter also referred to as a “tapered trench”). Therefore, the slight increase in the number of steps can solve the problem that the thickness of the gate insulating layer is partially reduced in a region adjacent to the offset trench insulating layer. , A desired uniform film thickness can be obtained. As a result, a highly reliable semiconductor device can be provided.

  In the method for manufacturing a semiconductor device according to the present invention, an inclination angle of the inclined surface with respect to a horizontal direction may be 10 to 30 °.

  In the method for manufacturing a semiconductor device according to the present invention, the horizontal length of the inclined surface may be 1 to 2 μm.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

1. Semiconductor Device First, the semiconductor device according to this embodiment will be described. FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to the present embodiment, and FIG. 2 is an enlarged view showing a portion indicated by reference numeral A in FIG.

  The semiconductor device according to the present embodiment has a semiconductor layer 10. The semiconductor device is provided with a high breakdown voltage transistor formation region 100 and a low voltage drive transistor formation region 200. The high breakdown voltage transistor formation region 100 includes an n-type high breakdown voltage transistor formation region 100N and a p-type high breakdown voltage transistor formation region 100P. The low voltage drive transistor formation region 200 includes an n-type low voltage drive transistor formation region 200N and a p-type low voltage drive transistor formation region 200P. An n-type high voltage transistor 100n is formed in the n-type high voltage transistor formation region 100N, and a p-type high voltage transistor 100p is formed in the p-type high voltage transistor formation region 100P. Similarly, an n-type low voltage drive transistor 200n is formed in the n-type low voltage drive transistor formation region 200N, and a p-type low voltage drive transistor 200p is formed in the p-type low voltage drive transistor formation region 200P. .

  That is, the n-type high voltage transistor 100n, the p-type high voltage transistor 100p, the n-type low voltage driving transistor 200n, and the p-type low voltage driving transistor 200p are mixedly mounted on the same substrate (same chip). . Although only four transistors are shown in FIG. 1, this is for convenience and it goes without saying that a plurality of transistors are formed on the same substrate.

1.1 High Voltage Transistor Formation Region 100 First, the high voltage transistor formation region 100 will be described. A first element isolation region 110 is formed at the boundary between the high breakdown voltage transistor formation region 100 and the low voltage drive transistor formation region 200. That is, the first element isolation region 110 separates the high breakdown voltage transistor formation region 100 and the low voltage drive transistor formation region 200. As a result, the high breakdown voltage transistor formation region 100 is surrounded by the first element isolation region 110.

  In the high breakdown voltage transistor formation region 100, an n-type high breakdown voltage transistor 100n and a p-type high breakdown voltage transistor 100p are formed. A second element isolation region 120 is provided between the adjacent n-type high voltage transistor 100n and the p-type high voltage transistor 100p.

  Next, the configuration of the n-type high voltage transistor 100n and the p-type high voltage transistor 100p will be described.

  The n-type high breakdown voltage transistor 100n includes a first gate insulating layer 60, an offset trench insulating layer 50, a gate electrode 70, an n-type offset impurity layer 30, a sidewall insulating layer 80, and an n-type source / drain region 90. And have.

  The first gate insulating layer 60 is formed at least above the p-type first well 20 and the n-type offset impurity layer 30 and between the two offset trench insulating layers 50. The p-type first well 20 is formed in the upper part of the n-type first well 22. Then, as shown in FIG. 2, the lower surface of the first gate insulating layer 60 adjacent to the offset trench insulating layer 50 is inclined so as to be lowered toward the offset trench insulating layer 50. ing. That is, the semiconductor layer 10 has a groove in a region adjacent to the offset trench insulating layer 50. The groove has an inclined surface that goes down toward the offset trench insulating layer 50. Therefore, the end portion of the first gate insulating layer 60 is formed to protrude downward.

  The inclination angle θ1 with respect to the horizontal direction of the lower surface of the end portion of the first gate insulating layer 60 is, for example, 10 to 30 °, and preferably 15 to 30 °. When the tilt angle θ1 is smaller than 10 °, when the thick first gate insulating layer 60 is formed, the first gate insulating layer is formed in a region where the offset trench insulating layer 50 and the first gate insulating layer 60 are adjacent to each other. The film thickness of 60 may be partially thinner than the desired film thickness. When the tilt angle θ1 exceeds 30 °, the first gate insulating layer 60 is located in the region where the offset trench insulating layer 50 and the first gate insulating layer 60 are adjacent, as in the case where the tilt angle θ1 is smaller than 10 °. May be partially thinner than the desired film thickness.

  The horizontal length L1 of the lower surface of the end portion of the first gate insulating layer 60 is, for example, 0.1 to 0.4 μm, and preferably 0.1 μm. When the length L1 is shorter than 0.1 μm, when the thick first gate insulating layer 60 is formed, the first gate insulating layer is formed in the region where the offset trench insulating layer 50 and the first gate insulating layer 60 are adjacent to each other. The layer 60 cannot have a desired film thickness. When the length L1 exceeds 0.4 μm, the plane area occupied by the first gate insulating layer 60 becomes large, and the semiconductor device cannot be sufficiently miniaturized.

  The offset trench insulating layer 50 is provided above the n-type offset impurity layer 30 at both ends of the first gate insulating layer 60. The gate electrode 70 is formed at least above the first gate insulating layer 60. The n-type offset impurity layer 30 is formed in the upper part in the p-type first well 20. The sidewall insulating layer 80 is formed on the side surface of the gate electrode 70. The n-type source / drain region 90 is provided in the semiconductor layer 10 outside the sidewall insulating layer 80.

  The p-type high voltage transistor 100p includes a first gate insulating layer 62, an offset trench insulating layer 52, a gate electrode 72, a p-type offset impurity layer 32, a sidewall insulating layer 82, and a p-type source / drain region 92. And have.

  The first gate insulating layer 62 is formed at least above the n-type first well 22 and the p-type offset impurity layer 32 and between the two offset trench insulating layers 52. In the end portion of the first gate insulating layer 62 adjacent to the offset trench insulating layer 52, the lower surface of the end portion is inclined so as to be lowered toward the offset trench insulating layer 52. The inclination angle and the horizontal length of the lower surface of the end portion of the first gate insulating layer 62 are the same as those of the n-type high breakdown voltage transistor 100n described above, and the description thereof is omitted.

  The offset trench insulating layer 52 is provided above the p-type offset impurity layer 32 at both ends of the first gate insulating layer 62. The gate electrode 72 is formed at least above the first gate insulating layer 62. The p-type offset impurity layer 32 is formed in the upper part in the n-type first well 22. The sidewall insulating layer 82 is formed on the side surface of the gate electrode 72. The p-type source / drain region 92 is provided in the semiconductor layer 10 outside the sidewall insulating layer 82.

1.2 Low Voltage Drive Transistor Formation Region 200 Next, the low voltage drive transistor formation region 200 will be described. In the low voltage drive transistor formation region 200, an n-type low voltage drive transistor 200n and a p-type low voltage drive transistor 200p are provided. A third element isolation region 210 is provided between the adjacent n-type low voltage driving transistor 200n and the p-type low voltage driving transistor 200p.

  Next, the configuration of each transistor will be described.

  The n-type low voltage driving transistor 200n includes a second gate insulating layer 64, a gate electrode 74, a sidewall insulating layer 84, an n-type extension region 34, and an n-type source / drain region 94.

  The second gate insulating layer 64 is provided at least above the channel region in the p-type second well 24. The gate electrode 74 is formed above the second gate insulating layer 64. The sidewall insulating layer 84 is formed on the side surface of the gate electrode 74. The n-type extension region 34 is formed in the upper part in the p-type second well 24. The n-type source / drain region 94 is provided in the semiconductor layer 10 outside the sidewall insulating layer 84.

  The p-type low voltage driving transistor 200p includes a second gate insulating layer 66, a gate electrode 76, a sidewall insulating layer 86, a p-type extension region 36, and a p-type source / drain region 96.

  The second gate insulating layer 66 is provided at least above the channel region in the n-type second well 26. The gate electrode 76 is formed above the second gate insulating layer 66. The sidewall insulating layer 86 is formed on the side surface of the gate electrode 76. The p-type extension region 36 is formed in the upper part in the n-type second well 26. The p-type source / drain region 96 is provided in the semiconductor layer 10 outside the sidewall insulating layer 86.

  The semiconductor device according to the present embodiment has the following features.

  In the semiconductor device according to the present embodiment, the lower surfaces of the end portions of the first gate insulating layers 60 and 62 of the high breakdown voltage transistors 100n and 100p adjacent to the offset trench insulating layers 50 and 52 are offset. It inclines so that it may go down toward the trench insulating layers 50 and 52. That is, the end portions of the first gate insulating layers 60 and 62 protrude downward. Therefore, the thickness of the end portions of the first gate insulating layers 60 and 62 is such that the lower surfaces of the end portions of the first gate insulating layers 60 and 62 are not inclined in the region adjacent to the offset trench insulating layers 50 and 52. It is thicker than As a result, the problem that the thickness of the first gate insulating layers 60 and 62 becomes partially thin in the region adjacent to the offset trench insulating layers 50 and 52 is solved, and the entire first gate insulating layers 60 and 62 are eliminated. However, it becomes a desired uniform film thickness. Therefore, a highly reliable semiconductor device can be provided.

  Further, in the semiconductor device according to the present embodiment, the element isolation regions 110, 120, 210 and the offset trench insulating layers 50, 52 are formed by the trench element isolation method, and the LOCOS method, the semi-recessed LOCOS method, or the like is used. In comparison, the semiconductor device can be miniaturized and the first gate insulating layers 60 and 62 can be partially thinned with fewer manufacturing steps.

2. Semiconductor Device Manufacturing Method Next, a semiconductor device manufacturing method according to the present embodiment will be described with reference to FIGS. 1 and 3 to 23. 1, FIG. 3 to FIG. 17 and FIG. 19 to FIG. 23 are cross-sectional views schematically showing the steps of the semiconductor device manufacturing method according to the present embodiment, and FIG. It is a figure which expands and shows a part.

  (A) First, as shown in FIG. 3, the pad layer 12 is formed on the semiconductor layer 10. The semiconductor layer 10 includes at least silicon and is made of silicon, silicon-germanium, or the like. The semiconductor layer 10 can be a silicon layer in a bulk silicon substrate or an SOI (Silicon On Insulator) substrate. As the pad layer 12, silicon oxide, silicon nitride oxide, or the like can be used. The pad layer 12 can be formed by, for example, a CVD method.

  (B) Next, as shown in FIG. 4, the stopper layer 14 is formed on the pad layer 12. As the stopper layer 14, for example, silicon nitride can be used. The stopper layer 14 can be formed by, for example, a CVD method.

  Next, a resist layer R1 having a predetermined pattern is formed on the stopper layer 14. In the high breakdown voltage transistor formation region 100, the resist layer R1 is formed to have an opening above the region where the first element isolation region 110, the second element isolation region 120, and the offset trench insulating layers 50 and 52 are formed. The low voltage driving transistor formation region 200 is formed to have an opening above the region where the first element isolation region 110 and the third element isolation region 210 are formed.

  (C) Next, as shown in FIG. 5, the stopper layer 14 and the pad layer 12 are etched using the resist layer R1 (see FIG. 4) as a mask. Next, the resist layer R1 is removed by ashing or the like. Next, using the stopper layer 14 and the pad layer 12 as a mask, the semiconductor layer 10 is etched to form offset trenches 40 and 42 and a trench 44. Etching of the semiconductor layer 10 is performed by dry etching, for example.

  (D) Next, as shown in FIG. 6, a trench oxide layer 46 is formed on the surfaces of the offset trenches 40, 42 and the trench 44. The trench oxide layer 46 is formed by, for example, a thermal oxidation method. The film thickness of the trench oxide layer 46 is, for example, 30 to 50 nm.

  Moreover, before forming the trench oxide layer 46, the edge part of the pad layer 12 can be etched as needed. By adopting such an embodiment, in forming the trench oxide layer 46, the semiconductor layer 10 and the trench oxide layer 46 at the upper ends of the offset trenches 40 and 42 and the trench 44 are formed to be rounded. Can do. Then, the semiconductor layer 10 at the upper ends of the offset trenches 40 and 42 and the trench 44 has a rounded shape, so that the gate insulating film becomes a thin film at the upper ends of the offset trenches 40 and 42 and the trench 44 in a later process. Therefore, it is possible to avoid influences such as a decrease in gate breakdown voltage and formation of parasitic transistor elements as much as possible. In addition, since the trench oxide layer 46 at the upper ends of the offset trenches 40 and 42 and the trench 44 is formed to be rounded, the level difference becomes gentle. Therefore, the offset trench insulating layers 50 and 52 are formed in a later step. In addition, the trench insulating layer 48 can be satisfactorily embedded.

  (E) Next, as shown in FIG. 7, the first insulating layer 54 is formed so as to fill the offset trenches 40 and 42 and the trench 44. The first insulating layer 54 is formed so as to fill at least the offset trenches 40 and 42 and the trench 44 and further cover the stopper layer 14.

  Next, a second insulating layer 56 is formed on the first insulating layer 54. By forming the second insulating layer 56, the first insulating layer 54 can be satisfactorily planarized in the next step (f). As the second insulating layer 56, for example, SOG can be used.

  Further, another means can be used to improve the flatness. For example, a mask layer such as a resist is formed in the concave portion of the first insulating layer 54 that is uneven due to the shape of the trench 44, and the convex portion of the first insulating layer 54 is replaced with the concave portion of the first insulating layer 54. It is also possible to use a means of etching so that the height is substantially the same as the height of.

  (F) Next, as shown in FIG. 8, the second insulating layer 56 and the first insulating layer 54 are removed until the upper surface of the stopper layer 14 is exposed. The removal of the second insulating layer 56 and the first insulating layer 54 is performed by, for example, a CMP method. Thus, offset trench insulating layers 50 and 52 are formed in the offset trenches 40 and 42 in the high breakdown voltage transistor formation region 100. A trench insulating layer 48 is formed in the trench 44. As a result, the first element isolation region 110, the second element isolation region 120, and the third element isolation region 210 are formed.

  (G) Next, as shown in FIG. 9, the stopper layer 14 and the pad layer 12 are removed. The stopper layer 14 is removed by, for example, wet etching with hot phosphoric acid. The pad layer 12 is removed by wet etching with hydrofluoric acid, for example.

  (H) Next, as shown in FIG. 10, a sacrificial oxide layer 13 is formed on the surface of the semiconductor layer 10. The sacrificial oxide layer 13 is formed by, for example, a thermal oxidation method. Next, the mask layer 16 is formed on the sacrificial oxide layer 13, the offset trench insulating layers 50 and 52, and the trench insulating layer 48. As mask layer 16, for example, a silicon nitride film can be used. The mask layer 16 can be formed by, for example, a CVD method.

  (I) Next, as shown in FIG. 11, in the p-type high breakdown voltage transistor formation region 100P, the first impurity layer 22a to be the n-type first well is formed. Specifically, a resist layer R2 having a predetermined pattern is formed by a lithography technique. By introducing n-type impurity ions such as phosphorus and arsenic into the semiconductor layer 10 using the resist layer R2 as a mask, the first impurity layer 22a is formed. Thereafter, the resist layer R2 is removed by ashing. Next, the semiconductor layer 10 is subjected to heat treatment to thermally diffuse the impurities in the first impurity layer 22a.

  (J) Next, as shown in FIG. 12, in the n-type high breakdown voltage transistor formation region 100N, the first impurity layer 20a to be the p-type first well is formed. Specifically, a resist layer R3 having a predetermined pattern is formed by a lithography technique. Using the resist layer R3 as a mask, a p-type impurity such as boron is implanted into the semiconductor layer 10 once or a plurality of times, thereby forming the first impurity layer 20a in the semiconductor layer 10. Thereafter, the resist layer R3 is removed by ashing. Next, heat treatment is performed on the semiconductor layer 10 to simultaneously thermally diffuse the impurity of the p-type first impurity layer 20a and the impurity of the n-type first impurity layer 22a formed in the step (i).

  (K) Next, as shown in FIG. 13, in the n-type high breakdown voltage transistor formation region 100N, a second impurity layer 30a is formed which becomes an n-type offset impurity layer in the n-type high breakdown voltage transistor. Specifically, first, a resist layer R4 that covers a predetermined region is formed. By introducing n-type impurities into the semiconductor layer 10 using the resist layer R4 as a mask, the second impurity layer 30a is formed. Thereafter, the resist layer R4 is removed by ashing.

  (L) Next, as shown in FIG. 14, in the p-type high breakdown voltage transistor formation region 100P, a second impurity layer 32a is formed which becomes a p-type offset impurity layer in the p-type high breakdown voltage transistor. Specifically, first, a resist layer R5 that covers a predetermined region is formed. A second impurity layer 32a is formed by introducing p-type impurities into the semiconductor layer 10 using the resist layer R5 as a mask. Thereafter, the resist layer R5 is removed by ashing. Note that the order of the steps (j) and (k) can be performed in the reverse order of the present embodiment.

  (M) Next, as shown in FIG. 15, the semiconductor layer 10 is subjected to a heat treatment, whereby the p-type first well 20, the n-type first well 22, the n-type offset impurity layer 30 in the n-type high breakdown voltage transistor, A p-type offset impurity layer 32 in the p-type high breakdown voltage transistor is formed. That is, the impurity of the first impurity layer 20a is diffused, and the p-type first well 20 is formed. Impurities in the first impurity layer 22a are diffused to form the n-type first well 22. The impurities of the second impurity layer 30a are diffused to form the n-type offset impurity layer 30 in the n-type high breakdown voltage transistor. The impurities of the second impurity layer 32a are diffused to form the p-type offset impurity layer 32 in the p-type high breakdown voltage transistor. The temperature of heat processing is 1100-1200 degreeC, for example.

  (N) Next, as shown in FIG. 16, in the high breakdown voltage transistor formation region 100, the region other than the region where the first gate insulating layer of the n-type high breakdown voltage transistor and the first gate insulating layer of the p-type high breakdown voltage transistor are formed. A resist layer R6 is formed so as to cover it. Using the resist layer R6 as a mask, the exposed mask layer 16 is removed. Next, channel doping is performed in the high breakdown voltage transistor formation region 100 as necessary. Channel doping can be performed, for example, by the following method.

  First, a resist layer (not shown) is formed so as to cover other than the n-type high breakdown voltage transistor formation region 100N. An n-type impurity such as phosphorus is implanted using the resist layer as a mask. Thereafter, the resist layer is removed by ashing. Next, a resist layer (not shown) is formed so as to cover other than the p-type high breakdown voltage transistor formation region 100P. For example, p-type impurities such as boron are implanted using the resist layer as a mask. Thereafter, the resist layer is removed by ashing.

  (O) Next, as shown in FIG. 17, a resist layer R 7 having a predetermined pattern is formed on the mask layer 16. In the high breakdown voltage transistor formation region 100, the resist layer R7 is formed so as to have an opening above a region (see FIG. 2) formed by protruding the end portion of the first gate insulating layer downward.

  Next, the sacrificial oxide layer 13 is etched using the resist layer R7 as a mask. Next, using the resist layer R7 and the sacrificial oxide layer 13 as a mask, the semiconductor layer 10 is taper-etched to form a taper trench 18. As shown in FIG. 18, the tapered trench 18 is formed in a region adjacent to the offset trench insulating layer 50 so that the bottom surface of the tapered trench 18 has an inclination that decreases toward the offset trench insulating layer 50.

  The inclination of the bottom surface of the taper trench 18 is formed by utilizing the difference in the etching rate of each surface orientation in the semiconductor layer 10. For example, when the semiconductor layer 10 is silicon and the plane orientation is [113], the inclination angle θ2 of the bottom surface of the tapered trench 18 is 30 °. For example, the inclination angle θ2 is 10 to 30 °, and preferably 15 to 30 °. The horizontal length L2 of the bottom surface of the tapered trench 18 is, for example, 0.1 to 0.4 μm, and preferably 0.1 μm. Since the taper trench 18 has the inclination angle θ2 and the length L2, the inclination angle θ1 and the length L1 of the lower surfaces of the end portions of the gate insulating layers 60 and 62 of the high breakdown voltage transistors 100n and 100p (see FIG. 2). Can be set to a desired value.

  The taper etching of the semiconductor layer 10 is performed by dry etching or wet etching.

  Thereafter, the resist layer R7 is removed by ashing.

  (P) Next, as shown in FIG. 19, first gate insulating layers 60 and 62 are formed in the high breakdown voltage transistor formation region 100. The first gate insulating layers 60 and 62 can be formed by a selective thermal oxidation method. As described above, since the tapered trench 18 (see FIGS. 17 and 18) is formed before the first gate insulating layers 60 and 62 are formed, the offset trench insulating layer 50 in the first gate insulating layers 60 and 62 is formed. , 52 can be formed so that the lower surface of the end portion is inclined. The film thickness of the first gate insulating layers 60 and 62 is, for example, 50 to 200 nm. Next, the remaining mask layer 16 is removed.

  (Q) Next, as shown in FIG. 20, the p-type second well 24 and the n-type second well 26 are formed in the low-voltage drive transistor formation region 200. Specifically, the p-type second well 24 and the n-type second well 26 are formed by forming a mask layer (not shown) having a predetermined pattern using a general lithography technique, and having a predetermined conductivity type. This is done by introducing the impurities. Then, if necessary, channel doping can be performed.

  (R) Next, as shown in FIG. 21, a resist layer R8 is formed and exposed in the high breakdown voltage transistor formation region 100 so as to cover the region where the first gate insulating layers 60 and 62 are formed. The pad layer 12 is removed. The pad layer 12 can be etched by, for example, wet etching with hydrofluoric acid. Thereafter, the resist layer R8 is removed by ashing.

  (S) Next, as shown in FIG. 22, an insulating layer 68 is formed. The insulating layer 68 becomes a gate insulating layer of the n-type low voltage driving transistor and a gate insulating layer of the p-type low voltage driving transistor. The insulating layer 68 is formed by, for example, a thermal oxidation method. The film thickness of the insulating layer 68 is, for example, 1.6 to 15 nm.

  Next, a conductive layer 78 is formed on the entire surface of the high breakdown voltage transistor formation region 100 and the low voltage drive transistor formation region 200. As the conductive layer 78, for example, a polysilicon layer can be used. When polysilicon is used as the material of the conductive layer 78, impurities can be ion-implanted into the conductive layer 78 to reduce the resistance of the conductive layer 78.

  (T) Next, as shown in FIG. 23, gate electrodes 70, 72, 74, 76 of the respective transistors are formed. Specifically, first, a resist layer (not shown) having a predetermined pattern is formed. Next, by patterning the conductive layer 78 using the resist layer as a mask, gate electrodes 70, 72, 74, and 76 are formed.

  Next, an impurity layer 34a serving as an n-type extension region is formed in the n-type low voltage driving transistor formation region 200N. In the p-type low voltage driving transistor formation region 200P, an impurity layer 36a that becomes a p-type extension region is formed. The impurity layers 34a and 36a can be formed by forming a mask layer using a general lithography technique and injecting a predetermined impurity.

  (U) Next, as shown in FIG. 1, an insulating layer (not shown) is formed on the entire surface, and this insulating layer is anisotropically etched to form side surfaces of the gate electrodes 70, 72, 74, and 76. Sidewall insulating layers 80, 82, 84, 86 are formed. Further, the insulating layer 68 is etched to form the gate insulating layer 64 of the n-type low voltage driving transistor 200n and the gate insulating layer 66 of the p-type low voltage driving transistor 200p.

  Next, by introducing n-type impurities into predetermined regions of the semiconductor layer 10 in the n-type high breakdown voltage transistor forming region 100N and the n-type low voltage driving transistor forming region 200N, the outside of the sidewall insulating layers 80 and 84 is removed. N-type source / drain regions 90 and 94 are formed in the semiconductor layer 10. The n-type source / drain regions 90 and 94 can be formed by a known method.

  Next, p-type impurities are introduced into predetermined regions of the semiconductor layer 10 in the p-type high breakdown voltage transistor formation region 100P and the p-type low-voltage drive transistor formation region 200P, so that the outside of the sidewall insulating layers 82 and 86 is increased. The p-type source / drain regions 92 and 96 are formed in the semiconductor layer 10. The p-type source / drain regions 92 and 96 can be formed by a known method.

  The semiconductor device according to this embodiment can be manufactured through the above steps. This method for manufacturing a semiconductor device has the following characteristics.

  According to the manufacturing method of the semiconductor device according to the present embodiment, the thickness of the first gate insulating layers 60 and 62 is made adjacent to the offset trench insulating layers 50 and 52 only by adding the step of forming the tapered trench 18. In the region to be formed, it can be formed thicker than in the case where there is no step of forming the tapered trench 18. Therefore, the slight increase in the number of steps can solve the problem that the thickness of the first gate insulating layers 60 and 62 is partially reduced in the region adjacent to the offset trench insulating layers 50 and 52. The entire gate insulating layers 60 and 62 can have a desired uniform film thickness. As a result, a highly reliable semiconductor device can be provided.

  In addition, according to the method of manufacturing a semiconductor device according to the present embodiment, the element isolation regions 110, 120, and 210 and the offset trench insulating layers 50 and 52 can be formed only by adding the step of forming the tapered trench. The problem caused when the trench element isolation method is used can be solved. A problem that arises when the trench element isolation method is used is that the film thickness of the first gate insulating layers 60 and 62 is partially reduced in a region adjacent to the offset trench insulating layers 50 and 52.

  Therefore, according to the manufacturing method of the semiconductor device according to the present embodiment, the trench isolation method is used as a method of forming the isolation regions 110, 120, 210 and the offset trench insulating layers 50, 52 by a slight increase in the number of steps. It is possible to eliminate the problems that occur when using. That is, the element isolation regions 110, 120, 210 and the offset trench insulating layers 50, 52 are formed by the trench element isolation method, and a highly reliable semiconductor device can be provided. Further, the semiconductor device can be miniaturized as compared with the case where the LOCOS method, the semi-recessed LOCOS method, or the like is used.

  As mentioned above, although an example of embodiment of this invention was described, this invention is not limited to these, Various aspects can be taken within the range of the summary. For example, in the present embodiment, as shown in FIG. 17, an example in which a plurality of tapered trenches 18 are formed simultaneously has been described, but each tapered trench 18 can be formed in a separate process. For example, the taper trench whose slope of the bottom surface of the taper trench 18 is downwardly inclined and the taper trench whose downward slope is leftward can be formed in separate steps.

  Further, for example, in the present embodiment, the example in which all the depths of the trenches 44 are set to the same depth has been described. However, the depths of the respective trenches may be different within a range in which the function is performed. it can. For example, the trench 44 in the first element isolation region 110 can be formed deeper than the trench 44 and the offset trenches 40 and 42 in the second element isolation region 120.

Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment, and the semiconductor device formed by the manufacturing method. The figure which expands and shows the part shown with the code | symbol A of FIG. Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment. Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment. Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment. Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment. Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment. Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment. Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment. Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment. Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment. Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment. Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment. Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment. Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment. Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment. Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment. The figure which expands and shows the part shown with the code | symbol A of FIG. Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment. Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment. Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment. Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment. Sectional drawing which shows the manufacturing method of the semiconductor device concerning embodiment.

Explanation of symbols

10 semiconductor layer, 12 pad layer, 13 sacrificial oxide layer, 14 stopper layer, 16 mask layer, 18 tapered trench, 20 p-type first well, 20a first impurity layer, 22 n-type first well, 22a first impurity Layer, 24 p-type second well, 26 n-type second well, 30 n-type offset impurity layer, 30a second impurity layer, 32 p-type offset impurity layer, 32a second impurity layer, 34 n-type extension region, 34a impurity Layer, 36 p-type extension region, 36a impurity layer, 50, 52 offset trench insulating layer, 60, 62 first gate insulating layer, 64, 66 second gate insulating layer, 68 insulating layer, 70, 72, 74, 76 gate Electrode, 78 conductive layer, 80, 82, 84, 86 sidewall insulating layer , 90 n-type source / drain region, 92 p-type source / drain region, 94 n-type source / drain region, 96 p-type source / drain region, 100 high breakdown voltage transistor formation region, 100N n-type high breakdown voltage transistor formation region, 100P p-type high breakdown voltage transistor formation region, 100n n-type high breakdown voltage transistor, 100p p-type high breakdown voltage transistor, 110 first element isolation region, 120 second element isolation region, 200 low voltage drive transistor formation region, 200N n type low voltage drive Transistor formation region, 200P p-type low voltage drive transistor formation region, 200n n-type low voltage drive transistor, 200p p-type low voltage drive transistor, 210 third element isolation region

Claims (9)

A semiconductor layer;
A gate insulating layer formed on the semiconductor layer;
An offset trench insulating layer formed by a trench isolation method on the side of the gate insulating layer,
An offset impurity layer formed below the offset trench insulating layer;
A gate electrode formed on the gate insulating layer,
The semiconductor device, wherein an end portion of the gate insulating layer adjacent to the offset trench insulating layer is inclined so that a lower surface of the end portion is lowered toward the offset trench insulating layer. In claim 1,
The semiconductor device, wherein an inclination angle of the lower surface of the end portion in the gate insulating layer with respect to a horizontal direction is 10 to 30 °. In claim 1 or 2,
The semiconductor device in which the horizontal length of the lower surface of the end portion in the gate insulating layer is 0.1 to 0.4 μm. A semiconductor layer;
An element isolation region formed by a trench element isolation method for separating the high breakdown voltage transistor formation region and the low voltage drive transistor formation region in the semiconductor layer;
A first gate insulating layer formed in the high breakdown voltage transistor formation region;
A first gate electrode formed on the first gate insulating layer;
An offset trench insulating layer formed by a trench isolation method on a side of the first gate insulating layer;
An offset impurity layer formed below the offset trench insulating layer;
A second gate insulating layer formed in the low-voltage driving transistor formation region;
A gate electrode formed on the second gate insulating layer,
The semiconductor device, wherein an end portion of the first gate insulating layer adjacent to the offset trench insulating layer is inclined so that a lower surface of the end portion is lowered toward the offset trench insulating layer. In claim 4,
The semiconductor device, wherein an inclination angle of the lower surface of the end portion in the first gate insulating layer with respect to a horizontal direction is 10 to 30 °. In claim 4 or 5,
The length of the lower surface of the said edge part in the said 1st gate insulating layer in the horizontal direction is a semiconductor device which is 0.1-0.4 micrometer. Forming a high breakdown voltage transistor formation region and a low voltage drive transistor formation region in a semiconductor layer, and forming an offset trench insulating layer in the high breakdown voltage transistor formation region by a trench element isolation method;
Forming an offset impurity layer below the offset trench insulating layer;
Etching the semiconductor layer adjacent to the offset trench insulating layer to form a surface inclined with respect to the upper surface of the semiconductor layer;
Forming a gate insulating layer in the high breakdown voltage transistor formation region;
Forming a gate electrode on the gate insulating layer,
The method of manufacturing a semiconductor device, wherein the inclined surface is lowered toward the offset trench insulating layer. In claim 7,
The manufacturing method of a semiconductor device, wherein an inclination angle of the inclined surface with respect to a horizontal direction is 10 to 30 °. In claim 7 or 8,
The length of the inclined surface in the horizontal direction is 1 to 2 μm.

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