JP2007073950A - Semiconductor device and method of fabricating the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile storage device which eliminates an obstacle against finer elements and the complexity of a manufacturing process, adds data at a time other than the manufacturing process, and prevents forgery or the like to be committed by rewriting, and also to provide a semiconductor device including the storage device. <P>SOLUTION: The semiconductor device includes storage cells and switching elements which are arranged on a substrate having an insulating surface. The cell has a first electrode, a second electrode, and a layer containing an organic compound. The first and second electrodes and the layer are disposed on the same plane. The layer containing the organic compound is formed between the first electrode and the second electrode, current passes from the first electrode to the second electrode, and the first electrode is electrically connected to the switching element. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device capable of storing data.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

  The memory element generally has a structure in which two electrodes are arranged above and below a dielectric layer as two terminals of the memory element.

Patent Document 1 discloses a memory device that stores information by placing electrodes on top and bottom of a layer containing an organic compound as two terminals of an element and applying a voltage to short-circuit the initial state to 0 and the conduction state to 1. A driving method has been proposed.
JP 2002-26277 A

As a memory circuit provided in a semiconductor device, a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory Memory), a FeRAM (Ferroelectric Random Access Memory Memory), a mask ROM (Masked Memory Read Memory). EEPROM (Electrically Erasable and Programmable Read Only Memory), flash memory, and the like. Among these, DRAM and SRAM are volatile storage circuits, and data is erased when the power is turned off. Therefore, it is necessary to write data every time the power is turned on. FeRAM is a non-volatile memory circuit, but a manufacturing process increases because a capacitor element including a ferroelectric layer is used. Although the mask ROM has a simple structure, it is necessary to write data in the manufacturing process and cannot be additionally written. Although EPROM, EEPROM, and flash memory are non-volatile memory circuits, there is a problem in that the number of manufacturing steps increases because an element including two gate electrodes is used.

  In addition, a memory circuit such as a DRAM using an inorganic material as a dielectric stores two values depending on the presence or absence of electric charge stored in a capacitor.

On the other hand, a memory circuit using an organic compound as a dielectric forms a memory element by providing an organic compound between a pair of upper and lower electrodes. When an electrode is formed on a layer containing an organic compound, Depending on the temperature, there is an influence on the layer containing an organic compound, so the temperature is limited. Due to this temperature limitation, the electrode formation method is limited, and the desired electrode cannot be formed, which hinders miniaturization of the element. Forming an electrode on a layer containing an organic compound is a problem to be solved from the aspect of hindering element miniaturization.

In the case of an organic memory element using a pair of electrodes formed above and below a layer containing an organic compound as two terminals, the pair of electrodes are arranged above and below to form the pair of electrodes in a plurality of steps. There must be. Therefore, there has been a problem that the manufacturing process becomes complicated. The complexity of the manufacturing process is a problem to be solved from the viewpoint of manufacturing cost.

In view of the above problems, it is an object of the present invention to solve the hindrance to element miniaturization and the complexity of the manufacturing process. It is another object of the present invention to provide a nonvolatile memory device capable of additionally recording data other than at the time of manufacture and capable of preventing forgery or the like due to rewriting and a semiconductor device having the nonvolatile memory device. It is another object to provide a highly reliable and inexpensive nonvolatile memory device and semiconductor device.

In view of the above problems, the present invention provides a memory element in which a first conductive layer functioning as two terminals of a memory element and a second conductive layer are arranged over the same insulating layer.

Further, in the present invention, a voltage is applied between the two terminals of the element, and the pair of electrodes is made conductive by a change in conductivity of the layer containing the organic compound caused by a change in the layer containing the organic compound or a short circuit of the electrodes. . In addition, a voltage is applied to the layer containing the organic compound in parallel with the substrate surface to conduct the pair of electrodes. The element of the present invention can store binary values corresponding to an “initial state” and a “state after conductivity change”. It can be said that the element of the present invention is an element having a structure in which a potential difference is formed between the pair of electrodes and the current path is irreversibly changed from a high resistance state to a low resistance state.

An example of the structure 1 of the invention disclosed in this specification is illustrated in FIGS. 1A, 1B, and 1C, and includes a plurality of elements over a substrate having an insulating surface. A semiconductor device in which a plurality of switching elements are arranged in a matrix, and the elements include a pair of electrodes arranged in the same plane and a layer containing an organic compound in the same plane, Among them, a current flows in a direction parallel to the substrate surface from one electrode to the other electrode, the layer containing the organic compound is disposed between the pair of electrodes, and one electrode of the pair of electrodes is A semiconductor device electrically connected to the switching element.

A gate line (gate electrode) of the switching element corresponds to a word line. In addition, there are at least two electrodes electrically connected to the semiconductor layer of the switching element in order to connect to the source region and the drain region included in the semiconductor layer. The bit line intersecting with the word line is electrically connected to the semiconductor layer of the switching element. In this specification, a pair of electrodes arranged in the same plane is also referred to as a first electrode and a second electrode, and an electrode electrically connected to the semiconductor layer of the switching element is referred to as a first electrode. . The second electrode provided to face the first electrode corresponds to a common line (common electrode). For example, when the switching element is an n-channel thin film transistor, the bit line is connected to the drain region of the n-channel thin film transistor, and the first electrode is connected to the source region of the n-channel thin film transistor. In the case where the switching element is a p-channel thin film transistor, the bit line is connected to the source region of the p-channel thin film transistor, and the first electrode is connected to the drain region of the p-channel thin film transistor.

  In the above structure 1, the layer containing the organic compound may be in contact with at least a part of one side surface of the first electrode and a part of the side surface of the common line facing the side surface.

  In addition, the layer containing an organic compound may be configured to surround the periphery with a pair of insulating layers, the first electrode, and the second electrode. The structure 2 of another invention is a substrate having an insulating surface. A semiconductor device in which a plurality of elements and a plurality of switching elements are arranged in a matrix form, the element including a pair of electrodes arranged in the same plane, a layer containing an organic compound in the same plane, and a pair of insulating layers And a current flows in a direction parallel to the substrate surface from one electrode to the other of the pair of electrodes, and the layer containing the organic compound includes the pair of insulating layers and the pair of electrodes. The semiconductor device is surrounded by electrodes, and one electrode of the pair of electrodes is electrically connected to the switching element.

This pair of insulating layers is provided to control the formation position of the layer containing an organic compound, and is also called a partition. The pair of insulating layers is provided in a region between one element and a memory element adjacent to the element. In the configuration 2 of the invention, the layer containing the organic compound is sandwiched between the pair of electrodes in the direction of the current path that is parallel to the substrate surface from one electrode to the other electrode, and is perpendicular to the current path. Then, it is sandwiched between a pair of insulating layers.

  In the configuration 2, the pair of insulating layers are arranged so as to sandwich the current path on both sides of the current path.

  In the above configuration 1 or 2, the total width (Wa + Wc) of the pair of electrodes is wider than the width (Wx) of the layer containing an organic compound, as shown as an example in FIG. Is one of the features. Here, the total width of the pair of electrodes and the width of the layer including an organic compound refer to the width in a cross section including the pair of electrodes. In addition, the shortest current path in the cross section including the pair of electrodes corresponds to the distance (Wb) between the pair of electrodes. The width (Wx) of the layer containing at least the organic compound is equal to or larger than the distance (Wb) between the pair of electrodes.

Further, the layer containing an organic compound is not particularly limited as long as it is disposed between the common line and the first electrode, and may have various pattern shapes as viewed from above. For example, the top surface shape of the layer containing an organic compound may be rectangular, elliptical, circular, or belt-shaped. The amount of material used can be reduced by selectively forming a layer containing an organic compound instead of forming a layer containing an organic compound over the entire surface.

  Further, as shown in FIG. 2A and FIG. 2B as an example, the layer containing the organic compound may be formed in a belt-like pattern as viewed from above, and each other in the direction of the current path. A plurality of adjacent elements may be shared. In this case, the total width of the pair of electrodes is narrower than the width of the layer containing the organic compound, that is, the length of the strip pattern. Note that a droplet discharge method (typically, an ink jet method, a dispense method, or the like) may be used as a method for forming a belt-like pattern. In addition, since a layer containing an organic compound is also disposed between the adjacent common line and the bit line, the distance Wd between the adjacent common line and the bit line is equal to the distance between the first electrode and the common line ( Wb) is more preferable, specifically 2 μm or more. In addition, a pair of insulating layers is provided in order to control the formation position of the layer containing an organic compound.

  3A and 3B, the layer containing the organic compound may be formed so as to partially overlap the first electrode or the common line. The side surface of the first electrode and its upper end portion may be covered with the side surface of the common line facing the side surface of the first electrode and its upper end portion. The width Wx of the layer containing an organic compound in FIG. 3A is wider than the width Wx of the layer containing an organic compound in FIG.

  As shown in FIG. 4A and FIG. 4B as an example, the layer containing the organic compound may be formed in a band-like pattern as viewed from above without providing a partition. A plurality of elements provided adjacent to each other in the direction of the path may be shared.

5A and 5B, an insulating layer is formed over the connection electrode and the bit line, and the first electrode, the second electrode, and the organic compound are formed over the insulating layer. The structure which forms the layer to contain may be sufficient. Note that the connection electrode is electrically connected to the first electrode through a contact hole provided in the insulating layer. The area occupied by the element can be reduced by providing an insulating layer on the connection electrode and the bit line.

In the above configuration 1 or 2, the side surface of the bit line, the side surface of the first electrode, and the side surface of the common line facing the side surface have a tapered shape. It is one. In this specification, that the side surface of the electrode (or wiring) has a tapered shape means that the side wall surface of the electrode (or wiring) is inclined with respect to the substrate surface. However, in this specification, the taper shape excludes the shape in which the upper end portion of the electrode (or wiring) protrudes, that is, the overhang shape.

By adopting a tapered shape, the gap between the opposing lower ends of the pair of electrodes can be narrowed, and the electric field tends to concentrate. Therefore, the layer containing an organic compound placed in the current path with relatively low power has high resistance. The state can be changed irreversibly from the low resistance state. In this specification, the side surface of an electrode (or wiring) having a tapered shape means that the side wall surface of the electrode (or wiring) is inclined. However, in this specification, the taper shape excludes the shape in which the upper end portion of the electrode (or wiring) protrudes, that is, the overhang shape.

  In addition, a manufacturing process for realizing the configuration 1 is also one aspect of the present invention. The present invention includes forming a semiconductor layer over a substrate having an insulating surface, forming an insulating film covering the semiconductor layer, A method for manufacturing a semiconductor device, wherein a pair of electrodes, one of which is electrically connected to the semiconductor layer, is formed on the same surface of an insulating film, and a layer containing an organic compound is selectively formed between the pair of electrodes. .

  In the structure of the invention relating to the above manufacturing method, when the pair of electrodes is formed, one of the characteristics is that the side surface of the bit line, the side surface of the first electrode, and the side surface of the common line are tapered. By adopting the taper shape, the coverage of the film formed thereon can be improved. In addition, when the method for forming a layer containing an organic compound is a droplet discharge method, when a material droplet is discharged between a pair of electrodes (a first electrode and a common line), a tapered shape is obtained even if the discharge position is shifted. If it can discharge to a certain electrode side surface, a material droplet will move to the insulating surface between a pair of electrodes along a side surface, and the insulating surface exposed between a pair of electrodes can be covered.

  In addition, a manufacturing process for realizing the above configuration 2 is also one aspect of the present invention. In the present invention, a semiconductor layer is formed over a substrate having an insulating surface, an insulating film covering the semiconductor layer is formed, A pair of electrodes, one of which is electrically connected to the semiconductor layer, is formed on the same surface of the insulating film, a pair of insulating layers are formed on the insulating film, and the pair of electrodes, the pair of insulating layers, In the method for manufacturing a semiconductor device, a layer containing an organic compound is selectively formed so as to overlap with a region surrounded by four sides.

  In the structure of the invention related to the manufacturing method, when the pair of electrodes is formed, a side surface of the pair of electrodes sandwiching at least the layer containing the organic compound has a tapered shape on a side surface in contact with the layer containing the organic compound. One of them. In addition, when the pair of insulating layers is formed, one of the characteristics is that a side surface in contact with the layer containing the organic compound among the side surfaces of the pair of insulating layers sandwiching at least the layer containing the organic compound is tapered.

According to the present invention, effects such as miniaturization of elements and simplification of a manufacturing process can be achieved.

In addition, since the memory device and the semiconductor device of the present invention include a memory element having a simple structure in which a layer containing an organic compound is sandwiched between a pair of electrodes over the same insulating layer, an inexpensive memory device and semiconductor device are provided. be able to.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment, a structural example of a memory element included in a semiconductor device of the present invention will be described with reference to drawings. More specifically, a structure example of a memory circuit in which a plurality of memory elements are arranged in a matrix is shown below.

  FIG. 1A illustrates part of a cross-sectional structure of a memory cell array including a plurality of memory elements of the present invention. FIG. 1B illustrates a top structure, and a cross section of FIG. 1B cut along a chain line AB corresponds to FIG. FIG. 1C illustrates a cross-sectional structure, and a cross section taken along a chain line CD corresponds to FIG.

The second insulating layer 104, the third insulating layer 106, and the fourth insulating layer 107 are provided with openings (contact holes) that reach the semiconductor layer 103. A bit line 109, a first electrode 108, and a common electrode (second electrode) 112 are provided so as to cover the opening. In addition, the first electrode 108 and the common electrode 112 which are electrically connected to the semiconductor layer 103 through the opening are provided over the fourth insulating layer 107. In FIG. 1A, the bit line 109, the first electrode 108, and the common electrode 112 are provided in the same layer, that is, over the fourth insulating layer 107.

Here, an example in which an n-channel thin film transistor is used as a switching element is shown. The semiconductor layer 103, the gate line (word line) 105, the first electrode 108 also serving as a source electrode, and the bit line 109 also serving as a drain electrode form an n-channel thin film transistor. The n-channel thin film transistor is electrically connected to a memory element including the first electrode 108, the common electrode 112, and the layer 113 containing an organic compound.

  Note that in the case where a p-channel transistor is used instead of the n-channel thin film transistor, the bit line functions as a source electrode of the thin film transistor and the first electrode functions as a drain electrode of the thin film transistor.

The semiconductor layer 103 has at least a channel formation region, a source region, and a drain region. In order to reduce the off-state current value, an n-channel thin film transistor may have a lightly doped drain (LDD) structure. In this LDD structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source region or a drain region formed by adding an impurity element at a high concentration. It is called. The LDD structure has the effect of relaxing the electric field in the vicinity of the drain and preventing deterioration due to hot carrier injection. In order to prevent deterioration of the on-current value due to hot carriers, an n-channel thin film transistor may have a GOLD (Gate-drain Overlapped LDD) structure. The GOLD structure in which the LDD region is disposed so as to overlap the gate electrode with the gate insulating film interposed therebetween has an effect of relaxing the electric field in the vicinity of the drain and preventing deterioration due to hot carrier injection as compared with the LDD structure. By adopting such a GOLD structure, the electric field strength in the vicinity of the drain is relaxed to prevent hot carrier injection and to effectively prevent the deterioration phenomenon.

As the semiconductor layer 103, an amorphous semiconductor film, a semiconductor film including a crystal structure, a compound semiconductor film including an amorphous structure, or the like can be used as appropriate. Further, the active layer of the TFT is a semiconductor having an intermediate structure between an amorphous structure and a crystal structure (including single crystal and polycrystal) and having a third state that is stable in terms of free energy, and has a short distance. A semi-amorphous semiconductor film (also referred to as a microcrystalline semiconductor film or a microcrystal semiconductor film) including a crystalline region having order and lattice strain can be used. There is no limitation on the material of the semiconductor layer 103, but it is preferable that the semiconductor layer 103 be formed of silicon or a silicon germanium (SiGe) alloy. Alternatively, an organic compound such as pentacene can be used for the semiconductor layer 103.

  If the transistor can function as a switching element, the present invention can be applied regardless of the structure of the switching element. FIG. 1A shows an example in which a top-gate thin film transistor is provided over an insulating substrate; however, a bottom-gate (reverse staggered) TFT or a forward staggered TFT can be used. is there. Further, the TFT is not limited to a single-gate TFT, and may be a multi-gate TFT having a plurality of channel formation regions, for example, a double-gate TFT.

The semiconductor layer 103, the gate line (word line) 105, the first electrode 108 that also serves as the source or drain electrode, and the bit line 109 that also serves as the source or drain electrode form a transistor. The first electrode 108 also serving as a source electrode or a drain electrode forms a memory element with the common electrode 112 and the layer 113 containing an organic compound.

  In this manner, the first electrode 108, the common electrode 112, and the layer 113 containing an organic compound are formed over the fourth insulating layer 107, so that the first electrode 108, the common electrode 112, and the organic compound are contained. A memory element including the layer 113 can be freely arranged.

A word line (gate line) 105 is a control signal line for selecting one column from the memory cell array. A memory cell array has a plurality of memory cells arranged in a matrix. One memory cell is arranged between the transistor arranged at the intersection of the bit line 109 and the word line (gate line) 105 and the common electrode 112, and the voltage of the word line corresponding to the address at which reading and writing are performed. Can be written and read.

  The bit line 109 is a signal line for taking out data from the memory cell array. The memory cell connected to the word line (gate line) 105 to which the voltage is applied reads the data by outputting the data recorded in the storage element to the bit line 109.

  In addition, a layer 113 containing an organic compound is provided so as to be in contact between the first electrode 108 and the common electrode 112. The memory element of the present invention includes a layer 113 containing an organic compound, a first electrode 108 that sandwiches the layer 113 containing an organic compound in the horizontal direction on the substrate surface, and a common electrode 112. As a material used for the layer 113 containing an organic compound, a substance whose crystal state, conductivity, or shape is changed by an electrical action, typically an organic compound or a mixture of an organic compound and an inorganic compound is used.

Since the conductivity of the memory element having the above structure is changed by an electric action, binary values corresponding to the “initial state” and the “state after conductivity change” can be stored. Note that the electrical action means that a voltage is applied to the first electrode and the common electrode, and a current is passed through the layer containing an organic compound.

Here, the change in conductivity of the memory element before and after voltage application will be described.

When a voltage is applied between the side surface of the first electrode 108 and the side surface of the common electrode 112, the conductivity of the layer 113 containing an organic compound is changed, and the conductivity of the memory element is increased. In addition, when a voltage is applied between the side surface of the first electrode 108 and the side surface of the common electrode 112, the first electrode 109 and the common electrode 112 may be short-circuited. In addition, when a voltage is applied between the side surface of the first electrode 109 and the side surface of the common electrode 112, dielectric breakdown may occur in the layer 113 containing an organic compound, which may show conductivity. This is because the electric field tends to concentrate on the end portion of the electrode, so that dielectric breakdown is likely to occur in the layer containing the organic compound. In any of the above cases, the conductivity changes due to the electrical action, so that binary values corresponding to the “initial state” and “after the conductivity change” can be stored. Dielectric breakdown refers to a phenomenon in which when an applied voltage exceeds a certain limit, the insulator is electrically destroyed and loses its insulating properties, causing current to flow. Although the layer containing is not an insulator depending on the material, a similar phenomenon occurs when the layer is considered to be an insulator, so that dielectric breakdown occurs in the layer containing an organic compound.

As an organic compound that can be applied to the layer 113 containing an organic compound and whose conductivity is changed by an external electric action, an organic compound having a high hole-transport property or an organic compound having a high electron-transport property is used. Can do.

As an organic compound having a high hole-transport property, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD) or 4,4′-bis [N -(3-Methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD) or 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: TDATA) 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) and 4,4′-bis (N- (4- ( N, N-di-m-tolylamino) phenyl) -N-phenylamino) biphenyl (abbreviation: DNTPD) and other aromatic amine-based compounds (that is, having a benzene ring-nitrogen bond) and phthalocyanines (abbreviation: H ₂ Pc), copper phthalocyan Phthalocyanine compounds such as nin (abbreviation: CuPc) and vanadyl phthalocyanine (abbreviation: VOPc) can be used. The substances described here are mainly substances having a hole mobility of 10 ⁻⁶ cm ² / Vs or higher. Note that other than the above substances, any substance that has a property of transporting more holes than electrons may be used.

Note that in the case where a mixed layer of an organic compound and an inorganic compound is provided as a layer containing an organic compound, it is preferable to mix an organic compound having a high hole-transport property and an inorganic compound that easily receives electrons. By forming the layer containing the organic compound, many hole carriers are generated in the organic compound that has essentially no intrinsic carrier, and the organic compound exhibits extremely excellent hole injecting / transporting properties. As a result, the layer containing an organic compound can obtain excellent conductivity.

  As an inorganic compound that easily receives electrons, a metal oxide, metal nitride, or metal oxynitride of a transition metal in any of Groups 4 to 12 of the periodic table can be used. Specifically, titanium oxide (TiOx), zirconium oxide (ZrOx), vanadium oxide (VOx), molybdenum oxide (MoOx), tungsten oxide (WOx), tantalum oxide (TaOx), hafnium oxide (HfOx), niobium oxide (NbOx), cobalt oxide (Cox), rhenium oxide (ReOx), ruthenium oxide (RuOx), zinc oxide (ZnO), nickel oxide (NiOx), copper oxide ( CuOx) or the like can be used. Further, although oxides are given as specific examples here, these nitrides and oxynitrides may of course be used.

As an organic compound having a high electron-transport property, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [h ] -Quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), etc. Can be used. In addition, bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) A material such as a metal complex having an oxazole-based or thiazole-based ligand such as ₂ ) can also be used. In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- ( 4-biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2, 4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), and the like can be used. The substances mentioned here are mainly substances having an electron mobility of 10 ⁻⁶ cm ² / Vs or higher. Note that other than the above substances, any substance that has a property of transporting more electrons than holes may be used.

Note that in the case where a mixed layer of an organic compound and an inorganic compound is provided as a layer containing an organic compound, it is preferable to mix an organic compound having a high electron-transport property and an inorganic compound that easily gives electrons. By adopting such a structure, many electron carriers are generated in an organic compound that has essentially no intrinsic carrier, and the organic compound exhibits extremely excellent electron injecting / transporting properties. As a result, the layer containing an organic compound can obtain excellent conductivity.

  As the inorganic compound that easily gives electrons, alkali metal oxides, alkaline earth metal oxides, rare earth metal oxides, alkali metal nitrides, alkaline earth metal nitrides, and rare earth metal nitrides can be used. Specifically, lithium oxide (LiOx), strontium oxide (SrOx), barium oxide (BaOx), erbium oxide (ErOx), sodium oxide (NaOx), lithium nitride (LiNx), magnesium nitride (MgNx), calcium nitride (CaNx), yttrium nitride (YNx), lanthanum nitride (LaNx), or the like can be used.

  Further, as the inorganic compound, any inorganic compound that can easily receive electrons from an organic compound or an inorganic compound that easily gives electrons to an organic compound may be used. Aluminum oxide (AlOx), gallium oxide (GaOx), silicon oxide ( In addition to SiOx), germanium oxide (GeOx), indium tin oxide (ITO) and the like, various metal oxides, metal nitrides or metal oxynitrides can be used.

  In addition, when the layer 113 containing an organic compound is formed of a compound selected from metal oxides or metal nitrides and a compound having a high hole-transport property, the layer 113 has a larger steric hindrance (unlike a planar structure, a space It is also possible to add a compound having a structure having a general spread. As the compound having a large steric hindrance, 5,6,11,12-tetraphenyltetracene (abbreviation: rubrene) is preferable. However, besides this, hexaphenylbenzene, t-butylperylene, 9,10-di (phenyl) anthracene, coumarin 545T, and the like can also be used. In addition, dendrimers and the like are also effective.

Furthermore, 4- (dicyanomethylene) -2-methyl-6- [2] is formed between a layer formed of an organic compound having a high electron-transport property and a layer formed of an organic compound having a high hole-transport property. -(1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] -4H-pyran (abbreviation: DCJT), 4- (dicyanomethylene) -2-tert-butyl-6- [2- ( 1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] -4H-pyran, periflanthene, 2,5-dicyano-1,4-bis [2- (10-methoxy-1,1,7) , 7-tetramethyl-julolidine-9-yl) ethenyl] benzene, N, N'-dimethyl quinacridone (abbreviation: DMQd), coumarin 6, coumarin 545T, tris (8-quinolinolato) aluminum (abbreviation: _Alq 3) 9,9′-bianthryl, 9,10-diphenylanthracene (abbreviation: DPA), 9,10-di (2-naphthyl) anthracene (abbreviation: DNA), 2,5,8,11-tetra-t-butylperylene A light-emitting substance such as (abbreviation: TBP) may be provided.

The layer 113 containing an organic compound can be formed by an evaporation method, an electron beam evaporation method, a sputtering method, a CVD method, or the like. Moreover, the mixed layer containing an organic compound and an inorganic compound can be formed by simultaneously forming the respective materials. The co-evaporation method using resistance heating evaporation, the co-evaporation method using electron beam evaporation, and resistance heating. It can be formed by a combination of the same or different methods such as co-evaporation by vapor deposition and electron beam vapor deposition, film formation by resistance heating vapor deposition and sputtering, and film formation by electron beam vapor deposition and sputtering.

  In addition, as a method for forming the layer 113 containing another organic compound, a spin coating method, a sol-gel method, a printing method, a droplet discharge method (an inkjet method or a dispensing method), or the like may be used. May be combined.

  The layer 113 containing an organic compound has a thickness at which the conductivity of the memory element is changed by an external electric action. A typical film thickness of the layer 113 containing an organic compound is 5 nm to 100 nm, preferably 10 nm to 60 nm.

As shown in FIG. 1A, the layer 113 containing an organic compound is in contact with one side surface (tapered side surface) of the common electrode 112. Further, the side surface of the first electrode 108 facing the side surface of the common electrode 112 in contact with the layer 113 containing an organic compound is also in contact with the layer 113 containing an organic compound.

In addition, as illustrated in FIGS. 1B and 1C, a fifth insulating layer 114 is provided with a layer 113 containing an organic compound interposed therebetween. The fifth insulating layer 114 (also referred to as a partition wall 114) is formed with a thickness of 0.1 μm to 0.5 μm perpendicular to the substrate surface. As shown in FIG. 1B, the layer 113 containing an organic compound is surrounded by the first electrode 108, the common electrode 112, and the fifth insulating layer 114, so that the layer containing an organic compound is included. The organic material used for 113 may be a material with high fluidity.

In FIG. 1B, the top surface shape of the layer 113 containing an organic compound is rectangular, but is not particularly limited, and may be a square, an ellipse, or a circle. The top surface shape of the layer 113 containing an organic compound is easily influenced by the film forming method. For example, when a resistance heating vapor deposition method or an electron beam vapor deposition method is used, a rectangular organic compound is formed by using a vapor deposition mask having a rectangular opening. A layer 113 containing can be obtained. Thus, when the layer 113 containing an organic compound is formed separately for each memory cell, the influence of the electric field in the lateral direction can be reduced between adjacent memory cells.

In order to reduce the number of processes, the bit line 109, the first electrode 108, and the common electrode 112 are preferably formed using the same process and the same material. In addition, in order to precisely control the distance between the bit line 109, the first electrode 108, and the common electrode 112, the bit line 109, the first electrode 108, and the common electrode 112 are patterned using the same photomask. Is preferred.

The distance Wb between the first electrode 108 and the common electrode 112 provided on the same insulating layer is parallel to the substrate surface, and is 0.1 μm to 0.05 μm, preferably 0.01 μm or less. In addition, the shortest distance in the current path 120 in the cross section including the first electrode 108 and the common electrode 112 forming a pair of electrodes corresponds to the distance (Wb) between the pair of electrodes. Writing at a low voltage can be performed by narrowing the distance between the first electrode 108 and the common electrode 112. That is, writing can be performed with low power consumption.

The total width (Wa + Wc) of the first electrode 108 and the common electrode 112 is preferably wider than the width (Wx) of the layer 113 containing an organic compound.

The word line (gate line) 105, the bit line 109, the first electrode 108, and the common electrode 112 are formed by vapor deposition, sputtering, CVD, printing, electroplating, electroless plating, droplet discharge, and the like. Use to form. The present invention is particularly effective when a material having a low heat-resistant temperature is used as the material used for the layer 113 containing an organic compound. In the present invention, the word line (gate line) 105, the bit line 109, the first electrode 108, and the common electrode 112 are formed before the layer 113 containing an organic compound. The film temperature is not limited, and various formation methods can be used.

As a material for the word line (gate line) 105, the bit line 109, the first electrode 108, and the common electrode 112, an element or a compound having high conductivity is used. Typically, gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), A kind of element selected from copper (Cu), palladium (Pd), carbon (C), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta) or the like, or an alloy containing a plurality of such elements. Can be used. Examples of the alloy containing a plurality of the above elements include an alloy containing Al and Ti, Al, an alloy containing Ti and C, an alloy containing Al and Ni, an alloy containing Al and C, and Al and Ni. An alloy containing C or an alloy containing Al and Mo can be used.

Further, different materials may be used for the word line (gate line) 105, the bit line 109, the first electrode 108, and the common electrode 112. Further, the formation method of the word line (gate line) 105, the bit line 109, the first electrode 108, and the common electrode 112 may be different from each other.

  In addition, the bit line 109 having the tapered side surface, the first electrode 108, and the common electrode 112 can be formed by appropriately adjusting the etching conditions during patterning. When formed in the same process, the bit line 109, the first electrode 108, and the common electrode 112 have the same tapered side surface. The taper-shaped side surface means that the cross section of the side surface of the electrode or bit line is inclined with respect to the substrate surface. Preferably, the side surfaces of the bit line 109, the first electrode 108, and the common electrode 112 with respect to the substrate surface have an inclination angle (taper angle) of 10 degrees to less than 85 degrees, preferably 60 degrees to 80 degrees. .

The memory element illustrated in FIGS. 1A, 1B, and 1C has a structure in which a voltage is applied to the layer 113 containing an organic compound in a direction parallel to the substrate surface. By reducing the distance between the electrode 108 and the common electrode 112, the area occupied by the memory element can be reduced.

Here, an example of a method for manufacturing the memory element illustrated in FIGS. 1A, 1B, and 1C is described below.

  First, the first insulating layer 102 is formed over the substrate 101 having an insulating surface.

  Next, a semiconductor layer is formed over the first insulating layer 102. The semiconductor layer 103 is formed by selectively etching the semiconductor layer using a photolithography method or the like. Next, the second insulating layer 104 is formed over the semiconductor layer 103 and the first insulating layer 102. Next, a conductive layer is formed over the second insulating layer. The conductive layer is selectively etched using a photolithography method or the like to form a word line (gate line) 105. Next, a third insulating layer 106 is formed over the word line (gate line) 105 and the second insulating layer. Next, a fourth insulating layer 107 is formed over the third insulating layer 106. Next, the second insulating layer, the third insulating layer, and the fourth insulating layer are selectively etched using a photolithography method or the like, so that an opening reaching the semiconductor layer 103 is formed. Next, a conductive layer is formed over the opening reaching the fourth insulating layer 107 and the semiconductor layer 103. The conductive layer is selectively etched using a photolithography method or the like to form the bit line 109, the first electrode 108, and the common electrode 112. Next, an insulating layer is formed over the bit line 109, the first electrode 108, and the common electrode 112, and etching is performed using a photolithography method or the like, so that the fifth insulating layer 114 is formed. Note that if a printing method or a droplet discharge method is used, the second insulating layer 104, the third insulating layer 106, the fourth insulating layer 107, and the fifth insulating layer 114 are formed without performing an etching step. It is possible.

  Next, a material liquid containing an organic substance is dropped into a region surrounded by the first electrode 108, the common electrode 112, and the fifth insulating layer 114 by a droplet discharge method. It is dropped so as to fill at least the gap between the first electrode 108 and the common electrode 112. The material liquid containing the dropped organic substance is fixed because it is surrounded on all sides by the first electrode 108, the common electrode 112, and the fifth insulating layer 114. Then, baking is performed to form a layer 113 containing an organic compound.

Note that although an example in which the position where the layer 113 containing an organic compound is formed is a position where the layer 113 does not overlap with the semiconductor layer 103 is shown, the position of the layer 113 containing an organic compound is not limited to the semiconductor layer 103 or the gate line. The area occupied by the memory element may be reduced as a position overlapping with the other.

  In the memory element illustrated in FIGS. 1A and 1B thus obtained, the bit electrode, the first electrode 108 sandwiching the layer 113 containing an organic compound, and the common electrode 112 can be formed at the same time. The process can be shortened.

(Embodiment 2)
Here, FIGS. 2A and 2B illustrate examples of memory elements that are partly different from those in FIGS. 1A, 1B, and 1C. 2A is a cross-sectional view of two memory elements, FIG. 2B is a top view of the two memory elements, and FIG. 2 is a diagram cut along a chain line EF in FIG. Corresponds to (A).

2A, as in FIG. 1A, a first insulating layer 202 is provided over a substrate 201 having an insulating surface, and a semiconductor layer 203 is provided over the first insulating layer 202. Yes. A second insulating layer 204 is provided over the first insulating layer 202 and the semiconductor layer 203, and a word line (gate line) 205 is provided over the second insulating layer 204. A third insulating layer 206 is provided over the word line (gate line) 205, and a fourth insulating layer 207 is provided over the third insulating layer 206. A bit line 209, a first electrode 208, and a common electrode 212 are provided over the fourth insulating layer 207. The bit line 209, the first electrode 208, and the common electrode 212 are formed of the same material. The second insulating layer 204, the third insulating layer 206, and the fourth insulating layer 207 are provided with a pair of left and right openings (contact holes) reaching the semiconductor layer 203. A bit line 209 and a first electrode 208 are provided so as to cover the opening. A bit line 209, a first electrode 208, and a common electrode 212 are provided in the same layer, that is, over the fourth insulating layer 207.

The semiconductor layer 203, the gate line (word line) 205, the first electrode 208, and the bit line 209 form a transistor.

  In the memory element illustrated in FIG. 2A, the layer 213 containing an organic compound is in contact with both side surfaces of the bit line 209, both side surfaces of the first electrode 208, and both side surfaces of the common electrode 212.

Further, the shortest distance of the current path 220 in the cross section including the first electrode 208 and the common electrode 212 forming a pair of electrodes corresponds to the distance (Wb) between the pair of electrodes.

  As shown in FIG. 2B, the layer 213 containing an organic compound is formed in a band shape (also referred to as a line shape). In addition, an insulating layer (partition wall) may be formed in order to fix the layer 213 containing an organic compound. In that case, a fifth insulating layer in a strip shape (also called a line shape) parallel to the layer 213 containing an organic compound is used. 214 is also formed. The fifth insulating layer 214 is formed so as to sandwich the layer 213 containing an organic compound.

  In FIG. 2B, the width of the layer 213 containing an organic compound is not particularly limited, and the width of the layer 213 containing an organic compound may be wider than the width of the fifth insulating layer 214.

A layer 213 containing an organic compound shown in FIG. 2B has a structure different from that of the top surface of the layer 113 containing an organic compound in FIG. Since the memory element illustrated in FIGS. 2A and 2B has a structure in which the width of the layer 213 containing an organic compound can be widened, the allowable range of misalignment when forming the layer 213 containing an organic compound is widened. can do.

In addition, since the layer 213 containing an organic compound is also disposed between the common electrode 212 and the bit line 209, the distance (Wd) between the adjacent common electrode 212 and the bit line 209 is equal to that of the first electrode. It is preferably larger than the distance (Wb) between the electrodes, specifically 2 μm or more. If the spacing distance (Wd) is the same as or narrower than the spacing distance (Wb), the adjacent common electrode 212 and the bit line 209 may be short-circuited, and writing or the like may be performed on the memory element. Therefore, it is possible to prevent malfunctions by setting the distance (Wd) wider than the distance (Wb).

  2A, a protective layer is provided so as to cover the fourth insulating layer 207, the bit line 209, the first electrode 208, the common electrode 212, and the layer 213 containing an organic compound. Also good.

  Further, this embodiment mode can be freely combined with Embodiment Mode 1.

(Embodiment 3)
Here, FIGS. 3A and 3B illustrate examples of memory elements that are partly different from those in FIGS. 1A, 1B, and 1C. 3A is a cross-sectional view of two memory elements, FIG. 3B is a top view of the two memory elements, and FIG. 3 is a diagram cut along a chain line GH in FIG. Corresponds to (A).

3A, similarly to FIG. 1A, a first insulating layer 302 is provided over a substrate 301 having an insulating surface, and a semiconductor layer 303 is provided over the first insulating layer 302. Yes. A second insulating layer 304 is provided over the first insulating layer 302 and the semiconductor layer 303, and a word line (gate line) 305 is provided over the second insulating layer 304. A third insulating layer 306 is provided over the word line (gate line) 305, and a fourth insulating layer 307 is provided over the third insulating layer 306. A bit line 309, a first electrode 308, and a common electrode 312 are provided over the fourth insulating layer 307. The bit line 309, the first electrode 308, and the common electrode 312 are formed of the same material. The second insulating layer 304, the third insulating layer 306, and the fourth insulating layer 307 are provided with a total of six pairs of left and right openings (contact holes) reaching the semiconductor layer 303. A bit line 309 and a first electrode 308 are provided so as to cover this opening. A bit line 309, a first electrode 308, and a common electrode 312 are provided in the same layer, that is, over the fourth insulating layer 307. As shown in FIG. 3B, a pair of fifth insulating layers (partition walls) 314 is also provided over the fourth insulating layer 307 so that the layer 313 containing an organic compound is interposed therebetween.

The semiconductor layer 303, the gate line (word line) 305, the first electrode 308, and the bit line 309 form a transistor.

In the memory element illustrated in FIGS. 3A and 3B, the shape of the layer 313 containing an organic compound is different from the cross-sectional shape and the top shape of the layer 113 containing an organic compound in FIG. FIG. 1A illustrates an example in which the layer 113 containing an organic compound is in contact with only the side surfaces of the first electrode 108 and the common electrode 112, but in FIG. 3A, the layer 313 containing an organic compound is The first electrode 308 and the side surface of the common electrode 312 are in contact with part of the upper surface (upper end portion). The top surface shape of the layer 313 containing an organic compound is a rectangle whose length of at least one side is Wx.

  In the memory element illustrated in FIG. 3A, a protective layer may be provided so as to cover the bit line 309, the first electrode 308, the common electrode 312, and the layer 313 containing an organic compound. In the memory element illustrated in FIGS. 3A and 3B, the gap between the pair of electrodes can be reliably filled with a layer containing an organic compound. Therefore, any memory element can have a uniform resistance, and the resistance between a pair of electrodes can be prevented from varying from one memory element to another. In addition, when the layer 313 containing an organic compound is formed by etching using a photolithography method or the like, it is easier to etch than the structure shown in FIGS.

  Further, this embodiment mode can be freely combined with Embodiment Mode 1 or Embodiment Mode 2.

(Embodiment 4)
Here, FIGS. 4A and 4B illustrate examples of memory elements that are partly different from those in FIGS. 1A, 1B, and 1C. 4A is a cross-sectional view of two memory elements, FIG. 4B is a top view of the two memory elements, and FIG. 4 is a diagram cut along a chain line JK in FIG. Corresponds to (A).

4A, as in FIG. 1A, a first insulating layer 402 is provided over a substrate 401 having an insulating surface, and a semiconductor layer 403 is provided over the first insulating layer 402. Yes. A second insulating layer 404 is provided over the first insulating layer 402 and the semiconductor layer 403, and a word line (gate line) 405 is provided over the second insulating layer 404. A third insulating layer 406 is provided over the word line (gate line) 405, and a fourth insulating layer 407 is provided over the third insulating layer 406. A bit line 409, a first electrode 408, and a common electrode 412 are provided over the fourth insulating layer 407. The bit line 409, the first electrode 408, and the common electrode 412 are formed of the same material. The second insulating layer 404, the third insulating layer 406, and the fourth insulating layer 407 are provided with a pair of left and right openings (contact holes) that reach the semiconductor layer 403. A bit line 409 and a first electrode 408 are provided so as to cover the opening. A bit line 409, a first electrode 408, and a common electrode 412 are provided in the same layer, that is, over the fourth insulating layer 407.

The semiconductor layer 403, the gate line (word line) 405, the first electrode 408, and the bit line 409 form a transistor.

As a material for the layer 413 containing an organic compound, it is desirable to use a material that is quickly cured. By using a material that cures quickly, the fifth insulating layer 114 as illustrated in FIG. 1B is not necessarily provided. In addition, when the layer 413 containing an organic compound is selectively formed using an evaporation mask by an evaporation method, the fifth insulating layer 114 as illustrated in FIG. 1B is not necessarily provided.

  In the memory element illustrated in FIG. 4A, the layer 413 containing an organic compound is in contact with both side surfaces of the bit line 409, both side surfaces of the first electrode 408, and both side surfaces of the common electrode 412.

  As shown in FIG. 4B, the layer 413 containing an organic compound is formed in a strip shape (also called a line shape). Alternatively, a pair of fifth insulating layers 114 as illustrated in FIG. 1B may be formed, in which case the fifth insulating layer is formed in a strip shape (also referred to as a line shape) parallel to the layer 413 containing an organic compound. A layer is also formed.

In the memory element illustrated in FIG. 4B, the top surface shape of the layer 413 including an organic compound is different from the top surface shape of the layer 113 including an organic compound in FIG. Since the memory element illustrated in FIGS. 4A and 4B has a structure in which the width of the layer 413 containing an organic compound can be widened, the allowable range of misalignment when forming the layer 413 containing an organic compound is widened. can do.

  In the memory element illustrated in FIG. 4A, a protective layer is provided so as to cover the fourth insulating layer 407, the bit line 409, the first electrode 408, the common electrode 412, and the layer 413 containing an organic compound. Also good.

  Further, this embodiment mode can be freely combined with Embodiment Mode 1, Embodiment Mode 2, or Embodiment Mode 3.

(Embodiment 5)
Here, FIGS. 5A and 5B illustrate examples of memory elements that are partly different from those in FIGS. 1A, 1B, and 1C. 5A is a cross-sectional view of three memory elements, FIG. 5B is a top view of the three memory elements, and FIG. 5 is a diagram cut along a chain line LM in FIG. Corresponds to (A).

5A, as in FIG. 1A, a first insulating layer 502 is provided over a substrate 501 having an insulating surface, and a semiconductor layer 503 is provided over the first insulating layer 502. Yes.

A second insulating layer 504 is provided over the first insulating layer 502 and the semiconductor layer 503, and a word line (gate line) 505 is provided over the second insulating layer 504. A third insulating layer 506 is provided over the word line (gate line) 505, and a fourth insulating layer 507 is provided over the third insulating layer 506. A bit line 509 and a connection electrode 508 are provided over the fourth insulating layer 507.

The bit line 509 and the connection electrode 508 are formed of the same material. The second insulating layer 504, the third insulating layer 506, and the fourth insulating layer 507 are provided with a pair of left and right openings (contact holes) reaching the semiconductor layer 503. A bit line 509 and a connection electrode 508 are provided so as to cover the opening. A fifth insulating layer 510 is provided over the fourth insulating layer 507, the bit line 509, and the connection electrode 508.

A first electrode 511 and a common electrode (second electrode) 512 are provided over the fifth insulating layer 510. The first electrode 511 and the common electrode 512 are formed of the same material. The fifth insulating layer 510 is provided with an opening (contact hole) reaching the connection electrode 508. A first electrode 511 is provided so as to cover the opening. That is, the first electrode 511 and the common electrode 512 are provided over the same insulating layer.

The semiconductor layer 503, the gate line (word line) 505, the connection electrode 508, and the bit line 509 form a transistor.

In addition, as illustrated in FIG. 5B, a sixth insulating layer (partition wall) 514 is provided with a layer 513 containing an organic compound interposed therebetween. The sixth insulating layer 514 is formed to have a thickness of 0.1 μm to 0.5 μm in a direction perpendicular to the substrate surface. As shown in FIG. 5B, the organic material used for the layer 513 containing an organic compound is such that the layer 513 containing an organic compound covers all sides of the first electrode 511, the common electrode 512, and the sixth insulating layer 514. Since it is surrounded, a material with high fluidity may be used.

The memory element of this embodiment can be provided so as to overlap with the transistor by providing the fifth insulating layer 510, so that the element can be integrated. The distance between adjacent memory elements can be shortened, and further miniaturization can be expected.

  In the memory element illustrated in FIG. 5A, a protective layer may be provided so as to cover the fifth insulating layer 510, the first electrode 511, the common electrode 512, and the layer 513 containing an organic compound.

  In addition, this embodiment mode can be freely combined with Embodiment Mode 1, Embodiment Mode 2, Embodiment Mode 3, or Embodiment Mode 4.

(Embodiment 6)
Here, FIGS. 6A and 6B illustrate examples of memory elements that are partly different from those in FIGS. 1A, 1B, and 1C. 6A is a cross-sectional view of the memory element, and FIG. 6B is a top view corresponding to FIG. 6A.

6A, as in FIG. 1A, a first insulating layer 1302 is provided over a substrate 1301 having an insulating surface, and a semiconductor layer 1303 is provided over the first insulating layer 1302. Yes. A second insulating layer 1304 is provided over the first insulating layer 1302 and the semiconductor layer 1303, and a word line (gate line) 1305 is provided over the second insulating layer 1304. A third insulating layer 1306 is provided over the word line (gate line) 1305. The second insulating layer 1304 and the third insulating layer 1306 are provided with a pair of left and right openings (contact holes) reaching the semiconductor layer 1303. A bit line 1309 and a connection electrode 1308 are provided on the third insulating layer 1306 so as to cover the opening. The bit line 1309 and the connection electrode 1308 are formed of the same material. A fourth insulating layer 1307 is provided over the third insulating layer 1306, the bit line 1309, and the connection electrode 1308. The fourth insulating layer 1307 is provided with an opening (contact hole) reaching the connection electrode. A first electrode 1311 and a common electrode (second electrode) 1312 are provided over the fourth insulating layer 1307 so as to cover the opening.

The semiconductor layer 1303, the gate line (word line) 1305, the connection electrode 1308, and the bit line 1309 form a transistor 1315.

In this embodiment, the memory element can be overlapped with the transistor 1315 with the fourth insulating layer 1307 provided therebetween. Thus, the layer 1313 containing an organic compound can be formed over the transistor 1315. Therefore, the distance between adjacent memory elements can be shortened, and further miniaturization can be expected.

In FIG. 6A, a layer 1313 containing an organic compound is in contact with side surfaces of the first electrode 1311 and the common electrode 1312.

In addition, as illustrated in FIG. 6B, a pair of fifth insulating layers (partition walls) 1314 is provided with a layer 1313 containing an organic compound interposed therebetween. The pair of fifth insulating layers 1314 is formed to have a thickness of 0.1 μm to 0.5 μm in a direction perpendicular to the substrate surface. As shown in FIG. 6B, the organic material used for the layer 1313 containing an organic compound is such that the layer 1313 containing an organic compound forms a first electrode 1311, a common electrode 1312, and a pair of fifth insulating layers 1314. Since it is surrounded on all sides, a material with high fluidity may be used.

  6A, a protective layer may be provided so as to cover the first electrode 1311, the common electrode 1312, and the layer 1313 containing an organic compound.

  This embodiment mode can be freely combined with Embodiment Mode 1, Embodiment Mode 2, Embodiment Mode 3, Embodiment Mode 4, or Embodiment Mode 5.

(Embodiment 7)
In this embodiment mode, a semiconductor device of the present invention is described with reference to equivalent circuits shown in FIGS. 7A and 7B.

One structural example of the memory device described in this embodiment includes a column decoder 801, a row decoder 802, a reading circuit 804, a writing circuit 805, a selector 803, and a memory cell array 822. The memory cell array 822 includes bit lines Bm (1 ≦ m ≦ x), word lines Wn (1 ≦ n ≦ y), and x × y memory cells 821 at the intersections of the bit lines and the word lines.

  The memory cell 821 includes a first wiring configuring a bit line Bx (1 ≦ x ≦ m), a second wiring configuring a word line Wy (1 ≦ y ≦ n), a transistor 840, and a memory element 841. And have. As in Embodiments 1 to 6, the memory element 841 has a structure in which a layer containing an organic compound is sandwiched between a pair of conductive layers arranged side by side. Note that the structure of the memory device 816 shown here is merely an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included, and a writing circuit may be provided in the bit line driver circuit.

The column decoder 801 receives an address signal designating a row of the memory cell array, and gives a signal to the selector 803 of the designated row. The selector 803 receives a signal from the column decoder 801 and selects a bit line in a specified row. The row decoder 802 receives an address signal designating a column of the memory cell array and selects a word line in the designated column. Through the above operation, one memory cell 821 corresponding to the address signal is selected. A reading circuit 804 reads, amplifies, and outputs data included in the memory element of the selected memory cell. The writing circuit 805 generates a voltage necessary for writing, and writes data by applying a voltage to the memory element of the selected memory cell.

FIG. 7B illustrates a structure of the writing circuit 805 included in the memory device of the present invention. The write circuit 805 includes a voltage generation circuit 811, a timing control circuit 812, switches SW0 and SW1, and an output terminal Pw. The voltage generation circuit 811 is composed of a booster circuit or the like, generates a voltage V1 necessary for writing, and outputs it from the output Pa. The timing control circuit 812 generates signals S0 and S1 for controlling the switches SW0 and SW1, respectively, from a write control signal (described as WE), a data signal (described as DATA), a clock signal (described as CLK), and the like. , Output from outputs P0 and P1, respectively. The switch SW0 is connected to the ground, the switch SW1 is connected to the output Pa of the voltage generation circuit 811, and the output voltage Vwrite from the output Pw of the writing circuit can be switched depending on which connection state the switch SW1 is in.

Next, the writing operation when the initial state in which the conductivity of the memory element is not changed is “0” and the short-circuit state in which the conductivity of the memory element is changed is “1” will be described. First, when the input signal WE becomes High level, the column decoder 801 that receives the address signal designating the row gives a signal to the selector 803 of the designated row, and the selector 803 electrically connects the bit line of the designated row and the output Pw of the write circuit. Connect. Undesignated bit lines are not connected (denoted as floating). The output voltage Vwrite of the writing circuit is V1, and the voltage V1 is applied to the bit line of the designated row. Similarly, the row decoder 802 that has received an address signal designating a column applies a voltage V2 to the word line of the designated column, and applies 0 V to an undesignated word line. Through the above operation, one storage element 841 corresponding to the address signal is selected. At this time, 0 V is applied to the second electrode of the memory element 841.

At the same time, by receiving the high level data signal DATA, the voltage generation circuit 811 can generate the voltage V1 and output it from the output Pa. The timing control circuit 812 can generate signals S0 = Low and S1 = High for controlling the switches SW0 and SW1 from the input signals WE, DATA, CLK, the power supply potential (VDD), and the like, and can output them from the outputs P0 and P1. . With the signals S0 and S1, the switch SW0 is turned off and the switch SW1 is turned on, and the writing circuit 805 can output the voltage V1 from the output Pw as the output voltage Vwrite.

In the selected memory element, the voltage V2 is applied to the word line, the voltage V1 is applied to the bit line, and 0 V is applied to the second electrode by the above operation. Then, the impurity region of the thin film transistor is turned on, and the voltage V1 of the bit line is applied to the first electrode of the memory element. As a result, the conductivity of the memory element changes, and a short circuit state is established, and “1” is written.

When the input signal WE is at a low level (a low voltage at which writing is not permitted), all the word lines are set to 0 V, and all the bit lines and the second electrodes of the storage elements are in a floating state. At this time, the timing control circuit 812 generates Low as the signals S0 and S1, respectively, and outputs them from the outputs P0 and P1, and the output Pw enters a floating state. With the above operation, the writing of “1” is completed.

Next, writing of “0” will be described. Writing “0” is writing that does not change the conductivity of the memory element, and this is realized by applying no voltage to the memory element, that is, maintaining the initial state. First, when the input signal WE is at a high level (a high voltage enabling writing) as in the case of writing “1”, the column decoder 801 that has received an address signal designating a row gives a signal to the selector of the designated row, and the selector 803 Connects the bit line of the designated row to the output Pw of the write circuit. At this time, the unspecified bit line is in a floating state. Similarly, the row decoder 802 that has received an address signal designating a column applies a voltage V2 to the word line of the designated column, and applies 0 V to an undesignated word line. Through the above operation, one memory element 807 corresponding to the address signal is selected. At this time, 0 V is applied to the second electrode of the memory element 841.

At the same time, upon receiving the low level input signal DATA, the timing control circuit 812 generates the control signals S0 = High and S1 = Low levels, respectively, and outputs the control signals from the outputs P0 and P1, respectively. The switch SW0 is turned on and SW1 is turned off by the control signal, and 0 V is output from the output Pw as the output voltage Vwrite.

In the selected memory element, V2 is applied to the word line by the above operation, and 0 V is applied to the bit line and the common electrode (second electrode). Then, no voltage is applied to the memory element, and the conductivity does not change, so the initial state “0” is maintained.

When the input signal WE becomes low level, all the word lines are set to 0 V, and all the bit lines and the second electrodes are in a floating state. At the same time, the timing control circuit 812 generates Low for the signals S0 and S1, and outputs them from the outputs P0 and P1, respectively, and the output Pwrite is in a floating state. With the above operation, writing of “0” is completed.

In this manner, writing “1” or “0” and writing can be completed.

In addition, the memory cell array 822 includes a plurality of transistors 840 functioning as switching elements over a substrate having an insulating surface and a memory element 841 connected to the transistor 840.

As shown in FIGS. 7A and 7B, the memory cell 821 includes a transistor 840 and a memory element 841. In the accompanying drawings of this specification, the memory element 821 is represented by a rectangle. In the transistor 840, a word line is connected to the gate electrode, a bit line is connected to one high concentration impurity region of the transistor, and a first electrode of the memory element 841 is connected to the other high concentration impurity region of the transistor. . The second electrode of the memory element is electrically connected to the second electrode of all the memory elements in the memory cell array, and a constant voltage is applied during operation of the memory device, that is, during writing and reading. Therefore, in this specification, the second electrode may be referred to as a common electrode.

  This embodiment mode can be freely combined with Embodiment Mode 1, Embodiment Mode 2, Embodiment Mode 3, Embodiment Mode 4, Embodiment Mode 5, or Embodiment Mode 6.

(Embodiment 8)
The structure of the semiconductor device of this embodiment will be described with reference to FIG. As shown in FIG. 8, the semiconductor device 1520 of the present invention has a function of communicating data without contact, and controls to control a power supply circuit 1511, a clock generation circuit 1512, a data demodulation / modulation circuit 1513, and other circuits. A circuit 1514, an interface circuit 1515, a memory circuit 1516, a data bus 1517, an antenna (antenna coil) 1518, a sensor 1523a, and a sensor circuit 1523b are included.

The power supply circuit 1511 is a circuit that generates various power supplies to be supplied to each circuit inside the semiconductor device 1520 based on the AC signal input from the antenna 1518. The clock generation circuit 1512 is a circuit that generates various clock signals to be supplied to each circuit inside the semiconductor device 1520 based on the AC signal input from the antenna 1518. The data demodulation / modulation circuit 1513 has a function of demodulating / modulating data communicated with the reader / writer 1519. The control circuit 1514 has a function of controlling the memory circuit 1516. The antenna 1518 has a function of transmitting and receiving radio waves. The reader / writer 1519 controls communication with the semiconductor device, control, and processing related to the data. The semiconductor device is not limited to the above-described configuration, and may be a configuration in which other elements such as a power supply voltage limiter circuit and hardware dedicated to cryptographic processing are added.

The memory circuit 1516 includes the memory element described in Embodiments 1 to 6 as the memory element in which the layer containing an organic compound that is changed by an external electric action is sandwiched between a pair of conductive layers. Note that the memory circuit 1516 may include only a memory element in which a layer containing an organic compound is interposed between a pair of conductive layers, or may include a memory circuit having another structure. The memory circuit having another configuration corresponds to, for example, one or more selected from DRAM, SRAM, FeRAM, mask ROM, PROM, EPROM, EEPROM, and flash memory.

The sensor 1523a is formed of a semiconductor element such as a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectromotive element, a transistor, a thermistor, or a diode. The sensor circuit 1523b detects a change in impedance, reactance, inductance, voltage, or current, performs analog / digital conversion (A / D conversion), and outputs a signal to the control circuit 1514.

Further, this embodiment mode can be freely combined with Embodiment Mode 1, Embodiment Mode 2, Embodiment Mode 3, Embodiment Mode 4, Embodiment Mode 5, Embodiment Mode 6, or Embodiment Mode 7. .

(Embodiment 9)
According to the present invention, a semiconductor device functioning as a wireless chip can be formed. Applications of wireless chips are wide-ranging. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 10A), packaging containers (wrapping paper, Bottle, etc., see FIG. 10C), recording medium (DVD software, video tape, etc., see FIG. 10B), vehicles (bicycle, etc., see FIG. 10D), personal items (bags, glasses, etc.) ), Foods, plants, animals, human bodies, clothing, daily necessities, electronic devices, etc. and goods such as luggage tags (see FIGS. 10E and 10F) for use. be able to. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also simply referred to as televisions, television receivers, television receivers), mobile phones, and the like.

The semiconductor device 9210 of the present invention is fixed to an article by being mounted on a printed board, pasted on a surface, or embedded. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin, and is fixed to each article. Since the semiconductor device 9210 of the present invention is small, thin, and lightweight, it does not impair the design of the article itself even after being fixed to the article. In addition, by providing the semiconductor device 9210 of the present invention for bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and forgery can be prevented by using this authentication function. Can do. In addition, by providing the semiconductor device of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved.

Next, one mode of an electronic device in which the semiconductor device of the present invention is mounted will be described with reference to the drawings. The electronic device illustrated here is a mobile phone, which includes housings 2700 and 2706, a panel 2701, a housing 2702, a printed wiring board 2703, operation buttons 2704, and a battery 2705 (see FIG. 9). The panel 2701 is detachably incorporated in the housing 2702, and the housing 2702 is fitted on the printed wiring board 2703. The shape and dimensions of the housing 2702 are changed as appropriate in accordance with the electronic device in which the panel 2701 is incorporated. A plurality of packaged semiconductor devices are mounted on the printed wiring board 2703, and the semiconductor device of the present invention can be used as one of them. The plurality of semiconductor devices mounted on the printed wiring board 2703 have any one function of a controller, a central processing unit (CPU), a memory, a power supply circuit, a sound processing circuit, a transmission / reception circuit, and the like.

The panel 2701 is fixed to the printed wiring board 2703 through the connection film 2708. The panel 2701, the housing 2702, and the printed wiring board 2703 are housed in the housings 2700 and 2706 together with the operation buttons 2704 and the battery 2705. A pixel region 2709 included in the panel 2701 is arranged so as to be visible from an opening window provided in the housing 2700.

As described above, the semiconductor device of the present invention is advantageous in that it is small, thin, and lightweight, and the above-described effects can effectively use a limited space inside the casings 2700 and 2706 of the electronic device. .

In addition, since the semiconductor device of the present invention includes a memory element having a simple structure in which a layer containing an organic compound that changes due to an external electric action is sandwiched between a pair of conductive layers, an electronic device using an inexpensive semiconductor device Equipment can be provided. In addition, since the semiconductor device of the present invention can be easily integrated, an electronic device using the semiconductor device including a large-capacity memory circuit can be provided. As the memory element included in the semiconductor device of the present invention, the memory element described in any of Embodiments 1 to 6 can be used.

In addition, a memory device included in the semiconductor device of the present invention writes data by an external electric action, is nonvolatile, and can additionally write data. With the above feature, forgery due to rewriting can be prevented, and new data can be added and written. Therefore, an electronic device using a semiconductor device that achieves high functionality and high added value can be provided.

Note that the housings 2700 and 2706 are examples of the appearance of a mobile phone, and the electronic device according to this embodiment can be modified into various modes depending on functions and uses.

In addition, this embodiment is free from the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, the sixth embodiment, the seventh embodiment, or the eighth embodiment. Can be combined.

4A and 4B are a cross-sectional view and a top view of a semiconductor device of the present invention. (Embodiment 1) 4A and 4B are a cross-sectional view and a top view of a semiconductor device of the present invention. (Embodiment 2) 4A and 4B are a cross-sectional view and a top view of a semiconductor device of the present invention. (Embodiment 3) 4A and 4B are a cross-sectional view and a top view of a semiconductor device of the present invention. (Embodiment 4) 4A and 4B are a cross-sectional view and a top view of a semiconductor device of the present invention. (Embodiment 5) 4A and 4B are a cross-sectional view and a top view of a semiconductor device of the present invention. (Embodiment 6) FIG. 5 is a diagram showing an equivalent circuit diagram of a semiconductor device of the present invention. (Embodiment 7) 8A and 8B illustrate a structure example of a semiconductor device of the present invention. (Embodiment 8) 4A and 4B each illustrate a usage pattern of a semiconductor device of the invention. (Embodiment 9) 6A and 6B illustrate an electronic device including a semiconductor device of the present invention. (Embodiment 10)

Explanation of symbols

101: substrate having an insulating surface 102: first insulating layer 103: semiconductor layer 104: second insulating layer 105: word line (gate line)
106: third insulating layer 107: fourth insulating layer 108: first electrode 109: bit line 112: common line 113: layer containing an organic compound 114: fifth insulating layer (partition wall)
120: Current path

Claims (13)

A semiconductor device in which a memory element and a switching element are arranged over a substrate having an insulating surface,
The memory element is
A first electrode,
A second electrode and a layer containing an organic compound between the first electrode and the second electrode;
The first electrode, the second electrode, and the layer containing the organic compound are formed in the same plane,
Current flows from the first electrode to the second electrode;
The semiconductor device, wherein the first electrode is electrically connected to the switching element. A semiconductor device in which a memory element and a switching element are arranged over a substrate having an insulating surface,
Having a pair of insulating layers;
The memory element is
A first electrode,
A second electrode,
A layer containing an organic compound between the first electrode and the second electrode;
The first electrode, the second electrode, and the layer containing the organic compound are formed in the same plane,
Current flows from the first electrode to the second electrode;
The layer containing the organic compound is surrounded by the pair of insulating layers, the first electrode, and the second electrode,
The semiconductor device, wherein the first electrode is electrically connected to the switching element. 3. The semiconductor device according to claim 2, wherein the pair of insulating layers are disposed so as to sandwich both sides of the layer containing the organic compound. 4. The memory element according to claim 1, wherein the memory element forms a potential difference between the first electrode and the second electrode, and the layer including the organic compound is changed from a high resistance state to a low resistance state. A semiconductor device that is an element having a structure that is irreversibly changed. 5. The semiconductor device according to claim 1, wherein a total width of electrode widths of the first electrode and the second electrode is wider than a width of the layer containing the organic compound. 6. The semiconductor device according to claim 1, wherein the gate electrode of the switching element is a word line. The semiconductor device according to claim 1, wherein an upper surface shape of the layer including the organic compound is a rectangular shape, an elliptical shape, a circular shape, or a belt shape.   8. The semiconductor device according to claim 1, wherein side surfaces of the first electrode and the second electrode have a tapered shape.   9. The semiconductor device according to claim 1, wherein the switching element is an n-channel thin film transistor.   9. The semiconductor device according to claim 1, wherein the switching element is a p-channel thin film transistor. Forming a semiconductor layer over a substrate having an insulating surface;
Forming an insulating film covering the semiconductor layer;
A pair of electrodes, one of which is electrically connected to the semiconductor layer, is formed on the same surface on the insulating film,
A method for manufacturing a semiconductor device, in which a layer containing an organic compound is formed between the pair of electrodes. Forming a semiconductor layer over a substrate having an insulating surface;
Forming an insulating film covering the semiconductor layer;
A pair of electrodes, one of which is electrically connected to the semiconductor layer, is formed on the same surface on the insulating film,
Forming a pair of insulating layers on the insulating film;
A method for manufacturing a semiconductor device, in which a layer containing an organic compound is formed so as to overlap with a region surrounded by the pair of electrodes and the pair of insulating layers. The method for manufacturing a semiconductor device according to claim 11, wherein an upper surface shape of the layer including the organic compound is a rectangular shape, an elliptical shape, a circular shape, or a belt shape.

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