JP4912671B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device containing an organic compound and a manufacturing method thereof.

  2. Description of the Related Art In recent years, attention has been focused on an individual recognition technique in which an ID (individual identification number) is given to an individual object to clarify information such as a history of the object and to be useful for production and management. Among them, development of semiconductor devices capable of transmitting and receiving data without contact is underway. As such a semiconductor device, a wireless chip (ID tag, IC tag, IC chip, RF tag (Radio Frequency), wireless tag, electronic tag, RFID (Radio Frequency Identification)) tag, etc. are particularly used in the company, on the market. Etc. have begun to be introduced.

  Many of these semiconductor devices in practical use have a circuit (also referred to as an IC (Integrated Circuit) chip) using a semiconductor substrate such as Si and an antenna, and the IC chip is a memory circuit (also referred to as a memory). ) And a control circuit. In particular, by providing a memory circuit capable of storing a large amount of data, a semiconductor device with higher functions and higher added value can be provided. In addition, these semiconductor devices are required to be manufactured at low cost, and in recent years, development of organic TFTs and organic memories using organic compounds in control circuits, memory circuits, etc. has been actively carried out (for example, Patent Document 1).

JP-A-2004-47791

  In general, as a memory circuit provided in a semiconductor device, a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), a FeRAM (Ferroelectric Random Access Memory), a mask ROM (Read Only Memory, a Read ROM). Examples include only memory (EEPROM), EEPROM (electrically erasable and programmable read only memory), and flash memory. Among these, DRAM and SRAM are volatile storage circuits, and data is erased when the power is turned off. Therefore, it is necessary to write data every time the power is turned on. FeRAM is a non-volatile memory circuit, but a manufacturing process increases because a capacitor element including a ferroelectric layer is used. Although the mask ROM has a simple structure, it is necessary to write data in the manufacturing process, and data cannot be added after manufacturing. Although EPROM, EEPROM, and flash memory are non-volatile memory circuits, the number of manufacturing steps increases because an element including two gate electrodes is used.

  On the other hand, in a memory circuit using an organic compound, an organic compound is provided between a pair of electrodes to form a memory element portion. However, when the organic compound layer is formed thick, current does not flow easily and driving voltage increases. Conversely, when the organic compound layer is formed thin in order to reduce the drive voltage, it becomes susceptible to physical damage due to short-circuiting between electrodes or application of stress. As a result, the reliability of the semiconductor device is increased. There is a risk of lowering.

  In view of the above problems, an object of the present invention is to provide a semiconductor device having a nonvolatile memory element that can additionally record data other than at the time of manufacturing and can prevent forgery or the like due to rewriting, and a manufacturing method thereof.

  In order to solve the above problems, the present invention takes the following measures.

  The semiconductor device of the present invention is provided at an intersection of a plurality of bit lines extending in a first direction, a plurality of word lines extending in a second direction different from the first direction, and the bit lines and the word lines. A memory cell array having a plurality of memory cells and a memory element provided in the memory cell, the memory element having a bit line, an organic compound layer, and a word line, and at least the bit line and the organic compound layer And the organic compound layer is in contact with the word line, and the organic compound layer has a layer in which an inorganic compound and an organic compound are mixed.

  According to another configuration of the semiconductor device of the present invention, a plurality of bit lines extending in a first direction, a plurality of word lines extending in a second direction different from the first direction, and an intersection of the bit line and the word line A memory cell array including a plurality of memory cells provided in a portion and a memory element provided in the memory cell, the memory element including a bit line, an organic compound layer, and a word line, and at least a bit line And the organic compound layer are in contact with each other, and the organic compound layer and the word line are in contact with each other. The organic compound layer is a stack of a layer in which an inorganic compound and a first organic compound are mixed and a layer having a second organic compound It is characterized by its structure.

  Another structure of the semiconductor device of the present invention includes a plurality of transistors including a first transistor and a second transistor provided over a substrate, a plurality of bit lines extending in a first direction, and a first direction. A plurality of word lines extending in different second directions; a memory cell array having a plurality of memory cells provided at intersections of bit lines and word lines; a memory element provided in the memory cells; and a first transistor The memory element includes a bit line, an organic compound layer, and a word line, and at least the bit line and the organic compound layer are in contact with each other and the organic compound is electrically connected to the antenna. The layer and the word line are in contact, at least one of the bit line and the word line is in contact with the second thin film transistor, and the organic compound layer is a mixture of an inorganic compound and an organic compound It is characterized by having a.

  Another structure of the semiconductor device of the present invention includes a plurality of transistors including a first transistor and a second transistor provided over a substrate, a plurality of bit lines extending in a first direction, and a first direction. A plurality of word lines extending in different second directions; a memory cell array having a plurality of memory cells provided at intersections of bit lines and word lines; a memory element provided in the memory cells; and a first transistor The memory element includes a bit line, an organic compound layer, and a word line, and at least the bit line and the organic compound layer are in contact with each other and the organic compound is electrically connected to the antenna. The layer and the word line are in contact, at least one of the bit line and the word line is in contact with the second thin film transistor, and the organic compound layer is a mixture of the inorganic compound and the first organic compound It is characterized by that the layer has a stacked structure of a layer having a second organic compound.

  The semiconductor device of the present invention is characterized in that in the above structure, a bit line, an organic compound layer, and a word line are stacked.

  Another structure of the semiconductor device of the present invention is characterized in that, in the above structure, the bit line and the word line are arranged in the same plane, and the organic compound layer is arranged between the bit line and the word line. It is said.

  In the above structure of the semiconductor device of the present invention, one or both of the conductive layer forming the bit line and the conductive layer forming the word line may have a light-transmitting property.

  In the semiconductor device of the present invention, in the above structure, a rectifying element is provided between the conductive layer forming the bit line and the organic compound layer or between the organic compound layer and the conductive layer forming the word line. It may be done. Note that as the rectifying element, a transistor or a diode in which a gate electrode and a drain electrode are connected can be used.

  Another configuration of the semiconductor device of the present invention is surrounded by a plurality of bit lines extending in a first direction, a plurality of word lines extending in a second direction different from the first direction, and the bit lines and the word lines. A memory cell array including a plurality of memory cells, the memory cell including a transistor and a memory element electrically connected to the transistor, wherein the memory element includes a first conductive layer and an organic compound layer. And the second conductive layer, at least the first conductive layer and the organic compound layer are in contact with each other, and the organic compound layer and the second conductive layer are in contact with each other. The organic compound layer includes an inorganic compound and an organic compound. Has a mixed layer.

  Another configuration of the semiconductor device of the present invention is surrounded by a plurality of bit lines extending in a first direction, a plurality of word lines extending in a second direction different from the first direction, and the bit lines and the word lines. A memory cell array including a plurality of memory cells, the memory cell including a transistor and a memory element electrically connected to the transistor, wherein the memory element includes a first conductive layer and an organic compound layer. And the second conductive layer, at least the first conductive layer and the organic compound layer are in contact with each other, and the organic compound layer and the second conductive layer are in contact with each other, and the organic compound layer includes the inorganic compound and the first conductive layer. A layered structure of a layer in which an organic compound is mixed and a layer having a second organic compound is characterized.

  Another structure of the semiconductor device of the present invention includes a plurality of transistors including a first transistor and a second transistor provided over a substrate, a plurality of bit lines extending in a first direction, and a first direction. A plurality of word lines extending in different second directions, a memory cell array having a plurality of memory cells surrounded by bit lines and word lines, and a conductive film functioning as an antenna electrically connected to the first transistor And the memory cell includes a second transistor and a memory element electrically connected to the second transistor. The memory element includes a first conductive layer, an organic compound layer, Two conductive layers, at least the first conductive layer and the organic compound layer are in contact, the organic compound layer and the second conductive layer are in contact, and the organic compound layer is a mixture of an inorganic compound and an organic compound. Have a layer It is characterized in that there.

  Another structure of the semiconductor device of the present invention includes a plurality of transistors including a first transistor and a second transistor provided over a substrate, a plurality of bit lines extending in a first direction, and a first direction. A plurality of word lines extending in different second directions, a memory cell array having a plurality of memory cells surrounded by bit lines and word lines, and a conductive film functioning as an antenna electrically connected to the first transistor And the memory cell includes a second transistor and a memory element electrically connected to the second transistor. The memory element includes a first conductive layer, an organic compound layer, Two conductive layers, at least the first conductive layer and the organic compound layer are in contact with each other, and the organic compound layer and the second conductive layer are in contact with each other. The organic compound layer includes the inorganic compound and the first organic compound. Mixed layers It is characterized in that a laminated structure of a layer having a second organic compound.

  In the above structure of the semiconductor device of the present invention, a conductive layer functioning as an antenna is provided in the same layer as the first conductive layer or the second conductive layer.

  In the semiconductor device of the present invention, the first conductive layer, the organic compound layer, and the second conductive layer are stacked in the above structure.

  In the semiconductor device of the present invention having the above structure, the first conductive layer and the second conductive layer are arranged in the same plane, and the organic compound layer is interposed between the first conductive layer and the second conductive layer. It is characterized by being arranged.

  In the semiconductor device of the present invention having the above structure, the transistor is an organic transistor.

  In the semiconductor device of the invention having the above structure, a transistor is provided over a flexible substrate or a glass substrate.

  A specific example of the layer provided by mixing an inorganic compound and an organic compound in the organic compound layer includes a layer provided by mixing a metal oxide or metal nitride and an organic compound. In addition, the organic compound layer can be provided in a stacked structure of a layer formed by mixing a metal oxide or metal nitride and an organic compound and a layer made of the organic compound. The organic compound can be provided using an electron transport material or a hole transport material. In addition, any organic compound that can transport carriers can be used.

  In a method for manufacturing a semiconductor device of the present invention, a plurality of transistors each including a first transistor and a second transistor are formed over a substrate, and a first conductive layer electrically connected to the first transistor and a second transistor A second conductive layer electrically connected to the transistor, an insulating layer is selectively formed so as to cover the first conductive layer and an end portion of the second conductive layer, and the first conductive layer A conductive layer functioning as an antenna is formed so as to be electrically connected, an organic compound layer is formed so as to cover the second conductive layer after the conductive layer functioning as an antenna is formed, and the organic compound layer is covered A third conductive layer is formed. In addition, a conductive layer functioning as an antenna is formed by performing heat treatment on a conductive paste provided by a screen printing method or a droplet discharge method.

  In another method for manufacturing a semiconductor device of the present invention, a plurality of transistors including a first transistor and a second transistor are formed over a substrate, and the first transistor functions as an antenna electrically connected to the first transistor. Forming a conductive layer and a second conductive layer electrically connected to the second transistor, and selectively forming an insulating layer so as to cover an end portion of the second conductive layer and the first conductive layer; An organic compound layer is formed so as to cover the second conductive layer, and a third conductive layer is formed so as to cover the organic compound layer. Further, the first conductive layer and the second conductive layer functioning as an antenna are formed by a sputtering method or a CVD method.

  In addition, the method for manufacturing a semiconductor device of the present invention is characterized in that the organic compound layer is formed of a layer in which an inorganic compound and an organic compound are mixed.

  By using the present invention, it is possible to obtain a semiconductor device in which data can be written (added) other than during chip manufacturing and forgery by rewriting can be prevented. In addition, by adding a layer in which an organic compound and an inorganic compound are mixed to the organic compound layer constituting the memory element portion, the layer can be formed thick without increasing the driving voltage at the time of data writing or reading. Therefore, a highly reliable semiconductor device can be provided. Further, by using the present invention, a semiconductor device having a memory circuit having a fine structure can be manufactured at low cost.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals may be used in common in different drawings.

(Embodiment 1)
In this embodiment mode, a structure in which a layer containing an organic compound (hereinafter also referred to as an organic compound layer) is provided between a pair of conductive layers in a memory element portion (hereinafter referred to as an “organic memory element”). A configuration example will be described with reference to the drawings.

  FIG. 1A shows a configuration example of a memory circuit including an organic compound layer (hereinafter also referred to as an organic memory), in which memory cells 21 each including an organic memory element are provided in a matrix. A cell line 22, a bit line driving circuit 26 having a column decoder 26a, a reading circuit 26b, and a selector 26c, a word line driving circuit 24 having a row decoder 24a and a level shifter 24b, an interface 23 having a writing circuit and the like for performing external communication. Have. Note that the structure of the memory circuit 16 shown here is just an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included, and a write circuit may be provided in the bit line driver circuit.

  The memory cell 21 includes a first conductive layer constituting the bit line Bx (1 ≦ x ≦ m), an organic compound layer, and a second conductive layer constituting the word line Wy (1 ≦ y ≦ n) An organic memory element having a stacked structure of The organic compound layer is provided as a single layer or a stacked layer between the first conductive layer and the second conductive layer.

  An example of a top surface structure and a cross-sectional structure of the memory cell array 22 is shown in FIG. Note that FIG. 2A illustrates a top structure of the memory cell array 22, and a cross-sectional structure taken along a line AB in FIG. 2A corresponds to FIG.

  The memory cell array 22 includes a first conductive layer 27 extending in a first direction, an organic compound layer 29 provided so as to cover the first conductive layer 27 on a substrate 30 having an insulating surface, And a second conductive layer extending in a second direction different from the direction (for example, a vertical direction). Note that the memory cell 21 is provided at the intersection of the first conductive layer 27 and the second conductive layer 28. An organic memory element 80 is formed by a stacked structure of the first conductive layer 27, the organic compound layer 29, and the second conductive layer 28. Here, an insulating layer 34 functioning as a protective film is provided so as to cover the second conductive layer 28 (FIG. 2B).

  Further, when there is a concern about the influence of the electric field in the lateral direction between adjacent memory cells, the organic compound layer provided in each memory cell is separated to separate the organic compound layer provided in each memory cell. An insulating layer 33 may be provided therebetween (FIG. 2C). In other words, an organic compound layer may be selectively provided for each memory cell.

  In addition, when the organic compound layer 29 is provided so as to cover the first conductive layer 27, the step of the organic compound layer 29 caused by the step between the first conductive layers 27 and the electric field in the lateral direction between the memory cells. In order to prevent the influence, an insulating layer 37 may be provided between the first conductive layers 27 (FIG. 2D). Note that the insulating layer 37 is preferably provided in a tapered shape. Thereafter, an organic compound layer 29 is formed so as to cover the first conductive layer 27 and the insulating layer 37.

  In the above configuration, as the substrate 30, a glass substrate, a flexible substrate, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, or the like can be used. The flexible substrate is a substrate that can be bent (flexible), and examples thereof include a plastic substrate made of polycarbonate, polyarylate, polyethersulfone, or the like. In addition, the memory cell array 22 may be provided above a field effect transistor (FET) formed on a semiconductor substrate such as Si or above a thin film transistor (TFT) formed on a substrate such as glass. it can.

  The first conductive layer 27 and the second conductive layer 28 are made of gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo ), Iron (Fe), cobalt (Co), copper (Cu), palladium (Pd), carbon (C), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), etc. A single layer or a laminated structure made of one kind of element or an alloy containing a plurality of such elements can be used. Examples of the alloy containing a plurality of the elements include an alloy containing Al, Ti and C, an alloy containing Al and Ni, an alloy containing Al and C, an alloy containing Al, Ni and C, or Al and Mo. An alloy or the like can be used.

  The first conductive layer 27 and the second conductive layer 28 can be formed by vapor deposition, sputtering, CVD, printing, or droplet discharge. Here, the first conductive layer 27 and the second conductive layer 28 are formed using any of these methods. Further, the first conductive layer 27 and the second conductive layer 28 may be formed by using another method. Note that a droplet discharge method is a method in which a droplet (also referred to as a dot) of a composition containing a material having conductivity, insulation, or semiconductor properties is selectively discharged (jetted) to a conductor at an arbitrary place. This is a method for forming an insulator or a semiconductor, and is also called an ink jet method depending on the method.

  In this embodiment mode, data writing to the organic memory is performed by applying an electric action or an optical action. When data writing is performed by an optical action, the first conductive layer 27 and the second conductive layer are written. One or both of the layers 28 are provided so as to have translucency. The light-transmitting conductive layer is formed using a transparent conductive material, or is formed with a thickness that allows light to pass even if it is not a transparent conductive material. As the transparent conductive material, other light-transmitting oxide conductive materials such as indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), gallium-doped zinc oxide (GZO), and the like are used. Is possible. Indium tin oxide containing ITO and silicon oxide, or indium oxide containing silicon oxide mixed with 2 to 20% zinc oxide (ZnO) may be used.

  The organic compound layer 29 has a layer formed by mixing an organic compound and an inorganic compound. As the organic compound layer 29, a mixed layer of an organic compound and an inorganic compound may be provided as a single layer, or a plurality of layers may be stacked. Alternatively, a mixed layer of an organic compound and an inorganic compound and a layer formed of another organic compound may be stacked. In this case, the organic compound material contained in the mixed layer and the organic compound material contained in the layer composed of another organic compound may be the same or different.

  The inorganic compound may be any inorganic compound material that easily accepts electrons from the organic compound, or any inorganic compound material that easily gives electrons to the organic compound, and various metal oxides, metal nitrides, or metal oxynitrides may be used. it can.

  As an inorganic compound material that easily receives electrons, a metal oxide, metal nitride, or metal oxynitride of a transition metal in any of Groups 4 to 12 of the periodic table can be used. Specifically, titanium oxide (TiOx), zirconium oxide (ZrOx), vanadium oxide (VOx), molybdenum oxide (MoOx), tungsten oxide (WOx), tantalum oxide (TaOx), hafnium oxide (HfOx), niobium oxide (NbOx), cobalt oxide (CoOx), rhenium oxide (ReOx), ruthenium oxide (RuOx), zinc oxide (ZnO), nickel oxide (NiOx), copper oxide ( CuOx) or the like can be used. Further, although oxides are given as specific examples here, these nitrides and oxynitrides may of course be used.

  As the inorganic compound material that easily gives electrons, alkali metal oxides, alkaline earth metal oxides, rare earth metal oxides, alkali metal nitrides, alkaline earth metal nitrides, and rare earth metal nitrides can be used. Specifically, lithium oxide (LiOx), strontium oxide (SrOx), barium oxide (BaOx), erbium oxide (ErOx), sodium oxide (NaOx), lithium nitride (LiNx), magnesium nitride (MgNx), calcium nitride (CaNx), yttrium nitride (YNx), lanthanum nitride (LaNx), or the like can be used.

  In addition to the above materials, as the inorganic compound, aluminum oxide (AlOx), gallium oxide (GaOx), silicon oxide (SiOx), germanium oxide (GeOx), indium tin oxide (ITO), etc. It may be used.

  As the organic compound, it is preferable to use an organic compound material having a high hole transporting property or an organic compound material having a high electron transporting property.

As an organic compound material having a high hole-transport property, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD), 4,4′-bis [ N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD) or 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: TDATA) ), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) and 4,4′-bis (N- (4- (N, N-di-m-tolylamino) phenyl) -N-phenylamino) biphenyl (abbreviation: DNTPD) and other aromatic amine-based compounds (that is, having a benzene ring-nitrogen bond) and phthalocyanines (abbreviation: H ₂ Pc), copper phthalo Phthalocyanine compounds such as cyanine (abbreviation: CuPc) and vanadyl phthalocyanine (abbreviation: VOPc) can be used. The substances described here are mainly substances having a hole mobility of 10 ⁻⁶ cm ² / Vs or higher. Note that other than the above substances, any substance that has a property of transporting more holes than electrons may be used. Note that in the case where a mixed layer of an organic compound and an inorganic compound is provided, it is preferable to mix an organic compound material having a high hole-transport property and an inorganic compound material that easily receives electrons. By adopting such a configuration, many hole carriers are generated in an organic compound which has essentially no inherent carrier, and exhibits extremely excellent hole injection / transport properties. As a result, the organic compound layer can obtain excellent conductivity.

As an organic compound material having a high electron-transport property, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [ h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), etc., and a metal complex having a quinoline skeleton or a benzoquinoline skeleton Materials can be used. In addition, bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) A material such as a metal complex having an oxazole-based or thiazole-based ligand such as ₂ ) can also be used. In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- ( 4-biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2, 4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), and the like can be used. The substances mentioned here are mainly substances having an electron mobility of 10 ⁻⁶ cm ² / Vs or higher. Note that other than the above substances, any substance that has a property of transporting more electrons than holes may be used. Note that in the case of providing a mixed layer of an organic compound and an inorganic compound, it is preferable to mix an organic compound material having a high electron-transport property and an inorganic compound material that easily gives electrons. By adopting such a structure, many electron carriers are generated in an organic compound having almost no carriers, and extremely excellent electron injecting / transporting properties are exhibited. As a result, the organic compound layer can obtain excellent conductivity.

  Further, when the organic compound layer 29 is formed of a compound selected from metal oxides or metal nitrides and a compound having a high hole transporting property, the steric hindrance is further increased (in contrast to the planar structure, spatial A structure in which a compound having a spread structure is added may be used. As the compound having a large steric hindrance, 5,6,11,12-tetraphenyltetracene (abbreviation: rubrene) is preferable. However, besides this, hexaphenylbenzene, t-butylperylene, 9,10-di (phenyl) anthracene, coumarin 545T, and the like can also be used. In addition, dendrimers and the like are also effective.

  Further, when the organic compound layer 29 is formed of a compound selected from metal oxides or metal nitrides and a compound having a high electron transporting property, electrons can be further donated to the substance having a high electron transporting property. Alkaline metals such as lithium (Li) and cesium (Cs), alkaline earth metals such as magnesium (Mg), calcium (Ca) and strontium (Sr), rare earth metals such as erbium and ytterbium, or oxidation thereof It is good also as a structure which added compounds, such as a thing and a halide.

  The organic compound layer 29 can be formed using a vapor deposition method, an electron beam vapor deposition method, a sputtering method, or the like. Moreover, the mixed layer containing an organic compound and an inorganic compound can be formed by simultaneously forming the respective materials. The co-evaporation method using resistance heating evaporation, the co-evaporation method using electron beam evaporation, and resistance heating. It can be formed by a combination of the same or different methods such as co-evaporation by vapor deposition and electron beam vapor deposition, film formation by resistance heating vapor deposition and sputtering, and film formation by electron beam vapor deposition and sputtering. In addition, when a layer containing three or more kinds of materials is formed, it can be similarly combined.

  As other forming methods, spin coating, a sol-gel method, a printing method, a droplet discharge method, or the like may be used, or the organic compound layer 29 may be formed by combining these methods. When the organic compound layer 29 is formed of a plurality of layers, for example, when the organic compound layer 29 is formed in a stacked structure of a mixed layer of an organic compound and an inorganic compound and a layer formed of the organic compound, different film formation is performed for each layer. You may form using a method.

  Thus, by providing the organic compound layer 29 with a mixed layer of an organic compound and an inorganic compound, an increase in resistance can be suppressed even when the organic compound layer 29 is formed thick. Therefore, the organic compound layer sandwiched between the pair of conductive layers can be formed thick to increase the distance between the conductive layers without increasing the driving voltage at the time of data writing or reading. As a result, a short circuit between the conductive layers in the organic memory element and damage to the memory cell due to external force can be prevented, and the reliability of the semiconductor device including the organic memory can be improved.

  Further, as a different structure from the above structure, a rectifying element may be provided between the first conductive layer 27 and the organic compound layer 29 or between the second conductive layer 28 and the organic compound layer 29. (FIG. 2 (E)). The rectifying element is typically a Schottky diode, a diode having a PN junction, a diode having a PIN junction, or a transistor in which a gate electrode and a drain electrode are connected. Of course, other configurations of diodes may be used. Here, a case where a PN junction diode including semiconductor layers 44 and 45 is provided between the first conductive layer and the organic compound layer is shown. One of the semiconductor layers 44 and 45 is an N-type semiconductor, and the other is a P-type semiconductor. In this manner, by providing an element having a rectifying action, the selectivity of the memory cell can be improved and the margin of the read or write operation can be improved.

  FIG. 2 shows an example in which a memory element portion including a plurality of organic memory elements is provided on the substrate 30. However, the present invention is not limited to this, and a thin film transistor 79 (TFT) is provided on the substrate 30 and a plurality of organic elements is provided thereon. A memory element portion 77 including a memory element may be provided (FIG. 19A), or a field effect transistor 78 (FET) is formed on a substrate using a semiconductor substrate such as Si or an SOI substrate as the substrate 30. A memory element portion 77 may be provided thereover (FIG. 19B). Note that although the example in which the memory element portion 77 is formed over the thin film transistor 79 or the field effect transistor 78 is shown here, the memory element portion 77 and the thin film transistor 79 or the field effect transistor 78 may be attached to each other. In this case, the memory element portion 77 and the thin film transistor 79 or the field effect transistor 78 can be provided by being manufactured in separate steps and then bonded using a conductive film or the like. The thin film transistor 79 or the field effect transistor 78 may have any configuration as long as it is a known one.

  Next, an operation when data is written to the organic memory will be described. Data writing is performed by optical action or electrical action. First, the case of writing data by electrical action will be described (FIG. 1A). Note that writing is performed by changing the electrical characteristics of the memory cell. Here, the initial state (state in which no electrical action is applied) of the memory cell is data “0”, and the state in which the electrical characteristics are changed is “ 1 ”.

  When writing data “1” to the memory cell 21, first, the memory cell 21 is selected by the row decoder 24 a, the column decoder 26 a, and the selector 26 c through the interface 23. Specifically, a predetermined voltage V2 is applied to the word line W3 connected to the memory cell 21 by the row decoder 24a. Further, the bit line B3 connected to the memory cell 21 is connected to the read circuit 26b by the column decoder 26a and the selector 26c. Then, the write voltage V1 is output from the read circuit 26b to the bit line B3. Thus, the voltage Vw = V1−V2 is applied between the first conductive layer and the second conductive layer constituting the memory cell 21. By appropriately selecting the potential Vw, the organic compound layer 29 provided between the conductive layers is changed physically or electrically, and data “1” is written. Specifically, at the read operation voltage, the electrical resistance between the first conductive layer and the second conductive layer in the data “1” state is significantly smaller than that in the data “0” state. It is good to change as follows. For example, it may be appropriately selected from the range of (V1, V2) = (0V, 5-15V), or (3-5V, -12--2V). The voltage Vw may be 5 to 15V, or -5 to -15V. In this case, the distance between the pair of conductive layers provided with the organic compound layer interposed therebetween may change.

  Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. For example, unselected word lines and unselected bit lines may be set in a floating state. The first conductive layer and the second conductive layer constituting the memory cell must have characteristics such as diode characteristics that can ensure selectivity.

  On the other hand, when data “0” is written in the memory cell 21, it is not necessary to apply an electrical action to the memory cell 21. In the circuit operation, for example, as in the case of writing “1”, the memory cell 21 is selected by the row decoder 24a, the column decoder 26a, and the selector 26c, but the output potential from the read circuit 26b to the bit line B3 is selected. The electrical potential of the memory cell 21 is not changed between the first conductive layer and the second conductive layer constituting the memory cell 21 so as to be approximately the same as the potential of the word line W3 or the unselected word line. (For example, −5 to 5 V) may be applied.

  Next, a case where data is written by applying an optical action will be described (FIGS. 3A to 3C).

  In the case of writing data by applying an optical action, the organic compound layer 29 is irradiated with laser light from the light-transmitting conductive layer side (herein, the second conductive layer 28). Here, the organic compound layer 29 included in a desired portion of the organic memory element is selectively irradiated with laser light to destroy the organic compound layer 29. Since the destroyed organic compound layer is carbonized and insulated, when an organic memory element including the destroyed organic compound layer and an organic memory element including an unbroken organic compound layer are compared, the first The electrical resistance between the conductive layer and the second conductive layer is greatly increased. As described above, data is written by utilizing the change in the electrical resistance between the two conductive layers provided with the organic compound layer 29 sandwiched by the laser light irradiation. For example, when an organic memory element including an organic compound layer not irradiated with laser light is set to “0” data, when writing “1” data, the laser light is selectively applied to a desired portion of the organic compound layer. The electrical resistance is increased by irradiating and destroying.

When laser light is irradiated, the change in the electrical resistance of the organic memory element depends on the size of the memory cell 21, but by irradiation with the laser light with a beam spot diameter reduced to μm or nm using an optical system such as a lens. Realize. For example, when a laser beam having a diameter of 1 μm passes at a linear velocity of 10 m / sec, the time for which the organic memory element included in one memory cell 21 is irradiated with laser light is 100 nsec. In order to change the phase within a short time of 100 nsec, the laser power is preferably 10 mW and the power density is 10 kW / mm ² . In the case of selectively irradiating laser light, it is preferable to use a pulsed laser irradiation apparatus.

  Here, an example of a laser irradiation apparatus will be briefly described with reference to FIG. A laser irradiation apparatus 1001 includes a computer 1002 (hereinafter, referred to as a PC 1002) that performs various controls when irradiating laser light, a laser oscillator 1003 that outputs laser light, a power source 1004 of the laser oscillator 1003, and laser light. An optical system 1005 (ND filter) for attenuating light, an acousto-optic modulator (AOM) 1006 for modulating the intensity of laser light, and a lens and an optical path for reducing the cross section of the laser light An optical system 1007 composed of a mirror for changing the angle, a moving mechanism 1009 having an X-axis stage and a Y-axis stage, a D / A conversion unit 1010 for digital-analog conversion of control data output from the PC, Acousto-optic conversion according to the analog voltage output from the D / A converter. A driver 1011 for controlling the vessel 1006, a driver 1012 for outputting a driving signal for driving the movement mechanism 1009 is provided with an auto-focus mechanism 1013 for focusing the laser beam on the irradiated object.

As the laser oscillator 1003, a laser oscillator that can oscillate ultraviolet light, visible light, or infrared light can be used. Examples of laser oscillators include excimer laser oscillators such as KrF, ArF, XeCl, and Xe, gas laser oscillators such as He, He—Cd, Ar, He—Ne, and HF, YAG, GdVO ₄ , YVO ₄ , YLF, and YAlO _3. A solid-state laser oscillator using a crystal doped with Cr, Nd, Er, Ho, Ce, Co, Ti, or Tm, and a semiconductor laser oscillator such as GaN, GaAs, GaAlAs, or InGaAsP can be used. In the solid-state laser oscillator, it is preferable to apply the fundamental wave or the second to fifth harmonics.

  Next, an irradiation method using a laser irradiation apparatus will be described. When the substrate 30 provided with the organic compound layer 29 is mounted on the moving mechanism 1009, the PC 1002 detects the position of the organic compound layer 29 to be irradiated with laser light by a camera not shown. Next, the PC 1002 generates movement data for moving the movement mechanism 1009 based on the detected position data.

  Thereafter, the PC 1002 controls the output light amount of the acousto-optic modulator 1006 via the driver 1011, so that the laser light output from the laser oscillator 1003 is attenuated by the optical system 1005 and then the acousto-optic modulator 1006. The light amount is controlled so as to be a predetermined light amount. On the other hand, the laser light output from the acousto-optic modulator 1006 is changed in optical path and beam spot shape by the optical system 1007 and condensed by the lens, and then the substrate 30 is irradiated with the laser light.

  At this time, according to the movement data generated by the PC 1002, the movement mechanism 1009 is controlled to move in the X direction and the Y direction. As a result, laser light is irradiated to a predetermined place, the light energy density of the laser light is converted into thermal energy, and the organic compound layer provided on the substrate 30 can be selectively irradiated with the laser light. Note that, here, an example in which the moving mechanism 1009 is moved and laser light irradiation is performed is shown; however, the laser light may be moved in the X direction and the Y direction by adjusting the optical system 1007.

  Next, an operation when data is read from the organic memory will be described (FIGS. 1A to 1C). In reading data, the electrical characteristics between the first conductive layer and the second conductive layer constituting the memory cell are different between the memory cell having data “0” and the memory cell having data “1”. Use it. For example, the effective electrical resistance between the first conductive layer and the second conductive layer constituting the memory cell having data “0” (hereinafter simply referred to as the electrical resistance of the memory cell) is R0 at the read voltage. A method of reading data by using the difference in electric resistance when the electric resistance of the memory cell having data “1” is R1 in the read voltage will be described. Note that R1 << R0. As the configuration of the reading circuit 26b, for example, a circuit using the resistance element 46 and the differential amplifier 47 illustrated in FIG. 1B can be considered. The resistance element 46 has a resistance value Rr, and R1 <Rr <R0. A transistor 48 may be used instead of the resistance element 46, and a clocked inverter 49 may be used instead of the differential amplifier (FIG. 1C). The clocked inverter 49 receives a signal or an inverted signal that becomes Hi when reading and becomes Lo when not reading. Of course, the circuit configuration is not limited to those shown in FIGS.

  When reading data from the memory cell 21, first, the memory cell 21 is selected by the row decoder 24a, the column decoder 26a, and the selector 26c via the interface 23. Specifically, a predetermined voltage Vy is applied to the word line Wy connected to the memory cell 21 by the row decoder 24a. Further, the bit line Bx connected to the memory cell 21 is connected to the terminal P of the read circuit 26b by the column decoder 26a and the selector 26c. As a result, the potential Vp of the terminal P becomes a value determined by resistance division of Vy and V0 by the resistance element 46 (resistance value Rr) and the memory cell 21 (resistance value R0 or R1). Therefore, when the memory cell 21 has data “0”, Vp0 = Vy + (V0−Vy) * R0 / (R0 + Rr). When the memory cell 21 has data “1”, Vp1 = Vy + (V0−Vy) * R1 / (R1 + Rr). As a result, in FIG. 1B, Vref is selected to be between Vp0 and Vp1, and in FIG. 1C, the change point of the clocked inverter is selected to be between Vp0 and Vp1. Thus, Lo / Hi (or Hi / Lo) is output as the output potential Vout according to the data “0” / “1”, and reading can be performed.

  For example, the differential amplifier is operated at Vdd = 3V, and Vy = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9, when the memory cell data is “0”, Vp0 = 2.7 V and Vout is Hi, and when the memory cell data is “1”, Vp1 = 0.3V and Lo is output as Vout. Thus, the memory cell can be read.

  According to the above method, the state of the electric resistance of the organic memory element is read as a voltage value using the difference in resistance value and resistance division. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. In addition, when the electrical characteristics of the memory cell have data “0” and “1” and diode characteristics with different threshold voltages, reading may be performed using the threshold voltage difference.

  As described above, since the organic memory described in this embodiment has a simple structure in which an organic compound layer is provided between a pair of conductive layers, a manufacturing process is simple and an inexpensive semiconductor device can be provided. . In addition, since the organic memory described in this embodiment is a nonvolatile memory, it is not necessary to incorporate a battery for holding data, and a small, thin, and lightweight semiconductor device can be provided. In addition, by using an irreversible material for the organic compound layer 29, data can be written (added), but data cannot be rewritten. Therefore, it is possible to provide a semiconductor device that prevents forgery and ensures security.

(Embodiment 2)
In this embodiment, a semiconductor device having a structure different from that of Embodiment 1 is described. Specifically, the case where the structure of the memory circuit is an active matrix type will be described.

  FIG. 4A illustrates an example of a structure of the organic memory described in this embodiment. A memory cell array 222 in which memory cells 221 are provided in a matrix, a column decoder 226a, a reading circuit 226b, and a selector 226c are included. A bit line driver circuit 226 having a word decoder; a word line driver circuit 224 having a row decoder 224a and a level shifter 224b; an interface 223 having a write circuit and the like and performing exchange with the outside. Note that the structure of the memory circuit 216 shown here is just an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included, and a writing circuit may be provided in the bit line driver circuit.

  The memory cell 221 includes a first wiring that forms a bit line Bx (1 ≦ x ≦ m), a second wiring that forms a word line Wy (1 ≦ y ≦ n), a transistor 240, and a storage element 241. And have. The memory element 241 has a structure in which an organic compound layer is sandwiched between a pair of conductive layers.

  Next, an example of a top view and a cross-sectional view of the memory cell array 222 having the above structure is described with reference to FIGS. 5A illustrates an example of a top view of the memory cell array 222. FIG. 5B is a cross-sectional view taken along line ab in FIG. 5A and a CMOS circuit included in the bit line driver circuit 226. The cross-sectional structure of is shown.

  The memory cell array 222 includes a plurality of transistors 240 that function as switching elements and memory elements 241 (hereinafter also referred to as organic memory elements 241) connected to the transistors 240 over a substrate 230 having an insulating surface (see FIG. 5 (A), (B)). The organic memory element 241 includes a first conductive layer 243, a second conductive layer 245, and an organic compound layer 244. The organic compound layer 244 includes the first conductive layer 243 and the second conductive layer 245. It is provided between them. Here, an insulating layer 249 is provided between adjacent memory cells 221, and an organic compound layer 244 and a second conductive layer 245 are stacked over the first conductive layer and the insulating layer 249. (FIG. 5B).

  In FIG. 5B, the first conductive layer 243 also functions as a source or drain electrode of the transistor 240 provided in the element formation layer 251; however, the first conductive layer 243 has the first conductive layer separately from the source or drain electrode. The conductive layer 243 may be formed (FIG. 5C). This is effective when, for example, the first conductive layer 243 is provided with a light-transmitting material such as ITO, that is, when the source and drain electrodes of the transistor and the first conductive layer 243 are formed with different materials. is there. Note that although the organic compound layer 244 is provided over the entire surface in the above structure, the organic compound layer 244 may be selectively provided only in each memory cell. In this case, for example, the use efficiency of the material can be improved by selectively using a droplet discharge method, a gravure printing method, a screen printing method, or the like.

  Alternatively, the insulating layer 250 may be provided as a protective film so as to cover the source and drain electrodes of the transistor 240, and the first conductive layer 243 may be provided over the insulating layer 250 (FIG. 11). In this case, an organic compound layer 244 may be formed over the entire surface so as to cover the first conductive layer 243 (FIG. 11B). In addition, when there is a concern about the step of the organic compound layer 244 between the adjacent memory cells or the influence of the electric field in the lateral direction, the organic compound layer included in the organic memory element provided in each memory cell. An insulating layer 249 may be provided in order to separate (FIG. 11C). FIG. 11C shows an example in which the organic compound layer 244 is selectively provided in each memory cell. However, as shown in FIG. 5C, the organic compound layer 244 is provided on the entire surface. It is good also as a structure.

  In this manner, the first conductive layer can be freely arranged by providing the insulating layer 250 and forming the memory element portion. That is, in the configuration in FIG. 5, the memory element 241 needs to be provided in a region where the source or drain electrode of the transistor 240 is avoided, but by using the above configuration, for example, the transistor 240 provided in the element formation layer 251. It is possible to form the memory element 241 above the upper portion. As a result, the memory circuit 216 can be more highly integrated (FIG. 11A).

  As another structure different from the above structure, the memory element portion can be formed by disposing the first conductive layer and the second conductive layer in the same layer. A configuration example in this case will be described with reference to FIG.

  In FIG. 5 or FIG. 11, the memory element portion is formed by stacking the organic compound layer 244 with the first conductive layer and the second conductive layer sandwiched between the upper and lower sides, but here the first conductive layer is formed. A memory element portion is formed by providing 243 and the second conductive layer 245 in the same layer and sandwiching the organic compound layer 244 in the horizontal direction (FIGS. 20A and 20B). In this case, the first conductive layer functions as a source or drain electrode of the transistor 240, and the second conductive layer 245 is also formed in the same layer as the source or drain electrode. In the case where the first conductive layer 243 and the second conductive layer 245 can be formed using the same material, the first conductive layer 243 and the second conductive layer 245 can be formed at the same time. The number of manufacturing steps can be reduced.

  Alternatively, the insulating layer 250 may be provided as a protective film so as to cover the source and drain electrodes of the transistor 240, and the first conductive layer 243 and the second conductive layer 245 may be provided over the insulating layer 250 ( FIG. 20 (C)). This is effective when, for example, the first conductive layer 243 is provided with a light-transmitting material such as ITO, that is, when the source and drain electrodes of the transistor and the first conductive layer 243 are formed with different materials. It is. In addition, since the first conductive layer and the second conductive layer can be freely arranged by providing the insulating layer 250 and forming the memory element portion, a more integrated memory element portion can be provided. Also in this case, when the materials of the first conductive layer 243 and the second conductive layer 245 are the same, the manufacturing steps can be reduced by forming them simultaneously.

  Note that in the structure in FIG. 20, the first conductive layer 243 and the second conductive layer 245 are not necessarily provided in the same layer. For example, in the structure of FIG. 20C, the second conductive layer 245 is formed above the organic compound layer 244, and the first conductive layer 243 and the second conductive layer are obliquely interposed through the organic compound layer 244. It is good also as a structure which 245 arrange | positions. With such a configuration, even when there is a contaminant such as dust on the first electrode, the influence can be prevented.

  In the plurality of structures described above, the transistor 240 may have any structure as long as it can function as a switching element. For example, a transistor may be formed directly on a semiconductor substrate such as Si, a thin film transistor (TFT) may be formed on a glass or flexible substrate, and the semiconductor layer constituting the transistor may be an organic layer. You may form with the organic transistor formed with a compound. An example in the case where the transistor 240 is an organic transistor is illustrated in FIG. A layer 270 containing an organic material is formed over the substrate 230 so as to cover a conductive layer to be a source electrode or a drain electrode, and a gate electrode 271 is formed above the layer 270 containing an organic material through a gate insulating film 272. Yes. The layer 270 including an organic material functions as a channel region of the transistor 240, and one of the conductive layers serving as a source electrode and a drain electrode functions as the first conductive layer 243 in the above structure.

  Further, although an example in which a planar thin film transistor is provided over an insulating substrate is described in this embodiment, a transistor can be formed with a staggered structure, an inverted staggered structure, or the like. (B). Further, the structure of the thin film transistor is not limited to the structure described above, and may be a single gate structure in which one channel region is formed, or a multi-gate structure such as a double gate structure in which two channel regions are formed or a triple gate structure in which three channel regions are formed Can be used. Alternatively, a dual gate type having two gate electrodes arranged above and below the channel region with an insulating film interposed therebetween may be used.

  Further, any structure of a semiconductor layer included in the transistor may be used. For example, an impurity region (including a source region, a drain region, and an LDD region) may be formed, or a p-channel type or an n-channel may be formed. You may form with either type | mold. In addition, an insulating layer (side wall) may be formed so as to be in contact with the side surface of the gate electrode, or a silicide layer may be formed in the source region, the drain region, and the gate electrode. As a material for the silicide layer, nickel, tungsten, molybdenum, cobalt, platinum, or the like can be used.

  A material and a formation method of the first conductive layer 243 and the second conductive layer 245 can be similarly performed using any of the materials and the formation method described in Embodiment Mode 1.

  In the case where data is written by an optical action, one or both of the first conductive layer 243 and the second conductive layer 245 are formed using the light-transmitting conductive material described in the above embodiment mode. Or it forms with the thickness which permeate | transmits light. In the case where data is written by an electrical action, there is no particular limitation on the material used for the first conductive layer 243 and the second conductive layer 245.

  The organic compound layer 244 can be provided using a material and a formation method similar to those of the organic compound layer described in Embodiment 1.

  Alternatively, a rectifying element may be provided between the first conductive layer 243 and the organic compound layer 244 or between the second conductive layer 245 and the organic compound layer 244. The rectifying element is typically a Schottky diode, a diode having a PN junction, a diode having a PIN junction, or a transistor in which a gate electrode and a drain electrode are connected. Of course, other configurations of diodes may be used. In this manner, by providing an element having a rectifying action, the selectivity of the memory cell can be improved and the margin of the read or write operation can be improved.

  Next, an operation when data is written to the memory circuit 216 will be described (FIG. 4).

  First, an operation when data is written by electrical action will be described. Writing is performed by changing the electrical characteristics of the memory cell. The initial state of the memory cell (the state where no electrical action is applied) is data “0”, and the state where the electrical characteristic is changed is “1”. To do.

  Here, a case where data is written to the memory cell 221 in the n-th row and the m-th column will be described. When data “1” is written to the memory cell 221, first, the memory cell 221 is selected by the row decoder 224a, the column decoder 226a, and the selector 226c via the interface 223. Specifically, a predetermined voltage V22 is applied to the word line Wn connected to the memory cell 221 by the row decoder 224a. Further, the bit line Bm connected to the memory cell 221 is connected to the read circuit 226b by the column decoder 226a and the selector 226c. Then, the write voltage V21 is output from the read circuit 226b to the bit line B3.

  Thus, the transistor 240 constituting the memory cell is turned on, the common electrode and the bit line are electrically connected to the organic memory element 241, and a voltage of approximately Vw = Vcom−V21 is applied. By appropriately selecting the potential Vw, the organic compound layer 29 provided between the conductive layers is changed physically or electrically, and data “1” is written. Specifically, at the read operation voltage, the electrical resistance between the first conductive layer and the second conductive layer in the data “1” state is significantly smaller than that in the data “0” state. It may be changed as described above, or it may be simply short-circuited. The potential may be appropriately selected from the range of (V21, V22, Vcom) = (5-15V, 5-15V, 0V), or (-12 to 0V, -12 to 0V, 3 to 5V). The voltage Vw may be 5 to 15V, or -5 to -15V. In this case, the distance between the pair of conductive layers provided with the organic compound layer interposed therebetween may change.

  Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. Specifically, a potential (for example, 0 V) for turning off the transistor of the memory cell to be connected is applied to the non-selected word line, and the non-selected bit line is in a floating state or approximately equal to Vcom. A potential may be applied.

  On the other hand, when data “0” is written in the memory cell 221, it is not necessary to apply an electrical action to the memory cell 221. In the circuit operation, for example, as in the case of writing “1”, the memory cell 221 is selected by the row decoder 224a, the column decoder 226a, and the selector 226c via the interface 223, but the read circuit 226b supplies the bit line B3 to the bit line B3. The output potential is set to the same level as Vcom or the bit line B3 is set in a floating state. As a result, since a small voltage (for example, −5 to 5 V) is applied to the organic memory element 241 or no voltage is applied, the electrical characteristics do not change and data “0” writing is realized.

  Next, a case where data is written by optical action will be described. In this case, the laser irradiation apparatus irradiates the organic compound layer 244 included in the organic memory element 241 with laser light from the light-transmitting conductive layer side (herein, the second conductive layer 245). By doing.

  By selectively irradiating the organic compound layer 244 with laser light, the organic compound layer 244 is oxidized or carbonized to be insulated. Then, the resistance value between the first conductive layer 243 and the second conductive layer 245 in the organic memory element 241 irradiated with the laser light increases, and the first conductive layer 243 in the organic memory element 241 not irradiated with the laser light. And the resistance value between the second conductive layer 245 do not change.

  Next, an operation when data is read by electrical action will be described. Data is read using the fact that the electrical characteristics of the organic memory element 241 are different between the memory cell having the data “0” and the memory cell having the data “1”. For example, the electrical resistance of the memory element constituting the memory cell having data “0” is R0 at the read voltage, and the electrical resistance of the memory element constituting the memory cell having data “1” is R1 at the read voltage. A method of reading using the difference will be described. Note that R1 << R0. As the structure of the reading circuit 226b, for example, a bit line driver circuit 226 using the resistance element 246 and the differential amplifier 247 illustrated in FIG. 4B can be considered. The resistance element has a resistance value Rr, and R1 <Rr <R0. A transistor 248 may be used instead of the resistance element 246, and a clocked inverter 249 may be used instead of the differential amplifier (FIG. 4C). Of course, the circuit configuration is not limited to FIGS. 4B and 4C.

  When reading data from the memory cell 221 in the n-th row and the m-th column, first, the memory cell 221 is selected by the row decoder 224a, the column decoder 226a, and the selector 226c via the interface 223. Specifically, the row decoder 224a applies a predetermined voltage V24 to the word line Wn connected to the memory cell 221 to turn on the transistor 240. Further, the bit line Bm connected to the memory cell 221 is connected to the terminal P of the read circuit 226b by the column decoder 226a and the selector 226c. As a result, the potential Vp of the terminal P becomes a value determined by resistance division of Vcom and V0 by the resistance element 246 (resistance value Rr) and the organic memory element 241 (resistance value R0 or R1). Therefore, when the memory cell 221 has data “0”, Vp0 = Vcom + (V0−Vcom) * R0 / (R0 + Rr). When the memory cell 221 has data “1”, Vp1 = Vcom + (V0−Vcom) * R1 / (R1 + Rr). As a result, in FIG. 4B, Vref is selected to be between Vp0 and Vp1, and in FIG. 4C, the changing point of the clocked inverter is selected to be between Vp0 and Vp1. Thus, Lo / Hi (or Hi / Lo) is output as the output potential Vout according to the data “0” / “1”, and reading can be performed.

  For example, the differential amplifier is operated at Vdd = 3V, and Vcom = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9 and the on-resistance of the transistor 240 can be ignored, when the data in the memory cell is “0”, Vp0 = 2.7V and Vout is output as Hi, When the data of “1” is “1”, Vp1 = 0.3 V and Lo is output as Vout. Thus, the memory cell can be read.

  According to the above method, the voltage value is read by utilizing the difference in resistance value and resistance division of the organic memory element 241. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. In addition, when the electrical characteristics of the memory cell have data “0” and “1” and diode characteristics with different threshold voltages, reading may be performed using the threshold voltage difference.

  Next, an example of reading data in the memory element portion by electrical action will be described with reference to FIG.

  FIG. 18 shows a current-voltage characteristic 951 of a memory element unit in which data “0” is written in the memory element unit, a current-voltage characteristic 952 of a memory element unit in which data “1” is written, and a resistance element A current-voltage characteristic 953 of H.246 is shown. Here, a case where a transistor is used as the resistance element 246 is shown. Further, a case where 3 V is applied between the first conductive layer 243 and the second conductive layer 245 as an operation voltage when reading data will be described.

  In FIG. 18, in a memory cell having a memory element portion in which data of “0” is written, an intersection 954 between the current-voltage characteristic 951 of the memory element part and the current-voltage characteristic 953 of the transistor serves as an operating point. The potential of the node α is V1 (V). The potential of the node α is supplied to the differential amplifier 247, and the data stored in the memory cell is determined as “0” in the differential amplifier 247.

  On the other hand, in a memory cell having a memory element portion in which data of “1” is written, an intersection 955 between the current-voltage characteristic 952 of the memory element part and the current-voltage characteristic 953 of the transistor serves as an operating point. The potential of α is V2 (V) (V1> V2). The potential of the node α is supplied to the differential amplifier 247, and the data stored in the memory cell is determined as “1” in the differential amplifier 247.

  As described above, the data stored in the memory cell can be determined by reading the resistance-divided potential in accordance with the resistance value of the memory element 241.

  In this embodiment mode, by forming an organic compound layer using a layer in which an organic compound and an inorganic compound are mixed, crystallization of the organic compound layer can be suppressed, and the organic compound layer does not increase in resistance. Can be formed thick. Therefore, even if there are irregularities due to dust or dirt on the substrate, the organic compound layer is hardly affected by the irregularities due to the thick film. Accordingly, it is possible to prevent defects such as a short circuit due to unevenness. Even when the organic memory is mounted on a flexible substrate, it is possible to resist physical stress such as bending by forming the memory element layer thick.

  Note that this embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 3)
In this embodiment, an example of a semiconductor device different from that in the above embodiment will be described with reference to drawings.

  The semiconductor device described in this embodiment is characterized in that data can be read and written in a non-contact manner. A data transmission format is an electromagnetic which performs communication by mutual induction with a pair of coils arranged opposite to each other. There are roughly divided into a coupling system, an electromagnetic induction system that communicates using an induction electromagnetic field, and a radio system that communicates using radio waves, but any system may be used. In addition, there are two types of antennas used for data transmission. When one antenna is provided on a substrate provided with a plurality of elements and organic memory elements, the other is a plurality of elements and organic memory elements. In some cases, a terminal portion is provided on a substrate provided with a terminal portion, and an antenna provided on another substrate is connected to the terminal portion.

  First, a structure example of a semiconductor device in the case where an antenna is provided over a substrate provided with a plurality of elements and organic memory elements will be described with reference to FIGS.

  FIG. 6A illustrates a semiconductor device having an organic memory element formed of a passive matrix type, in which an element formation layer 351 including a transistor 451 is provided over a substrate 350 and a memory element is provided above the element formation layer 351. A portion 352 and an antenna portion 353 are provided. Note that here, the case where the memory element portion 352 or the antenna portion 353 is provided above the element formation layer 351 is shown; however, the present invention is not limited to this structure, and the memory element portion 352 or the antenna portion 353 is disposed below the element formation layer 351. Or in the same layer.

  Each of the plurality of organic memory elements included in the memory element portion 352 is provided by stacking a first conductive layer 361, an organic compound layer 362, and a second conductive layer 363, and covers the second conductive layer 363. An insulating layer 366 that functions as a protective film is formed. The organic compound layer 362 may be formed over the entire surface so as to cover the first conductive layer 361. However, if there is a concern about the influence of the electric field in the lateral direction in adjacent memory cells, the organic compound layer 362 may An insulating layer 364 for separating the compound layer may be provided. Note that the memory element portion 352 can be formed using the material or the manufacturing method described in the above embodiment modes.

  Further, in the memory element portion 352, as shown in the above embodiment mode, rectification is performed between the first conductive layer 361 and the organic compound layer 362 or between the organic compound layer 362 and the second conductive layer 363. A device having a property may be provided. The above-described elements having a rectifying property can also be used.

  The antenna portion 353 is provided with a conductive layer 355 that functions as an antenna. The conductive layer 355 functioning as an antenna is connected to a transistor that forms a waveform shaping circuit or a rectifier circuit. In addition, data sent from the outside in a non-contact manner is shaped by a waveform shaping circuit or a rectifier circuit, and then exchanged with an organic memory element (data writing or reading) through a reading circuit or a writing circuit. . Here, the conductive layer 355 is provided in the same layer as the first conductive layer 361, and the conductive layer 355 and the first conductive layer 361 may be formed using the same material. The conductive layer 355 may be formed over the insulating layer 364 or the insulating layer 366. In the case where the insulating layer 364 is provided over the insulating layer 364, the second conductive layer 363 can be formed using the same material.

  As a material of the conductive layer 355, gold (Au), platinum (Pt), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), aluminum (Al), manganese ( A kind of element selected from Mn), titanium (Ti) or the like, or an alloy containing a plurality of such elements can be used. As a method for forming the conductive layer 355, vapor deposition, a sputtering method, a CVD method, various printing methods such as screen printing or gravure printing, a droplet discharge method, or the like can be used.

  The transistor 451 included in the element formation layer 351 can be a p-channel TFT, an n-channel TFT, or a CMOS circuit in which these are combined. In addition, any structure of a semiconductor layer included in the transistor 451 may be used. For example, an impurity region (including a source region, a drain region, and an LDD region) may be formed, or a p-channel type or n-type may be used. Either channel type may be used. In addition, an insulating layer (side wall) may be formed so as to be in contact with the side surface of the gate electrode, or a silicide layer may be formed in the source region, the drain region, and the gate electrode. As a material for the silicide layer, nickel, tungsten, molybdenum, cobalt, platinum, or the like can be used.

  Alternatively, the transistor 451 included in the element formation layer 351 may be an organic transistor in which a semiconductor layer included in the transistor is formed using an organic compound. In this case, the element formation layer 351 including an organic transistor can be formed using a direct printing method, a droplet discharge method, or the like over a flexible substrate such as a plastic as the substrate 350. At this time, as described above, the memory element portion 352 is formed using a printing method, a droplet discharge method, or the like, whereby a semiconductor device can be manufactured at lower cost.

  FIG. 6B illustrates an example of a semiconductor device including an active matrix organic memory. Note that FIG. 6B will be described with respect to portions different from those in FIG.

  In the semiconductor device illustrated in FIG. 6B, an element formation layer 351 including transistors 451 and 354 is provided over a substrate 350, and a memory element portion 356 and an antenna portion 353 are provided above the element formation layer 351. Note that here, the transistor 354 functioning as a switching element of the memory element portion 356 is provided in the same layer as the transistor 451, and the memory element portion 356 and the antenna portion 353 are provided above the element formation layer 351. The transistor 354 may be provided above or below the element formation layer 351 without being limited to this structure, and the memory element portion 356 and the antenna portion 353 may be provided below the element formation layer 351 or in the same layer. is there.

  The memory element portion 356 is provided by stacking a first conductive layer 371, an organic compound layer 372, and a second conductive layer 373, and an insulating layer 376 is provided as a protective film so as to cover the second conductive layer 373. Is formed. Here, the insulating layer 374 is formed so as to cover the end portion of the first conductive layer 371, and the organic compound layer 372 is selectively formed in each memory cell, but the first conductive layer 371 and You may form in the whole surface so that the insulating layer 374 may be covered. Note that the memory element portion 356 can be formed using the material or the manufacturing method described in the above embodiment modes. In the memory element portion 356, as described above, a rectifying element is provided between the first conductive layer 371 and the organic compound layer 372 or between the organic compound layer 372 and the second conductive layer 373. May be provided.

  The conductive layer 355 provided in the antenna portion 353 may be formed in the same layer as the first conductive layer 371 or may be formed over the insulating layer 374 or the insulating layer 376. In the case where the conductive layer 355 is provided in the same layer as the first conductive layer 371 or the second conductive layer 373, they are formed together using the same material as the first conductive layer 371 or the second conductive layer 373, respectively. You can also.

  The transistor 354 provided in the element formation layer 351 functions as a switching element when data is written to or read from the memory element portion 356. Therefore, the transistor 354 is preferably provided using either a p-channel TFT or an n-channel TFT. The semiconductor layer included in the transistor 354 may have any structure, for example, an impurity region (including a source region, a drain region, and an LDD region) may be formed, or a p-channel type or an n-channel type You may form with either type | mold. In addition, an insulating layer (side wall) may be formed so as to be in contact with the side surface of the gate electrode, or a silicide layer may be formed in the source region, the drain region, and the gate electrode. As a material for the silicide layer, nickel, tungsten, molybdenum, cobalt, platinum, or the like can be used.

  Further, as described above, the element formation layer 351, the memory element portion 356, and the antenna portion 353 can be formed by vapor deposition, a sputtering method, a CVD method, a printing method, a droplet discharge method, or the like. Note that a different method may be used depending on each place. For example, the transistor 451 that requires high-speed operation is provided by forming a semiconductor layer made of Si or the like over a substrate and then crystallizing it by heat treatment. After that, a transistor 354 that functions as a switching element is provided above the element formation layer 351. An organic transistor can be provided by a printing method or a droplet discharge method.

  Note that the memory element portion 356 illustrated in FIG. 6B has a structure in which the first conductive layer 371 is connected to the source or drain electrode of the transistor in the element formation layer 351 through an insulating layer as illustrated in FIG. Of course, as shown in FIGS. 5B and 5C, the transistor can be formed in the same layer as the source or drain electrode of the transistor.

  Next, a structure example of a semiconductor device in which a terminal portion is provided over a substrate provided with a plurality of elements and memory elements and an antenna provided over another terminal is connected to the terminal portion is described with reference to FIGS. I will explain. 7 will be described with respect to portions different from FIG.

  FIG. 7A illustrates a semiconductor device having a passive matrix organic memory, in which an element formation layer 351 is provided over a substrate 350, a memory element portion 352 is provided above the element formation layer 351, and a substrate 365 is formed. The antenna portion 357 provided in the is connected to the element formation layer. Note that here, the case where the memory element portion 352 or the antenna portion 353 is provided above the element formation layer 351 is shown; however, the present invention is not limited to this structure, and the memory element portion 352 is provided below the element formation layer 351 or in the same layer. Alternatively, the antenna portion 353 can be provided below the element formation layer 351.

  The memory element portion 352 is provided by stacking a first conductive layer 361, an organic compound layer 362, and a second conductive layer 363. Further, when there is a concern about the step of the organic compound layer 362 or the influence of the electric field in the lateral direction in adjacent memory cells, the organic compound layer is separated for each memory cell as shown in FIG. An insulating layer may be provided. Note that the memory element portion 352 can be formed using the material or the manufacturing method described in the above embodiment modes.

  Further, the substrate including the element formation layer 351 and the memory element portion 352 and the substrate 365 provided with the antenna portion 357 are attached to each other with a resin 375 having adhesiveness. The element formation layer 351 and the conductive layer 358 are electrically connected through conductive fine particles 359 included in the resin 375. Further, a conductive adhesive such as a silver paste, a copper paste, or a carbon paste, or a method of performing solder bonding, a substrate including an element formation layer 351 and a memory element portion 352, and a substrate 365 provided with an antenna portion 357 are provided. You may stick together.

  FIG. 7B illustrates a semiconductor device in which the organic memory described in Embodiment 2 is provided. An element formation layer 351 including transistors 451 and 354 is provided over a substrate 350, and the element formation layer 351 is provided above the element formation layer 351. The memory element portion 352 is provided, and the antenna portion 357 provided on the substrate 365 is provided so as to be connected to the element formation layer. Note that here, a case where the transistor 354 is provided in the same layer as the transistor 451 in the element formation layer 351 and the antenna portion 353 is provided above the element formation layer 351 is shown; however, the present invention is not limited to this structure, and the memory element portion 352 is provided. Can be provided below the element formation layer 351 or in the same layer, or the antenna portion 353 can be provided below the element formation layer 351.

  The memory element portion 356 is provided by stacking a first conductive layer 371, an organic compound layer 372, and a second conductive layer 373. In the case where there is a concern about the influence of the electric field in the horizontal direction in adjacent memory cells, an insulating layer may be provided to separate adjacent organic compound layers as shown in FIG. Note that the memory element portion 356 can be formed using the material or the manufacturing method described in the above embodiment modes.

  7B, the substrate including the element formation layer 351 and the memory element portion 356 and the substrate provided with the antenna portion 357 can be provided by bonding with a resin 375 including conductive fine particles 359. .

  Thus, a semiconductor device including an organic memory and an antenna can be formed. In this embodiment mode, a thin film transistor can be formed over the substrate 350 to provide an element formation layer, or a semiconductor substrate such as Si is used as the substrate 350, and a field effect transistor (FET) is formed over the substrate. By doing so, an element formation layer may be provided. Alternatively, an SOI substrate may be used as the substrate 350 and an element formation layer may be provided thereover. In this case, the SOI substrate may be formed by using a method of bonding wafers or a method called SIMOX in which an insulating layer is formed inside by implanting oxygen ions into the Si substrate.

  In the semiconductor device including the organic memory described in this embodiment mode, the memory element portion of the organic memory is formed using a layer in which an organic compound and an inorganic compound are mixed. Therefore, the layer is formed thick without increasing resistance. can do. Therefore, even when the semiconductor device is provided over a flexible substrate, physical forces such as bending can be resisted. Therefore, even if there are irregularities due to dust or dirt on the substrate, the organic compound layer is hardly affected by the irregularities due to the thick film. Accordingly, it is possible to prevent defects such as a short circuit of the memory cell due to the unevenness.

Note that this embodiment can be freely combined with the above embodiment.
(Embodiment 4)
In this embodiment, a method for manufacturing a semiconductor device of the present invention including a thin film transistor, a memory element, and an antenna will be described with reference to drawings.

  First, the separation layer 702 is formed over one surface of the substrate 701 (FIG. 12A). As the substrate 701, a glass substrate, a quartz substrate, a metal substrate, a stainless steel substrate with an insulating layer formed on one surface, a heat-resistant plastic substrate that can withstand the processing temperature in this step, or the like may be used. With such a substrate 701, there is no significant limitation on the area and shape thereof. For example, if the substrate 701 is a rectangular substrate having a side of 1 meter or more and a rectangular shape, productivity is remarkably improved. Can be made. Such an advantage is a great advantage compared to the case of using a circular silicon substrate. Note that in this step, the separation layer 702 is provided over the entire surface of the substrate 701. However, if necessary, after the separation layer is provided over the entire surface of the substrate 701, the separation layer 702 is selectively etched by photolithography. It may be provided. In addition, although the separation layer 702 is formed so as to be in contact with the substrate 701, an insulating layer serving as a base is formed so as to be in contact with the substrate 701 as necessary, and the separation layer 702 is formed so as to be in contact with the insulation layer. May be.

  The separation layer 702 is formed by sputtering, plasma CVD, or the like using tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium. An element selected from (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), lead (Pb), osmium (Os), iridium (Ir), silicon (Si) or the element as a main component A layer made of an alloy material or a compound material is formed as a single layer or a stacked layer. The crystal structure of the layer containing silicon may be any of amorphous, microcrystalline, and polycrystalline.

  In the case where the separation layer 702 has a single-layer structure, for example, a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum is formed. Alternatively, a layer containing tungsten oxide or oxynitride, a layer containing molybdenum oxide or oxynitride, or a layer containing oxide or oxynitride of a mixture of tungsten and molybdenum is formed. Note that the mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum. The oxide of tungsten may be expressed as tungsten oxide.

  In the case where the separation layer 702 has a stacked structure, a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum is formed as a first layer, and an oxide or nitride of tungsten, molybdenum, or a mixture of tungsten and molybdenum is formed as a second layer Forming an oxide, oxynitride or nitride oxide.

Note that in the case where a stacked structure of a layer containing tungsten and a layer containing an oxide of tungsten is formed as the separation layer 702, a layer containing tungsten is formed, and a layer containing silicon oxide is formed thereover. The fact that a layer containing an oxide of tungsten is formed at the interface between the layer and the silicon oxide layer may be utilized. The same applies to the case where a layer containing tungsten nitride, oxynitride, and nitride oxide is formed. After forming a layer containing tungsten, a silicon nitride layer, a silicon oxynitride layer, and a silicon nitride oxide layer are formed thereon. A layer may be formed. The oxide of tungsten is represented by WOx, X is 2 to 3, X is 2 (WO ₂ ), X is 2.5 (W ₂ O ₅ ), and X is 2.75. (W ₄ O ₁₁ ) and X is 3 (WO ₃ ). In forming the tungsten oxide, there is no particular limitation on the value of X mentioned above, and it is preferable to determine which oxide is formed based on the etching rate or the like. Note that the best etching rate is a layer containing tungsten oxide (WOx, 0 <X <3) formed by a sputtering method in an oxygen atmosphere. Therefore, in order to shorten the manufacturing time, a layer containing a tungsten oxide is preferably formed as the separation layer by a sputtering method in an oxygen atmosphere.

  Next, an insulating layer 703 serving as a base is formed so as to cover the separation layer 702. The insulating layer 703 is formed as a single layer or a stacked layer including a silicon oxide or a silicon nitride by a sputtering method, a plasma CVD method, or the like. The silicon oxide material is a substance containing silicon (Si) and oxygen (O), and corresponds to silicon oxide, silicon oxynitride, silicon nitride oxide, or the like. The silicon nitride material is a substance containing silicon and nitrogen (N), and corresponds to silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. In the case where the insulating layer serving as a base has a two-layer structure, for example, a silicon nitride oxide layer may be formed as the first layer and a silicon oxynitride layer may be formed as the second layer. When the underlying insulating layer has a three-layer structure, a silicon oxide layer is formed as the first insulating layer, a silicon nitride oxide layer is formed as the second insulating layer, and oxynitriding is performed as the third insulating layer A silicon layer may be formed. Alternatively, a silicon oxynitride layer may be formed as the first insulating layer, a silicon nitride oxide layer may be formed as the second insulating layer, and a silicon oxynitride layer may be formed as the third insulating layer. The insulating layer serving as a base functions as a blocking film that prevents impurities from entering from the substrate 701.

  Next, an amorphous semiconductor layer 704 (eg, a layer containing amorphous silicon) is formed over the insulating layer 703. The amorphous semiconductor layer 704 is formed with a thickness of 25 to 200 nm (preferably 30 to 150 nm) by a sputtering method, an LPCVD method, a plasma CVD method, or the like. Subsequently, the amorphous semiconductor layer 704 is subjected to a known crystallization method (laser crystallization method, thermal crystallization method using an RTA or furnace annealing furnace, thermal crystallization method using a metal element that promotes crystallization, crystallization A crystalline semiconductor layer is formed by crystallization by a combination of a thermal crystallization method using a promoting metal element and a laser crystallization method). After that, the obtained crystalline semiconductor layer is etched into a desired shape to form crystalline semiconductor layers 706 to 710 (FIG. 12B).

An example of a manufacturing process of the crystalline semiconductor layers 706 to 710 will be briefly described below. First, an amorphous semiconductor layer having a thickness of 66 nm is formed using a plasma CVD method. Next, after a solution containing nickel, which is a metal element for promoting crystallization, is held on the amorphous semiconductor layer, the amorphous semiconductor layer is subjected to dehydrogenation treatment (500 ° C., 1 hour), heat Crystallization treatment (550 ° C., 4 hours) is performed to form a crystalline semiconductor layer. Thereafter, laser light is irradiated as necessary, and crystalline semiconductor layers 706 to 710 are formed by a photolithography method. In the case of forming a crystalline semiconductor layer by a laser crystallization method, a continuous wave or pulsed gas laser or solid state laser is used. As the gas laser, excimer laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, Ti: sapphire laser, or the like is used. As the solid-state laser, a laser using a crystal such as YAG, YVO ₄ , YLF, or YAlO ₃ doped with Cr, Nd, Er, Ho, Ce, Co, Ti, or Tm is used.

  In addition, when an amorphous semiconductor layer is crystallized using a metal element that promotes crystallization, it is possible to crystallize at a low temperature for a short time and the crystal orientation is aligned. Remains in the crystalline semiconductor layer, resulting in an increase in off-current and unstable characteristics. Therefore, an amorphous semiconductor layer functioning as a gettering site is preferably formed over the crystalline semiconductor layer. Since the amorphous semiconductor layer serving as a gettering site needs to contain an impurity element such as phosphorus or argon, it is preferably formed by a sputtering method in which argon can be contained at a high concentration. After that, heat treatment (RTA method or thermal annealing using a furnace annealing furnace) is performed to diffuse the metal element in the amorphous semiconductor layer, and then the amorphous semiconductor layer containing the metal element is removed. To do. Then, the content of the metal element in the crystalline semiconductor layer can be reduced or removed.

  Next, a gate insulating layer 705 is formed to cover the crystalline semiconductor layers 706 to 710. The gate insulating layer 705 is formed by a single layer or a stack of layers containing silicon oxide or silicon nitride by a plasma CVD method, a sputtering method, or the like. Specifically, a layer containing silicon oxide, a layer containing silicon oxynitride, or a layer containing silicon nitride oxide is formed as a single layer or a stacked layer.

  Next, a first conductive layer and a second conductive layer are stacked over the gate insulating layer 705. The first conductive layer is formed with a thickness of 20 to 100 nm by a plasma CVD method, a sputtering method, or the like. The second conductive layer is formed with a thickness of 100 to 400 nm by a plasma CVD method, a sputtering method, or the like. The first conductive layer and the second conductive layer include tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium ( Nb) or the like or an alloy material or a compound material containing these elements as a main component. Alternatively, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus is used. Examples of the combination of the first conductive layer and the second conductive layer include a tantalum nitride layer and a tungsten layer, a tungsten nitride layer and a tungsten layer, a molybdenum nitride layer and a molybdenum layer, and the like. Since tungsten and tantalum nitride have high heat resistance, heat treatment for thermal activation can be performed after the formation of the first conductive layer and the second conductive layer. In the case of a three-layer structure instead of a two-layer structure, a stacked structure of a molybdenum layer, an aluminum layer, and a molybdenum layer may be employed.

  Next, a resist mask is formed by photolithography, and an etching process is performed to form a gate electrode and a gate line, so that a conductive layer functioning as a gate electrode (sometimes referred to as a gate electrode layer) 716 to 725 are formed.

  Next, a resist mask is formed by photolithography, and an impurity element imparting N-type is added to the crystalline semiconductor layers 706 and 708 to 710 at a low concentration by ion doping or ion implantation. N-type impurity regions 711 and 713 to 715 and channel regions 780 and 782 to 784 are formed. The impurity element imparting N-type may be an element belonging to Group 15, for example, phosphorus (P) or arsenic (As).

  Next, a resist mask is formed by photolithography, and an impurity element imparting P-type conductivity is added to the crystalline semiconductor layer 707, so that a P-type impurity region 712 and a channel region 781 are formed. For example, boron (B) is used as the impurity element imparting P-type.

  Next, an insulating layer is formed so as to cover the gate insulating layer 705 and the conductive layers 716 to 725. The insulating layer is formed by a single layer or a stack of layers including an inorganic material such as silicon, silicon oxide, or silicon nitride, or an organic material such as an organic resin, by plasma CVD or sputtering. To do. Next, the insulating layer is selectively etched by anisotropic etching mainly in the vertical direction to form insulating layers (also referred to as sidewalls) 739 to 743 that are in contact with the side surfaces of the conductive layers 716 to 725 (see FIG. 12 (C)). At the same time as the formation of the insulating layers 739 to 743, insulating layers 734 to 738 obtained by etching the insulating layer 705 are formed. The insulating layers 739 to 743 are used as a mask for doping when an LDD (Lightly Doped Drain) region is formed later.

  Next, an impurity element imparting N-type conductivity is added to the crystalline semiconductor layers 706 and 708 to 710 using a resist mask formed by a photolithography method and the insulating layers 739 to 743 as masks. N-type impurity regions (also referred to as LDD regions) 727, 729, 731 and 733, and second N-type impurity regions 726, 728, 730 and 732 are formed. The concentration of the impurity element contained in the first N-type impurity regions 727, 729, 731, and 733 is lower than the concentration of the impurity element in the second N-type impurity regions 726, 728, 730, and 732. Through the above steps, N-type thin film transistors 744 and 746 to 748 and a P-type thin film transistor 745 are completed.

  Note that when forming the LDD region, an insulating layer of a sidewall is preferably used as a mask. The technique using the sidewall insulating layer as a mask makes it easy to control the width of the LDD region, and the LDD region can be reliably formed.

  Next, an insulating layer is formed as a single layer or a stacked layer so as to cover the thin film transistors 744 to 748 (FIG. 13A). An insulating layer covering the thin film transistors 744 to 748 is formed by an SOG (Spin on Glass) method, a droplet discharge method, or the like, an inorganic material such as silicon oxide or silicon nitride, polyimide, polyamide, benzocyclobutene, acrylic, epoxy It is formed of a single layer or a laminated layer using an organic material such as siloxane. Note that the siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. For example, when the insulating layer covering the thin film transistors 744 to 748 has a three-layer structure, a layer containing silicon oxide is formed as the first insulating layer 749, and a layer containing resin is formed as the second insulating layer 750, A layer containing silicon nitride is preferably formed as the third insulating layer 751.

  Note that before the insulating layers 749 to 751 are formed or after one or more thin films of the insulating layers 749 to 751 are formed, the crystallinity of the semiconductor layer is restored and the activity of the impurity element added to the semiconductor layer is increased. Heat treatment for the purpose of hydrogenation of the semiconductor layer is preferably performed. For the heat treatment, thermal annealing, laser annealing, RTA, or the like is preferably applied.

  Next, the insulating layers 749 to 751 are etched by photolithography to form contact holes that expose the N-type impurity regions 726 and 728 to 732 and the P-type impurity region 785. Subsequently, a conductive layer is formed so as to fill the contact hole, and the conductive layer is patterned to form conductive layers 752 to 761 functioning as a source wiring and a drain wiring.

  The conductive layers 752 to 761 are formed of an element selected from titanium (Ti), aluminum (Al), and neodymium (Nd) by a plasma CVD method, a sputtering method, or the like, or an alloy material or a compound material containing these elements as a main component Thus, a single layer or a stacked layer is formed. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. The conductive layers 752 to 761 include, for example, a stacked structure of a barrier layer, an aluminum silicon (Al—Si) layer, and a barrier layer, and a stacked structure of a barrier layer, an aluminum silicon (Al—Si) layer, a titanium nitride (TiN) layer, and a barrier layer. A structure should be adopted. Note that the barrier layer corresponds to a thin film formed of titanium, a nitride of titanium, molybdenum, or a nitride of molybdenum. Aluminum and aluminum silicon are optimal materials for forming the conductive layers 752 to 761 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier layer made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor layer, the natural oxide film is reduced, and the crystalline semiconductor layer is excellent. Contact can be made.

  Next, an insulating layer 762 is formed so as to cover the conductive layers 752 to 761 (FIG. 13B). The insulating layer 762 is formed as a single layer or a stacked layer using an inorganic material or an organic material by an SOG method, a droplet discharge method, or the like. The insulating layer 762 is preferably formed with a thickness of 0.75 to 3 μm.

  Subsequently, the insulating layer 762 is etched by photolithography to form contact holes that expose the conductive layers 757, 759, and 761. Subsequently, a conductive layer is formed so as to fill the contact hole. The conductive layer is formed using a conductive material by a plasma CVD method, a sputtering method, or the like. Next, the conductive layer is patterned to form conductive layers 763 to 765. Note that the conductive layers 763 to 765 are one of a pair of conductive layers included in the memory element. Therefore, the conductive layers 763 to 765 are preferably formed as a single layer or a stacked layer using titanium, or an alloy material or compound material containing titanium as a main component. Since titanium has a low resistance value, it leads to a reduction in the size of the memory element, and high integration can be realized. In the photolithography process for forming the conductive layers 763 to 765, wet etching may be performed so that the thin film transistors 744 to 748 are not damaged, and the etching agent is hydrogen fluoride (HF). Alternatively, ammonia overwater may be used.

  Next, an insulating layer 766 is formed so as to cover the conductive layers 763 to 765. The insulating layer 766 is formed as a single layer or a stack using an inorganic material or an organic material by an SOG method, a droplet discharge method, or the like. The insulating layer 762 is preferably formed with a thickness of 0.75 to 3 μm. Subsequently, the insulating layer 766 is etched by photolithography to form contact holes 767 to 769 that expose the conductive layers 763 to 765.

  Next, a conductive layer 786 functioning as an antenna is formed in contact with the conductive layer 765 (FIG. 14A). The conductive layer 786 is formed using a conductive material by a plasma CVD method, a sputtering method, a printing method, a droplet discharge method, or the like. Preferably, the conductive layer 786 is an element selected from aluminum (Al), titanium (Ti), silver (Ag), and copper (Cu), or an alloy material or a compound material containing these elements as a main component. It is formed by layer or lamination. Specifically, the conductive layer 786 is formed by screen printing, for example, using a conductive paste containing silver, and then heat-treated at 50 to 350 degrees. Alternatively, an aluminum layer is formed by a sputtering method, and the aluminum layer is formed by patterning. For the pattern processing of the aluminum layer, wet etching processing may be used, and after the wet etching processing, heat treatment at 200 to 300 degrees may be performed.

  Next, an organic compound layer 787 is formed so as to be in contact with the conductive layers 763 and 764 (FIG. 14B). The organic compound layer 787 is formed by a droplet discharge method, an evaporation method, or the like. Subsequently, a conductive layer 771 is formed so as to be in contact with the organic compound layer 787. The conductive layer 771 is formed by a sputtering method, an evaporation method, or the like.

  Through the above steps, a memory element portion 789 including a stack of the conductive layer 763, the organic compound layer 787, and the conductive layer 771, and a memory element portion 790 including a stack of the conductive layer 764, the organic compound layer 787, and the conductive layer 771. Is completed.

  Note that the above-described manufacturing step is characterized in that the organic compound layer 787 is formed after the step of forming the conductive layer 786 functioning as an antenna because the heat resistance of the organic compound layer 787 is not strong.

  Next, an insulating layer 772 functioning as a protective layer is formed by an SOG method, a screen printing method, a droplet discharge method, or the like so as to cover the memory element portions 789 and 790 and the conductive layer 786 functioning as an antenna. The insulating layer 772 is formed of a layer containing carbon such as DLC (diamond-like carbon), a layer containing silicon nitride, a layer containing silicon nitride oxide, or an organic material, and preferably formed of an epoxy resin.

  Next, the insulating layer is etched by photolithography so that the separation layer 702 is exposed, so that openings 773 and 774 are formed (FIG. 15A).

Next, an etchant is introduced into the openings 773 and 774 to remove the peeling layer 702 (FIG. 15B). As the etchant, a gas or liquid containing halogen fluoride or an interhalogen compound is used. For example, chlorine trifluoride (ClF ₃ ) is used as a gas containing halogen fluoride. Then, the thin film integrated circuit 791 is peeled from the substrate 701. Note that the thin film integrated circuit 791 includes the thin film transistors 744 to 748, the element groups of the memory element portions 789 and 790, and the conductive layer 786 functioning as an antenna. Note that the peeling layer 702 may not be completely removed but may partially remain. By doing so, the processing time can be shortened.

  The substrate 701 from which the thin film integrated circuit 791 is peeled is preferably reused for cost reduction. The insulating layer 772 is formed so that the thin film integrated circuit 791 is not scattered after the peeling layer 702 is removed. Since the thin film integrated circuit 791 is small and thin, the thin film integrated circuit 791 is likely to be scattered after being removed from the substrate 701 after the peeling layer 702 is removed. However, by forming the insulating layer 772 over the thin film integrated circuit 791, the thin film integrated circuit 791 is weighted and scattering from the substrate 701 can be prevented. In addition, although the thin film integrated circuit 791 is thin and light, the insulating layer 772 is formed, so that a certain shape of strength can be secured without forming a wound shape.

  Next, one surface of the thin film integrated circuit 791 is adhered to the first base body 776 and completely peeled from the substrate 701 (FIG. 16). Subsequently, the other surface of the thin film integrated circuit 791 is bonded to the second substrate 775, and then one or both of heat treatment and pressure treatment are performed, so that the thin film integrated circuit 791 is bonded to the first substrate 776 and the first substrate 776. Sealing with the second substrate 775 is performed. The first substrate 776 and the second substrate 775 are a film made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, a paper made of a fibrous material, a base film (polyester, polyamide, inorganic vapor deposition film, Paper) and an adhesive synthetic resin film (acrylic synthetic resin, epoxy synthetic resin, etc.). The film is subjected to heat treatment and pressure treatment by thermocompression bonding. When the heat treatment and pressure treatment are performed, the film is either an adhesive layer provided on the outermost surface of the film or the A layer (not an adhesive layer) provided in the outer layer is melted by heat treatment and bonded by pressure. In addition, an adhesive layer may be provided on the surfaces of the first base body 776 and the second base body 775, or the adhesive layer may not be provided. The adhesive layer corresponds to a layer containing an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, or a resin additive.

  Through the above steps, a flexible semiconductor device can be manufactured.

Note that this embodiment mode can be freely combined with the above embodiment modes.
(Embodiment 5)
In this embodiment, the case where the semiconductor device of the present invention is used as a wireless chip capable of transmitting and receiving data without contact will be described with reference to FIGS.

  The wireless chip 20 has a function of communicating data without contact, and includes a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, a control circuit 14 for controlling other circuits, an interface circuit 15, and a storage circuit 16. And a data bus 17 and an antenna (antenna coil) 18 (FIG. 8A).

  The power supply circuit 11 is a circuit that generates various power supplies to be supplied to each circuit inside the semiconductor device based on the AC signal input from the antenna 18. The clock generation circuit 12 is a circuit that generates various clock signals to be supplied to each circuit in the semiconductor device based on the AC signal input from the antenna 18. The data demodulation / modulation circuit 13 has a function of demodulating / modulating data communicated with the reader / writer 19. The control circuit 14 has a function of controlling the memory circuit 16. The antenna 18 has a function of transmitting and receiving an electromagnetic field or a radio wave. The reader / writer 19 controls communication and control with the semiconductor device and processing related to the data.

  Further, the memory circuit 16 is formed by any structure of the organic memory shown in the above embodiment. Note that the wireless chip is not limited to the above-described configuration, and may be a configuration in which other elements such as a power supply voltage limiter circuit and cryptographic processing dedicated hardware are added.

  In addition, the wireless chip may be of a type in which power supply voltage is supplied to each circuit by radio waves without mounting a power supply (battery), or power supply (battery) is supplied to each circuit instead of an antenna. It may be a type that is mounted, or may be a type that supplies a power supply voltage by radio waves and a power source.

  When the semiconductor device of the present invention is used for a wireless chip or the like, the point of performing contactless communication, the point that multiple reading is possible, the point that data can be written, the point that it can be processed into various shapes, selection Depending on the frequency to be used, there are advantages such as wide directivity and wide recognition range. Wireless chips can be used for IC tags that can identify individual information about people and things by wireless communication without contact, labels that can be attached to target objects by label processing, wristbands for events and amusements, etc. Can be applied. Further, the wireless chip may be molded using a resin material, or may be directly fixed to a metal that hinders wireless communication. Furthermore, the wireless chip can be used for system operations such as an entrance / exit management system and a payment system.

  Next, one mode when the semiconductor device is actually used as a wireless chip will be described. A reader / writer 320 is provided on the side surface of the portable terminal including the display portion 321, and a wireless chip 323 is provided on the side surface of the article 322 (FIG. 8B). When the reader / writer 320 is held over the wireless chip 323 included in the product 322, the display unit 321 displays information about the product, such as a description of the product, such as the raw material and origin of the product, the inspection result for each production process, and the history of the distribution process. The In addition, when the product 326 is conveyed by a belt conveyor, the product 326 can be inspected using the reader / writer 324 and the wireless chip 325 provided in the product 326 (FIG. 8C). In this manner, by using a wireless chip in the system, information can be easily acquired, and high functionality and high added value are realized.

Note that this embodiment can be freely combined with the above embodiment.
(Embodiment 6)
The semiconductor device of the present invention has a wide range of uses, but can be used, for example, in electronic devices that store and display information. As an electronic device, for example, it can be used for a television receiver, a computer, a portable information terminal such as a mobile phone, a digital camera, a video camera, a navigation system, and the like. A case where the semiconductor device of the present invention is applied to a cellular phone will be described with reference to FIG.

  The cellular phone includes housings 2700 and 2706, a panel 2701, a housing 2702, a printed wiring board 2703, operation buttons 2704, and a battery 2705. The panel 2701 is detachably incorporated in the housing 2702, and the housing 2702 is fitted on the printed wiring board 2703. The shape and dimensions of the housing 2702 are changed as appropriate in accordance with the electronic device in which the panel 2701 is incorporated. A plurality of packaged semiconductor devices are mounted on the printed wiring board 2703, and the semiconductor device of the present invention can be used as one of them. The plurality of semiconductor devices mounted on the printed wiring board 2703 have any one function of a controller, a central processing unit (CPU), a memory, a power supply circuit, a sound processing circuit, a transmission / reception circuit, and the like.

  The panel 2701 is connected to the printed wiring board 2703 through the connection film 2708. The panel 2701, the housing 2702, and the printed wiring board 2703 are housed in the housings 2700 and 2706 together with the operation buttons 2704 and the battery 2705. A pixel region 2709 included in the panel 2701 is arranged so as to be visible from an opening window provided in the housing 2700.

  The semiconductor device of the present invention is characterized in that it is small, thin, and lightweight. With the above characteristics, a limited space inside the housings 2700 and 2706 of the electronic device can be used effectively. In addition, the semiconductor device of the present invention is characterized by having a memory circuit with a simple structure, and by the above characteristics, an electronic device using the semiconductor device having a memory circuit highly integrated is provided at low cost. Can do. Furthermore, the semiconductor device of the present invention is characterized in that it has a nonvolatile memory circuit that can be additionally written, and an electronic device that realizes high functionality and high added value by the above characteristics. Can do.

  The semiconductor device of the present invention can also be used as a wireless chip. For example, banknotes, coins, securities, certificates, bearer bonds, packaging containers, books, recording media, personal belongings, vehicles It can be used in foods, clothing, health supplies, daily necessities, medicines, electronic devices and the like. These examples will be described with reference to FIG.

  Banknotes and coins are money that circulates in the market, and include those that are used in the same way as money in a specific area (cash vouchers), commemorative coins, and the like. Securities refer to checks, securities, promissory notes, etc. (see FIG. 10A). The certificate refers to a driver's license, a resident's card, etc. (see FIG. 10B). Bearer bonds refer to stamps, gift tickets, various gift certificates, and the like (see FIG. 10C). Packaging containers refer to wrapping paper for lunch boxes, plastic bottles, and the like (see FIG. 10D). Books refer to books, books, and the like (see FIG. 10E). The recording media refer to DVD software, video tapes, and the like (see FIG. 10F). The vehicles refer to vehicles such as bicycles, ships, and the like (see FIG. 10G). Personal belongings refer to bags, glasses, and the like (see FIG. 10H). Foods refer to food products, beverages, and the like. Clothing refers to clothing, footwear, and the like. Health supplies refer to medical equipment, health equipment, and the like. Livingware refers to furniture, lighting equipment, and the like. Chemicals refer to pharmaceuticals, agricultural chemicals, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (TV receivers, flat-screen TV receivers), mobile phones, and the like.

  Forgery can be prevented by providing wireless chips on bills, coins, securities, certificates, bearer bonds, and the like. In addition, by providing wireless chips in personal items such as packaging containers, books, recording media, personal items, foods, daily necessities, electronic devices, etc., the efficiency of inspection systems and rental store systems can be improved. it can. By providing wireless chips for vehicles, health supplies, medicines, etc., counterfeiting and theft can be prevented, and medicines can prevent mistakes in taking medicines. As a method of providing the wireless chip, the wireless chip is provided on the surface of the article or embedded in the article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in the organic resin. Further, when writing (additional writing) is performed by applying an optical action later, it is preferable to form the transparent element so that light can be applied to the portion of the memory element provided on the chip. Furthermore, forgery can be effectively prevented by using a memory element in which data once written cannot be rewritten. In addition, problems such as privacy after a user purchases a product can be solved by providing a system for erasing data in a storage element provided in the wireless chip.

  In this way, by providing wireless chips in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of inspection systems and rental store systems can be improved. it can. In addition, forgery and theft can be prevented by providing a wireless chip in vehicles. Moreover, by embedding it in creatures such as animals, it is possible to easily identify individual creatures. For example, by burying a wireless chip in a living creature such as livestock, it is possible to easily identify the year of birth, sex or type.

  As described above, the semiconductor device of the present invention can be provided and used for any article that stores data. Note that this embodiment can be freely combined with the above embodiment.

  In this embodiment, a result of manufacturing a memory element portion over a substrate and writing data to the memory element portion by an electrical action will be described.

The memory element portion is an element in which a first conductive layer, an organic compound layer (a mixed layer of an organic compound material and an inorganic compound material + a layer made of an organic compound material), and a second conductive layer are stacked in this order on a substrate. (Hereinafter referred to as element structure 1). Note that indium tin oxide containing silicon oxide was used for the first conductive layer. As the organic compound layer, a stacked structure of a mixed layer of an organic compound material and an inorganic compound material and a layer made of the organic compound material was used. The mixed layer of the organic compound material and the inorganic compound material includes 4,4′-bis [N- (1-naphthyl) -N-phenylamino] biphenyl (sometimes abbreviated as α-NPD) and MoO ₃ . Was deposited by co-evaporation. For the layer made of an organic compound material, 4,4′-bis [N- (3-methylphenyl) -N-phenylamino] biphenyl (sometimes abbreviated as TPD) was used. Aluminum was used for the second conductive layer.

  In addition, in order to compare with the memory element portion having the above structure, an element in which a first conductive layer, a layer made of an organic compound material, and a second conductive layer were stacked in this order on a substrate was formed (hereinafter referred to as element structure 2 and Write down). A compound of indium tin oxide containing silicon oxide was used as the first conductive layer, TPD was used as the layer made of an organic compound material, and aluminum was used as the second conductive layer. That is, it is the structure which remove | excluded the mixed layer of the organic compound material and the inorganic compound material from the said structure.

Next, FIG. 17 shows the measurement results of the current-voltage characteristics of the element structure 1 and the element structure 2 before the memory element part is short-circuited by an electric action and after the memory element part is short-circuited by an electric action. Show. In FIG. 17, the horizontal axis indicates the voltage value (V), and the vertical axis indicates the current density (mA / cm ² ). In FIG. 17, a plot 261a shows the current-voltage characteristics of the element structure 1 before the memory element portion is short-circuited by applying an electrical action, and a plot 261b is after the memory element portion is short-circuited by applying an electrical action. The current-voltage characteristic of the element structure 1 is shown. A plot 862a shows the current-voltage characteristics of the element structure 2 before the memory element part is short-circuited by applying an electric action, and a plot 262b shows the element structure 2 after the memory element part is short-circuited by applying an electric action. The current-voltage characteristics are shown.

From FIG. 17, there is a large change in the current-voltage characteristics of the element structure 1 and the element structure 2 before and after the memory element portion is short-circuited. For example, at an applied voltage of 1 V, the current densities of the element structure 1 and the element structure 2 before short-circuiting the memory element portion are 1.6 × 10 ⁻⁴ mA / cm ² and 2.4 × 10 ⁻⁴ mA / cm ^{2, respectively.} On the other hand, the current densities of the element structure 1 and the element structure 2 after the storage element portion is short-circuited are 2.5 × 10 ² mA / cm ² and 4.3 × 10 ² mA / cm ² , respectively. The current value has changed by 6 digits before and after the storage element portion is short-circuited. That is, after the memory element portion is short-circuited, the resistance values of the element structure 1 and the element structure 2 are greatly reduced compared to the resistance value before the short-circuiting.

  As described above, before the memory element portion is short-circuited and after the memory element portion is short-circuited, the resistance value of the memory element portion changes, and the change in the resistance value of the element structure 1 or the element structure 2 is expressed as follows. By reading the voltage value or the current value, it can function as a memory circuit.

  In addition, as shown in FIG. 17, the voltages when the memory element portion is short-circuited by applying an electrical action to the element structure 1 and the element structure 2 are 9.6 V and 18.2 V, respectively, and the element structure 1 is lower. It was possible to short-circuit the memory element portion with voltage. In other words, as the organic compound layer, a mixed layer of an inorganic compound material and an organic compound material is provided on a layer made of an organic compound material, thereby reducing the drive voltage when writing data by short-circuiting the memory element. Is possible. As a result, in addition to a layer made of an organic compound material in the organic compound layer, a mixed layer of an organic compound material and an inorganic compound material is provided to simultaneously achieve a thicker memory element and lower power consumption. Can do.

  In this example, the dependence of the organic compound layer on the film thickness with respect to the write voltage, write current value, and current density of the organic memory element is shown. Here, writing was performed by applying a voltage to the organic memory element to short-circuit the organic memory element.

  ITO containing silicon oxide is formed as a first conductive layer on a glass substrate by a sputtering method, and molybdenum oxide and DNTPD (4 are used as a layer provided by mixing an inorganic compound and an organic compound on the first conductive layer. , 4′-Bis (N- {4- [N, N-bis (3-methylphenyl) amino] phenyl} -N-phenylamino) biphenyl) is co-evaporated at a ratio of 2: 4 to form an inorganic compound and an organic compound. NPB is vapor-deposited as an organic compound layer on a layer provided by mixing and an aluminum layer is vapor-deposited as a second conductive layer on the organic compound layer, and the size of the organic memory element in the horizontal plane is 100 μm × 100 μm. An organic memory element was formed.

  In addition, the thickness of the layer provided by mixing the inorganic compound and the organic compound was set to 80 nm, and organic memory elements having thicknesses of 10 nm, 20 nm, 30 nm, 40 nm, and 50 nm, respectively, were formed. Further, an organic memory element having an organic compound layer thickness of 10 nm is designated as sample 1, an organic memory element having an organic compound layer thickness of 20 nm is designated as sample 2, and an organic memory element having an organic compound layer thickness of 30 nm is designated as a sample. 3 and an organic memory element having an organic compound layer thickness of 40 nm as sample 4, an organic memory element having an organic compound layer thickness of 50 nm as sample 5, and the voltage, current value, and current when writing each sample. The density is shown in Table 1.

  As shown in Table 1, the write voltage can be reduced by reducing the thickness of the organic compound layer.

  Next, voltage and current values at the time of writing in the organic memory element in which the size of the organic memory element in the horizontal plane and the thickness of the layer in which the inorganic compound and the organic compound are mixed are different are shown. Similarly, writing was performed by applying a voltage to the organic memory element to short-circuit the organic memory element.

  A titanium layer is formed as a first conductive layer on a glass substrate by a sputtering method, and molybdenum oxide and NPB are co-deposited as a layer provided by mixing an inorganic compound and an organic compound on the first conductive layer. NPB was deposited as an organic compound layer on a layer provided by mixing an inorganic compound and an organic compound, and an aluminum layer was deposited as a second conductive layer on the organic compound layer to form an organic memory element.

  Note that the thickness of the layer provided by mixing the inorganic compound and the organic compound is 20 nm, the mixing ratio of molybdenum oxide and NPB is 1: 4, and the length of one side of the organic memory element is 3 μm and 5 μm. Table 2 shows voltage and current values when writing the following samples, where the organic memory elements are Sample 6 and Sample 7, respectively.

  The thickness of the layer provided by mixing the inorganic compound and the organic compound is 40 nm, the mixing ratio of molybdenum oxide and NPB is 1: 4, the length of one side of the organic memory element is 2 μm, 5 μm, and Table 3 shows voltage and current values at the time of writing the following samples, where the organic memory elements having a thickness of 10 μm are Sample 8, Sample 9, and Sample 10, respectively.

  As shown in Tables 1 to 3, electrical writing is performed in an organic memory element having a layer provided by mixing an inorganic compound and an organic compound between the first conductive layer and the organic compound layer. Was possible.

8A and 8B illustrate an example of a semiconductor device and a driving method thereof according to the present invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 4A and 4B illustrate an example of writing data into a semiconductor device of the present invention with a laser. 8A and 8B illustrate an example of a semiconductor device and a driving method thereof according to the present invention. . 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 8A and 8B illustrate usage patterns of a semiconductor device of the present invention. 8A and 8B illustrate usage patterns of a semiconductor device of the present invention. 8A and 8B illustrate usage patterns of a semiconductor device of the present invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 8A and 8B illustrate a semiconductor device manufacturing process of the present invention. 8A and 8B illustrate a semiconductor device manufacturing process of the present invention. 8A and 8B illustrate a semiconductor device manufacturing process of the present invention. 8A and 8B illustrate a semiconductor device manufacturing process of the present invention. 8A and 8B illustrate a semiconductor device manufacturing process of the present invention. FIG. 6 is a measurement diagram of current-voltage characteristics of a memory element in a semiconductor device of the present invention. 4A and 4B illustrate reading of data stored in a semiconductor device of the present invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention.

Explanation of symbols

16 memory circuit 21 memory cell 22 memory cell array 23 interface 24 word line drive circuit 24a row decoder 24b level shifter 26 bit line drive circuit 26a column decoder 26b read circuit 26c selector 27 first conductive layer 28 second conductive layer 29 organic compound layer 30 Substrate 33 Insulating layer 34 Insulating layer 37 Insulating layer 44 Semiconductor layer 45 Semiconductor layer 46 Resistive element 47 Differential amplifier 48 Transistor 49 Clocked inverter 77 Memory element part 78 Field effect transistor 79 Thin film transistor 80 Organic memory element 216 Memory circuit 221 Memory cell 222 Memory cell array 223 Interface 224 Word line drive circuit 224a Row decoder 224b Level shifter 226 Bit line drive circuit 226a Column decoder 226b Read Circuit 226c Selector 229 Clocked inverter 230 Substrate 240 Transistor 241 Organic memory element 241 Memory element 243 First conductive layer 244 Organic compound layer 245 Second conductive layer 246 Resistance element 247 Differential amplifier 248 Transistor 249 Insulating layer 250 Insulating layer 251 Element formation layer

Claims (8)

A bit line, a word line, and a memory element;
The memory element includes a first conductive layer forming the bit lines, the first conductive layer in contact with the organic compound layer in contact with the organic compound layer, and a second conductive layer forming the word line and, have,
The organic compound layer has a layer with an inorganic compound and an organic compound,
A semiconductor device , wherein data is written to the memory element by oxidizing or carbonizing the organic compound layer by irradiating a laser beam . A bit line, a word line, and a memory element;
The memory element includes a first conductive layer forming the bit lines, the first conductive layer in contact with the organic compound layer in contact with the organic compound layer, and a second conductive layer forming the word line and, have,
The organic compound layer includes a layer having an inorganic compound and a first organic compound, and a layer having a second organic compound ,
A semiconductor device , wherein data is written to the memory element by oxidizing or carbonizing the organic compound layer by irradiating a laser beam . A bit line, a word line, a memory element, and a transistor;
A gate of the transistor is electrically connected to the word line;
One of the source or drain of the transistor is electrically connected to the bit line,
The memory element includes a first conductive layer constituting the source and the drain other of said transistors, said first conductive layer in contact with the organic compound layer, and a second conductive layer in contact with the organic compound layer, the Have
The organic compound layer has a layer with an inorganic compound and an organic compound,
A semiconductor device , wherein data is written to the memory element by oxidizing or carbonizing the organic compound layer by irradiating a laser beam . A bit line, a word line, a memory element, and a transistor;
A gate of the transistor is electrically connected to the word line;
One of the source or drain of the transistor is electrically connected to the bit line,
The memory element includes a first conductive layer constituting the source and the drain other of said transistors, said first conductive layer in contact with the organic compound layer, and a second conductive layer in contact with the organic compound layer, the Have
The organic compound layer includes a layer having an inorganic compound and a first organic compound, and a layer having a second organic compound ,
A semiconductor device , wherein data is written to the memory element by oxidizing or carbonizing the organic compound layer by irradiating a laser beam . A bit line, a word line, a memory element, and a transistor;
A gate of the transistor is electrically connected to the word line;
One of the source or drain of the transistor is electrically connected to the bit line,
The memory element includes a first conductive layer constituting the other of a source and a drain of the transistor, a second conductive layer provided on the same plane as the first conductive layer, and the first conductive layer anda organic compound layer provided between the second conductive layer and,
The organic compound layer has a layer with an inorganic compound and an organic compound,
A semiconductor device , wherein data is written to the memory element by oxidizing or carbonizing the organic compound layer by irradiating a laser beam . A bit line, a word line, a memory element, and a transistor;
A gate of the transistor is electrically connected to the word line;
One of the source or drain of the transistor is electrically connected to the bit line,
The memory element includes a first conductive layer constituting the other of a source and a drain of the transistor, a second conductive layer provided on the same plane as the first conductive layer, and the first conductive layer anda organic compound layer provided between the second conductive layer and,
The organic compound layer includes a layer having an inorganic compound and a first organic compound, and a layer having a second organic compound ,
A semiconductor device , wherein data is written to the memory element by oxidizing or carbonizing the organic compound layer by irradiating a laser beam . In any one of Claims 1 thru | or 6,
The semiconductor device characterized by between the organic compound layer and the first conductive layer or between the organic compound layer and the second conductive layer, and has an element having a rectifying property. In any one of Claims 1 thru | or 7,
A semiconductor device, wherein the organic compound layer is destroyed by irradiating the laser beam.

Images