JP5230119B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device including a memory element formed using an organic compound.

  In recent years, development of semiconductor devices having various functions in which a plurality of circuits are integrated on an insulating surface has been promoted. In addition, development of a semiconductor device capable of transmitting and receiving data wirelessly by providing an antenna is in progress. Such a semiconductor device is called a wireless chip (also called an ID tag, an IC tag, an IC chip, an RF (Radio Frequency) tag, a wireless tag, an electronic tag, or an RFID (Radio Frequency Identification)), and has already been partly marketed. Introduced in.

Many of these semiconductor devices in practical use have a circuit (also referred to as an IC (Integrated Circuit) chip) using a semiconductor substrate such as Si and an antenna, and the IC chip is a memory circuit (also referred to as a memory). ) And a control circuit. In particular, by providing a memory circuit capable of storing a large amount of data, a semiconductor device with higher functions and higher added value can be provided. In addition, these semiconductor devices are required to be manufactured at low cost, and in recent years, development of organic thin film transistors and organic memories using organic compounds in control circuits, memory circuits, and the like has been actively performed (for example, Patent Document 1).
JP 2004-47791 A

  The storage circuit, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), FeRAM (Ferroelectric Random Access Memory), mask ROM (Read Only Memory), EPROM (Electrically Programmable Read Only Memory), EEPROM (Electrically Erasable and Programmable Read Only Memory), flash memory, and the like. Among these, DRAM and SRAM are volatile storage circuits, and data is erased when the power is turned off. Therefore, it is necessary to write data every time the power is turned on. FeRAM is a non-volatile memory circuit, but a manufacturing process increases because a capacitor element including a ferroelectric layer is used. Although the mask ROM has a simple structure, it is necessary to write data in the manufacturing process and cannot be additionally written. Although EPROM, EEPROM, and flash memory are non-volatile memory circuits, the number of manufacturing steps increases because an element including two gate electrodes is used.

  On the other hand, when a semiconductor device is manufactured using a vapor deposition method or a sputtering method using a metal mask, a metal mask alignment positioning step is used. In general, in a technique such as a photolithography process or laser ablation, the alignment accuracy is high and is about several μm, and the alignment alignment margin does not need to be considered much. However, in the vapor deposition method and the sputtering method using a metal mask, the alignment accuracy is low, and a margin of several tens to several hundreds of μm is taken in consideration of the wraparound to the metal mask part during film formation. There is a need. For this reason, it is difficult to manufacture a fine-structured element or the like, and it is difficult to reduce the size, weight, and performance of the semiconductor device.

  In view of the above problems, the present invention provides a semiconductor device having a non-volatile memory element that can additionally record data other than at the time of manufacture and can prevent forgery or the like due to rewriting. In addition, a semiconductor device capable of high integration is provided. Furthermore, a semiconductor device that can be miniaturized is provided.

One embodiment of the present invention is a semiconductor device including a memory element including a first conductive layer, a second conductive layer, and an organic compound layer sandwiched between the first conductive layer and the second conductive layer. The second conductive layer is a semiconductor device connected to the connection wiring through the opening formed in the substrate.

  Another embodiment of the present invention is a semiconductor device including a memory element including a first conductive layer, a second conductive layer, and an organic compound layer sandwiched between the first conductive layer and the second conductive layer. The second conductive layer is a semiconductor device connected to the first connection wiring and the second connection wiring through the opening formed in the compound layer.

  Note that the connection wiring is in contact with the same insulating layer or insulating substrate as the first conductive layer. The connection wiring is formed simultaneously with the first conductive layer. The connection wiring is made of the same material as the first conductive layer.

  The connection wiring is formed in the periphery of the first conductive layer. Further, the first connection wiring and the second connection wiring are formed in a peripheral portion sandwiching the first conductive layer as viewed from the top surface of the first conductive layer.

  According to another aspect of the present invention, a first conductive layer and a connection wiring are formed, an organic compound layer is formed over the first conductive layer and the connection wiring, a part of the organic compound layer is removed, and the connection wiring is formed. This is a method for manufacturing a semiconductor device in which a second conductive layer connected to a connection wiring is formed after part of the semiconductor device is exposed.

  According to another aspect of the present invention, the first conductive layer and the connection wiring are formed, the organic compound layer is formed over the first conductive layer and the connection wiring, and the second conductive layer is formed over the organic compound layer. Then, a method for manufacturing a semiconductor device in which the second conductive layer is irradiated with laser light to connect the second conductive layer and a connection wiring.

  According to another aspect of the present invention, the first conductive layer, the first connection wiring, and the second connection wiring are formed, and the first conductive layer, the first connection wiring, and the second connection wiring are formed on the first conductive layer, the first connection wiring, and the second connection wiring. After forming the organic compound layer and forming the second conductive layer on the organic compound layer, a voltage is applied to the second conductive layer, and the first connection wiring and the second conductive layer are connected to each other through the second conductive layer. This is a method for manufacturing a semiconductor device in which the second connection wiring is electrically connected.

  Note that the connection wiring, the first connection wiring, and the second connection wiring are connected to a driving circuit such as a decoder, a selector, and a read / write circuit 126, and a common electrode.

According to the present invention, by providing a memory element having an organic compound layer, it is possible to obtain a semiconductor device having a nonvolatile memory element in which data can be additionally recorded other than at the time of manufacture and forgery or the like due to rewriting can be prevented. . Further, high integration can be achieved by connecting the connection wiring and the second conductive layer through an opening formed in the organic compound layer. Thus, a semiconductor device that can be miniaturized can be obtained.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different forms, and those skilled in the art can easily understand that the forms and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment mode, a main structure of a semiconductor device of the present invention is described. Typically, a memory cell array in which memory cells including memory elements each including a first conductive layer, an organic compound layer, and a second conductive layer are arranged in a matrix will be described with reference to FIGS. To do. 1A shows a top view of the memory cell array, FIG. 1B shows a cross-sectional view taken along line AB of FIG. 1A, and FIG. 1C shows a CD of FIG. FIG.

Here, the first conductive layer 22a extends in the first direction, the second conductive layer 24a extends in the second direction intersecting the first direction, and the connection wiring 21a includes a plurality of first conductive layers. However, instead, the first conductive layer extends in the second direction, the second conductive layer extends in the first direction, and the wiring extends outside the first conductive layer. May be formed.

In the memory cell array 18, memory cells 19 are provided in a matrix (see FIG. 1A). The memory cell 19 includes a memory element 10a (see FIG. 1B). The memory element 10a includes a first conductive layer 22a extending in a first direction on the substrate 20, an organic compound layer 23a covering the first conductive layer 22a, and a second direction intersecting the first direction. And a second conductive layer 24a extending in the direction. Further, the connection wiring 21a formed simultaneously with the first conductive layer 22a is formed outside the plurality of first conductive layers. That is, the first conductive layer 22 a and the connection wiring 21 a are in contact with the same substrate 20. Further, an insulating layer functioning as a protective layer may be provided so as to cover the second conductive layer 24a.

  FIG. 1B illustrates a cross-sectional structure of a connection wiring portion and a memory cell array.

  A connection wiring 21 a and a first conductive layer 22 a are formed on the substrate 20. An organic compound layer 23a is formed on the substrate 20, the connection wiring 21a, and the first conductive layer 22a. The second conductive layer 24a is formed on the organic compound layer 23a and part of the connection wiring 21a. The second conductive layer 24a is connected to the connection wiring 21a at the opening 26a of the organic compound layer 23a.

FIG. 1C illustrates a cross-sectional structure of the memory cell array. Note that FIG. 1C illustrates a cross-sectional structure in a direction perpendicular to the cross-sectional direction in FIG.

A first conductive layer 22 a is formed on the substrate 20. An organic compound layer 23b and insulating layers 25a and 25b functioning as partition walls are formed over the first conductive layer 22a. In addition, organic compound layers 27a and 27b are also formed on the insulating layers 25a and 25b functioning as partition walls. The organic compound layer 23b and the organic compound layers 27a and 27b are insulated because they are divided. A second conductive layer 24b is formed on the organic compound layer 23b. In addition, second conductive layers 28a and 28b are formed on the organic compound layers 27a and 27b. In addition, the memory element 10b is configured by the first conductive layer 22a, the organic compound layer 23b, and the second conductive layer 24b.

As the substrate 20, a glass substrate, a flexible substrate, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, paper made of a fibrous material, or the like can be used. The flexible substrate is a substrate that can be bent (flexible), and examples thereof include a plastic substrate made of polycarbonate, polyarylate, polyethersulfone, or the like. A film having a thermoplastic resin layer (made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, or the like) can also be used.

As the first conductive layer 22a, the connection wiring 21a, and the second conductive layer 24a, a single layer or a stacked structure made of a highly conductive metal, alloy, compound, or the like can be used. Typically, a metal, an alloy, a conductive compound, or a mixture thereof having a large work function (specifically, 4.0 eV or more), or a metal, an alloy having a small work function (specifically, 3.8 eV or less). , Conductive compounds, and mixtures thereof can be used.

  Typical examples of metals, alloys, and conductive compounds having a high work function (specifically, 4.0 eV or more) include indium tin oxide (hereinafter referred to as ITO) or silicon-containing ITO, 2 to 20% And indium oxide containing zinc oxide (ZnO). Also, titanium (Ti), gold (Au), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), copper (Cu ), Palladium (Pd), or a nitride of a metal material (eg, titanium nitride (TiN), tungsten nitride (WN), molybdenum nitride (MoN)), or the like can also be used.

  Typical examples of metals, alloys, and conductive compounds having a small work function (specifically, 3.8 eV or less) include metals belonging to Group 1 or 2 of the periodic table of elements, that is, lithium (Li) or cesium (Cs). Alkali metals such as magnesium, alkaline earth metals such as magnesium (Mg), calcium (Ca), strontium (Sr), and alloys containing any of these (MgAg, AlLi), europium (Er), ytterbium (Yb) And rare earth metals and alloys containing them.

  In the case where an electrode for injecting holes into the organic compound layers 23a, 23b, 27a, and 27b, that is, an anode is used for the first conductive layer 22a or the second conductive layer 24a, an electrode having a large work function is used. Is preferably used. Conversely, when using an electrode for injecting electrons into the organic compound layers 23a, 23b, 27a, and 27b, it is preferable to use an electrode having a small work function.

The organic compound layers 23a, 23b, 27a, and 27b are formed of an organic compound whose crystal state, conductivity, and shape change depending on the voltage applied to the first conductive layer 22a and the second conductive layer 24a. The organic compound layers 23a, 23b, 27a, and 27b may be provided as a single layer, or a plurality of layers formed of different organic compounds may be stacked.

  Note that the organic compound layers 23a and 23b are formed with a film thickness at which the electrical resistance of the memory element changes due to external voltage application. The typical film thickness of the organic compound layers 23a and 23b is 5 nm to 100 nm, preferably 10 nm to 60 nm.

  The organic compound layers 23a, 23b, 27a, and 27b can be formed using an organic compound having a hole transporting property or an organic compound having an electron transporting property.

As an organic compound having a hole-transport property, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: NPB), 4,4′-bis [N- ( 3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD) and 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: TDATA), 4 , 4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) and 4,4′-bis (N- (4- (N, N-di-m-tolylamino) phenyl) -N-phenylamino) biphenyl (abbreviation: DNTPD) and other aromatic amine-based compounds (that is, having a benzene ring-nitrogen bond) and phthalocyanines (abbreviation: H ₂ PC) ), Copper lid Russia Emissions (abbreviation: CuPC), vanadyl phthalocyanine (abbreviation: VOPc) phthalocyanine compound or the like can be used. The substances described here are mainly substances having a hole mobility of 10 ⁻⁶ cm ² / Vs or higher.

As the organic compound having an electron transporting property, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [h ] -Quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), etc. Can be used. In addition, bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) A material such as a metal complex having an oxazole-based or thiazole-based ligand such as ₂ ) can also be used. In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- ( 4-biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2, 4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), and the like can be used. The substances mentioned here are mainly substances having an electron mobility of 10 ⁻⁶ cm ² / Vs or higher.

  Further, in order to change the hole transport property or electron transport property of the organic compound layers 23a, 23b, 27a, 27b, the organic compound layers 23a, 23b, 27a, 27b are formed from a plurality of organic compounds having different charge transport properties. May be. Such an organic compound layer can be formed by co-evaporating organic compounds having different charge transport properties.

Furthermore, in order to change the hole transport property or the electron transport property of the organic compound layers 23a, 23b, 27a, and 27b, the organic compound layers 23a, 23b, 27a, and 27b may be formed of an organic compound and an insulator. . Such an organic compound layer can be formed by co-evaporation of an organic compound and an inorganic compound, addition of an inorganic compound to the organic compound layer, a stacked structure of the organic compound layer and the inorganic compound layer, or the like. Inorganic compounds include insulators and semiconductors. As an inorganic compound having insulating properties, insulating properties represented by MgO, CaO, SrO, BaO, Sc ₂ O ₃ , ZrO ₂ , Fe ₂ O ₃ , CoO, PdO, Ag ₂ O, Al ₂ O _3, etc. Insulating oxides such as LiF, KF, CaF _2, insulating fluorides such as LiCl, NaCl, KCl, BeCl ₂ , CaCl ₂ , BaCl _2, insulating chlorides such as KBr, Insulating bromides represented by CsBr, AgBr, etc., insulating iodides represented by NaI, KI, BaI ₂ etc., MgCO ₃ , CaCO ₃ , SrCO ₃ , BaCO ₃ , MnCO ₃ , FeCO ₃ , carbonates having an insulating property typified CoCO ₃ or the _{like, Li 2 SO 4, K 2} SO 4, Na 2 SO 4, MgSO 4, CaSO 4 SrSO _4, BaSO ₄ or sulfate having an insulating property typified by, AlN, there is a nitride having an insulating property typified by SiN. In addition, as an inorganic compound indicating a semiconductor, molybdenum oxide, tin oxide, bismuth oxide, silicon film, vanadium oxide, nickel oxide, zinc oxide, silicon germanium, gallium arsenide, gallium nitride, indium oxide, indium phosphide, indium nitride , Cadmium sulfide, cadmium telluride, and strontium titanate films.

In the present embodiment, the shape of the insulating layers 25a and 25b functioning as the partition walls is preferably an inverted trapezoid whose upper side is longer than the bottom in the cross section. In addition, it is preferable that the second conductive layer is formed in a stripe shape in the second direction. With such a shape, when forming the organic compound layer and the second conductive layer, the organic compound layer and the second conductive layer formed in regions on the insulating layers 25a and 25b in a self-aligning manner, The organic compound layer and the second conductive layer formed on the first conductive layer 22a can be separated into stripes. For this reason, it is possible to reduce the number of steps of the organic compound layer and the second conductive layer.

The insulating layers 25a and 25b functioning as partition walls are formed using an organic resin or an organic compound such as polyimide, polyethylene, polypropylene, polystyrene resin, epoxy resin, or acrylic resin.

  Note that the memory cell 19 is preferably provided with a rectifying element in addition to the memory element 10. The rectifying element includes a transistor in which a gate electrode and a drain electrode are connected, a diode, or the like. Typical examples of the diode include a PN junction diode, a diode having a PIN junction, an avalanche diode, and the like. Moreover, you may use the diode of another structure. An element having a rectifying property can be provided between the substrate 20 and the first conductive layer 22a. Further, a rectifying element can be provided on the side opposite to the organic compound layers 23a and 23b through the second conductive layer. The element having a rectifying property can be provided between the organic compound layers 23a and 23b and the first conductive layer 22a. Further, a rectifying element can be provided between the organic compound layers 23a and 23b and the second conductive layer 24a. In this manner, by providing a rectifying element, current flows only in one direction, so that read errors are reduced.

  When forming the first conductive layer, the organic compound layer, the second conductive layer, and the connection wiring constituting the memory element, when forming the organic compound layer or the second conductive layer using a metal mask, the metal mask Therefore, it is necessary to design a layout in consideration of a certain margin in consideration of the alignment accuracy and the wraparound at the time of film formation.

  FIG. 18 is a top view of an end portion of a memory cell array in which a conventional memory element is formed, and FIG. 19C is a cross-sectional view taken along line AB of FIG. In FIG. 18, in order to separate the plurality of second conductive layers 24 in the direction intersecting the first conductive layer 22, the inverted trapezoidal interlayer insulating layer 25 is disposed in the direction intersecting the first conductive layer 22. Provided. On the interlayer insulating layer 25, a conductive layer 28 formed simultaneously with the organic compound layer and the second conductive layer 24 is provided.

When the layout is designed so that the connection wiring 21 and the second conductive layer 24 are connected without providing an organic compound layer therebetween, when the organic compound layer 23c covering the first conductive layer 22 is formed, the organic compound layer 23 In consideration of the shift of the metal mask that forms the film, the margin d1 is necessary.

  Further, in order to prevent the organic compound layer 23c from being formed in the region where the connection wiring 21 and the second conductive layer 24 are connected, a margin d2 is necessary in consideration of the shift of the metal mask forming the organic compound layer 23c. It is.

  Further, when the second conductive layer 24 connected to the connection wiring 21 is formed, an end where the connection wiring 21 and the second conductive layer 24 are connected is considered in consideration of a shift of a metal mask forming the second conductive layer 24. A margin d3 is required from the portion 26c.

  The broken line 23d is a region where the organic compound layer needs to be formed at a minimum, the broken line M1 shows a region where the opening of the metal mask for forming the organic compound layer can be designed, and the broken line M2 shows the second conductive layer. The opening design possible area | region of the metal mask for forming the layer 24 is shown.

  However, the margin of the metal mask can be reduced by connecting the connection wiring 21 and the second conductive layer 24 in the opening 26a formed in the organic compound layer 23c as in the present invention shown in FIG. .

  FIG. 17 is a top view of an end portion of a memory cell array in which the memory element of the present invention is formed, FIG. 19A is a cross-sectional view taken along line AB of FIG. 17A, and FIG. FIG. 17B is a cross-sectional view taken along line AB of FIG. In FIG. 17A, similarly to FIG. 18, in order to separate the plurality of second conductive layers 24 in the direction intersecting the first conductive layer 22, an inverted trapezoidal interlayer insulating layer (not shown) ) In a direction crossing the first conductive layer 22. An organic compound layer formed simultaneously with the organic compound layer 23 c and a conductive layer 28 formed simultaneously with the second conductive layer 24 are provided on the interlayer insulating layer.

  As shown in FIG. 17A, when the organic compound layer 23c covering the first conductive layer 22 is formed, the margin d11 (margin d1 in FIG. 18) is considered in consideration of the shift of the metal mask forming the organic compound layer 23c. Is required). In addition, when the second conductive layer 24 is formed in the opening 26a, the margin d12 is necessary in consideration of the shift of the metal mask for forming the second conductive layer 24.

  Furthermore, in order to connect the connection wiring 21 and the 2nd conductive layer 24 reliably, the opening part 26a is provided and the connection wiring 21 and the 2nd conductive layer 24 are connected in the said area | region.

  However, as in the conventional example shown in FIG. 18, the organic compound layer is not formed in the region to which the connection wiring 21 and the second conductive layer 24 are connected (in FIG. 17A, the opening 26a). The margin d2 is not necessary.

  Furthermore, the opening 26a can be formed by a photolithography process or laser ablation with high alignment accuracy. Therefore, the connection wiring 21 can be provided at a position close to the first conductive layer 22. As a result, the region where the connection wiring 21 and the second conductive layer 24 are connected can be brought close to the memory cell array.

  The cross section has a forward taper shape (that is, a trapezoidal shape in which the top side of the cross section is shorter than the bottom side) and is formed on almost the entire surface of the substrate, and has an opening 16 that exposes part of the connection wiring 21 and the first conductive layer 22. The case where the interlayer insulating layer 15 is formed will be described with reference to FIGS. 17B and 19B.

In the case where the organic compound layer 23c is formed on the first conductive layer 22, a margin d13 (corresponding to the margin d1 in FIG. 18) is necessary in consideration of the shift of the metal mask for forming the organic compound layer 23c.

  Further, when the second conductive layer 24 is formed in the opening 26b, the margin d14 is necessary in consideration of the shift of the metal mask for forming the second conductive layer 24. Furthermore, in order to connect the connection wiring 21 and the 2nd conductive layer 24 reliably, the opening part 26b is provided and the connection wiring 21 and the 2nd conductive layer 24 are connected in the said area | region.

  However, unlike the conventional example shown in FIG. 18, the organic compound layer 23c is not formed in the region (the opening 26b in FIG. 17B) to which the connection wiring 21 and the second conductive layer 24 are connected. This margin d2 is not necessary.

  Furthermore, the opening 26b can be formed by a photolithography process or laser ablation with high alignment accuracy. Therefore, the connection wiring 21 can be provided at a position close to the first conductive layer 22. As a result, the region where the connection wiring 21 and the second conductive layer 24 are connected can be brought close to the memory cell array.

  By adopting the structure of the present invention, the region to which the second conductive layer 24 and the connection wiring 21 are connected can be brought close to the memory cell array, and the semiconductor device can be downsized. Further, in the same area as the conventional area, more memory elements can be integrated in the memory circuit, and a semiconductor device with increased information recording can be manufactured.

  Next, a method for manufacturing the semiconductor device described in this embodiment will be described with reference to FIGS.

2 (A), (C), (E), and (G) show a manufacturing process of AB in FIG. 1 (B), and FIGS. 2 (B), (D), (F), and ( H) shows a manufacturing process of CD in FIG.

As shown in FIGS. 2A and 2B, the first conductive layer 22a and the connection wiring 21a are formed over the substrate 20, and the insulating layer functioning as a partition wall over the first conductive layer 22a and the connection wiring 21a. 25a and 25b are formed.

The first conductive layer 22a and the connection wiring 21a are formed using a vapor deposition method, a sputtering method, a CVD method, a printing method, an electrolytic plating method, an electroless plating method, a droplet discharge method, or the like. Here, the droplet discharge method is a method of forming a pattern with a predetermined shape by discharging a droplet of a composition containing fine particles from a minute hole.

  Here, after a titanium film with a thickness of 50 to 200 nm is formed by a sputtering method, the first conductive layer 22a and the connection wiring 21a are formed by etching into a desired shape by a photolithography method.

The insulating layers 25a and 25b functioning as partition walls can be formed using a dry etching method, a wet etching method, or the like. In the case where the insulating layers 25a and 25b are formed using a photosensitive resin, the insulating layers 25a and 25b can be formed using a photolithography process or the like. Note that the insulating layers 25a and 25b functioning as partition walls are preferably formed in a direction intersecting with the first conductive layer 22a.

Next, as shown in FIGS. 2C and 2D, organic compound layers 23a and 23b are formed over the substrate 20, the connection wiring 21a, and the first conductive layer 22a. Note that in this embodiment, since the cross sections of the insulating layers 25a and 25b functioning as partition walls are inverted trapezoidal, they are formed on the insulating layers 25a and 25b functioning as partition walls when the organic compound layer is formed. In addition, it is also formed between the insulating layers 25a and 25b functioning as partition walls. That is, the organic compound layer 23a formed on the substrate 20 and the first conductive layer 22a is separated from the organic compound layers 27a and 27b formed on the insulating layers 25a and 25b, and the first conductive layer 22a and It is formed in the intersecting direction.

  The organic compound layers 23a, 23b, 27a, and 27b can be formed using an evaporation method, an electron beam evaporation method, a sputtering method, a CVD method, or the like. Further, a spin coating method, a sol-gel method, a printing method, a droplet discharge method, or the like may be used, or the above method may be combined with these.

  Here, after forming a tin oxide layer having a thickness of 0.1 to 10 nm, preferably 1 to 5 nm by a vapor deposition method, an organic compound layer is formed using NPB having a thickness of 5 to 50 nm, preferably 10 to 20 nm by a vapor deposition method. 23a, 23b, 27a, 27b are formed.

Next, the organic compound layer 23a is irradiated with laser light 29, and a part of the organic compound layer 23a is ablated to form an opening 26a as shown in FIG. Note that, when the organic compound layer 23a is formed, the opening 26a can be formed without using the laser light 29 irradiation step illustrated in FIG. 2C by using a mask capable of forming the opening 26a. Can do.

Next, as shown in FIGS. 2G and 2H, the second conductive layers 24a and 24b are formed on the organic compound layers 23a and 23b, and the second conductive layers 24a and 27b are formed on the second conductive layers 24a and 27b. Conductive layers 28a and 28b are formed. Further, an aluminum layer having a thickness of 50 to 200 nm is formed by vapor deposition as the second conductive layers 24a, 24b, 28a, and 28b.

  The second conductive layers 24a and 24b are formed on the organic compound layers 27a and 27b without using a mask because the insulating layers 25a and 25b functioning as a partition with an inverted trapezoidal cross section are formed. The second conductive layers 24a and 24b can be formed in a direction separated from the two conductive layers 28a and 28b and intersecting the first conductive layer 22a.

FIG. 3 illustrates a method for manufacturing a semiconductor device which can be formed by a method different from the above.

As shown in FIGS. 3A and 3B, as in FIGS. 2A and 2B, the first conductive layer 22a and the connection wiring 21a are formed over the substrate 20.

Next, as shown in FIGS. 3C and 3D, as in FIGS. 2C and 2D, the organic compound layers 23a and 23b and the insulation functioning as a partition are formed over the first conductive layer 22a. Layers 25a and 25b are formed. Organic compound layers 27a and 27b are formed on the insulating layers 25a and 25b functioning as partition walls.

Next, as shown in FIGS. 3E and 3F, second conductive layers 24a, 24b, 28a, and 28b are formed on the organic compound layers 23a, 23b, 27a, and 27b. Next, a region where the connection wiring 21a, the organic compound layer 23a, and the second conductive layer 24a overlap is irradiated with a laser beam 29 to melt at least the organic compound layer 23a and the second conductive layer 24a. As shown in FIG. 3G, the connection wiring 21a is connected to the second conductive layer 24a.

At this time, the laser output is adjusted so that the second conductive layer 24a is driven to the depth of the connection wiring 21a. Here, laser irradiation is performed using an Nd: YVO _four- pulse laser with a laser wavelength of 266 nm and an oscillation frequency of 15 kHz and an average output of 3 W. This condition is only a representative condition, and is not particularly limited to this condition. By this laser irradiation, the second conductive layer 24a and the connection wiring 21a are electrically connected to each other as shown in FIG. Specifically, as shown in FIG. 3G, an opening 26a is formed in the organic compound layer 23a at a position irradiated with laser light, and the connection wiring 21a is formed along the side wall portion of the opening 26a. The second conductive layer 24a has penetrated to the surface.

Through the above steps, the second conductive layer 24a connected to the connection wiring 21a formed simultaneously with the first conductive layer 22a in the opening 26a of the organic compound layer 23a can be formed. In addition, it is possible to manufacture a semiconductor device that is smaller than the conventional size. In addition, in a semiconductor device having the same area as that in the past, a semiconductor device with an increased amount of stored information can be manufactured.

(Embodiment 2)
In this embodiment mode, a main structure of a semiconductor device in which the connection wiring and the second conductive layer are connected in the above embodiment mode will be described with reference to FIGS.

In this embodiment, a memory cell array in which memory cells each including a first conductive layer, an organic compound layer, and a second conductive layer are arranged in a matrix will be described with reference to FIGS. 4A is a top view of the memory cell array, FIG. 4B is a cross-sectional view taken along lines AB and EF in FIG. 4A, and FIG. 4C is FIG. 4A. Sectional drawing of CD is shown. Note that in this embodiment mode, the first connection wiring and the second connection wiring are connected to both ends of the second conductive layer.

In the memory cell array 18, memory cells 19 are provided in a matrix (see FIG. 4A). The memory cell 19 includes the memory element 10 (see FIG. 4B). The memory element 10 includes a first conductive layer 22a extending in the first direction on the substrate 20, an organic compound layer 23a covering the first conductive layer 22a, and a second direction intersecting the first direction. And a second conductive layer 24a extending in the direction. In addition, a connection wiring formed simultaneously with the first conductive layer is formed outside the plurality of first conductive layers. That is, the first conductive layer, the first connection wiring, and the second connection wiring are in contact with the same substrate 20.

  FIG. 4B illustrates a cross-sectional structure of the first connection wiring, the second connection wiring, and the memory cell array.

  In the region AB in FIG. 4B, the first connection wiring 21 a and the first conductive layer 22 a are formed over the substrate 20. An organic compound layer 23a is formed on the substrate 20, the first connection wiring 21a, and the first conductive layer 22a. Further, the second conductive layer 24a is formed on the organic compound layer 23a and on a part of the first connection wiring 21a. The second conductive layer 24a is connected to the first connection wiring 21a at the opening 26a of the organic compound layer 23a. 4B, the second connection wiring 21b and the first conductive layer 22b are formed over the substrate 20. In FIG. An organic compound layer 23a is formed on the substrate 20, the second connection wiring 21b, and the first conductive layer 22b. Further, the second conductive layer 24a is formed on the organic compound layer 23a and a part of the second connection wiring 21b. The second conductive layer 24a is connected to the second connection wiring 21b at the opening 26b of the organic compound layer 23a. That is, the second conductive layer 24a is connected to the first connection wiring 21a and the second connection wiring 21b.

FIG. 4C illustrates a cross-sectional structure taken along line CD of the memory cell array in FIG. FIG. 4C has a cross-sectional structure similar to that in FIG.

  Next, a method for manufacturing the semiconductor device described in this embodiment will be described with reference to FIGS.

FIGS. 5A and 5C show the manufacturing steps of AB and EF in FIG. 4B, and FIG. 5B shows the manufacturing of CD in FIG. 4C. A process is shown.

As shown in FIG. 5A, the first conductive layers 22a and 22b, the first connection wiring 21a, and the second connection wiring 21b are formed over the substrate 20 as in the first embodiment.

Next, as illustrated in FIG. 5B, insulating layers 25a and 25b functioning as partition walls are formed over the first conductive layer 22a.

Next, as illustrated in FIG. 5C, an organic compound layer 23a is formed over the substrate 20, the first connection wiring 21a, the second connection wiring 21b, and the first conductive layers 22a and 22b. Although not shown in FIG. 5C, in this embodiment mode, the side surfaces of the insulating layers 25a and 25b functioning as partition walls have an inverted trapezoidal shape. Therefore, when the organic compound layer is formed, An organic compound layer is formed on the functioning insulating layers 25a and 25b, and is also formed therebetween. That is, the organic compound layer 23a formed on the substrate 20 and the first conductive layer 22a is separated from the organic compound layer formed on the insulating layers 25a and 25b and intersects the first conductive layer 22a. Formed.

Next, as shown in FIG. 5D, a second conductive layer 24a is formed over the organic compound layer 23a.

Next, a predetermined voltage is applied to the first connection wiring 21 a and the second connection wiring 21 b to change the crystal state, conductivity, and shape of the organic compound layer 23 a, so that the first connection wiring 21 a and the second connection wiring 21 a are changed. The conductive layer 24a and the second connection wiring 21b are short-circuited. As a result, the first connection wiring 21a, the second conductive layer 24a, and the second connection wiring 21b are connected in the openings 26a and 26b of the organic compound layer 23a, respectively.

Through the above steps, the second conductive layer connected to the plurality of connection wirings formed simultaneously with the first conductive layer in the opening of the organic compound layer can be formed. In addition, it is possible to manufacture a semiconductor device that is smaller than the conventional size. In addition, in a semiconductor device having the same area as that in the past, a semiconductor device with an increased amount of stored information can be manufactured.

(Embodiment 3)
A method for manufacturing a semiconductor device in which the shape of the insulating layer functioning as a partition in the above embodiment is different from that in the above embodiment will be described with reference to FIGS.

In this embodiment, a memory cell array in which memory cells each including a first conductive layer, an organic compound layer, and a second conductive layer are arranged in a matrix is described with reference to FIGS. 6A is a top view of the memory cell array, FIG. 6B is a cross-sectional view taken along line AB of FIG. 6A, and FIG. 6C is a cross-sectional view taken along line CD of FIG. FIG.

In the memory cell array 18, memory cells 19 are provided in a matrix (see FIG. 6A). The memory cell 19 includes the memory element 10 (see FIG. 6B). The memory element 10 includes a first conductive layer 22a extending in the first direction on the substrate 20, an organic compound layer 32 covering the first conductive layer 22a, and a second direction intersecting the first direction. And a second conductive layer 33a extending in the direction. In addition, a connection wiring formed simultaneously with the first conductive layer is formed outside the plurality of first conductive layers. That is, the first conductive layer and the connection wiring are in contact with the same substrate 20.

  FIG. 6B illustrates a cross-sectional structure of the connection wiring and the memory cell array.

  A connection wiring 21 a and a first conductive layer 22 a are formed on the substrate 20. An insulating layer 31 that functions as a partition is formed over the substrate 20, the connection wiring 21a, and the first conductive layer 22a. In addition, in the opening 35a of the insulating layer 31, the organic compound layer 32 is formed on the first conductive layer 22a connection wiring 21a. A second conductive layer 33 a is formed on the organic compound layer 32. The second conductive layer 33 a is connected to the connection wiring 21 a at the opening 36 a of the organic compound layer 32.

FIG. 6C illustrates a cross-sectional structure of the memory cell array. Note that FIG. 6C illustrates a cross-sectional structure in a direction perpendicular to the cross-sectional direction in FIG.

A first conductive layer 22 a is formed on the substrate 20. An insulating layer 31 that functions as a partition is formed over the first conductive layer 22a. In addition, the organic compound layer 32 is formed in the openings 35b and 35c of the insulating layer 31 functioning as a partition and on the exposed portion of the first conductive layer 22a. Second conductive layers 33 b and 33 c are formed on the organic compound layer 32.

The first conductive layer 22a, the organic compound layer 32, and the second conductive layer 33a constitute a memory element. The first conductive layer 22a, the organic compound layer 32, and the second conductive layer 33b constitute a memory element. Further, the first conductive layer 22a, the organic compound layer 32, and the second conductive layer 33c constitute a memory element.

As the second conductive layers 33a to 33c, the same material as that of the second conductive layers 24a and 24b in the above embodiment can be used.

As a material and a manufacturing method of the organic compound layer 32, the same materials as the organic compound layers 23a, 23b, 27a, and 27b described in the above embodiment can be used. However, since the cross-sectional shape of the insulating layer 31 functioning as a partition wall is a so-called trapezoid whose base is longer than the upper side, the organic compound layer formed on the insulating layer 31 and the first conductive layer 22a is separated. Stay connected.

As the insulating layer 31 functioning as a partition, the material of the insulating layers 25a and 25b functioning as the partition described in the above embodiment can be used as appropriate.

  As shown in this embodiment mode, the connection wiring formed simultaneously with the first conductive layer and the second conductive layer are connected in the opening formed in the organic compound layer, thereby aligning the mask. It is possible to reduce the margin amount. Therefore, the area of the memory cell can be reduced as compared with the conventional case, and the semiconductor device can be miniaturized. In addition, in a semiconductor device having the same area as that of a conventional device, the amount of integration of memory cells can be increased, so that high integration can be achieved.

  Next, a method for manufacturing the semiconductor device described in this embodiment will be described with reference to FIGS.

7 (A), (C), (E), and (G) show a manufacturing process of AB in FIG. 6 (B), and FIGS. 7 (B), (D), (F), and ( H) shows a manufacturing process of CD in FIG.

As shown in FIGS. 7A and 7B, the first conductive layer 22a and the connection wiring 21a are formed on the substrate 20, and the insulating layer functioning as a partition on the first conductive layer 22a and the connection wiring 21a. 31 is formed. The insulating layer 31 functioning as a partition can be formed using a photosensitive or non-photosensitive material. In the case of using a photosensitive material, the insulating layer 31 can be formed by selectively exposing and developing the photosensitive material using a photomask. Alternatively, the insulating layer 31 can be formed by selectively irradiating a laser beam to expose a photosensitive material and developing the material.

Next, as illustrated in FIGS. 7C and 7D, an organic compound layer 32 is formed over the connection wiring 21 a, the first conductive layer 22 a, and the insulating layer 31. In the present embodiment, since the cross section of the insulating layer 31 functioning as a partition is trapezoidal, the organic compound layer is not divided on the substrate, and the continuous organic compound layer 32 includes the insulating layer 31 and the first conductive layer. It is formed on the layer 22a and the connection wiring 21a.

Next, the organic compound layer 32 is irradiated with laser light 29, and a part of the organic compound layer 32 is ablated to form an opening 36a as shown in FIG. Note that when the organic compound layer 32 is formed, the opening 36a can be formed without using the laser light 29 irradiation step illustrated in FIG. 7C by using a mask capable of forming the opening 36a. Can do.

Next, as illustrated in FIGS. 7G and 7H, second conductive layers 33 a to 33 c are formed over the organic compound layer 32.

  For the second conductive layers 33a to 33c, a method similar to that of the second conductive layers 24a and 24b described in the above embodiment can be applied as appropriate. Note that in the case of using a sputtering method or a CVD method, after forming a conductive layer over the organic compound layer 32, the conductive layer is selectively etched using a mask to form a second layer as shown in FIG. Striped second conductive layers 33a to 33c are formed in the direction.

In the present embodiment, the first embodiment is used as the method for connecting the second conductive layers 24a and 24b and the connection wiring 21a. However, the second embodiment can be used as appropriate.

Through the above steps, the second conductive layer connected to the connection wiring formed simultaneously with the first conductive layer in the opening of the organic compound layer can be formed. In addition, it is possible to manufacture a semiconductor device that is smaller than the conventional size. In addition, in a semiconductor device having the same area as that in the past, a semiconductor device with an increased amount of stored information can be manufactured.

(Embodiment 4)
Data writing and reading operations of the semiconductor device described in the above embodiment are described with reference to FIGS.

  As shown in FIG. 8A, the semiconductor device 122 of this embodiment includes a memory cell array 116 and drive circuits such as decoders 123 and 124, a selector 125, and a read / write circuit 126. The memory cell array 116 is formed of a plurality of memory cells 121. In the memory cell 121, a first conductive layer, an organic compound layer, and a second conductive layer are sequentially stacked. The first conductive layer is connected to the word line Wy (1 ≦ y ≦ n) or uses the word line Wy. The second conductive layer uses a bit line Bx (1 ≦ x ≦ m).

An operation when data is written to the memory cell will be described. A case where data is written by electrical action will be described. Writing is performed by changing the electrical characteristics of the memory cell. The initial state of the memory cell (the state where no electrical action is applied) is data “0”, and the state where the electrical characteristic is changed is “1”. To do.

When data “1” is written in the memory cell 121, first, the memory cell 121 is selected by the decoders 123 and 124 and the selector 125. Specifically, the decoder 124 applies a predetermined voltage V2 to the word line W3 connected to the memory cell 121. In addition, the bit line B 3 connected to the memory cell 121 is connected to the read / write circuit 126 by the decoder 123 and the selector 125. Then, the write voltage V1 is output from the read / write circuit 126 to the bit line B3. Thus, the voltage Vw = V1−V2 is applied between the first conductive layer and the second conductive layer that constitute the memory cell 121. By appropriately selecting the potential Vw, the organic compound layer provided between the conductive layers is changed physically or electrically, and data “1” is written. Specifically, at the read operation voltage, the electrical resistance between the first conductive layer and the second conductive layer in the data “1” state is significantly smaller than that in the data “0” state. The voltage Vw may be 5 to 15 V, or −5 to −15 V. For example, (V1, V2) = (0V, 5-15V), (3-5V, -12--2V), or the like can be set.

Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. For example, unselected word lines and unselected bit lines may be set in a floating state. The first conductive layer and the second conductive layer constituting the memory cell must have characteristics such as diode characteristics that can ensure selectivity.

On the other hand, when data “0” is written in the memory cell 121, it is not necessary to apply an electrical action to the memory cell 121. In the circuit operation, for example, as in the case of writing “1”, the memory cells 121 are selected by the decoders 123 and 124 and the selector 125, but the output potential from the read / write circuit 126 to the bit line B3 is selected. The potential of the word line W3 or the potential of the non-selected word line is set to the same level so that the electrical characteristics of the memory cell 121 are not changed between the first conductive layer and the second conductive layer constituting the memory cell 121. A voltage (for example, −5 to 5 V) may be applied.

Next, an operation for reading data from a memory cell will be described (see FIGS. 8B and 8C). In reading data, the electrical characteristics between the first conductive layer and the second conductive layer constituting the memory cell are different between the memory cell having data “0” and the memory cell having data “1”. Use it. For example, the effective electrical resistance between the first conductive layer and the second conductive layer constituting the memory cell having data “0” (hereinafter simply referred to as the electrical resistance of the memory cell) is R0 at the read voltage. A method of reading data by using the difference in electric resistance when the electric resistance of the memory cell having data “1” is R1 in the read voltage will be described. Note that R1 << R0. As the reading / writing circuit, for example, a circuit 126 using a resistance element 146 and a differential amplifier 147 shown in FIG. The resistance element 146 has a resistance value Rr, and R1 <Rr <R0. A transistor 148 may be used instead of the resistance element 146, and a clocked inverter 149 may be used instead of the differential amplifier (FIG. 8C). The clocked inverter 149 receives a signal φ or an inverted signal φ that is High when reading is performed and is Low when the reading is not performed. Of course, the circuit configuration is not limited to FIGS. 8B and 8C.

When reading data from the memory cell 121, first, the memory cell 121 is selected by the decoders 123 and 124 and the selector 125. Specifically, the decoder 124 applies a predetermined voltage Vy to the word line Wy connected to the memory cell 121. In addition, the bit line Bx connected to the memory cell 121 is connected to the terminal P of the read / write circuit 126 by the decoder 123 and the selector 125. As a result, the potential Vp of the terminal P becomes a value determined by resistance division by the resistance element 146 (resistance value Rr) and the memory cell 121 (resistance value R0 or R1). Therefore, when the memory cell 121 has data “0”, Vp0 = Vy + (V0−Vy) × R0 / (R0 + Rr). When the memory cell 121 has data “1”, Vp1 = Vy + (V0−Vy) × R1 / (R1 + Rr). As a result, in FIG. 8B, Vref is selected to be between Vp0 and Vp1, and in FIG. 8C, the change point of the clocked inverter is selected to be between Vp0 and Vp1. Thus, Low / High (or High / Low) is output as the output potential Vout according to the data “0” / “1”, and reading can be performed.

For example, the differential amplifier is operated at Vdd = 3V, and Vy = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9, if the memory cell data is “0”, Vp0 = 2.7 V and Vout is High, and if the memory cell data is “1”, Vp1 = 0.3V and Low is output as Vout. Thus, the memory cell can be read.

According to the above method, the state of the electrical resistance of the organic compound layer is read as a voltage value using the difference in resistance value and resistance division. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. In addition, when the electrical characteristics of the memory cell have data “0” and “1” and diode characteristics with different threshold voltages, reading may be performed using the threshold voltage difference.

(Embodiment 5)
In this embodiment mode, main parts of a semiconductor device are described. Typically, a main structure of a semiconductor device including a memory cell array including a switching element and a memory element in a memory cell will be described with reference to FIGS. Note that the memory element includes a first conductive layer, an organic compound layer, and a second conductive layer. 9A is a top view of the memory cell array, and FIGS. 9B and 9C are cross-sectional views taken along lines AB and CD in FIG. 9A.

  In the memory cell array 222, a plurality of memory cells 220 are provided in a matrix. The memory cell 220 includes a transistor 202 functioning as a switching element and a memory element 212 connected to the transistor 202 over a substrate 200 having an insulating surface (see FIGS. 9A and 9B). .) The memory element 212 includes a first conductive layer 206 formed on the insulating layer 205, an organic compound layer 209, and a second conductive layer 210. Note that the organic compound layer 209 is formed over the first conductive layer 206 and the insulating layer 208 functioning as a partition wall that covers part of the first conductive layer 206. Further, a thin film transistor is used as the transistor 202. Further, an insulating layer that covers the second conductive layer 210 and functions as a protective layer may be provided.

In FIG. 9A, the second conductive layer 210 of the memory element 212 is formed in stripes in a direction parallel to the gate wiring of the thin film transistor. The connection wiring 207 is formed on the extension of the second conductive layer 210. Note that the second conductive layer 210 of the memory element 212 may be formed in a stripe shape in a direction parallel to the source wiring of the thin film transistor. In this case, the connection wiring 207 is formed on the extension of the second conductive layer 210.

In FIG. 9B, a connection wiring 207 formed at the same time as the first conductive layer 206 is formed over the insulating layer 205, and the insulating layer 208 having an opening is formed over the connection wiring 207. An organic compound layer 209 and a second conductive layer 210 are formed. Further, the connection wiring 207 and the second conductive layer 210 are connected by the opening 211 of the organic compound layer 209.

  Further, the connection wiring can be formed at the same time as the gate electrode of the transistor. Further, the connection wiring can be formed simultaneously with the transistor wiring. FIG. 9C illustrates a mode in which the connection wiring 215 formed at the same time as the transistor wirings 204 a and 204 b is connected to the second conductive layer 210 in the opening 216 of the organic compound layer 209.

  The above embodiment can be applied as appropriate to the connection method of the second conductive layer 210 and the connection wirings 207 and 215 of the memory element 212.

  One mode of a thin film transistor that can be used for the transistor 202 is described with reference to FIGS. FIG. 16A illustrates an example in which a top-gate thin film transistor is applied. An insulating layer 201 is provided over the substrate 200 having an insulating surface, and a thin film transistor is provided over the insulating layer 201. In the thin film transistor, a semiconductor layer 1302 and an insulating layer 1303 which can function as a gate insulating layer are provided over the insulating layer 201. Over the insulating layer 1303, a gate electrode 202a is formed corresponding to the semiconductor layer 1302, and an insulating layer 203a functioning as a protective layer and an insulating layer 203b functioning as an interlayer insulating layer are provided thereover. In addition, wirings 204a and 204b connected to the source region and the drain region of the semiconductor layer are formed.

  The semiconductor layer 1302 is a layer formed of a semiconductor having a crystal structure, and a non-single-crystal semiconductor or a single-crystal semiconductor can be used. In particular, an amorphous or microcrystalline semiconductor is crystallized by crystallizing a semiconductor that is crystallized by laser light irradiation, a crystallized semiconductor that is crystallized by heat treatment, or a combination of heat treatment and laser light irradiation. It is preferable to apply a crystalline semiconductor. In the heat treatment, a crystallization method using a metal element such as nickel which has an action of promoting crystallization of a silicon semiconductor can be applied.

In the case of crystallization by irradiating with laser light, high repetition frequency with continuous wave laser light irradiation or repetition frequency of 10 MHz or more and pulse width of 1 nanosecond or less, preferably 1 to 100 picoseconds. By irradiating with ultrashort pulse light, crystallization can be performed while continuously moving the molten zone in which the crystalline semiconductor is melted in the irradiation direction of the laser light. By such a crystallization method, a crystalline semiconductor having a large particle diameter and a crystal grain boundary extending in one direction can be obtained. By adjusting the carrier drift direction to the direction in which the crystal grain boundary extends, the field-effect mobility in the transistor can be increased. For example, 400 cm ² / V · sec or more can be realized.

When the crystallization process is performed using a crystallization process at a heat resistant temperature (about 600 ° C.) or lower of the glass substrate, a large-area glass substrate can be used. Therefore, a large amount of semiconductor devices can be manufactured per substrate, and the cost can be reduced.

Alternatively, the semiconductor layer 1302 may be formed by performing a crystallization step by heating at a temperature equal to or higher than the heat resistant temperature of the glass substrate. Typically, a quartz substrate is used as the insulating substrate 200, and an amorphous or microcrystalline semiconductor is heated at 700 ° C. or higher to form the semiconductor layer 1302. As a result, a semiconductor with high crystallinity can be formed. Therefore, a thin film transistor that has favorable characteristics such as response speed and mobility and can operate at high speed can be provided.

  As the insulating layer 1303 which can function as a gate insulating layer, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like is appropriately formed by a thin film formation method such as a CVD method or a PVD method.

  The gate electrode 202a can be formed using a metal or a polycrystalline semiconductor to which an impurity of one conductivity type is added. In the case of using a metal, tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), aluminum (Al), or the like can be used. Further, a metal nitride obtained by nitriding the above metal can be used. Or it is good also as a structure which laminated | stacked the 1st layer which consists of the said metal nitride, and the 2nd layer which consists of the said metal. In the case of a laminated structure, the end of the first layer may protrude outward from the end of the second layer. At this time, a barrier metal can be formed by using a metal nitride for the first layer. That is, the second layer metal can be prevented from diffusing into the insulating layer 1303 and the semiconductor layer 1302 below the insulating layer 1303.

Sidewalls (sidewall spacers) 1308 are formed on the side surfaces of the gate electrode 202a. The sidewall can be formed by forming an insulating layer made of silicon oxide on the substrate by a CVD method and anisotropically etching the insulating layer by a RIE (Reactive ion etching) method.

  Various structures such as a single drain structure, an LDD (lightly doped drain) structure, and a gate overlap drain structure can be applied to a transistor formed by combining the semiconductor layer 1302, the insulating layer 1303, the gate electrode 202a, and the like. Here, a thin film transistor having an LDD structure in which a low concentration impurity region 1310 is formed in a semiconductor layer where sidewalls overlap is shown. It is also possible to apply a single gate structure, equivalently a multi-gate structure in which transistors to which a gate voltage of the same potential is applied are connected in series, or a dual gate structure in which a semiconductor layer is sandwiched between gate electrodes. it can.

The insulating layer 203a is formed using a thin film formation method such as a plasma CVD method or a sputtering method, using silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, aluminum oxynitride, aluminum oxide, or another insulating material. It is preferable to do.

  The insulating layer 203b is formed using an inorganic insulating material such as silicon oxide or silicon oxynitride, or an organic insulating material such as an acrylic resin or a polyimide resin. When a coating method such as spin coating or roll coater is used, silicon oxide in which an insulating layer is formed by heat treatment after coating an insulating layer material dissolved in an organic solvent can also be used. For example, an insulating layer that can be formed by heat treatment at 200 to 400 ° C. after forming a coating layer containing a siloxane bond can be used. By forming the insulating layer 203b by an application method or an insulating layer flattened by reflow, disconnection of wiring formed over the layer can be prevented. It can also be used effectively when forming multilayer wiring.

  The wirings 204a and 204b formed over the insulating layer 203b can be provided so as to intersect with a wiring formed in the same layer as the gate electrode 202a, thereby forming a multilayer wiring structure. A multilayer wiring structure can be formed by stacking a plurality of insulating layers having the same function as the insulating layer 203a and forming wirings on the insulating layers. The wirings 204a and 204b are made of a low resistance material such as aluminum (Al), such as a laminated structure of titanium (Ti) and aluminum (Al), a laminated structure of molybdenum (Mo) and aluminum (Al), titanium (Ti), It is preferably formed in combination with a barrier metal using a refractory metal material such as molybdenum (Mo).

  FIG. 16B illustrates an example in which a bottom-gate thin film transistor is applied. An insulating layer 201 is formed over a substrate 200 having an insulating surface, and a thin film transistor is provided thereover. The thin film transistor is provided with a gate electrode 202a, an insulating layer 1303 functioning as a gate insulating layer, a semiconductor layer 1302, a channel protective layer 1309, an insulating layer 1305 functioning as a protective layer, and an insulating layer 203b functioning as an interlayer insulating layer. . Further, an insulating layer functioning as a protective layer may be formed thereon. The wirings 204a and 204b can be formed over the insulating layer 1305 or over the insulating layer 203b. Note that in the case of a bottom-gate thin film transistor, the insulating layers 1305 and 203b are not necessarily formed.

In the case where the substrate 200 having an insulating surface is a flexible substrate, the heat resistant temperature is lower than that of a non-flexible substrate such as a glass substrate. Therefore, the semiconductor layer of the transistor can be formed using an organic semiconductor.

Further, the thin film transistor and the organic semiconductor transistor may be provided in any configuration as long as they can function as a switching element.

Here, a structure of a thin film transistor using an organic semiconductor as the transistor 202 is described with reference to FIGS. FIG. 16C illustrates an example in which a staggered organic semiconductor transistor is applied. An organic semiconductor transistor is provided as the transistor 202 over the substrate 200. The organic semiconductor transistor includes a gate electrode 202a, an insulating layer 1403 functioning as a gate insulating layer, a semiconductor layer 1404 overlapping with the gate electrode 202a and the insulating layer 1403 functioning as a gate insulating layer, and a first wiring 204a connected to the semiconductor layer 1404. 204b are formed. Note that the semiconductor layer 1404 is partly sandwiched between the insulating layer 1403 functioning as a gate insulating layer and the first wirings 204a and 204b.

The gate electrode 202a can be formed by drying and baking using a droplet discharge method. Alternatively, the gate electrode 202a can be formed by printing a paste containing fine particles over a flexible substrate by a printing method, followed by drying and baking. As typical examples of the fine particles, fine particles mainly containing any of gold, copper, an alloy of gold and silver, an alloy of gold and copper, an alloy of silver and copper, and an alloy of gold, silver, and copper may be used. Further, fine particles mainly containing a conductive oxide such as indium tin oxide (ITO) may be used.

The insulating layer 1403 functioning as a gate insulating layer can be formed using a material and a method similar to those of the insulating layer 1303. However, when an insulating layer is formed by heat treatment after applying an insulating layer material that dissolves in an organic solvent, the heat treatment temperature is lower than the heat resistance temperature of the flexible substrate.

Examples of the material of the semiconductor layer 1404 of the organic semiconductor transistor include polycyclic aromatic compounds, conjugated double bond compounds, phthalocyanines, and charge transfer complexes. For example, anthracene, tetracene, pentacene, 6T (hexathiophene), TCNQ (tetracyanoquinodimethane), PTCDA (perylene carboxylic acid anhydride), NTCDA (naphthalene carboxylic acid anhydride) and the like can be used. Examples of the material for the semiconductor layer 1404 of the organic semiconductor transistor include π-conjugated polymers such as organic polymer compounds, carbon nanotubes, polyvinyl pyridine, and phthalocyanine metal complexes. In particular, when a polyacetylene, polyaniline, polypyrrole, polythienylene, polythiophene derivative, poly (3 alkylthiophene), polyparaphenylene derivative or polyparaphenylene vinylene derivative is used, which is a π-conjugated polymer whose skeleton is composed of conjugated double bonds preferable.

  As a method for forming the semiconductor layer 1404 of the organic semiconductor transistor, a method capable of forming a film with a uniform thickness over the substrate may be used. The thickness is 1 nm to 1000 nm, preferably 10 nm to 100 nm. As a specific method, an evaporation method, a coating method, a spin coating method, a bar coating method, a solution casting method, a dip method, a screen printing method, a roll coater method, or a droplet discharge method can be used.

FIG. 16D illustrates an example in which a coplanar organic semiconductor transistor is used. An organic semiconductor transistor is provided as the transistor 202 over the substrate 200. The organic semiconductor transistor includes a gate electrode 202a, an insulating layer 1403 functioning as a gate insulating layer, a first wiring 204a and 204b, a gate electrode 202a, and a semiconductor layer 1404 overlapping with the insulating layer 1403 functioning as a gate insulating layer. Yes. The first wirings 204a and 204b are partly sandwiched between the insulating layer 1403 and the semiconductor layer 1404 which function as gate insulating layers.

  Alternatively, a transistor may be formed using a single crystal substrate or an SOI substrate, and a memory element may be provided thereover. The SOI substrate may be formed using a method called wafer bonding or a method called SIMOX in which an insulating layer is formed inside by implanting oxygen ions into the Si substrate.

Since a transistor formed using such a single crystal semiconductor has favorable characteristics such as response speed and mobility, a transistor that can operate at high speed can be provided. In addition, since the transistor has less variation in characteristics, a semiconductor device that achieves high reliability can be provided.

The memory element 212 includes a first conductive layer 206 formed over the insulating layer 205, a partition wall (insulating layer) 208 that covers part of the first conductive layer 206, a first conductive layer 206, and a partition wall ( An organic compound layer 209 covering the insulating layer 208 and a second conductive layer 210.

  In this manner, the first conductive layer 206 can be freely disposed by providing the insulating layer 205 and forming the memory element 212. That is, the memory element 212 can be formed above the transistor 202. As a result, the semiconductor device can be more highly integrated. In addition, by forming the memory element 212 immediately above the gate electrode 202a without covering the wirings 204a and 204b and the end portions of the gate electrode 202a, the base region (that is, the insulating layer 205 of the insulating layer 205) is formed. It is possible to reduce unevenness of the surface. Therefore, unevenness of the surface of the first conductive layer 206 can be reduced, unintended writing of the memory element 212 can be controlled, and reliability can be improved.

  The materials and formation methods of the first conductive layer 206, the organic compound layer 209, and the second conductive layer 210 are the same as those of the first conductive layer 22a, the organic compound layer 23a, and the second conductive layer described in the above embodiment mode. This can be similarly performed using any of the materials and formation methods of the layers 24a to 24b.

  The insulating layer 208 can be formed using a material and a formation method which are similar to those of the insulating layers 25a, 25b, and 31 described in the above embodiment modes as appropriate.

  Further, a rectifying element may be provided between the insulating layer 205 and the first conductive layer 206. Alternatively, a rectifying element may be provided between the first conductive layer 206 and the organic compound layer 209. Alternatively, a rectifying element may be provided between the organic compound layer 209 and the second conductive layer 210. Alternatively, the rectifying element described in Embodiment 1 may be provided over the second conductive layer 210.

In addition, a separation layer is provided between the substrate 200 having an insulating surface and the insulation layer 201, and after forming an element formation layer including a switching element and a memory element 212 over the separation layer, the element formation layer is separated from the separation layer. An element formation layer may be attached to a flexible substrate with an adhesive layer interposed therebetween. As a peeling method, (1) a metal oxide layer is provided as a peeling layer between a substrate having an insulating surface and an element formation layer, the metal oxide layer is weakened by crystallization, and the element formation layer is peeled off. (2) An amorphous silicon layer containing hydrogen is provided as a separation layer between a substrate having an insulating surface and an element formation layer, and the amorphous silicon layer is removed by laser light irradiation or etching. , A method of peeling the element formation layer, (3) mechanically removing the substrate having an insulating surface on which the element formation layer is formed, or using a solution, halogen fluoride gas such as NF ₃ , BrF ₃ , or ClF ₃ (4) A metal layer and a metal oxide layer are provided as a separation layer between a substrate having an insulating surface and an element formation layer, and the metal oxide layer is weakened by crystallization, and the metal layer Part of the solution or NF _For example, a method of physically peeling off the weakened metal oxide layer after removing by etching with halogen fluoride gas such as ₃ or BrF ₃ or ClF ₃ may be used.

In addition, as a flexible substrate to which the element formation layer is attached, a flexible substrate, a film having a thermoplastic resin, a paper made of a fibrous material, or the like is used, so that the memory device is small, thin, and lightweight. Can be achieved. Examples of the flexible substrate include plastic substrates made of polycarbonate, polyarylate, polyether sulfone, and the like. Moreover, as a film having a thermoplastic resin layer, polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, or the like can be used.

(Embodiment 6)
Data writing and reading operations of the semiconductor device described in the above embodiment are described with reference to FIGS.

The semiconductor device 221 includes decoders 223 and 224, a selector 225, a read / write circuit 226, and a memory cell array 222. The memory cell array 222 includes a memory cell 220 including a transistor 240 and a memory element 241. The memory element 241 has a structure in which an organic compound layer is sandwiched between a pair of conductive layers. The gate electrode of the transistor 240 is connected to the word line Wy (1 ≦ y ≦ n), either the source electrode or the drain electrode is connected to the bit line Bx (1 ≦ x ≦ m), and the remaining one is the memory element 241. Is connected to the first conductive layer. The remaining second conductive layer of the memory element 241 is connected to a connection wiring. The connection wiring is connected to the common electrode (potential Vcom).

  Next, an operation when data is written to the semiconductor device 221 is described.

Here, a case where data is written to the memory cell 220 in the n-th row and the m-th column by electrical action will be described. Writing is performed by changing the electrical characteristics of the memory cell. The initial state of the memory cell (the state where no electrical action is applied) is data “0”, and the state where the electrical characteristic is changed is “1”. To do.

When data “1” is written to the memory cell 220, first, the memory cell 220 is selected by the decoders 223 and 224 and the selector 225. Specifically, the decoder 224 applies a predetermined voltage V22 to the word line Wn connected to the memory cell 220. Further, the bit line Bm connected to the memory cell 220 is connected to the read / write circuit 226 by the decoder 223 and the selector 225. Then, the write voltage V21 is output from the read / write circuit 226 to the bit line B3.

Thus, the transistor 240 included in the memory cell is turned on, the bit line is electrically connected to the memory element 241, and a voltage of approximately Vw = Vcom−V21 is applied. Note that the second conductive layer of the memory element 241 is connected to the common electrode having the potential Vcom. By appropriately selecting the potential Vw, the organic compound layer provided between the pair of conductive layers is physically or electrically changed, and data “1” is written. Specifically, at the read operation voltage, the electrical resistance between the first conductive layer and the second conductive layer in the data “1” state is significantly smaller than that in the data “0” state. It may be changed as described above, or it may be simply short-circuited. The potential may be appropriately selected from the range of (V21, V22, Vcom) = (5-15V, 5-15V, 0V), or (-12 to 0V, -12 to 0V, 3 to 5V). The voltage Vw may be 5 to 15V, or -5 to -15V.

Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. Specifically, a potential (for example, 0 V) for turning off the transistor of the memory cell to be connected is applied to the non-selected word line, and the non-selected bit line is in a floating state or approximately equal to Vcom. A potential may be applied.

On the other hand, when data “0” is written in the memory cell 220, it is not necessary to apply an electrical action to the memory cell 220. In the circuit operation, for example, as in the case of writing “1”, the memory cell 220 is selected by the decoders 223 and 224 and the selector 225, but the output potential from the read / write circuit 226 to the bit line B3 is the same as Vcom. Or the bit line B3 is in a floating state. As a result, a small voltage (for example, −5 to 5 V) is applied to the memory element 241 or no voltage is applied, so that the electrical characteristics do not change and data “0” writing is realized.

Next, an operation when data is read by electrical action will be described. Data is read by utilizing the fact that the electrical characteristics of the memory element 241 are different between the memory cell having the data “0” and the memory cell having the data “1”. For example, the electrical resistance of the memory element constituting the memory cell having data “0” is R0 at the read voltage, and the electrical resistance of the memory element constituting the memory cell having data “1” is R1 at the read voltage. A method of reading using the difference will be described. Note that R1 << R0. As the structure of the reading / writing circuit, for example, a circuit 226 using a resistance element 246 and a differential amplifier 247 shown in FIG. 10B can be considered. The resistance element has a resistance value Rr, and R1 <Rr <R0. A transistor 250 may be used instead of the resistance element 246, and a clocked inverter 251 may be used instead of the differential amplifier 247 (FIG. 10C). Of course, the circuit configuration is not limited to FIGS. 10B and 10C.

When reading data from the memory cell 220 in the xth column and the yth row, first, the memory cell 220 is selected by the decoders 223 and 224 and the selector 225. Specifically, the decoder 224 applies a predetermined voltage V24 to the word line Wy connected to the memory cell 220, and the transistor 240 is turned on. In addition, the bit line Bx connected to the memory cell 220 is connected to the terminal P of the read / write circuit 226 by the decoder 223 and the selector 225. As a result, the potential Vp of the terminal P becomes a value determined by resistance division by the resistance element 246 (resistance value Rr) and the memory element 241 (resistance value R0 or R1). Therefore, when the memory cell 220 has data “0”, Vp0 = Vcom + (V0−Vcom) × R0 / (R0 + Rr). When the memory cell 220 has data “1”, Vp1 = Vcom + (V0−Vcom) × R1 / (R1 + Rr). As a result, in FIG. 10B, Vref is selected to be between Vp0 and Vp1, and in FIG. 10C, the change point of the clocked inverter is selected to be between Vp0 and Vp1. Thus, the output potential Vout is Low / High (or High / Low) according to the data “0” / “1”, and reading can be performed.

For example, the differential amplifier is operated at Vdd = 3V, and Vcom = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9 and the on-resistance of the transistor 240 can be ignored, when the data in the memory cell is “0”, Vp0 = 2.7V and Vout is output as high, and the memory cell When the data of “1” is “1”, Vp1 = 0.3V and Vout is output as Low. Thus, the memory cell can be read.

According to the above method, the voltage value is read by utilizing the difference in resistance value of the memory element 241 and the resistance division. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. In addition, when the electrical characteristics of the memory cell have data “0” and “1” and diode characteristics with different threshold voltages, reading may be performed using the threshold voltage difference.

  In this embodiment, application examples of a semiconductor device including the above-described memory circuit and capable of inputting and outputting data without contact will be described below with reference to the drawings. A semiconductor device in which data can be input / output without contact is also referred to as an RFID tag, an ID tag, an IC tag, an IC chip, an RF tag, a wireless tag, an electronic tag, or a wireless chip depending on the application.

  The semiconductor device 800 has a function of exchanging data without contact, and controls a high frequency circuit 810, a power supply circuit 820, a reset circuit 830, a clock generation circuit 840, a data demodulation circuit 850, a data modulation circuit 860, and other circuits. A control circuit 870, a memory circuit 880, and an antenna 890 are provided (FIG. 11). The high-frequency circuit 810 is a circuit that receives a signal from the antenna 890 and outputs the signal received from the data modulation circuit 860 from the antenna 890, and the power supply circuit 820 is a circuit that generates a power supply potential from the received signal, and a reset circuit 830. Is a circuit that generates a reset signal, the clock generation circuit 840 is a circuit that generates various clock signals based on the reception signal input from the antenna 890, and the data demodulation circuit 850 demodulates the reception signal to control the circuit 870. The data modulation circuit 860 is a circuit that modulates the signal received from the control circuit 870. As the control circuit 870, for example, a code extraction circuit 910, a code determination circuit 920, a CRC determination circuit 930, and an output unit circuit 940 are provided. The code extraction circuit 910 is a circuit that extracts a plurality of codes included in the instruction sent to the control circuit 870, and the code determination circuit 920 compares the extracted code with a code corresponding to a reference. The CRC determination circuit 930 is a circuit that detects the presence or absence of a transmission error or the like based on the determined code.

  Next, an example of operation of the above-described semiconductor device will be described. First, a radio signal is received by the antenna 890. The wireless signal is sent to the power supply circuit 820 via the high frequency circuit 810, and a high power supply potential (hereinafter referred to as VDD) is generated. VDD is supplied to each circuit included in the semiconductor device 800. The signal sent to the data demodulation circuit 850 via the high frequency circuit 810 is demodulated (hereinafter, demodulated signal). Further, the signal passing through the reset circuit 830 and the demodulated signal passing through the clock generation circuit 840 are sent to the control circuit 870 via the high frequency circuit 810. The signal sent to the control circuit 870 is analyzed by the code extraction circuit 910, the code determination circuit 920, the CRC determination circuit 930, and the like. Then, information on the semiconductor device stored in the memory circuit 880 is output in accordance with the analyzed signal. The output semiconductor device information is encoded through the output unit circuit 940. Further, the encoded information of the semiconductor device 800 passes through the data modulation circuit 860 and is transmitted on the radio signal by the antenna 890. Note that a low power supply potential (hereinafter referred to as VSS) is common in the plurality of circuits included in the semiconductor device 800, and VSS can be GND. Further, the memory circuit described in the above embodiment can be applied to the memory circuit 880.

  As described above, a signal is transmitted from the reader / writer to the semiconductor device 800, and the signal transmitted from the semiconductor device 800 is received by the detector (for example, the reader / writer), thereby reading the data of the semiconductor device. It becomes possible.

  Further, the semiconductor device 800 may be of a type in which power supply voltage is supplied to each circuit by electromagnetic waves without mounting a power supply (battery), or each circuit is mounted by electromagnetic waves or power supply (battery). It is good also as a type which supplies a power supply voltage to.

  Next, an example of the structure of the semiconductor device will be described with reference to the drawings. A top view of the semiconductor device of this embodiment is shown in FIG. 12A, and a cross-sectional structure taken along line XY in FIG. 12A is shown in FIG.

As shown in FIG. 12A, the semiconductor device is provided with a memory circuit 404, an integrated circuit portion 421, and an antenna 431 over a substrate 400. The storage circuit 404 shown in FIG. 12 corresponds to the storage circuit 880 shown in FIG. 11, and the integrated circuit portion 421 includes the high-frequency circuit 810, the power supply circuit 820, the reset circuit 830, the clock generation circuit 840, and the data demodulation circuit shown in FIG. 850, the data modulation circuit 860, and the control circuit 870, and the antenna 431 corresponds to the antenna 890 shown in FIG.

As shown in FIG. 12B, the element formation layer 403 is sandwiched between substrates 400 and 401 in the semiconductor device. The element formation layer 403 and the substrates 400 and 401 are fixed by adhesives 406 and 405, respectively. In the element formation layer 403, an insulating layer 453 and a transistor 442 are formed. An insulating layer 454 is formed over the transistor 442, and a wiring and a memory cell array 433 are formed in the insulating layer 454. In addition, the conductive layer 430 and the antenna 431 are formed over the insulating layer 455 and the wiring, and the insulating layer 432 is formed over the antenna 431 and the insulating layer 455. The conductive layer 430 and the antenna 431 are connected to a wiring 456 formed over the insulating layer 454 in an opening formed in the insulating layer 455. The wiring 456 is connected to a high-frequency circuit that is part of the integrated circuit. Further, although the memory circuit 404 includes the memory circuit described in the above embodiment and the integrated circuit portion 421 includes the transistor 442, the memory circuit 404 includes a resistor, a capacitor, a rectifier, and the like.

In this embodiment, the insulating layer 455 is formed using a polyimide layer, the conductive layer 430 is a conductive layer in which a titanium layer, an aluminum layer, and a titanium layer are stacked, and the antenna 431 is formed by a printing method. Each layer is used. The insulating layer 432 is formed in order to reduce unevenness of the antenna 431, and is preferably formed by applying a composition by a coating method, drying, and baking. Here, the insulating layer 432 is formed using an epoxy resin layer. A PEN film is used for the substrates 400 and 401, and a thermoplastic resin is used for the adhesives 406 and 405.

Note that the antenna may be provided so as to overlap with the memory circuit or may be provided around the memory circuit without overlapping. When overlapping, the entire surface may overlap, or a structure where a part overlaps may be used. The structure in which the antenna unit and the memory circuit overlap can reduce the malfunction of the semiconductor device due to the noise etc. on the signal when the antenna communicates and the fluctuation of electromotive force generated by electromagnetic induction. This is possible and improves reliability. In addition, the semiconductor device can be reduced in size.

As a signal transmission method in the semiconductor device capable of inputting / outputting non-contact data described above, an electromagnetic coupling method, an electromagnetic induction method, a microwave method, or the like can be used. The transmission method may be appropriately selected by the practitioner in consideration of the intended use, and an optimal antenna may be provided according to the transmission method.

For example, when an electromagnetic coupling method or an electromagnetic induction method (for example, 13.56 MHz band) is applied as a signal transmission method in a semiconductor device, the antenna 431 is formed in a ring shape (for example, in order to use electromagnetic induction due to a change in magnetic field density). , Loop antenna), and spiral (for example, spiral antenna).

In addition, when a microwave method (for example, UHF band (860 to 960 MHz band), 2.45 GHz band, or the like) is applied as a signal transmission method in a semiconductor device, the wavelength of an electromagnetic wave used for signal transmission is considered. For example, the antenna 431 may be formed in a linear shape (for example, a dipole antenna), a flat shape (for example, a patch antenna), a ribbon shape, or the like. it can. The shape of the antenna 431 is not limited to a linear shape, and may be provided in a curved shape, a meandering shape, or a combination thereof in consideration of the wavelength of electromagnetic waves.

The antenna 431 is formed using a conductive material by a CVD method, a sputtering method, a printing method such as screen printing or gravure printing, a droplet discharge method, a dispenser method, a plating method, or the like. Conductive materials are aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), platinum (Pt) nickel (Ni), palladium (Pd), tantalum (Ta), molybdenum An element selected from (Mo) or an alloy material or a compound material containing these elements as a main component is formed in a single layer structure or a laminated structure.

For example, when an antenna is formed using a screen printing method, a conductive paste in which conductive particles having a particle diameter of several nanometers to several tens of micrometers are dissolved or dispersed in an organic resin is selectively printed and dried. And it can provide by baking. Conductor particles include silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo) and titanium (Ti). Any one or more metal particles, silver halide fine particles, or dispersible nanoparticles can be used. In addition, as the organic resin contained in the conductive paste, one or more selected from organic resins functioning as a binder of metal particles, a solvent, a dispersant, and a coating material can be used. Typically, an organic resin such as an epoxy resin or a silicone resin can be given. In addition to the materials described above, ceramic, ferrite, or the like may be applied to the antenna.

Further, in the case where an electromagnetic coupling method or an electromagnetic induction method is applied and a semiconductor device provided with an antenna is provided in contact with a metal, a magnetic material having a permeability between the semiconductor device and the metal is used. It is preferable to provide it. When a semiconductor device provided with an antenna is provided in contact with a metal, an eddy current flows in the metal as the magnetic field changes, and the change in the magnetic field is weakened by the demagnetizing field generated by the eddy current, thereby reducing the communication distance. . Therefore, by providing a material having magnetic permeability between the semiconductor device and the metal, it is possible to suppress the eddy current of the metal and suppress the decrease in the communication distance. As the magnetic material, ferrite or metal thin film having high magnetic permeability and low high-frequency loss can be used.

In this embodiment, a semiconductor device in which a semiconductor element such as a transistor and an antenna are directly formed in the element formation layer is shown; however, the present invention is not limited to this. For example, the semiconductor element and the antenna may be provided over different substrates and then bonded to be electrically connected.

According to the present invention, it is possible to manufacture a semiconductor device having a nonvolatile memory element that can additionally record data other than at the time of manufacturing and can prevent forgery or the like due to rewriting. In addition, a highly reliable and inexpensive semiconductor device can be manufactured.

  There are a wide range of uses for semiconductor devices that can input and output data without contact. For example, banknotes, coins, securities, bearer bonds, certificate documents (driver's license, resident's card, etc., see FIG. 13A) ), Packaging containers (wrapping paper, bottles, etc., see FIG. 13C), recording media (DVD software, video tape, etc., see FIG. 13B), vehicles (bicycles, FIG. 13D) See), personal items (such as bags and glasses), foods, plants, clothing, daily necessities, electronic products, etc., and goods such as luggage tags (see FIGS. 13E and 13F) Can be used. Moreover, it can provide in animals and a human body. Electronic devices refer to liquid crystal display devices, EL (Electro Luminescence) display devices, television devices (also simply referred to as televisions, television receivers, television receivers), mobile phones, and the like.

  The semiconductor device 9210 of the present invention is fixed to an article by mounting on a printed board, sticking to a surface, embedding, or the like. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin, and is fixed to each article. Since the semiconductor device 9210 of the present invention is small, thin, and lightweight, it does not impair the design of the article itself even after being fixed to the article. In addition, by providing the semiconductor device 9210 of the present invention for bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and forgery can be prevented by using this authentication function. Can do. Further, by providing the semiconductor device 9210 of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., it is possible to improve the efficiency of systems such as inspection systems. .

  Next, an example of a usage pattern of a semiconductor device capable of inputting and outputting data without contact will be described. A detector (eg, a reader / writer) 3200 is provided on the side surface of the portable terminal including the display portion 3210, and a semiconductor device 3230 is provided on the side surface of the article 3220 (FIG. 14A). When a detector (for example, a reader / writer) 3200 is placed over a semiconductor device 3230 included in the item 3220, the raw material and origin of the item, the inspection results for each production process, the history of distribution processes, etc., further explanation of the product, etc. Information about the product is displayed. Further, when the product 3260 is conveyed by the belt conveyor, the product 3260 can be inspected by using the detector (eg, reader / writer) 3240 and the semiconductor device 3250 provided in the product 3260 (FIG. 14 (B)). In this manner, by using a semiconductor device in the system, information can be easily acquired, and high functionality and high added value are realized.

  Next, one mode of an electronic device in which the semiconductor device of the present invention is mounted will be described with reference to the drawings. The electronic device illustrated here is a mobile phone, which includes housings 2700 and 2706, a panel 2701, a housing 2702, a printed wiring board 2703, operation buttons 2704, and a battery 2705 (see FIG. 15). The panel 2701 is detachably incorporated in the housing 2702, and the housing 2702 is fitted on the printed wiring board 2703. The shape and dimensions of the housing 2702 are changed as appropriate in accordance with the electronic device in which the panel 2701 is incorporated. A plurality of packaged semiconductor devices are mounted on the printed wiring board 2703, and the semiconductor device 2710 of the present invention can be used as one of them. A plurality of semiconductor devices mounted on the printed wiring board 2703 have any one function of a controller, a central processing unit (CPU), a memory circuit, a power supply circuit, a sound processing circuit, a transmission / reception circuit, and the like.

  The panel 2701 is connected to the printed wiring board 2703 through the connection film 2708. The panel 2701, the housing 2702, and the printed wiring board 2703 are housed in the housings 2700 and 2706 together with the operation buttons 2704 and the battery 2705. A pixel region 2709 included in the panel 2701 is arranged so as to be visible from an opening window provided in the housing 2700.

  As described above, the semiconductor device of the present invention is characterized in that it is small, thin, and lightweight, and the limited space inside the housings 2700 and 2706 of the electronic device can be effectively used due to the above characteristics. .

  In addition, since the semiconductor device of the present invention includes a memory element having a simple structure in which an organic compound layer that is changed by external voltage application is sandwiched between a pair of conductive layers, an electronic device using an inexpensive semiconductor device is provided. can do. In addition, since the semiconductor device of the present invention can be easily integrated, an electronic device using the semiconductor device including a large-capacity memory circuit can be provided.

  In addition, a semiconductor device included in the semiconductor device of the present invention writes data by applying voltage from the outside, is nonvolatile, and can additionally write data. With the above feature, forgery due to rewriting can be prevented, and new data can be added and written. Therefore, an electronic device using a semiconductor device that achieves high functionality and high added value can be provided.

  Note that the housings 2700 and 2706 are examples of the appearance of a mobile phone, and the electronic device according to the present embodiment can be transformed into various modes depending on the function and application.

4A and 4B are a top view and a cross-sectional view illustrating a semiconductor device of the invention. FIG. 11 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. FIG. 11 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. 4A and 4B are a top view and a cross-sectional view illustrating a semiconductor device of the invention. FIG. 11 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. 4A and 4B are a top view and a cross-sectional view illustrating a semiconductor device of the invention. FIG. 11 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. It is a figure explaining the semiconductor device of the present invention. 4A and 4B are a top view and a cross-sectional view illustrating a semiconductor device of the invention. It is a figure explaining the semiconductor device of the present invention. It is a figure explaining the semiconductor device of the present invention. 4A and 4B are a top view and a cross-sectional view illustrating a semiconductor device of the invention. It is a figure which shows the example of application of the semiconductor device of this invention. It is a figure which shows the example of application of the semiconductor device of this invention. It is a figure which shows the example of application of the semiconductor device of this invention. It is a diagram showing a structure of a transistor applicable to the present invention. It is a top view illustrating a semiconductor device of the present invention. It is a top view explaining the conventional semiconductor device. It is sectional drawing explaining this invention and the conventional semiconductor device.

Claims (7)

Substrate upper side, a first conductive layer, and the connection wiring,
An insulating layer above the substrate, the first conductive layer, and the connection wiring;
An organic compound layer above the first conductive layer , the connection wiring , and the insulating layer ;
A second conductive layer above the organic compound layer,
The first conductive layer extends in a first direction;
The connection wiring extends in a second direction intersecting the first direction;
The second conductive layer extends in the second direction;
The first conductive layer, the organic compound layer, and the second conductive layer form a memory element in an opening of the insulating layer ,
The connection wiring and the second conductive layer, wherein a is electrically connected at the opening of the organic compound layer. In claim 1,
The connection wiring to a semiconductor device characterized by being formed simultaneously with the first conductive layer. In claim 1 or 2 ,
A semiconductor device, wherein a rectifying element is connected to the memory element. In any one of Claims 1 thru | or 3 ,
A semiconductor device, wherein a switching element is connected to the first conductive layer. Towards the substrate, forming a first conductive layer and connection wiring at the same time,
Forming an insulating layer on the substrate, the first conductive layer, and the connection wiring;
After removing a part of the insulating layer to expose the first conductive layer and a part of the connection wiring , an organic compound layer is formed above the first conductive layer , the connection wiring , and the insulation layer. Forming,
After removing a part of the organic compound layer and exposing a part of the connection wiring, a second conductive layer is formed on the organic compound layer and an exposed part of the connection wiring,
The method for manufacturing a semiconductor device, wherein the connection wiring and the second conductive layer are electrically connected at an exposed portion of the connection wiring. In claim 5 ,
A method for manufacturing a semiconductor device, wherein a part of the organic compound layer is irradiated with laser light to remove a part of the organic compound layer. Towards the substrate, forming a first conductive layer and connection wiring at the same time,
Forming an insulating layer on the substrate, the first conductive layer, and the connection wiring;
After removing a part of the insulating layer to expose the first conductive layer and a part of the connection wiring , an organic compound layer is formed above the first conductive layer , the connection wiring , and the insulation layer. Forming,
The organic compound layer on side, forming a second conductive layer,
A region where the connection wiring, the organic compound layer, and the second conductive layer overlap is irradiated with laser light to melt the organic compound layer and the second conductive layer, thereby the connection wiring and the second conductive layer. A method for manufacturing a semiconductor device, wherein layers are electrically connected.

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