JP5252827B2 - Memory element - Google Patents

Description

  The present invention relates to a memory element and a semiconductor device including the memory element.

  In recent years, development of semiconductor devices having various functions in which a plurality of circuits are integrated on an insulating surface has been promoted. In addition, development of a semiconductor device capable of transmitting and receiving data wirelessly by providing an antenna is in progress. Such semiconductor devices are called wireless chips (also called ID tags, IC tags, RF (Radio Frequency) tags, wireless tags, electronic tags, RFID (Radio Frequency Identification) tags) and have already been introduced in some markets. Has been.

Many of these semiconductor devices in practical use have a circuit (also referred to as an IC (Integrated Circuit) chip) using a semiconductor substrate such as Si and an antenna, and the IC chip includes a memory circuit ( Memory) and a control circuit. In particular, by providing a memory circuit capable of storing a large amount of data, a semiconductor device with higher functions and higher added value can be provided. In addition, these semiconductor devices are required to be manufactured at low cost. In recent years, an organic memory using an organic compound for a memory circuit or the like has been developed (for example, see Non-Patent Document 1).
S. Moller and 4 others, NATURE, Vol426, p166-p199 (2003)

  However, when a layer containing an organic compound is provided between a pair of electrodes as in Non-Patent Document 1, if the layer containing an organic compound is formed thin in order to reduce the writing voltage, the electrodes may be short-circuited in the initial state. is there. In addition, an initial failure occurs in a semiconductor device having such a memory element.

  In general, a memory circuit provided in a semiconductor device includes a DRAM (Dynamic Random Access Memory), a SRAM (Static Random Access Memory), a FeRAM (Ferroelectric Random Access Memory), a mask ROM (Read ROM, Read ROM, and Read ROM). Examples thereof include Programmable Read Only Memory (EEPROM), EEPROM (Electrically Erasable and Programmable Read Only Memory), and flash memory. Among these, DRAM and SRAM are volatile storage circuits, and data is erased when the power is turned off. Therefore, it is necessary to write data every time the power is turned on. FeRAM is a non-volatile memory circuit, but a manufacturing process increases because a capacitor element including a ferroelectric layer is used. Although the mask ROM has a simple structure, it is necessary to write data at the time of manufacture and cannot be additionally written. Although EPROM, EEPROM, and flash memory are non-volatile memory circuits, the number of manufacturing steps increases because an element including two gate electrodes is used.

  In view of the above problems, an object of the present invention is to provide a memory element with reduced initial defects and a semiconductor device having the memory element. It is another object of the present invention to provide a nonvolatile memory element that can additionally record data other than at the time of manufacture and can prevent forgery and the like due to rewriting, and a semiconductor device having the memory element.

  In order to solve the above problems, a memory element of the present invention includes a first conductive layer, a second conductive layer, and a compound exhibiting liquid crystallinity sandwiched between the first conductive layer and the second conductive layer. A layer including an organic compound in contact with a layer including a compound including liquid crystallinity and sandwiched between the first conductive layer and the second conductive layer and including a compound exhibiting liquid crystallinity. The layer is formed in contact with the first conductive layer, and is a layer that undergoes a phase transition from at least the first phase to the second phase.

  According to another structure of the memory element of the present invention, the layer containing a compound exhibiting liquid crystallinity has a first change due to a temperature change caused by applying a voltage between the first conductive layer and the second conductive layer. It is characterized in that the phase transition from the phase to the second phase.

  Another structure of the memory element of the present invention is characterized in that the first phase of the layer containing a compound exhibiting liquid crystallinity is in a solid state and the second phase is in a liquid crystal state or a liquid state. Note that in this specification, a compound exhibiting liquid crystallinity means a compound that can be in a liquid crystal state by phase transition. Therefore, a compound that does not exhibit liquid crystallinity in a solid state or a liquid state is included in a category although it can be in a liquid crystal state by phase transition.

  In another structure of the memory element of the present invention, the layer containing an organic compound is a layer containing an organic resin, a layer containing an organic compound having a hole transporting property, or a layer containing an organic compound having an electron transporting property. It is characterized by that.

  The semiconductor device of the present invention includes a memory cell array in which a plurality of memory cells are provided in a matrix, a circuit for selecting at least one of the plurality of memory cells and writing data, and at least one of the plurality of memory cells. Each of the plurality of memory cells is provided with at least a storage element, and the storage element is sandwiched between a pair of conductive layers and a pair of conductive layers, And a layer containing a compound exhibiting liquid crystallinity in contact with the layer and a layer containing an organic compound sandwiched between a pair of conductive layers and in contact with the layer containing a compound exhibiting liquid crystallinity.

  According to another configuration of the semiconductor device of the present invention, a memory cell array in which a plurality of memory cells are provided in a matrix, a circuit for selecting at least one of the plurality of memory cells and writing data, and the plurality of memory cells Each of the plurality of memory cells is provided with at least a storage element and a transistor connected to the storage element. The storage element includes a pair of conductive layers. A layer containing a compound exhibiting liquid crystallinity sandwiched between a pair of conductive layers and in contact with one conductive layer; a layer including an organic compound sandwiched between a pair of conductive layers and in contact with a layer containing a compound exhibiting liquid crystallinity; It is characterized by having.

  In another structure of the semiconductor device of the present invention, a layer containing a compound exhibiting liquid crystallinity transitions from a solid state to a liquid crystal state or a liquid state due to a temperature change caused by applying a voltage between a pair of conductive layers. It is a layer.

  In another configuration of the semiconductor device of the present invention, the layer containing an organic compound is a layer containing an organic resin, a layer containing an organic compound having a hole transporting property, or a layer containing an organic compound having an electron transporting property. It is characterized by that.

  Another structure of the semiconductor device of the present invention is characterized in that a memory cell array, a circuit for writing data, and a circuit for reading data are provided over a glass substrate.

  According to the present invention, a memory element in which an initial failure hardly occurs and a semiconductor device including the memory element can be obtained. Accordingly, the yield of the memory element and the semiconductor device including the memory element can be improved.

  Further, according to the present invention, it is possible to provide a memory element in which data can be written (added) other than at the time of manufacturing and forgery due to rewriting can be prevented, and a semiconductor device including the memory element.

  Hereinafter, the best mode for carrying out the invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and it is easy for those skilled in the art to make various changes in form and details without departing from the spirit and scope of the present invention. To be understood. Therefore, the present invention should not be construed as being limited to the description of the embodiment modes.

(Embodiment 1)
An example of the memory element of the present invention will be described with reference to FIGS. The memory element of the present invention includes a layer containing an organic compound between a pair of conductive layers (hereinafter also referred to as an organic compound layer) and a layer containing a compound exhibiting liquid crystallinity in contact with the organic compound layer (hereinafter also referred to as a liquid crystal layer). It is set as the structure which has.

  A memory element 110 illustrated in FIG. 1 has a structure in which a first conductive layer 102, a liquid crystal layer 104, an organic compound layer 106, and a second conductive layer 108 are sequentially stacked over a substrate 100. The liquid crystal layer 104 and the organic compound layer 106 are sandwiched between the first conductive layer and the second conductive layer. That is, the liquid crystal layer 104 is provided in contact with the first conductive layer 102 and the organic compound layer 106. The organic compound layer 106 is provided in contact with the liquid crystal layer 104 and the second conductive layer 108.

  As the substrate 100, a glass substrate, a flexible substrate, a quartz substrate, a semiconductor substrate, a metal substrate, a stainless steel substrate, paper made of a fibrous material, or the like can be used. The flexible substrate is a substrate that can be bent (hereinafter also referred to as flexible). For example, a plastic substrate made of polycarbonate, polyacrylate, polyether sulfone, or the like can be given. In addition, a film showing thermoplasticity (polyolefin, polyolefin containing fluorine, polyester, or the like) can also be used.

  Note that the memory element 110 may be provided above a field effect transistor (FET) formed on a semiconductor substrate such as Si or above a thin film transistor (hereinafter also referred to as TFT) formed on a substrate such as glass. it can.

  The first conductive layer 102 or the second conductive layer 108 can be formed using a metal, an alloy thereof, a metal compound, an oxide conductive material, or the like. Specifically, gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), A kind of element selected from copper (Cu), palladium (Pd), carbon (C), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta) or the like, or an alloy containing a plurality of such elements. Can be used. Alternatively, a nitride of the metal, for example, titanium nitride (TiN), tungsten nitride (WN), molybdenum nitride, or the like can be used. In addition, alkali metals such as lithium (Li) and cesium (Cs), and alkaline earth metals such as magnesium (Mg), calcium (Ca), and strontium (Sr), and alloys containing any of these (MgAg, AlLi ), Rare earth metals such as europium (Er) and ytterbium (Yb), and alloys containing these.

  The first conductive layer 102 or the second conductive layer 108 is made of indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc oxide (GZO) added with gallium, or silicon oxide. A light-transmitting oxide conductive material such as indium tin oxide (hereinafter referred to as ITSO) can be used. In addition, it can be formed by a sputtering method using a target in which 2 wt% to 20 wt% zinc oxide (ZnO) is mixed with indium oxide containing silicon oxide.

  The first conductive layer 102 or the second conductive layer 108 can be formed using the above-described material with a single-layer structure or a stacked structure by an evaporation method, a sputtering method, a printing method, or a droplet discharge method.

  The liquid crystal layer 104 can be formed using a compound exhibiting liquid crystallinity that undergoes phase transition from at least a first phase to a second phase due to a temperature change. In addition, the compound which shows liquid crystallinity means the compound which can be in a liquid crystal state by a phase transition. Therefore, a compound that does not exhibit liquid crystallinity in a solid state or a liquid state is included in a category although it can be in a liquid crystal state by phase transition. That is, the liquid crystal layer 104 can be formed using a compound that can exhibit liquid crystallinity by phase transition. The liquid crystal layer 104 is formed using a compound that at least undergoes a phase transition from the first phase to the second phase due to a temperature change and forms a mixture with the conductive layer in contact with the conductive layer (the first conductive layer 102 in this embodiment). Can be formed. Specifically, high molecular liquid crystals as shown in the following structural formulas (1) to (4), low molecular liquid crystals as shown in the following structural formulas (5) to (8), and the following structural formulas (9) to (12). ), Fluorine-containing liquid crystals as shown in the following structural formulas (14) and (16), and metal complex liquid crystals as shown in the following general formulas (13) and (15), as shown in the following general formulas (17) and (18). Such an organometallic polymer liquid crystal can be used.

（但し、式中、Ｒはアルキル基、アルコキシル基、アリール基またはシアノ基を表す。）

（但し、式中、Ｒはアルキル基、アルコキシル基、アリール基またはシアノ基を表す。Ｍはニッケル（Ｎｉ）または白金（Ｐｔ）を表す。）

（但し、式中、Ｍはニッケル（Ｎｉ）、パラジウム（Ｐｄ）または白金（Ｐｔ）を表す。）

（但し、式中、Ｍはニッケル（Ｎｉ）、パラジウム（Ｐｄ）または白金（Ｐｔ）を表す。）

(In the formula, R represents an alkyl group, an alkoxyl group, an aryl group or a cyano group.)

(In the formula, R represents an alkyl group, an alkoxyl group, an aryl group, or a cyano group. M represents nickel (Ni) or platinum (Pt).)

(In the formula, M represents nickel (Ni), palladium (Pd), or platinum (Pt).)

(In the formula, M represents nickel (Ni), palladium (Pd), or platinum (Pt).)

  The liquid crystal layer 104 can be formed by a liquid crystal dropping method, an inkjet method, an evaporation method, or a spin coating method. For example, the liquid crystal layer 104 can be formed by dropping a liquid crystal compound or a liquid crystal compound in a molten state or a solution state over the first conductive layer 102 using a dispenser device or an ink jet device. it can. The dropping of the compound exhibiting liquid crystallinity or the compound exhibiting liquid crystallinity in a molten state or a solution state can be performed under atmospheric pressure or reduced pressure. In the case where a compound exhibiting liquid crystallinity or a compound exhibiting liquid crystallinity in a molten state or a solution state is dropped, a substance exhibiting liquid crystallinity that has been defoamed under reduced pressure in advance may be used. Further, the substrate 100 may be heated while the compound exhibiting liquid crystallinity or the compound exhibiting liquid crystallinity in a molten state or a solution state is being dropped. In the present specification, the term “under reduced pressure” means that the pressure is lower than the atmospheric pressure.

  The organic compound layer 106 can be formed with a single-layer structure or a stacked structure using an organic compound whose crystal state, resistance value, or shape changes by an electrical action. Specifically, organic resins such as polyimides, polyacrylic acid esters, and polymethacrylic acid esters, organic compounds having a hole transporting property, or organic compounds having an electron transporting property can be used.

As the organic compound having a hole-transport property, 4,4′-bis [N- (1-naphthyl) -N-phenylamino] biphenyl (abbreviation: α-NPD), 4,4′-bis [N- ( 3-methylphenyl) -N-phenylamino] biphenyl (abbreviation: TPD), 4,4 ′, 4 ″ -tris (N, N-diphenylamino) triphenylamine (abbreviation: TDATA), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenylamino] triphenylamine (abbreviation: MTDATA), N, N′-bis [4- [bis (3-methylphenyl) amino] phenyl] An aromatic amine-based compound (that is, having a benzene ring-nitrogen bond) such as —N, N′-diphenyl- [1,1′-biphenyl] -4,4′-diamine (abbreviation: DNTPD) It is done. In addition, phthalocyanine compounds such as phthalocyanine (abbreviation: H ₂ Pc), copper phthalocyanine (abbreviation: CuPc), and vanadyl phthalocyanine (abbreviation: VOPc) can also be used. The compounds described here mainly have a hole mobility of 10 ⁻⁶ cm ² / Vs or higher.

As an organic compound having an electron transporting property, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo) [H] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), and other metal complexes having a quinoline skeleton or a benzoquinoline skeleton The material which consists of is mentioned. In addition, bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) A material such as a metal complex having an oxazole-based or thiazole-based ligand such as ₂ ) can be used. In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- ( 4-biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2, 4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), and the like can be used. The compounds described here mainly have an electron mobility of 10 ⁻⁶ cm ² / Vs or higher. Note that the organic compound layer 106 can be formed by an evaporation method, an electron beam evaporation method, a sputtering method, an inkjet method, or a spin coating method. In the case where the organic compound layer 106 is formed using a plurality of materials, the organic compound layer 106 can be formed by simultaneously forming each material. For example, co-evaporation method by resistance heating evaporation, co-evaporation method by electron beam evaporation, co-evaporation method by resistance heating evaporation and electron beam evaporation, film formation by resistance heating evaporation and sputtering, film formation by electron beam evaporation and sputtering, etc. It can be formed by combining the same type and different types of methods.

  In the memory element of the present invention, when a voltage is applied between a pair of conductive layers including a first conductive layer and a second conductive layer, a crystal state, a resistance value, or a shape of the organic compound layer changes, and a liquid crystal The layer undergoes a phase transition. Specifically, the organic compound layer changes its crystal state, resistance value, or shape of the organic compound layer when a voltage of a predetermined value or more is applied. In addition, the liquid crystal layer undergoes a phase transition from the first phase to the second phase due to a temperature change caused by voltage application for a predetermined value and for a predetermined period or longer, and then comes into contact with the conductive layer (in this embodiment, the first conductive layer). Layer) and a mixture. The region where the liquid crystal layer and the first conductive layer form a mixture functions as the first conductive layer. That is, the portion functioning as the liquid crystal layer before voltage application functions as a conductive layer by applying voltage. Then, the first conductive layer and the second conductive layer including a region in which the liquid crystal layer and the conductive layer in contact with the liquid crystal layer form a mixture are short-circuited (hereinafter also referred to as short-circuit), or the liquid crystal layer and the liquid crystal layer When the resistance value of the organic compound layer between the first conductive layer and the second conductive layer including the region in which the conductive layer in contact with the first conductive layer is changed, the electric resistance of the memory element changes. As described above, since the electrical resistance of the memory element of the present invention changes before and after the voltage application, the memory element before the voltage application is set to the “initial state”, and the memory element in which the electrical resistance after the voltage application is changed is “written”. By setting the “state”, two values can be stored. The solid state (or crystal state) of the liquid crystal layer is the first phase, and the liquid crystal state or liquid state (or isotropic liquid state) of the liquid crystal layer is the second phase.

  Next, the estimated operation principle of the memory element of the present invention will be described in detail with reference to FIG.

  A memory element 110 illustrated in FIG. 2A corresponds to the memory element 110 in FIG. 1 described above. That is, the memory element 110 has a structure in which the first conductive layer 102, the liquid crystal layer 104, the organic compound layer 106, and the second conductive layer 108 are sequentially stacked over the substrate 100. In addition, the memory element 110 illustrated in FIG. 2A is in a state before voltage application, and the liquid crystal layer 104 is in a solid state. Note that the solid state of the liquid crystal layer 104 is a first phase.

  In the memory element illustrated in FIGS. 2B1 and 2B2, a voltage is applied between the first conductive layer and the second conductive layer, so that the liquid crystal layer shifts from the first phase to the second phase. And a phase transition. Specifically, the liquid crystal layer is in a state of phase transition from a solid state to a liquid crystal state, or from a solid state to a liquid state. Note that FIG. 2B1 illustrates the case where only the liquid crystal layer is changed by application of voltage. On the other hand, FIG. 2B2 illustrates the case where the liquid crystal layer undergoes phase transition and the organic compound layer is deformed by voltage application. The memory element of the present invention may be in any of the states shown in FIGS. 2B1 and 2B2.

  In the memory element illustrated in FIG. 2B1, the liquid crystal layer 114 is in a liquid crystal state or a liquid state. Note that the liquid crystal state or the liquid state of the liquid crystal layer 114 is a second phase. At this time, the shape of the organic compound layer 106 has not changed. Note that the crystal state or resistance value of the organic compound layer 106 may be changed. In the memory element illustrated in FIG. 2B1, since the liquid crystal layer 114 is provided, the electrical resistance of the memory element itself is not significantly changed.

  In the memory element illustrated in FIG. 2B2, the liquid crystal layer 114 is in a liquid crystal state or a liquid state. Note that the liquid crystal state or the liquid state of the liquid crystal layer 114 is a second phase. Further, the shape of the organic compound layer 106 is changed by application of a voltage. Further, as the shape of the organic compound layer 106 changes, the second conductive layer 108 is deformed, and the second conductive layer 108 and the liquid crystal layer 114 are partially in contact with each other. At this time, since the liquid crystal layer 114 exists between the second conductive layer 108 and the first conductive layer 102, the electrical resistance of the memory element is not significantly changed. Note that in FIG. 2B 2, the organic compound layer 106 may have a changed crystal state or resistance value in addition to the change in the shape of the organic compound layer 106.

  In the memory element illustrated in FIG. 2C1, a voltage that is higher than or equal to a predetermined value and a predetermined period is applied between the first conductive layer 102 and the second conductive layer 108 so that the liquid crystal layer is in contact with the liquid crystal layer. In this state, a mixture is formed with the conductive layer. A region where a mixture is formed at a portion where the liquid crystal layer and the first conductive layer are in contact with each other is referred to as a mixture region 124. The mixture region 124 functions as the first conductive layer 122. Further, the crystal state or the resistance value of the organic compound layer 106 is changed by application of a voltage. Therefore, only the organic compound layer 106 is sandwiched between the first conductive layer 122 and the second conductive layer 108, and the electric resistance of the memory element is changed by a change in the crystal state or the resistance value of the organic compound layer 106. Changes.

  In the memory element illustrated in FIG. 2C2, the first conductive layer 102 is in contact with the liquid crystal layer by applying a voltage of a predetermined value and a predetermined period or more between the first conductive layer 102 and the second conductive layer 108. In this state, a mixture is formed with the conductive layer. A region where a mixture is formed at a portion where the liquid crystal layer and the first conductive layer are in contact with each other is referred to as a mixture region 124. The mixture region 124 functions as the first conductive layer 122. Further, the shape of the organic compound layer 106 is changed by application of a voltage. Therefore, the first conductive layer 122 including the mixture region 124 and the deformed second conductive layer 108 are short-circuited, and the electric resistance of the memory element changes.

  As described above, the electrical resistance of the memory element of the present invention changes, and data can be written using the change in electrical resistance. In the memory element of the present invention, the liquid crystal layer forms a mixture with the first conductive layer, so that only the organic compound layer is sandwiched between the first conductive layer and the second conductive layer. The electrical resistance changes due to a change in the crystal state or resistance value of the sandwiched organic compound layer or a short circuit between the first conductive layer and the second conductive layer. Therefore, the change in electrical resistance of the memory element of the present invention is controlled by the phase transition of the liquid crystal layer.

  Note that since the memory element of the present invention is controlled by the liquid crystal layer, the course of change of the organic compound layer 106 due to the application of voltage is not limited to FIG.

  The memory element of the present invention can be thickened by providing a liquid crystal layer and an organic compound layer between the first conductive layer and the second conductive layer, and prevents initial defects such as a short circuit in the initial state. be able to.

(Embodiment 2)
An example of a memory element of the present invention and a semiconductor device having the memory element, typically a memory device, will be described with reference to FIGS. Specifically, an example of a passive matrix storage device will be described.

  FIG. 3A shows an example of a memory device of the present invention, which includes a memory cell array 10, a bit line driver circuit 32, a word line driver circuit 40, and an interface 30 provided over a substrate 20. .

  The memory cell array 10 includes a plurality of bit lines Bx (1 ≦ x ≦ m) extending in the x direction and a plurality of word lines Wy (1 ≦ y ≦ n) extending in the y direction orthogonal to the x direction. It is configured. A memory cell 12 having a memory element 14 is provided at a portion where the bit line Bx and the word line Wy intersect. The memory cells 12 are provided in a matrix in the memory cell array 10.

  The bit line drive circuit 32 includes a column decoder 34, a read / write circuit 36, and a selector 38. The bit line driving circuit 32 is connected to the bit line Bx and the interface 30.

  The word line driving circuit 40 includes a row decoder 42 and a level shifter 44. The word line driving circuit 40 is connected to the word line Wy and the interface 30.

  The interface 30 is a circuit that supplies a signal input from the outside to the bit line driving circuit 32 or the word line driving circuit 40 or supplies a signal output from the bit line driving circuit 32 to the outside.

  Note that the structure illustrated in FIG. 3A is merely an example, and may include other circuits such as a sense amplifier, an output circuit, and a buffer circuit. In addition, a writing circuit may be provided in the interface 30.

  Next, the memory cell 12 will be described in detail with reference to FIG. FIG. 4A shows an example of a top view of the memory cell array 10. FIG. 4B illustrates an example of a cross-sectional view taken along dashed line OP in FIG. Note that in FIG. 4A, the structures other than the first conductive layer and the second conductive layer are partly omitted.

  The memory cell 12 is provided at a portion where the first conductive layer 22 constituting the bit line Bx and the second conductive layer 28 constituting the word line Wy intersect. Further, the memory cell 12 includes the memory element 14 as shown in the first embodiment. Note that the memory element 14 includes at least a first conductive layer, a liquid crystal layer in contact with the first conductive layer, an organic compound layer in contact with the liquid crystal layer, and a second conductive layer in contact with the organic compound layer. It is only necessary to have a structure in which the layers are sequentially stacked. Therefore, the memory element 14 can be configured as shown in FIG. Note that the memory element illustrated in FIG. 5 corresponds to a cross-sectional view taken along broken line OP or broken line QR in FIG.

  For example, as shown in FIG. 5A, a rectifying element may be provided on the side opposite to the organic compound layer 26 with the first conductive layer 22 interposed therebetween. The rectifying element is a Schottky diode, a diode having a PN junction, a diode having a PIN junction, or a transistor in which a gate electrode and a drain electrode are connected. Here, the diode 50 including the third conductive layer 52 and the semiconductor layer 54 is provided in contact with the first conductive layer 22. At this time, the semiconductor layer 54 is sandwiched between the first conductive layer 22 and the third conductive layer 52. Note that a rectifying element may be provided on the side opposite to the organic compound layer 26 with the second conductive layer 28 interposed therebetween. Also in this case, the semiconductor layer is sandwiched between the second conductive layer 28 and the third conductive layer. Further, a rectifying element may be provided between the organic compound layer 26 and the second conductive layer 28. Typical examples of the diode include a PN junction diode, a diode having a PIN junction, an avalanche diode, and the like. Moreover, you may use the diode of another structure. Thus, by providing an element having a rectifying property, the direction of current flow can be controlled in only one direction. Therefore, errors are reduced and read reliability is improved. Note that an insulating layer 55 for insulating the diode is provided between adjacent memory elements.

  Further, a thin film transistor (TFT) may be provided over an insulating substrate and the memory element 14 may be provided thereover, or a semiconductor substrate such as Si or an SOI substrate may be used instead of the insulating substrate. Alternatively, a field effect transistor (FET) may be formed, and a memory element 14 may be provided thereon. Note that although the example in which the memory element 14 is formed over a thin film transistor or a field effect transistor is shown here, the memory element 14 can be provided by bonding the thin film transistor or the field effect transistor. In this case, the memory element and the thin film transistor or the field effect transistor can be provided by being manufactured in separate steps and then bonded together using a conductive film, an anisotropic conductive adhesive, or the like. Further, any configuration of the thin film transistor or the field effect transistor may be used as long as it is a known one.

  In addition, when there is a concern about the influence of the electric field in the lateral direction between adjacent memory elements, the organic compound layer provided in each memory element is separated to separate the organic compound layer provided in each memory element. An insulating layer functioning as a partition wall (hereinafter also referred to as a partition layer) may be provided therebetween. Alternatively, an organic compound layer may be selectively provided for each memory cell.

  For example, as shown in FIG. 5B, when the liquid crystal layer 24 and the organic compound layer 26 are provided so as to cover the first conductive layer 22, a partition layer 56 is provided between the adjacent first conductive layers 22. Also good. With such a structure, it is possible to prevent the step of the liquid crystal layer 24 and the organic compound layer 26 caused by the step of the first conductive layer 22 and the influence of the electric field in the lateral direction between the memory cells. In the cross section of the partition layer 56, the side surface of the partition layer 56 preferably has an inclination angle of 10 degrees to less than 60 degrees, preferably 25 degrees to 45 degrees with respect to the surface of the first conductive layer 22. . Furthermore, it is preferable that it is curved. Thereafter, the liquid crystal layer 24, the organic compound layer 26, and the second conductive layer 28 are formed so as to cover the first conductive layer 22 and the partition wall layer 56.

  Alternatively, the partition wall layer 56 may be formed after the liquid crystal layer 24 is formed over the first conductive layer 22. In this case, it is preferable to form the partition wall layer 56 using a material that can form the liquid crystal layer 24 and a material that can have an etching selection ratio.

  Further, as shown in FIG. 5C, an interlayer insulating layer 62 that covers a part of the first conductive layer 22 provided on the substrate 20 and extends in the x direction, and a partition layer on the interlayer insulating layer 62 64 may be provided. Note that the interlayer insulating layer 62 has an opening at least for each memory element 14. The partition layer 64 is provided so as to extend in the y direction on a region where the opening of the interlayer insulating layer 62 is not formed. As for the cross section of the partition layer 64, it is preferable that the side wall of the partition layer 64 has an inclination angle of 95 ° to 135 ° with respect to the surface of the interlayer insulating layer 62.

  The material of the partition wall layer 64 is not particularly limited. For example, the partition wall layer 64 can be formed by a photolithography method using a positive photosensitive resin in which an unexposed portion remains. In this case, it is possible to form the partition wall layer having a preferable inclination angle by adjusting the exposure amount or the development time so that the lower part of the pattern to be the partition wall layer is etched more. The partition layer 64 may be formed by a photolithography method and an etching method using an inorganic insulating material, an organic insulating material, or the like.

  Further, the thickness of the interlayer insulating layer 62 and the partition wall layer 64 is set to be larger than the thickness of the liquid crystal layer 24, the organic compound layer 26, and the second conductive layer 28. As a result, only in the step of depositing the organic compound layer 26 and the second conductive layer 28 on the entire surface of the substrate 20, the stripes are separated into a plurality of electrically independent regions and extend in the y direction intersecting the x direction. The organic compound layer 26 and the second conductive layer 28 can be formed. Therefore, the number of processes can be reduced. Note that the liquid crystal layer 25, the organic compound layer 27, and the second conductive layer 29 are also formed over the partition layer 64, and these are the liquid crystal layer 24, the organic compound layer 26, and the second conductive layer that constitute the memory element 14. The layer 28 is separated.

  Next, an example of data writing operation in the storage device of the present invention will be described. For example, when data is written to the memory cell 12 located in the xth column and the yth row among the plurality of memory cells 12 provided in the memory cell array 10 shown in FIG. 3A, first, the row decoder 42, the column The decoder 34 and the selector 38 select the bit line Bx in the xth column and the word line Wy in the yth row, and select the memory cell 12 located at the intersection of the bit line Bx and the word line Wy. Then, data is written into the selected memory cell 12 using a writing circuit.

  The memory cell 12 has a storage element 14. As described in the first embodiment, the electrical resistance of the memory element 14 changes before and after voltage application. Therefore, data can be selectively written into the memory cell 12 by utilizing the change in the electrical resistance of the memory element.

  A specific operation when data is written to the storage device of the present invention will be described below with reference to FIG. Note that writing is performed by changing the electrical characteristics such as the electrical resistance of the memory cell. The initial state (state in which no electrical action is applied) of the memory cell is data “0”, and the state in which the electrical characteristic is changed is “ 1 ”.

  When data “1” is written in the memory cell 12, first, the memory cell 12 is selected by the row decoder 42, the level shifter 44, the column decoder 34, and the selector 38 shown in FIG. For example, when the memory cell 12 located at the intersection of the bit line B3 and the word line W3 is selected, a predetermined voltage V2 is applied to the word line W3 connected to the memory cell 12 by the row decoder 42 and the level shifter 44. . Further, the bit line B 3 connected to the memory cell 12 is connected to the read / write circuit 36 by the column decoder 34 and the selector 38. Then, the write voltage V1 is output from the read / write circuit 36 to the bit line B3. Thus, the voltage Vw = V1−V2 is applied between the first conductive layer and the second conductive layer constituting the memory cell 12. By appropriately selecting the voltage Vw to be applied, a mixture is formed at a portion where the first conductive layer and the liquid crystal layer of the memory element 14 are in contact, and an organic compound provided between the liquid crystal layer and the second conductive layer Data “1” can be written by changing the layer physically or electrically. Specifically, in the read operation voltage, the electrical resistance between the first conductive layer and the second conductive layer in the data “1” state is significantly smaller than that in the data “0” state. It is good to change as follows. For example, it may be appropriately selected from the range of (V1, V2) = (0V, 5V to 15V), or (3V to 5V, −12V to −2V). The voltage Vw may be 5V to 15V, or -5V to -15V.

  Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. For example, unselected word lines and unselected bit lines may be set in a floating state. The layer between the first conductive layer and the second conductive layer constituting the memory cell needs to have characteristics that can ensure selectivity, such as diode characteristics.

  On the other hand, when data “0” is written in the memory cell 12, it is not necessary to apply an electrical action to the memory cell 12. In terms of circuit operation, for example, as in the case of writing “1”, the memory cell 12 is selected by the row decoder 42, the level shifter 44, the column decoder 34, and the selector 38, but from the read / write circuit 36 to the bit line B3. Is set to the same level as the potential of the selected word line W3 or the potential of the non-selected word line, and the memory cell 12 is connected between the first conductive layer and the second conductive layer. What is necessary is just to apply the voltage (for example, -5V-5V) of the grade which does not change an electrical property.

  Next, a specific operation when reading data from the organic memory will be described. In reading data, the electrical characteristics between the first conductive layer and the second conductive layer constituting the memory cell are different between the memory cell having data “0” and the memory cell having data “1”. Use it. For example, the effective electrical resistance between the first conductive layer and the second conductive layer constituting the memory cell having data “0” (hereinafter simply referred to as the electrical resistance of the memory cell) is R0 at the read voltage. A method of reading data by using the difference in electric resistance when the electric resistance of the memory cell having data “1” is R1 in the read voltage will be described. Note that R1 << R0. For the read / write circuit 36, for example, a circuit using a resistance element 72 and a differential amplifier 74 shown in FIG. The resistance element 72 has a resistance value Rr, and R1 <Rr <R0. Further, as shown in FIG. 3C, a transistor 76 may be used instead of the resistance element 72, and a clocked inverter 78 may be used instead of the differential amplifier. The clocked inverter 78 receives a signal φ or an inverted signal φ that is High when reading is performed and is Low when the reading is not performed. Of course, the circuit configuration is not limited to that shown in FIGS.

  When reading data from the memory cell 12, first, the memory cell 12 is selected by the row decoder 42, the level shifter 44, the column decoder 34, and the selector 38. Specifically, a predetermined voltage Vy is applied to the word line Wy connected to the memory cell 12 by the row decoder 42 and the level shifter 44. Further, the bit line Bx connected to the memory cell 12 is connected to the terminal P of the read / write circuit 36 by the column decoder 34 and the selector 38. As a result, the potential Vp of the terminal P becomes a value determined by resistance division by the resistance element 72 (resistance value Rr) and the memory cell 12 (resistance value R0 or R1). Therefore, when the memory cell 12 has data “0”, Vp0 = Vy + (V0−Vy) × R0 / (R0 + Rr). When the memory cell 12 has data “1”, Vp1 = Vy + (V0−Vy) × R1 / (R1 + Rr). As a result, in FIG. 3B, Vref is selected to be between Vp0 and Vp1, and in FIG. 3C, the change point of the clocked inverter is selected to be between Vp0 and Vp1. Thus, Low / High (or High / Low) is output as the output potential Vout according to the data “0” / “1”, and reading can be performed.

  For example, the differential amplifier 74 is operated at Vdd = 3V, and Vy = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9, if the memory cell data is “0”, Vp0 = 2.7 V and Vout is High, and if the memory cell data is “1”, Vp1 = 0.3V and Low is output as Vout. Thus, the memory cell can be read.

  According to the above method, the state of the electrical resistance of the memory element 14 is read as a voltage value using the difference in resistance value and resistance division. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. In addition, when the electrical characteristics of the memory cell have data “0” and “1” and diode characteristics with different threshold voltages, reading may be performed using the threshold voltage difference. It is also possible to adopt a method of reading the resistance value of the memory element by replacing it with the magnitude of the current, or a method of precharging the bit line.

  Note that this embodiment mode can be freely combined with the above embodiment modes.

  According to the present invention, initial defects of a memory element can be reduced, and the manufacturing yield of a semiconductor device having the memory element can be improved.

  In addition, according to the present invention, it is possible to provide a semiconductor device having a memory element that can write (additional) data other than at the time of manufacture and can prevent forgery due to rewriting.

(Embodiment 3)
An example of a memory element of the present invention and a semiconductor device including the memory element, typically a memory device, will be described with reference to FIGS. Specifically, an example of an active matrix storage device will be described.

  FIG. 6A illustrates an example of a memory device, which includes a memory cell array 610, a bit line driver circuit 632, a word line driver circuit 640, and an interface 630 provided over a substrate 620.

  The memory cell array 610 includes a plurality of bit lines Bx (1 ≦ x ≦ m) extending in the x direction and a plurality of word lines Wy (1 ≦ y ≦ n) extending in the y direction orthogonal to the x direction. It is configured. A memory cell 612 including a transistor 680 and a memory element 614 is provided at a portion where the bit line Bx and the word line Wy intersect. The memory cells 612 are provided in a matrix in the memory cell array 610.

  The bit line driver circuit 632 includes a column decoder 634, a read / write circuit 636, and a selector 638. The bit line driving circuit 632 is connected to the bit line Bx and the interface 630.

  The word line driver circuit 640 includes a row decoder 642 and a level shifter 644. The word line driving circuit 640 is connected to the word line Wy and the interface 630.

  The interface 630 is a circuit that supplies a signal input from the outside to the bit line driving circuit 632 or the word line driving circuit 640 or supplies a signal output from the bit line driving circuit 632 to the outside.

  Note that the structure illustrated in FIG. 6A is merely an example, and may include other circuits such as a sense amplifier, an output circuit, and a buffer circuit. Further, a writing circuit may be provided in the interface 630.

  Next, the memory cell 612 will be described in detail with reference to FIG. FIG. 7A illustrates an example of a top view of the memory cell array 610. FIG. 7B illustrates an example of a cross-sectional view taken along dashed line AB in FIG. Note that in FIG. 7A, part of the structure except the transistor and the first conductive layer is omitted.

  The memory cell 612 includes an electrode (source electrode or drain electrode) connected to the bit line Bx (1 ≦ x ≦ m), an electrode connected to the word line Wy (1 ≦ y ≦ n), a memory element 614, A transistor 680. The memory element 614 has a structure as shown in Embodiment Modes 1 and 2, and includes at least a first conductive layer, a liquid crystal layer in contact with the first conductive layer, and an organic compound layer in contact with the liquid crystal layer. The second conductive layer in contact with the organic compound layer has a stacked structure. The gate electrode of the transistor 680 is connected to the word line Wy, one of the source electrode and the drain electrode is connected to the bit line Bx, and the other is connected to the first conductive layer 622 of the memory element 614. Alternatively, the first conductive layer 622 functions. The second conductive layer 628 of the memory element is connected to the common electrode (potential Vcom).

  For example, as illustrated in FIG. 7B, the memory element 614 can be formed over a substrate 620 provided with a transistor 680. As in the memory element described in Embodiment 1 or 2, the memory element 614 includes a first conductive layer 622, a liquid crystal layer 624, an organic compound layer 626, and a second conductive layer 628 which are sequentially stacked. Has a structure. In addition, a partition layer 654 that covers an end portion of the first conductive layer 622 is provided between adjacent first conductive layers. Further, in this embodiment, an insulating layer 656 that functions as a protective layer is provided over the memory element 614.

  The transistor 680 is provided over the substrate 620 with a base insulating layer 650 interposed therebetween. The conductive layer functioning as a source electrode or a drain electrode of the transistor 680 is connected to the first conductive layer 622 of the memory element 614.

  Various transistors can be used as the transistor 680 in this embodiment. Here, an example of an applicable transistor 680 is described with reference to FIGS.

  For example, FIG. 8A illustrates an example in which a top-gate thin film transistor (hereinafter also referred to as TFT) is applied. A transistor (TFT) 680 shown here includes a semiconductor layer 1302 provided over the base insulating layer 650, a gate insulating layer 1303 provided over the semiconductor layer 1302, and a gate provided over the gate insulating layer 1303. An electrode 1304.

  An insulating layer 651 and an insulating layer 652 functioning as interlayer insulating layers are provided over the semiconductor layer 1302 and the gate electrode 1304. Further, a conductive layer 1312 connected to the semiconductor layer 1302 through insulating layers 651 and 652 is provided. The conductive layer 1312 functions as a source electrode or a drain electrode of the transistor 680. One of the conductive layers 1312 is connected to the first conductive layer 622 of the memory element 614 or functions as the first conductive layer 622 of the memory element 614.

  The semiconductor layer 1302 is a layer formed of a semiconductor having a crystal structure, and a non-single-crystal semiconductor or a single-crystal semiconductor can be used. In particular, an amorphous or microcrystalline semiconductor is crystallized by crystallizing a semiconductor that is crystallized by laser light irradiation, a crystallized semiconductor that is crystallized by heat treatment, or a combination of heat treatment and laser light irradiation. It is preferable to apply a crystalline semiconductor. In the heat treatment, a crystallization method using a metal element such as nickel which has an action of promoting crystallization of a silicon semiconductor can be applied.

In the case of crystallization by irradiating with laser light, irradiation with continuous wave laser light or repetition frequency is 10 MHz or more and pulse width is 1 nanosecond or less, preferably 1 to 100 picoseconds. By irradiating the return frequency ultrashort pulse light, crystallization can be performed while continuously moving the molten zone in which the crystalline semiconductor is melted in the irradiation direction of the laser light. By such a crystallization method, a crystalline semiconductor having a large particle diameter and a crystal grain boundary extending in one direction can be obtained. By adjusting the carrier drift direction to the direction in which the crystal grain boundary extends, the field-effect mobility in the transistor can be increased. For example, 400 cm ² / V · sec or more can be realized.

  Further, when crystallization is performed using a crystallization process at a heat resistant temperature (about 600 ° C.) or lower of the glass substrate, a large area glass substrate can be used. Therefore, a large amount of semiconductor devices can be manufactured per substrate, and the cost can be reduced.

  Note that the semiconductor layer 1302 can also be formed by performing a crystallization step by heating at or above a heat resistant temperature of the glass substrate. Typically, a quartz substrate is used as the insulating substrate, and the semiconductor layer 1302 is formed by heating an amorphous or microcrystalline semiconductor at 700 ° C. or higher. As a result, a semiconductor with high crystallinity can be formed. Therefore, a thin film transistor that has favorable characteristics such as response speed and mobility and can operate at high speed can be provided.

  The semiconductor layer 1302 includes a channel formation region 1313, a pair of high concentration impurity regions 1311 functioning as a source region or a drain region, and a pair of low concentration impurity regions located between the channel formation region and the high concentration impurity region. 1310 (also referred to as an LDD region). The high-concentration impurity region 1311 and the low-concentration impurity region 1310 are doped with one conductivity type impurity, and the high-concentration impurity region 1311 is doped with an impurity at a higher impurity concentration than the low-concentration impurity region 1310. The channel formation region 1313 overlaps with the gate electrode 1304 with the gate insulating layer 1303 interposed therebetween, and the low-concentration impurity region 1310 overlaps with the sidewall 1308 with the gate insulating layer 1303 interposed therebetween. Note that the present invention is not particularly limited, and the low-concentration impurity region may be formed so as to overlap with the gate electrode, or the low-concentration impurity region may not be formed.

As the gate insulating layer 1303, an insulating layer containing silicon nitride, silicon oxide, or other silicon is formed with a single layer or a stacked structure by a thin film formation method such as a plasma CVD method or a sputtering method. Alternatively, the gate insulating layer 1303 can be formed using an insulating solution by a droplet discharge method, a coating method, a sol-gel method, or the like. Typical examples of the insulating solution include a solution in which fine particles of inorganic oxide are dispersed, polyimide, polyamide, polyester, acrylic, PSG (phosphorus glass), BPSG (boron phosphorous glass), silicate material, alkoxysilicate material, A solution containing SiO ₂ having a Si—CH ₂ bond represented by a polysilazane material and polymethylsiloxane can be used as appropriate.

  The gate electrode 1304 can be formed using a metal or a polycrystalline semiconductor to which an impurity of one conductivity type is added. In the case of using a metal, tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), aluminum (Al), or the like can be used. Alternatively, a metal nitride obtained by nitriding the metal can be used. Or it is good also as a structure which laminated | stacked the 1st layer which consists of metal nitride, and the 2nd layer which consists of metals. In the case of a laminated structure, the end of the first layer may protrude outward from the end of the second layer. At this time, a barrier metal can be formed by using a metal nitride for the first layer. That is, the second layer metal can be prevented from diffusing into the gate insulating layer 1303 and the semiconductor layer 1302 below the gate insulating layer 1303.

  A side wall (side wall spacer) 1308 is provided on the side surface of the gate electrode 1304. The sidewall 1308 is formed by forming a gate electrode 1304, forming an insulating layer containing silicon oxide by a CVD method, and anisotropically etching the insulating layer by a RIE (Reactive Ion Etching) method. Can be formed. Note that the sidewall 1308 is not necessarily provided.

  The insulating layers 651 and 652 are formed using an inorganic insulating material such as silicon oxide and silicon oxynitride, or an organic insulating material such as an acrylic resin and a polyimide resin. In the case of using a coating method such as spin coating or a roll coater method, an insulating layer formed of silicon oxide by heat treatment can be used after applying a liquid insulating material. For example, an insulating layer containing silicon oxide formed by applying a material containing a siloxane bond and performing heat treatment at 200 to 400 degrees can be used. By forming an insulating layer formed by a coating method or an insulating layer flattened by reflow as the insulating layers 651 and 652, disconnection of wirings formed on the layers can be prevented. It can also be used effectively when forming multilayer wiring. Note that although the interlayer insulating layer has a two-layer structure here, there is no particular limitation, and a single-layer structure or a stacked structure of three or more layers can also be used.

  One of the conductive layers 1312 formed over the insulating layer 652 is connected to the first conductive layer 622 of the memory element 614 or functions as the first conductive layer 622 of the memory element 614. Here, the conductive layer 1312 and the first conductive layer 622 are formed as the same layer, and the conductive layer 1312 also functions as the first conductive layer 622. That is, part of the conductive layer 1312 corresponds to the first conductive layer 622. Note that the conductive layer 1312 functioning as the first conductive layer can be provided so as to intersect with a wiring formed in the same layer as the gate electrode 1304 and forms a multilayer wiring structure. A multilayer wiring structure can be formed by stacking a plurality of insulating layers having functions similar to those of the insulating layer 652 and forming wirings on the insulating layers. The conductive layer 1312 may be formed of a combination of a layer including a low resistance material such as aluminum (Al) and a layer including a barrier metal using a refractory metal material such as titanium (Ti) or molybdenum (Mo). preferable. For example, a stacked structure of a layer containing titanium (Ti) and a layer containing aluminum (Al), or a stacked structure of a layer containing molybdenum (Mo) and a layer containing aluminum (Al) can be used.

  In addition, the transistor 680 has a multi-gate structure including a semiconductor layer including at least two or more channel formation regions connected in series and at least two or more gate electrodes for applying an electric field to each channel formation region. Alternatively, a dual gate structure in which a semiconductor layer is sandwiched between gate electrodes up and down can be employed.

  FIG. 8B illustrates an example in which a bottom-gate TFT is applied. A transistor (TFT) 680 shown here includes a gate electrode 1304 provided over the base insulating layer 650, a gate insulating layer 1303 provided over the gate electrode 1304, and a semiconductor provided over the gate insulating layer 1303. A layer 1302 and a channel protective layer 1309 provided over the semiconductor layer 1302. Over the semiconductor layer 1302, insulating layers 651 and 652 functioning as interlayer insulating layers are provided. Further, a conductive layer 1312 connected to the semiconductor layer 1302 through insulating layers 651 and 652 is provided. The conductive layer 1312 functions as a source electrode or a drain electrode of the transistor 680. One of the conductive layers 1312 is connected to the first conductive layer 622 of the memory element 614 or functions as the first conductive layer 622 of the memory element 614. Note that although the conductive layer 1312 is formed through the insulating layer 652 and the insulating layer 651 here, the conductive layer 1312 may be formed through the insulating layer 651 alone. In the case of a bottom-gate TFT, the base insulating layer 650 is not necessarily formed.

  In the case where the substrate 620 is a flexible substrate, the heat resistant temperature is lower than that of a non-flexible substrate such as a glass substrate. Therefore, in the case where a transistor is formed over a flexible substrate, an organic semiconductor is preferably used.

  FIG. 8C illustrates an example in which a staggered organic semiconductor transistor is applied. The transistor 680 shown here is provided over a flexible substrate 1401. The transistor 680 includes a gate electrode 1402, a gate insulating layer 1403 provided over the gate electrode 1402, a semiconductor layer 1404 provided over the gate insulating layer 1403, and a conductive layer 1412 connected to the semiconductor layer 1404. . One of the conductive layers 1412 is connected to the first conductive layer 622 of the memory element 614 or functions as the first conductive layer 622 of the memory element 614. The semiconductor layer 1404 is partly sandwiched between the gate insulating layer 1403 and the conductive layer 1412.

  The gate electrode 1402 can be formed using a material and a method similar to those of the gate electrode 1304. Further, the gate electrode 1402 can be formed by drying and baking using a droplet discharge method. Alternatively, the gate electrode 1402 can be formed by printing a paste containing conductive fine particles on a flexible substrate by a printing method, followed by drying and baking. As typical examples of the conductive fine particles, fine particles mainly containing any one of gold, copper, an alloy of gold and silver, an alloy of gold and copper, an alloy of silver and copper, and an alloy of gold, silver and copper may be used. Further, fine particles mainly containing a conductive oxide such as indium tin oxide (ITO) may be used.

  The gate insulating layer 1403 can be formed using a material and a method similar to those of the gate insulating layer 1303. However, when an insulating layer is formed by heat treatment after applying a liquid insulating material, the heat treatment temperature is lower than the heat resistance temperature of the flexible substrate.

  Examples of the material of the semiconductor layer 1404 of the organic semiconductor transistor include polycyclic aromatic compounds, conjugated double bond compounds, phthalocyanines, and charge transfer complexes. For example, anthracene, tetracene, pentacene, 6T (hexathiophene), TCNQ (tetracyanoquinodimethane), PTCDA (perylene carboxylic acid anhydride), NTCDA (naphthalene carboxylic acid anhydride) and the like can be used. Examples of the material for the semiconductor layer 1404 of the organic semiconductor transistor include π-conjugated polymers such as organic polymer compounds, carbon nanotubes, polyvinyl pyridine, and phthalocyanine metal complexes. In particular, when a polyacetylene, polyaniline, polypyrrole, polythienylene, polythiophene derivative, poly (3 alkylthiophene), polyparaphenylene derivative or polyparaphenylene vinylene derivative is used, which is a π-conjugated polymer whose skeleton is composed of conjugated double bonds preferable.

  In addition, as a method for forming the semiconductor layer 1404 of the organic semiconductor transistor, a method that can be formed over the substrate with a uniform film thickness may be used. The film thickness is 1 nm to 1000 nm, preferably 10 nm to 100 nm. As a specific method, a vapor deposition method, a coating method, a spin coating method, an overcoat method, a solution casting method, a dip method, a screen printing method, a roll coater method, or a droplet discharge method can be used.

  FIG. 8D illustrates an example in which a coplanar organic semiconductor transistor is applied. The transistor 680 shown here is provided over a flexible substrate 1401. The transistor 680 includes a gate electrode 1402, a gate insulating layer 1403 provided over the gate electrode 1402, a conductive layer 1412 provided over the gate insulating layer 1403, a part of the conductive layer 1412, and a gate insulating layer. A semiconductor layer 1404 provided over the semiconductor layer 1403; One of the conductive layers 1412 is connected to the first conductive layer 622 of the memory element 614 or functions as the first conductive layer 622 of the memory element 614. In addition, the conductive layer 1412 is partly sandwiched between the gate insulating layer 1403 and the semiconductor layer 1404.

  Note that the thin film transistors and organic semiconductor transistors illustrated in FIGS. 8A to 8D may have any structure as long as they can function as switching elements.

  Alternatively, a transistor may be formed using a single crystal substrate or an SOI substrate, and a memory element may be provided thereover. The SOI substrate may be formed using a method called wafer bonding or a method called SIMOX in which an insulating layer is formed inside by implanting oxygen ions into the Si substrate. Here, as shown in FIG. 7C, a memory element 614 is connected to a field-effect transistor 662 provided over a single crystal semiconductor substrate 660. Specifically, the conductive layer 663 connected to the impurity region of the field effect transistor 662 and the first conductive layer 622 are connected to each other through the insulating layer 672. In other words, the insulating layer 672 is provided so as to cover the conductive layer 663 functioning as a source electrode or a drain electrode of the field-effect transistor 662, and the memory element 614 is provided over the insulating layer 672. Note that the field effect transistor 662 is separated by a field oxide film 661.

  Since a transistor formed using such a single crystal semiconductor has favorable characteristics such as response speed and mobility, a transistor that can operate at high speed can be provided. In addition, since a transistor formed using a single crystal semiconductor has less variation in characteristics, a semiconductor device with high reliability can be provided.

  In addition, by providing the insulating layer 672 over the field-effect transistor 662 to form the memory element 614, the first conductive layer 622 can be freely arranged. That is, in the structure of FIGS. 7A and 7B, it is necessary to provide the memory element 614 in a region avoiding the upper portion of the transistor 680. By using the structure shown in FIG. The memory element 614 can be formed over the transistor 662 provided in the layer 671 having a transistor.

  7B and 7C, the organic compound layer 626 is provided over the entire surface of the substrate, but may be selectively provided only in each memory cell. In this case, the use efficiency of the material can be improved by selectively providing an organic compound layer by discharging and baking an organic compound using a droplet discharge method or the like.

  A material and a formation method of the memory element 614 can be similarly performed using any of the materials and the formation method described in Embodiment Mode 1 or 2.

  The partition layer 654 can be provided using a material and a formation method similar to those of the partition layers 56 and 64 described in Embodiment 2.

In addition, as illustrated in FIG. 9, a separation layer is provided over a substrate having an insulating surface, a layer 692 having a transistor and a memory element 614 are formed over the separation layer, and then the layer 692 having a transistor and the memory element 614 are separated. The layer 692 including a transistor and the memory element 614 may be attached to the substrate 690 with an adhesive layer 694 interposed therebetween. Note that as a peeling method, (1) a layer having a transistor is provided by providing a metal oxide layer as a peeling layer between a substrate having high heat resistance and a layer having a transistor, and weakening the metal oxide layer by crystallization. (2) An amorphous silicon film containing hydrogen is provided as a peeling layer between a substrate having high heat resistance and a layer having a transistor, and hydrogen gas of the amorphous silicon film is released by laser light irradiation. And a method of peeling a layer having the transistor by providing an amorphous silicon film as a peeling layer and removing the amorphous silicon film by etching, (3 ) A method of mechanically removing a substrate with high heat resistance on which a layer having a transistor is formed or removing by etching with a solution; (4) Between a substrate with high heat resistance and a layer having a transistor; The metal layer and metal oxide layer formed as the separation layer, the metal oxide layer is weakened by crystallization, a part of the metal layer solution and NF _3, BrF _3, by etching with halogen fluoride gas such as ClF ₃ After removal, a method of physically peeling the weakened metal oxide layer or the like may be used.

  As the substrate 690, a flexible substrate, a film showing thermoplasticity, paper made of a fibrous material, or the like can be used, so that the memory device can be reduced in size, thickness, and weight.

  Next, a specific operation when data is written to the storage device of the present invention will be described with reference to FIG. Writing is performed by changing the electrical characteristics of the memory cell. The initial state of the memory cell (the state where no electrical action is applied) is data “0”, and the state where the electrical characteristic is changed is “1”. To do.

  Here, a case where data is written to the memory cell 612 in the third column and the third row will be described. When data “1” is written to the memory cell 612, first, the memory cell 612 is selected by the row decoder 642, the column decoder 634, and the selector 638. Specifically, the row decoder 642 applies a predetermined voltage V22 to the word line W3 connected to the memory cell 612. Further, the bit line B 3 connected to the memory cell 612 is connected to the read / write circuit 636 by the column decoder 634 and the selector 638. Then, the write voltage V21 is output from the read / write circuit 636 to the bit line B3.

  Thus, the transistor 680 included in the selected memory cell 612 is turned on, the bit line is electrically connected to the memory element 614, and a voltage of approximately Vw = Vcom−V21 is applied. Note that one electrode of the memory element 614 is connected to a common electrode of the potential Vcom. By appropriately selecting the potential Vw, a mixture is formed at a portion where the first conductive layer and the liquid crystal layer included in the memory element 614 are in contact, and an organic compound layer provided between the liquid crystal layer and the second conductive layer is formed. Data “1” can be written by physical or electrical change. Specifically, at the read operation voltage, the electrical resistance between the first conductive layer and the second conductive layer in the data “1” state is significantly smaller than that in the data “0” state. It may be changed as described above, or it may be simply short-circuited. The potential may be appropriately selected from the range of (V21, V22, Vcom) = (5V to 15V, 5V to 15V, 0V), or (−12V to 0V, −12V to 0V, 3V to 5V). The voltage Vw may be 5V to 15V, or -5V to -15V.

  Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. Specifically, a potential (for example, 0 V) for turning off the transistor of the memory cell to be connected is applied to the non-selected word line, and the non-selected bit line is in a floating state or approximately equal to Vcom. A potential may be applied.

  On the other hand, when data “0” is written to the memory cell 612, it is not necessary to apply an electrical action to the memory cell 612. In circuit operation, for example, as in the case of writing “1”, the memory cell 612 is selected by the row decoder 642, the column decoder 634, and the selector 638, but the output potential from the read / write circuit 636 to the bit line B3 is changed. The bit line B3 is set in a floating state or the same level as Vcom. As a result, a small voltage (for example, −5 to 5 V) is applied to the memory element 614 or no voltage is applied, so that the electrical characteristics do not change and data “0” writing is realized.

  Next, an operation when data is read by electrical action will be described. Data is read using the fact that the electrical characteristics of the memory element 614 differ between the memory cell having data “0” and the memory cell having data “1”. For example, the electrical resistance of the memory element constituting the memory cell having data “0” is R0 at the read voltage, and the electrical resistance of the memory element constituting the memory cell having data “1” is R1 at the read voltage. A method of reading using the difference will be described. Note that R1 << R0. As the structure of the reading / writing circuit, for example, a reading / writing circuit 636 using a resistance element 673 and a differential amplifier 674 shown in FIG. 6B can be considered. The resistance element has a resistance value Rr, and R1 <Rr <R0. Note that as shown in FIG. 6C, a transistor 676 may be used instead of the resistance element 673, and a clocked inverter 678 may be used instead of the differential amplifier 674. Of course, the circuit configuration is not limited to FIGS. 6B and 6C.

  When reading data from the memory cell 612 in the x-th column and the y-th row, first, the memory cell 612 is selected by the row decoder 642, the column decoder 634, and the selector 638. Specifically, the row decoder 642 applies a predetermined voltage V24 to the word line Wy connected to the memory cell 612 to turn on the transistor 680. Further, the bit line Bx connected to the memory cell 612 is connected to the terminal P of the read / write circuit 636 by the column decoder 634 and the selector 638. As a result, the potential Vp of the terminal P becomes a value determined by resistance division of Vcom and V0 by the resistance element 673 (resistance value Rr) and the memory element 614 (resistance value R0 or R1). Therefore, when the memory cell 612 has data “0”, Vp0 = Vcom + (V0−Vcom) × R0 / (R0 + Rr). When the memory cell 612 has data “1”, Vp1 = Vcom + (V0−Vcom) × R1 / (R1 + Rr). As a result, in FIG. 6B, by selecting Vref to be between Vp0 and Vp1, in FIG. 6C, the change point of the clocked inverter 678 is between Vp0 and Vp1. By selecting, the output potential Vout is Low / High (or High / Low) according to the data “0” / “1”, and reading can be performed.

  For example, the differential amplifier 674 is operated at Vdd = 3V, and Vcom = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9 and the on-resistance of the transistor 680 can be ignored, when the data in the memory cell is “0”, Vp0 = 2.7 V and Vout is output as High When the data of “1” is “1”, Vp1 = 0.3V and Vout is output as Low. Thus, the memory cell can be read.

  According to the above method, the voltage value is read by utilizing the difference in resistance value of the memory element 614 and the resistance division. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. In addition, when the electrical characteristics of the memory cell have data “0” and “1” and diode characteristics with different threshold voltages, reading may be performed using the threshold voltage difference.

  Note that this embodiment mode can be freely combined with the above embodiment modes.

  According to the present invention, initial defects of a memory element can be reduced, and the manufacturing yield of a semiconductor device having the memory element can be improved.

  In addition, according to the present invention, it is possible to provide a semiconductor device having a memory element that can write (additional) data other than at the time of manufacture and can prevent forgery due to rewriting.

(Embodiment 4)
In this embodiment, a memory element of the present invention, a semiconductor device including the memory element, a manufacturing method thereof, and an application example of the semiconductor device will be described with reference to FIGS.

  The semiconductor device described in this embodiment is characterized in that data can be read and written without contact. Data transmission formats are broadly divided into three types: electromagnetic coupling method in which a pair of coils are arranged facing each other to communicate by mutual induction, electromagnetic induction method to communicate by inductive electromagnetic field, and radio wave method to communicate using radio waves. However, any method may be used. There are two types of antennas used for data transmission. One is provided on a substrate provided with a transistor and a memory element, and the other is provided on a substrate provided with a transistor and a memory element. There is a case where a terminal portion is provided and an antenna provided on another substrate is connected to the terminal portion. Here, an antenna, a circuit connected to the antenna, and a part of the memory circuit are illustrated as part of a cross section of the semiconductor device.

  First, a structure example of a semiconductor device in the case where an antenna is provided over a substrate provided with a plurality of semiconductor elements and memory elements will be described with reference to FIGS.

  10A includes a transistor 1451, a transistor 1452, a layer 1250 having a transistor, a memory element portion 1352 formed over the layer 1250 having a transistor, and a conductive layer functioning as an antenna. A layer 1353.

  Note that although the case where the memory element portion 1352 and the conductive layer 1353 functioning as an antenna are provided above the insulating layer 1252 is shown here, the present invention is not particularly limited. For example, the memory element portion 1352 or the conductive layer 1353 functioning as an antenna may be provided below or in the same layer as the layer 1250 having a transistor.

  The memory element portion 1352 includes a memory element 1351a and a memory element 1351b. The memory element 1351a includes a first conductive layer 1361a formed over the insulating layer 1252, a liquid crystal layer 1362a formed over the first conductive layer 1361a, and an organic layer formed over the liquid crystal layer 1362a. It has a compound layer 1363a and a second conductive layer 1364a formed over the organic compound layer 1363a. Similarly, the memory element 1351b includes a first conductive layer 1361b formed over the insulating layer 1252, a liquid crystal layer 1362b formed over the first conductive layer 1361b, and a liquid crystal layer 1362b. An organic compound layer 1363b and a second conductive layer 1364b formed over the organic compound layer 1363b are provided.

  An insulating layer 1366 functioning as a protective film is formed so as to cover the memory elements 1351a and 1351b and the conductive layer 1353 functioning as an antenna. The memory element portion 1352 can be formed using a material or a manufacturing method similar to those of the memory element described in the above embodiment.

  Here, the conductive layer 1353 functioning as an antenna is provided over the conductive layer 1360 formed using the same layer as the second conductive layers 1364a and 1364b. Note that a conductive layer functioning as an antenna may be formed in the same layer as the second conductive layers 1364a and 1364b. The conductive layer 1353 functioning as an antenna is connected to a source wiring or a drain wiring of the transistor 1451. Note that the transistor 1451 forms part of a circuit connected to the antenna.

  The transistor 1452 forms part of a driver circuit that controls the operation of the memory element portion 1352. The driving circuit is provided with a plurality of transistors, for example, a decoder, a buffer, and the like.

  As a material of the conductive layer 1353 functioning as an antenna, gold (Au), platinum (Pt), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), aluminum (Al ), Manganese (Mn), titanium (Ti), or the like, or an alloy containing a plurality of such elements can be used. As a method for forming the conductive layer 1353 functioning as an antenna, various printing methods such as an evaporation method, a sputtering method, a screen printing method, a gravure printing method, a droplet discharge method, or the like can be used.

  As the transistors 1451 and 1452 included in the transistor-containing layer 1250, the transistor 680 described in Embodiment 3 can be used as appropriate.

  Further, a separation layer, a layer 1250 having a transistor, a memory element portion 1352, and a conductive layer 1353 functioning as an antenna are formed over a substrate, and the layer 1250 having a transistor is formed using the separation method described in Embodiment 3 as appropriate. The element portion 1352 and the conductive layer 1353 functioning as an antenna may be peeled off and attached to another substrate using an adhesive layer. As another substrate, a flexible substrate, a film showing thermoplasticity, paper made of a fibrous material, a base film, or the like can be used, so that the storage device can be reduced in size, thickness, and weight. .

  FIG. 10B illustrates an example of a semiconductor device which is different from that illustrated in FIG. Note that FIG. 10B will be described with respect to portions different from FIG.

  10B includes a layer 1250 including a transistor over a substrate 1350, and a memory element portion 1355 and a conductive layer 1353 functioning as an antenna over the layer 1250 including a transistor. Here, the transistor 1453 and the transistor 1454 which function as a switching element of the memory element portion 1355 are provided in the same layer as the transistors 1451 and 1452, and the conductive element 1353 which functions as a memory element portion 1355 and an antenna is provided above the layer 1250 including the transistor. The case where it has is shown. Note that the present invention is not particularly limited, and the memory element portion 1355 and the conductive layer 1353 functioning as an antenna can be provided below the transistor layer 1250 or in the same layer.

  The memory element portion 1355 includes a memory element 1356a and a memory element 1356b. The memory element 1356a includes a first conductive layer 1371a formed over the insulating layer 1252, a liquid crystal layer 1370 formed over the first conductive layer 1371a, and an organic layer formed over the liquid crystal layer 1370. A compound layer 1372 and a second conductive layer 1373 formed over the organic compound layer 1372 are included. Similarly, the memory element 1356b includes a first conductive layer 1371b formed over the insulating layer 1252, a liquid crystal layer 1370 formed over the first conductive layer 1371b, and a liquid crystal layer 1370 formed over the liquid crystal layer 1370. An organic compound layer 1372 and a second conductive layer 1373 formed over the organic compound layer 1372 are included. Further, the end portion of the first conductive layer 1371 a of the memory element 1356 a and the end portion of the first conductive layer 1371 b of the memory element 1356 b are covered with a partition layer 1374.

  Note that in the memory elements 1356a and 1356b, a common layer is used as the liquid crystal layer 1370, the organic compound layer 1372, and the second conductive layer 1373. That is, the liquid crystal layer 1370, the organic compound layer 1372, and the second conductive layer 1373 are sequentially stacked over the first conductive layers 1371a and 1371b and the partition layer 1374 that covers the end portions of the first conductive layers 1371a and 1371b. Is provided.

  In addition, the memory element 1356a is connected to the transistor 1454, and the memory element 1356b is connected to the transistor 1453. Specifically, the first conductive layer 1371a is connected to a source wiring or a drain wiring of the transistor 1454. Similarly, the first conductive layer 1371b is connected to the source wiring or the drain wiring of the transistor 1453.

  An insulating layer 1366 that functions as a protective film is formed so as to cover the memory elements 1356a and 1356b and the conductive layer 1353 that functions as an antenna. The memory element portion 1355 can be formed using a material or a manufacturing method similar to those of the memory element described in the above embodiment.

Note that the memory elements 1356a and 1356b can be formed using the materials or manufacturing methods described in Embodiments 1 to 3.

  The layer 1250 having a transistor, the memory element portion 1355, and the conductive layer 1353 functioning as an antenna can be formed by a vapor deposition method, a sputtering method, a CVD method, a printing method, a droplet discharge method, or the like as described above. it can. Note that a different method may be used depending on each place.

  A peeling layer, a layer 1250 having a transistor, a memory element portion 1355, and a conductive layer 1353 functioning as an antenna are formed over a substrate, and a layer 1250 having a transistor and a memory element portion are appropriately formed using the peeling method described in Embodiment 3. 1355 and the conductive layer 1353 functioning as an antenna may be separated and attached to another substrate using an adhesive layer. As another substrate, a flexible substrate, a film showing thermoplasticity, paper made of a fibrous material, a base film, or the like can be used, so that the storage device can be reduced in size, thickness, and weight. .

  Note that the sensor element may be provided on the same substrate. Examples of the sensor element include an element that detects temperature, humidity, illuminance, gas (gas), gravity, pressure, sound (vibration), acceleration, and other characteristics by physical or chemical means. The sensor element is typically a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermal photovoltaic element, a transistor, a thermistor, a diode, a capacitive element, or a piezoelectric element. It is formed with an element.

  Next, an example of a method for manufacturing the memory element of the present invention and a semiconductor device including the memory element will be described with reference to FIGS. Here, a manufacturing method in which the semiconductor device illustrated in FIG. 10B is a semiconductor device such as an IC tag or an RFID will be described.

  First, the separation layer 1102 is formed over one surface of the substrate 1100 (see FIG. 11A). As the substrate 1100, a glass substrate, a quartz substrate, a metal substrate, a stainless steel substrate with an insulating film formed on one surface, a heat-resistant plastic substrate that can withstand the processing temperature in this step, or the like can be used. Further, although the release layer 1102 is provided over the entire surface of the substrate 1100, the present invention is not particularly limited. For example, the separation layer 1102 may be selectively provided using a photolithography method and an etching method. Further, although the peeling layer 1102 is formed so as to be in contact with the substrate 1100, an insulating layer serving as a base in contact with the substrate 1100 is formed as necessary, and the peeling layer 1102 is formed so as to be in contact with the insulating layer. Also good.

  The peeling layer 1102 is formed by tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium by sputtering or plasma CVD. An element selected from (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), lead (Pb), osmium (Os), iridium (Ir), silicon (Si) or the element as a main component A layer made of an alloy material or a compound material is formed as a single layer or a stacked layer. The crystal structure of the layer containing silicon may be any of amorphous, microcrystalline, and polycrystalline.

  In the case where the separation layer 1102 has a single-layer structure, a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum is preferably formed. Alternatively, a layer containing tungsten oxide or oxynitride, a layer containing molybdenum oxide or oxynitride, or a layer containing an oxide or oxynitride of a mixture of tungsten and molybdenum is formed. Note that the mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum. The oxide of tungsten may be expressed as tungsten oxide.

  In the case where the separation layer 1102 has a stacked structure, a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum is preferably formed as the first layer. As the second layer, oxide, nitride, oxynitride, or nitride oxide of tungsten, molybdenum, or a mixture of tungsten and molybdenum is formed.

  Note that in the case where a stacked structure of a layer containing tungsten and a layer containing an oxide of tungsten is formed as the separation layer 1102, a layer containing tungsten is formed, and a layer containing silicon oxide is formed thereover. The fact that a layer containing an oxide of tungsten is formed at the interface between the layer and the silicon oxide layer may be utilized. The same applies to the case of forming a layer containing tungsten nitride, oxynitride, and nitride oxide. After forming a layer containing tungsten, an insulating layer containing silicon nitride, silicon oxide, or other silicon is formed thereon. Form a layer. Note that after forming a layer containing tungsten, an insulating layer containing silicon nitride, silicon oxide, other silicon, or the like formed over the layer functions as an insulating layer to be a base later.

The oxide of tungsten is represented by WOx, and x is 0 or more and 3 or less (excluding 0). When x is 2 (WO ₂ ), when x is 2.5 (W ₂ O ₅ ), when x is 2.75 (W ₄ O ₁₁ ), when x is 3 (WO ₃ ), etc. . In forming the tungsten oxide, the above-mentioned value of x is not particularly limited, and may be determined based on the etching rate. However, the layer having the best etching rate is a layer containing tungsten oxide (WOx, 0 <X ≦ 3) formed by a sputtering method in an oxygen atmosphere. Therefore, in order to shorten the manufacturing time, a layer containing a tungsten oxide is preferably formed as the separation layer by a sputtering method in an oxygen atmosphere.

  Next, a base insulating layer 1104 is formed so as to cover the separation layer 1102. As the base insulating layer 1104, an insulating layer containing silicon nitride, silicon oxide, or other silicon is formed with a single layer or a stacked structure by a thin film formation method such as a sputtering method or a plasma CVD method. The base insulating layer can also function as a blocking layer that prevents impurities from entering from the substrate 1100.

  Next, as with the transistor 680 described in Embodiment 3, transistors 1451, 1452, 1453, and 1454 are formed. (See FIG. 11B). Note that here, the top-gate thin film transistor illustrated in FIG. 8A is manufactured. Specifically, a semiconductor layer is formed over the base insulating layer, a gate insulating layer is formed over the semiconductor layer, a gate electrode and a sidewall are formed over the gate insulating layer, and the semiconductor layer, the gate electrode, and the side are formed. An insulating layer covering the wall is formed. Then, a conductive layer functioning as a source wiring or a drain wiring is formed so as to be connected to the semiconductor layer.

  An impurity element having one conductivity type is added to the transistors 1451, 1452, 1453, and 1454, and a pair of first impurities functioning as a channel formation region and a low-concentration impurity region (also referred to as an LDD region) in each semiconductor layer A region and a pair of second impurity regions functioning as a source region or a drain region are formed. The impurity concentration of the second impurity region is higher than the impurity concentration of the first impurity region. Note that the present invention is not particularly limited, and the first impurity region may not be provided.

  Here, a channel formation region 1106, a pair of first impurity regions 1108, and a pair of second impurity regions 1110 are formed in the transistor 1451. The transistor 1452 includes two transistors to which an impurity element having a different conductivity type is added. Each transistor includes a channel formation region 1112, a pair of first impurity regions 1114, and a pair of second impurity regions. 1116 or a channel formation region 1118, a pair of first impurity regions 1120, and a pair of second impurity regions 1122 are formed. Note that in the transistor 1452, the first impurity region 1114 and the second impurity region 1116, and the first impurity region 1120 and the second impurity region 1122 are formed by adding impurity elements having different conductivity types. The transistor 1453 forms a channel formation region 1124, a pair of first impurity regions 1126, and a pair of second impurity regions 1128. The transistor 1454 forms a channel formation region 1130, a pair of first impurity regions 1132, and a pair of second impurity regions 1134.

  Next, an insulating layer 1136 and an insulating layer 1252 are stacked over the conductive layer functioning as a source wiring or a drain wiring of the transistors 1451, 1452, 1453, and 1454 (see FIG. 12A). The insulating layers 1136 and 1252 are formed using an inorganic insulating material such as silicon oxide or silicon oxynitride, or an organic insulating material such as an acrylic resin or a polyimide resin. When a coating method such as spin coating or roll coater is used, an insulating layer formed of silicon oxide by heat treatment can be used after applying a liquid insulating material. For example, an insulating layer containing silicon oxide can be used by applying a material containing a siloxane bond and performing heat treatment at 200 to 400 ° C. As the insulating layers 1136 and 1252, by forming an insulating layer formed by a coating method or an insulating layer flattened by reflow, wirings formed over the layers (here, function as a first conductive layer and an antenna of a memory element) Disconnection of the conductive layer connecting the transistor to the transistor) can be prevented. Note that although the interlayer insulating layer has a two-layer structure here, there is no particular limitation, and a single-layer structure or a stacked structure of three or more layers can also be used. In addition, when the insulating layer 1136 in contact with the conductive layer of the transistor is formed using an inorganic insulating material such as silicon oxide or silicon oxynitride, the transistor can function as a protective layer.

  Next, the insulating layers 1136 and 1252 are etched by photolithography to form contact holes that expose the conductive layers functioning as source wirings or drain wirings of the transistors 1451, 1453, and 1454. Then, a conductive layer is formed over the insulating layer 1252 so as to fill the contact holes. The conductive layer is formed using a metal, an alloy thereof, a metal compound, or an oxide conductive material by a sputtering method, a printing method, or a droplet discharge method. Specifically, gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), Metals such as copper (Cu), palladium (Pd), carbon (C), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), or alloys thereof, or lithium (Li) or cesium ( Alkali metals such as Cs) and alkaline earth metals such as magnesium (Mg), calcium (Ca) and strontium (Sr), and alloys containing any of these (MgAg, AlLi), europium (Er), ytterbium ( Rare earth metals such as Yb) and alloys containing them can be used. Alternatively, a metal compound such as titanium nitride (TiN), tungsten nitride (WN), or molybdenum nitride can be used. Further, an oxide conductive material such as indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc oxide added with gallium (GZO), or indium tin oxide containing silicon oxide (ITSO) is used. be able to. Alternatively, it can be formed by a sputtering method using a target in which indium oxide containing silicon oxide is mixed with 2 to 20% by weight of zinc oxide (ZnO).

  The conductive layer formed as described above is processed using a photolithography method and an etching method, so that a first conductive layer 1371a and a first conductive layer 1371b which form a memory element, and a conductive layer 1138 are formed. The first conductive layer 1371a is connected to the source wiring or the drain wiring of the transistor 1454. The first conductive layer 1371b is connected to a source wiring or a drain wiring of the transistor 1453. In addition, the conductive layer 1138 functions as a wiring that connects the transistor 1451 and an antenna formed later.

  Next, an insulating layer is formed so as to cover the first conductive layer 1371a, the first conductive layer 1371b, and the conductive layer 1138. The insulating layer is formed using an inorganic insulating material such as silicon oxide or silicon nitride, an organic insulating material such as an acrylic resin, a polyimide resin, or another resist material, or a material containing a siloxane bond. The insulating layer is formed by a sputtering method, a CVD method, a coating method, or the like depending on a material to be used.

  Next, the insulating layer is etched using a photolithography method and an etching method, so that the first conductive layer 1371a and the first conductive layer 1371b are exposed. The insulating layer remaining here is referred to as a partition layer 1374. The partition layer 1374 is formed so as to cover end portions of the first conductive layer 1371a and the first conductive layer 1371b. For the insulating layer over the conductive layer 1138, a contact hole is formed so that wiring can be formed, and part of the conductive layer 1138 is exposed. Note that in the case where a positive photosensitive resin in which an unexposed portion remains is used as the insulating layer, the process can be shortened because the insulating layer can be formed only by a photolithography method.

  Next, a liquid crystal layer 1370 is formed over the first conductive layer 1371a and the first conductive layer 1371b. The liquid crystal layer 1370 is formed using a liquid crystal compound by a liquid crystal dropping method, an inkjet method, an evaporation method, or a spin coating method. The compound exhibiting liquid crystallinity used here is a compound that undergoes a phase transition from the first phase to the second phase at least due to a temperature change. Further, it is a compound that exhibits liquid crystallinity and forms a mixture with the first conductive layers 1371a and 1371b which are in contact therewith.

  Next, an organic compound layer 1372 is formed over the liquid crystal layer 1370. The organic compound layer 1372 is formed by an evaporation method, an electron beam evaporation method, a sputtering method, or a CVD method using an organic compound whose crystal state, resistance value, or shape of the organic compound layer is changed by an electric action. Specifically, organic resins such as polyimides, polyacrylic acid esters, and polymethacrylic acid esters, organic compounds having a hole transporting property, or organic compounds having an electron transporting property can be used. In the case where the organic compound layer 1372 is formed using a plurality of materials, the organic compound layer 1372 can be formed by simultaneously forming each material. For example, co-evaporation method by resistance heating evaporation, co-evaporation method by electron beam evaporation, co-evaporation method by resistance heating evaporation and electron beam evaporation, film formation by resistance heating evaporation and sputtering, film formation by electron beam evaporation and sputtering, etc. It can be formed by combining the same type and different types of methods.

  Next, a second conductive layer 1373 is formed over the organic compound layer 1372. The second conductive layer 1373 is formed using a metal, an alloy thereof, a metal compound, or an oxide conductive material by a sputtering method, a printing method, or a droplet discharge method. Specifically, gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), Metals such as copper (Cu), palladium (Pd), carbon (C), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), or alloys thereof, or lithium (Li) or cesium ( Alkali metals such as Cs) and alkaline earth metals such as magnesium (Mg), calcium (Ca) and strontium (Sr), and alloys containing any of these (MgAg, AlLi), europium (Er), ytterbium ( Rare earth metals such as Yb) and alloys containing them can be used. Alternatively, a metal compound such as titanium nitride (TiN), tungsten nitride (WN), or molybdenum nitride can be used. Further, an oxide conductive material such as indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc oxide added with gallium (GZO), or indium tin oxide containing silicon oxide (ITSO) is used. You can also. Alternatively, it can be formed by a sputtering method using a target in which indium oxide containing silicon oxide is mixed with 2 to 20% by weight of zinc oxide (ZnO).

  In addition, the conductive layer 1360 is formed at the same time as the second conductive layer 1373. The conductive layer 1360 is formed so as to fill a contact hole formed so that the conductive layer 1138 is exposed.

  Note that here, the liquid crystal layer 1370, the organic compound layer 1372, and the second conductive layer 1373 are over the first conductive layers 1371 a and 1371 b and the partition layer 1374 that covers the end portions of the first conductive layers 1371 a and 1371 b. In addition, although they are sequentially stacked as a common layer, they may be selectively provided over the first conductive layer 1371a and the first conductive layer 1371b.

  Next, a conductive layer 1353 functioning as an antenna is formed in contact with the conductive layer 1360. The conductive layer 1353 is formed using a conductive material by various printing methods such as an evaporation method, a sputtering method, screen printing, or gravure printing, or a droplet discharge method. Specifically, the conductive layer 1353 includes gold (Au), platinum (Pt), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), aluminum (Al), An element selected from manganese (Mn), titanium (Ti), or the like, or an alloy material or a compound material containing these elements as a main component is formed in a single layer or a stacked layer.

  Next, the insulating layer 1366 and the insulating layer 1140 are formed over the second conductive layer 1373, the partition wall layer 1374, the conductive layer 1360, and the conductive layer 1353. Here, the insulating layer 1366 functions as a protective layer, and the insulating layer 1140 formed over the insulating layer 1366 functions as a planarization layer. The insulating layer 1366 and the insulating layer 1140 are formed using an inorganic insulating material such as silicon oxide and silicon oxynitride, an organic insulating material such as an acrylic resin and a polyimide resin, or a material including a siloxane bond by a sputtering method, a CVD method, or a coating method. To form. Note that the insulating layer 1366 is preferably formed using an inorganic insulating material such as silicon oxide or silicon oxynitride. The insulating layer 1140 is preferably formed using an organic insulating material such as an acrylic resin and a polyimide resin, or a material including a siloxane bond. Note that a layer including the transistors 1451, 1452, 1453, and 1454, the memory elements 1356a and 1356b, the conductive layer 1353 functioning as an antenna, and the like which are formed above the base insulating layer 1104 is referred to as an element layer 1141.

Next, the element layer 1141 is peeled from the substrate 1100. For example, after the opening 1142 and the opening 1144 are formed by irradiation with laser light (for example, UV light) (see FIG. 13A), the element layer 1141 is peeled from the substrate 1100 using physical force. (See FIG. 13B). Further, before the element layer 1141 is peeled from the substrate 1100, the peeling layer 1102 may be removed by introducing an etchant into the openings 1142 and 1144. As the etchant, a gas or liquid containing halogen fluoride or an interhalogen compound is used. For example, chlorine trifluoride (ClF ₃ ) is used as a gas containing halogen fluoride. Then, the element layer 1141 is peeled from the substrate 1100. Note that a part of the peeling layer 1102 may be left without being completely removed. By doing so, it is possible to suppress the consumption of the etching agent and shorten the processing time required for removing the release layer. Further, the element layer 1141 can be held on the substrate 1100 even after the peeling layer 1102 is removed. The substrate 1100 from which the element layer 1141 is peeled is preferably reused for cost reduction.

  Next, one surface of the element layer 1141 is bonded to the first base 1146 and is completely separated from the substrate 1100. Subsequently, the other surface of the element layer 1141 is bonded to the second substrate 1148, and then one or both of heat treatment and pressure treatment are performed, so that the element layer 1141 is bonded to the first substrate 1146 and the second substrate 1148. The substrate 1148 is sealed (see FIG. 14). The first base 1146 and the second base 1148 are a film showing thermoplasticity (polyolefin, polyolefin containing fluorine, polyester, etc.), paper made of a fibrous material, base film (polyester, polyamide, inorganic vapor deposition film). , Paper, etc.) and an adhesive synthetic resin film (acrylic synthetic resin, epoxy synthetic resin, etc.).

  The film is bonded to the object to be processed by thermocompression bonding. When performing the heat treatment and the pressure treatment, the adhesive layer provided on the outermost surface of the film or the layer (not the adhesive layer) provided on the outermost layer is melted by the heat treatment and adhered by the pressure. Further, an adhesive layer may be provided on the surfaces of the first base 1146 and the second base 1148, or the adhesive layer may not be provided. The adhesive layer corresponds to a layer containing an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, or a resin additive.

  Through the above steps, a semiconductor device including the memory element and the antenna of the present invention can be manufactured. Note that this embodiment mode can be freely combined with the above embodiment modes.

  According to the present invention, initial defects of a memory element can be reduced, and the manufacturing yield of a semiconductor device having the memory element can be improved.

  In addition, according to the present invention, it is possible to provide a semiconductor device having a memory element that can write (additional) data other than at the time of manufacture and can prevent forgery due to rewriting.

  In addition, the semiconductor device of this embodiment includes a memory element and an antenna, and can exchange data without contact. Furthermore, a flexible semiconductor device can be obtained through the above steps.

  Next, an example in which the semiconductor device of the present invention capable of reading and writing data without contact as shown in FIG. 14 is applied to a wireless chip will be described with reference to FIGS.

  A wireless chip 9210 using the semiconductor device of the present invention can be used for various applications. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 15A), packaging containers (wrapping paper, bottles, etc., see FIG. 15C) ), Recording media (DVD software, videotape, etc., see FIG. 15B), vehicles (bicycles, etc., see FIG. 15D), personal items (bags, glasses, etc.), foods, plants, clothing It can be used for goods such as daily necessities, electronic devices, etc., and goods such as luggage tags (see FIGS. 15E and 15F). It can also be pasted or embedded in animals and human bodies. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also simply referred to as televisions, television receivers, television receivers), mobile phones, and the like.

  The semiconductor device of the present invention can be fixed to an article by being mounted on a printed board, pasted on the surface of the article, or embedded in the article. For example, a book can be fixed to each article by being embedded in paper, and a package made of an organic resin can be embedded in the organic resin. Since the semiconductor device of the present invention realizes a small size, a thin shape, and a light weight, the design of the article itself is not impaired even after being fixed to the article. In addition, by providing the semiconductor device of the present invention in bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and if this authentication function is utilized, counterfeiting can be prevented. it can. In addition, by providing the semiconductor device of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved.

  Next, one mode of an electronic device in which the semiconductor device of the present invention is mounted will be described with reference to the drawings. The electronic device illustrated here is a mobile phone, which includes a housing 2700, a housing 2706, a panel 2701, a housing 2702, a printed wiring board 2703, operation buttons 2704, and a battery 2705 (see FIG. 16). The panel 2701 is detachably incorporated in the housing 2702, and the housing 2702 is fitted on the printed wiring board 2703. The shape and dimensions of the housing 2702 are changed as appropriate in accordance with the electronic device in which the panel 2701 is incorporated. A plurality of packaged semiconductor devices are mounted on the printed wiring board 2703, and the semiconductor device of the present invention can be used as one of them. The plurality of semiconductor devices mounted on the printed wiring board 2703 have any one function of a controller, a central processing unit (CPU), a memory, a power supply circuit, a sound processing circuit, a transmission / reception circuit, and the like.

  The panel 2701 is connected to the printed wiring board 2703 through the connection film 2708. The panel 2701, the housing 2702, and the printed wiring board 2703 are housed in the housings 2700 and 2706 together with the operation buttons 2704 and the battery 2705. A pixel region 2709 included in the panel 2701 is arranged so as to be visible from an opening window provided in the housing 2700.

  As described above, the semiconductor device of the present invention is characterized in that it is small, thin, and lightweight, and the limited space inside the housings 2700 and 2706 of the electronic device can be effectively used due to the above characteristics. .

  In addition, the semiconductor device of the present invention has a simple structure in which an organic compound layer that changes when an external voltage is applied and a layer containing a liquid crystal compound that undergoes phase transition when an external voltage is applied are sandwiched between a pair of conductive layers. Since the memory element has the structure, an electronic device using an inexpensive semiconductor device can be provided. In addition, since the semiconductor device of the present invention can be easily integrated, an electronic device using the semiconductor device including a large-capacity memory circuit can be provided.

  In addition, the memory element included in the semiconductor device of the present invention writes data by applying voltage from the outside, is nonvolatile, and can additionally write data. With the above feature, forgery due to rewriting can be prevented, and new data can be added and written. Therefore, an electronic device using a semiconductor device that achieves high functionality and high added value can be provided.

  Note that the housings 2700 and 2706 are examples of the appearance of a mobile phone, and the electronic device according to this embodiment can be modified into various modes depending on functions and uses.

FIG. 6 shows an example of a memory element of the present invention. The conceptual diagram explaining this invention. FIG. 11 illustrates an example of a semiconductor device of the invention. 4A and 4B are a top view and a cross-sectional view illustrating an example of a semiconductor device of the invention. FIG. 14 is a cross-sectional view illustrating an example of a semiconductor device of the invention. FIG. 11 illustrates an example of a semiconductor device of the invention. 4A and 4B are a top view and a cross-sectional view illustrating an example of a semiconductor device of the invention. FIG. 14 is a cross-sectional view illustrating an example of a semiconductor device of the invention. FIG. 14 is a cross-sectional view illustrating an example of a semiconductor device of the invention. FIG. 11 illustrates an example of a semiconductor device of the invention. 4A and 4B illustrate an example of a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate an example of a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate an example of a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate an example of a method for manufacturing a semiconductor device of the present invention. FIG. 11 illustrates an example of a semiconductor device of the invention. FIG. 11 illustrates an example of a semiconductor device of the invention.

Explanation of symbols

100 substrate 102 first conductive layer 104 liquid crystal layer 106 organic compound layer 108 second conductive layer 110 memory element 114 liquid crystal layer 122 first conductive layer 124 mixture region

Claims (5)

A first conductive layer;
A second conductive layer;
A layer containing a compound exhibiting liquid crystallinity sandwiched between the first conductive layer and the second conductive layer;
A layer containing an organic compound that is sandwiched between the first conductive layer and the second conductive layer and is in contact with the layer containing a compound exhibiting liquid crystallinity,
A memory element in which an electrical resistance between the first conductive layer and the second conductive layer is changed by applying a voltage between the first conductive layer and the second conductive layer,
The layer containing a compound exhibiting liquid crystallinity is formed in contact with the first conductive layer, and is a layer that undergoes a phase transition from the first phase to the second phase at least due to a temperature change ,
Before applying a voltage between the first conductive layer and the second conductive layer, the layer containing a compound exhibiting liquid crystallinity is in a solid state,
Before applying a voltage between the first conductive layer and the second conductive layer, the layer containing a compound exhibiting liquid crystallinity and the layer containing an organic compound are insulators,
By applying a voltage between the first conductive layer and the second conductive layer, a mixture including the liquid crystal compound-containing layer and the first conductive layer is formed, and the mixture is electrically conductive. A memory element characterized by exhibiting the characteristics. In claim 1,
The memory element, wherein the first phase of the layer containing a compound exhibiting liquid crystallinity is in a solid state, and the second phase is in a liquid crystal state or a liquid state. In claim 1 or claim 2,
By applying a voltage between the first conductive layer and the second conductive layer, the layer containing a compound exhibiting liquid crystallinity undergoes a phase transition from the first phase to the second phase. A memory element. In any one of Claims 1 thru | or 3,
By applying a voltage between the first conductive layer and the second conductive layer, the shape of the layer containing the organic compound changes, and the first conductive layer and the second conductive layer are short-circuited. And a storage element. In any one of Claims 1 thru | or 4,
The memory element, wherein the layer containing an organic compound is a layer containing an organic resin, a layer containing an organic compound having a hole transporting property, or a layer containing an organic compound having an electron transporting property.

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