JP4974555B2 - Memory element - Google Patents

Description

  The present invention relates to a memory element, a memory device including the memory element, and a semiconductor device.

  In recent years, development of semiconductor devices having various functions in which a plurality of circuits are integrated on an insulating surface has been promoted. In addition, development of a semiconductor device capable of transmitting and receiving data wirelessly by providing an antenna is in progress. Such a semiconductor device is called a wireless chip (ID tag, IC tag, IC chip, RF (Radio Frequency) tag, wireless tag, electronic tag, or RFID (Radio Frequency Identification)) tag, and already part of it Has been introduced in the market.

Many of these semiconductor devices in practical use have a circuit (also referred to as an IC (Integrated Circuit) chip) using a semiconductor substrate such as Si and an antenna, and the IC chip is a memory circuit (also referred to as a memory). ) And a control circuit. In particular, by providing a memory circuit capable of storing a large amount of data, a semiconductor device with higher functions and higher added value can be provided. In addition, these semiconductor devices are required to be manufactured at a low cost, and in recent years, an organic memory using an organic compound for a memory circuit or the like has been developed (for example, Patent Document 1).
JP 2002-26277 A

  The storage circuit, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), FeRAM (Ferroelectric Random Access Memory), mask ROM (Read Only Memory), EPROM (Electrically Programmable Read Only Memory), EEPROM (Electrically Erasable and Programmable Read Only Memory), flash memory, and the like. Among these, DRAM and SRAM are volatile storage circuits, and data is erased when the power is turned off. Therefore, it is necessary to write data every time the power is turned on. FeRAM is a non-volatile memory circuit, but a manufacturing process increases because a capacitor element including a ferroelectric layer is used. Although the mask ROM has a simple structure, it is necessary to write data in the manufacturing process and cannot be additionally written. Although EPROM, EEPROM, and flash memory are non-volatile memory circuits, the number of manufacturing steps increases because an element including two gate electrodes is used.

  On the other hand, in a memory element using an organic compound, an organic compound is provided between a pair of electrodes to form a memory element. However, when the organic compound layer is formed thick, current does not easily flow and the writing voltage increases. Conversely, when the organic compound layer is formed thin in order to reduce the writing voltage, there is a case where a short circuit occurs between the electrodes in the initial state. As a result, the reliability of the memory device and the semiconductor device may be reduced.

  In view of the above problems, an object of the present invention is to provide a non-volatile memory element capable of additionally writing data other than at the time of manufacture and capable of preventing forgery or the like due to rewriting, a memory device having the memory element, and a semiconductor device. And Another object is to provide a highly reliable and inexpensive memory device and semiconductor device.

According to one aspect of the present invention, a first conductive layer, a second conductive layer, the first conductive layer, an organic compound layer sandwiched between the second conductive layers, the first conductive layer, A memory element comprising: a first insulating layer provided between the second conductive layers and in contact with the first conductive layer and having a thickness of 0.1 nm to 4 nm.

Another aspect of the present invention is a first conductive layer, a second conductive layer, an organic compound layer sandwiched between the first conductive layer and the second conductive layer, and the first conductive layer. And a first insulating layer having a thickness of 0.1 nm to 4 nm in contact with the first conductive layer, the first conductive layer, and the second conductive layer. And a second insulating layer having a thickness of 0.1 nm or more and 4 nm or less in contact with the second conductive layer.

As shown in FIG. 3A, the first and second insulating layers may be discontinuous layers in which non-uniform shapes are randomly dispersed. Further, as shown in FIG. 3B, a striped discontinuous layer may be used. As the striped discontinuous layer, the width of the discontinuous layer and the interval between adjacent discontinuous layers may be equal. Moreover, the width | variety of a discontinuous layer and the space | interval of an adjacent discontinuous layer may differ. Further, as shown in FIG. 3C, a net-like discontinuous layer may be used.

Further, the first and second insulating layers may be continuous layers covering at least the surface of the first conductive layer as shown in FIG. Furthermore, as shown in FIG. Typically, the interface between the first insulating layer or the second insulating layer and the organic compound layer may have unevenness. The interface between the first insulating layer and the first conductive layer or the interface between the second insulating layer and the second conductive layer may have unevenness.

Another aspect of the present invention is a first conductive layer, a second conductive layer, an organic compound layer sandwiched between the first conductive layer and the second conductive layer, and the first conductive layer. And an insulating particle having a diameter of 0.1 nm or more and 4 nm or less that is provided between the second conductive layer and in contact with the first conductive layer.

Another aspect of the present invention is a first conductive layer, a second conductive layer, an organic compound layer sandwiched between the first conductive layer and the second conductive layer, and the first conductive layer. First insulating particles having a diameter of 0.1 nm to 4 nm in contact with the first conductive layer, the first conductive layer, and the second conductive layer. And a second insulating particle having a diameter of 0.1 nm or more and 4 nm or less in contact with the second conductive layer.

The organic compound layer of the memory element of the present invention is formed using an electron transport material or a hole transport material. In addition, data is written by a change in resistance value due to voltage application. In addition, a part of the first conductive layer and the second conductive layer which form a pair is connected to the memory element after writing. Further, a diode connected to the first conductive layer or the second conductive layer may be included.

Another embodiment of the present invention is a memory device including a memory cell array in which the memory elements are arranged in a matrix and a writing circuit.

The memory cell array and the writing circuit are provided over a glass substrate or a flexible substrate, and the writing circuit may be formed using a thin film transistor. The memory cell array and the writing circuit may be provided over a single crystal semiconductor substrate, and the writing circuit may be formed using a field effect transistor.

Another embodiment of the present invention includes the above memory element, a first transistor connected to the memory element, a conductive layer functioning as an antenna, and a second transistor connected to the conductive layer. It is a semiconductor device.

In the above semiconductor device, the first transistor, the second transistor, the memory element, and the conductive layer functioning as an antenna may be formed over the first substrate. The first transistor is formed over the first substrate, the storage element is formed over the second substrate, and the conductive layer functioning as the source wiring or the drain wiring of the first transistor and the storage element are electrically conductive. It may be connected via a property particle. The second transistor is formed over the first substrate, the conductive layer functioning as an antenna is formed over the second substrate, the conductive layer functioning as the source wiring or drain wiring of the second transistor, and the antenna The functional conductive layer may be connected via conductive particles.

  The thicknesses of the first insulating layer and the second insulating layer of the present invention are as follows: AFM (Atomic Force Microscope), DFM (Dynamic Force Microscope), MFM (Magnetic Force Microscope, Magnetic Force Microscope). , EFM (Electric Force Microscope, electric force microscope), TEM (Transmission Electron Microscope, transmission electron microscope) and the like.

  By using the present invention, it is possible to obtain a semiconductor device in which data can be written (added) other than during chip manufacturing and forgery due to rewriting can be prevented. In the memory element of the present invention, an insulating layer having a thickness of 4 nm or less, preferably 2 nm or less is provided between the conductive layer and the organic compound layer so as to be in contact with the conductive layer, so that a tunnel current is generated in the insulating layer. Therefore, variation in applied voltage and current value at the time of writing to the memory element can be reduced. Further, by providing an insulating layer having a thickness of 4 nm or less, preferably 2 nm or less, between the conductive layer and the organic compound layer so as to be in contact with the conductive layer, the charge injection property due to the tunnel effect is increased, and the organic compound layer The film thickness can be increased and a short circuit in the initial state can be prevented. As a result, the reliability of the memory device and the semiconductor device can be improved. Furthermore, since the memory device and the semiconductor device of the present invention have a memory element with a simple structure in which an organic compound layer is sandwiched between a pair of conductive layers, an inexpensive memory device and semiconductor device can be provided.

Embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.

(Embodiment 1)
In this embodiment, structural examples of memory elements included in the memory device of the present invention will be described with reference to drawings. More specifically, the case where the structure of the memory device is a passive matrix type will be described.

  FIG. 5A shows a configuration example of the organic memory of this embodiment, which includes a memory cell array 22 in which memory cells 21 are provided in a matrix, a column decoder 26a, a read circuit 26b, and a selector 26c. It has a bit line driving circuit 26, a word line driving circuit 24 having a row decoder 24a and a level shifter 24b, an interface 23 having a writing circuit and the like and performing exchanges with the outside. Note that the structure of the memory circuit 16 shown here is just an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included, and a write circuit may be provided in the bit line driver circuit.

  The memory cell 21 includes a first conductive layer that forms a bit line Bx (1 ≦ x ≦ m), a second conductive layer that forms a word line Wy (1 ≦ y ≦ n), and a first conductive layer And an organic compound layer. The organic compound layer is provided as a single layer or a stacked layer between the first conductive layer and the second conductive layer.

  An example of a top surface structure and a cross-sectional structure of the memory cell array 22 is shown in FIG. Note that FIG. 1A illustrates a top surface structure of the memory cell array 22, and a cross-sectional structure between A and B in FIG. 1A corresponds to FIG. Note that the insulating layer 27 functioning as a protective film is omitted in FIG.

Memory cells 21 are provided in a matrix in the memory cell array 22 (see FIG. 1A). The memory cell 21 includes a memory element 80 (see FIG. 1B). The memory element 80 includes a first conductive layer 31 extending in the first direction on the substrate 30, an organic compound layer 29 covering the first conductive layer 31, and a second direction orthogonal to the first direction. And an insulating layer 32 in contact with the first conductive layer 31 and the organic compound layer 29. The insulating layer 32 is an insulating layer capable of injecting electric charges into the organic compound layer at a predetermined voltage or higher due to the tunnel effect. Here, an insulating layer 27 that functions as a protective film is provided so as to cover the second conductive layer 28.

In the configuration of the memory element 80, as the substrate 30, a glass substrate, a flexible substrate, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, paper made of a fibrous material, or the like can be used. The flexible substrate is a substrate that can be bent (flexible), and examples thereof include a plastic substrate made of polycarbonate, polyacrylate, polyethersulfone, or the like. Further, a film exhibiting thermoplasticity (made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, etc.) can also be used. In addition, the memory cell array 22 may be provided above a field effect transistor (FET) formed on a semiconductor substrate such as Si or above a thin film transistor (TFT) formed on a substrate such as glass. it can.

  The first conductive layer 31 and the second conductive layer 28 can be a single layer or a stacked structure made of a highly conductive metal, alloy, compound, or the like. Typically, a metal, an alloy, a conductive compound, or a mixture thereof having a large work function (specifically, 4.0 eV or more), or a metal, an alloy having a small work function (specifically, 3.8 eV or less). , Conductive compounds, and mixtures thereof can be used.

As typical examples of metals, alloys, and conductive compounds having a high work function (specifically, 4.0 eV or more), indium tin oxide (hereinafter referred to as ITO), silicon-containing indium tin oxide, 2 Examples thereof include indium oxide containing -20% zinc oxide (ZnO). Also, titanium (Ti), gold (Au), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), copper (Cu ), Palladium (Pd), or a nitride of a metal material (for example, titanium nitride: TiN, tungsten nitride (WN), molybdenum nitride (MoN)), or the like can also be used.

Typical examples of metals, alloys, and conductive compounds having a small work function (specifically, 3.8 eV or less) include metals belonging to Group 1 or Group 2 of the element periodic rule, that is, lithium (Li) or cesium (Cs). Alkali metals such as magnesium, alkaline earth metals such as magnesium (Mg), calcium (Ca), strontium (Sr), and alloys containing any of these (MgAg, AlLi), europium (Er), ytterbium (Yb) And rare earth metals and alloys containing them.

Note that in the case where an electrode for injecting holes into the organic compound layer, that is, an anode is used for the first conductive layer 31 or the second conductive layer 28, an electrode having a large work function is preferably used. Conversely, when an electrode for injecting electrons into the organic compound layer is used, it is preferable to use an electrode having a small work function.

  Further, the first conductive layer 31 and the second conductive layer 28 are formed by stacking a layer formed of the above highly conductive metal, alloy, or compound and a layer formed of a semiconductor material. Also good. In this case, a semiconductor layer is preferably provided on the side in contact with the insulating layer 32 or the organic compound layer 29.

  As a layer formed of a semiconductor material, a layer formed using a semiconductor element such as silicon or germanium, tin oxide, molybdenum oxide, indium oxide, zinc oxide, tungsten oxide, titanium oxide, copper oxide, nickel oxide, oxide A layer formed using a semiconductor oxide such as vanadium, yttrium oxide, or chromium oxide can be used as appropriate.

  The first conductive layer 31 is formed using a vapor deposition method, a sputtering method, a CVD method, a printing method, an electrolytic plating method, an electroless plating method, or the like.

The second conductive layer 28 can be formed by vapor deposition, sputtering, CVD, printing, or droplet discharge. Here, the droplet discharge method is a method of forming a pattern with a predetermined shape by discharging a droplet of a composition containing fine particles from a minute hole.

Here, after a titanium film with a thickness of 50 to 200 nm is formed by a sputtering method, the first conductive layer 31 is formed by etching into a desired shape by a photolithography method. Also, aluminum is deposited by a deposition method to form the second conductive layer 28 having a thickness of 50 to 200 nm.

The organic compound layer 29 is formed of an organic compound whose crystal state, conductivity, and shape are changed by applying an external voltage. The organic compound layer 29 may be provided as a single layer, or a plurality of layers formed of different organic compounds may be provided.

Note that the organic compound layer 29 is formed with a film thickness at which the electrical resistance of the memory element changes due to external voltage application. A typical film thickness of the organic compound layer 29 is 5 nm to 100 nm, preferably 10 nm to 60 nm, preferably 5 nm to 20 nm, preferably 5 nm to 10 nm.

The organic compound layer 29 can be formed using an organic compound having a hole transporting property or an organic compound having an electron transporting property.

As an organic compound having a hole-transport property, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD), 4,4′-bis [N -(3-Methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD) or 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: TDATA) 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) and 4,4′-bis (N- (4- ( N, N-di-m-tolylamino) phenyl) -N-phenylamino) biphenyl (abbreviation: DNTPD) and other aromatic amine-based compounds (that is, having a benzene ring-nitrogen bond) and phthalocyanines (abbreviation: H ₂ Pc), copper phthalosis A phthalocyanine compound such as anine (abbreviation: CuPc) or vanadyl phthalocyanine (abbreviation: VOPc), PVK (polyvinylcarbazole), or the like can be used. The substances mentioned here are mainly substances having a hole mobility of 10 ⁻⁶ cm ² / Vs or higher, preferably 10 ⁻⁶ to 10 ⁻² cm ² / Vs.

Examples of the organic compound having a high electron-transport property include tris (8-quinolinolato) aluminum (abbreviation: Alq), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), and bis (10-hydroxybenzo [h]. -Quinolinato) Beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), etc. Can be used. In addition, bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) A material such as a metal complex having an oxazole-based or thiazole-based ligand such as ₂ ) can also be used. In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- ( 4-biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2, 4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), and the like can be used. The substances mentioned here are mainly substances having an electron mobility of 10 ⁻⁶ cm ² / Vs or higher, preferably 10 ⁻⁶ to 10 ⁻² cm ² / Vs.

  Furthermore, in the above organic compound, a plurality of different organic compounds may be stacked to form an organic compound layer.

  Furthermore, an organic compound in which a plurality of the organic compounds are mixed may be formed.

  The organic compound layer 29 can be formed using a vapor deposition method, an electron beam vapor deposition method, a sputtering method, a CVD method, or the like. In addition, as another method for forming the organic compound layer 29, a spin coating method, a sol-gel method, a printing method, a droplet discharge method, or the like may be used, or the above method may be combined with these methods.

The insulating layer 32 is a layer that injects holes or electrons from the first conductive layer or the second conductive layer into the organic compound layer by a tunnel effect. Typically, the electrical conductivity is 10 ⁻¹⁰ to 10 ⁻² S / m or less, preferably 10 ⁻¹⁰ to 10 ⁻¹⁴ S / m. The insulating layer 32 is formed with a thickness capable of injecting charges into the organic compound layer 29 by a tunnel effect at a predetermined voltage. A typical thickness of the insulating layer 32 is an insulating layer having a thickness of 0.1 nm to 4 nm, preferably 1 nm to 4 nm, preferably 0.1 nm to 2 nm, preferably 1 nm to 2 nm. Since the thickness of the insulating layer 32 is as extremely thin as 0.1 nm or more and 4 nm or less, a tunnel effect occurs in the insulating layer 32 and the charge injection property to the organic compound layer 29 is enhanced. Therefore, when the insulating layer 32 is thicker than 4 nm, the tunnel effect in the insulating layer 32 does not occur, charge injection into the organic compound layer 29 becomes difficult, and the applied voltage at the time of writing to the memory element increases. In addition, since the thickness of the insulating layer 32 is as extremely thin as 0.1 nm or more and 4 nm or less, the throughput is improved.

The insulating layer 32 is formed of a thermally and chemically stable compound. Typically, it is preferable to form with an inorganic compound or an organic compound which is not carrier-injected.

Representative examples of the inorganic compound having insulating properties include Li ₂ O, Na ₂ O, K ₂ O, Rb ₂ O, BeO, MgO, CaO, SrO, BaO, Sc ₂ O ₃ , ZrO ₂ , HfO ₂ , RfO. ₂ , TaO, TcO, Fe ₂ O ₃ , CoO, PdO, Ag ₂ O, Al ₂ O ₃ , Ga ₂ O ₃ , Bi ₂ O _3, etc. Insulating oxides, LiF, NaF, KF , RbF, BeF ₂ , MgF ₂ , CaF ₂ , SrF ₂ , BaF ₂ , AlF ₃ , NF ₃ , SF ₆ , AgF, MnF _{3, and} other insulating fluorides, LiCl, NaCl, KCl, CsCl , BeCl ₂ , CaCl ₂ , BaCl ₂ , AlCl ₃ , SiCl ₄ , GeCl ₄ , SnCl ₄ , AgCl, ZnCl, TiCl ₄ , TiCl ₃ , ZrCl ₄ , FeCl ₃ , PdCl ₂ , SbCl ₃ , SbCl ₂ , SrCl ₂ , TlCl, CuCl, MnCl ₂ , RuCl _2, etc., an insulating chloride, KBr, CsBr, AgBr, BaBr ₂ , SiBr ₄ , bromides having an insulating property typified by such _{LiBr, NaI, KI, BaI 2} , TlI, AgI, TiI 4, CaI 2, SiI 4, iodides having an insulating property typified by CsI or the _like, Li 2 _{CO 3, K 2 CO 3, Na 2 CO} 3, MgCO 3, CaCO 3, SrCO 3, BaCO 3, MnCO 3, FeCO 3, CoCO 3, NiCO 3, CuCO 3, Ag 2 CO 3, insulating typified ZnCO _3, etc. Carbonates having properties, Li ₂ SO ₄ , K ₂ SO ₄ , Na ₂ SO ₄ , MgSO ₄ , Ca SO ₄ , SrSO ₄ , BaSO ₄ , Ti ₂ (SO ₄ ) ₃ , Zr (SO ₄ ) ₂ , MnSO ₄ , FeSO ₄ , Fe ₂ (SO ₄ ) ₃ , CoSO ₄ , Co ₂ (SO ₄ ) ₃ , NiSO ₄ , CuSO ₄ , Ag ₂ SO ₄ , ZnSO ₄ , Al ₂ (SO ₄ ) ₃ , In ₂ (SO ₄ ) ₃ , SnSO ₄ , Sn (SO ₄ ) ₂ , Sb ₂ (SO ₄ ) ₃ , Bi ₂ ( Insulative sulfates represented by SO ₄ ) _{3 and the} like, LiNO ₃ , KNO ₃ , NaNO ₃ , Mg (NO ₃ ) ₂ , Ca (NO ₃ ) ₂ , Sr (NO ₃ ) ₂ , Ba (NO ₃₎ ) ₂ , Ti (NO ₃ ) ₄ , Sr (NO ₃ ) ₂ , Ba (NO ₃ ) ₂ , Ti (NO ₃ ) ₄ , Zr (NO ₃ ) ₄ , Mn (NO ₃ ) ₂ , Fe (NO ₃ ) ₂ , Fe (NO ₃ ) ₃ , Co (NO ₃ ) ₂ , Ni (NO ₃ ) ₂ , Cu (NO ₃ ) ₂ , AgNO ₃ , Zn (NO ₃ ) ₂ , Al (NO ₃ ) ₃ , In (NO ₃ ) ₃ , Sn ( Nitrate having insulation properties typified by NO ₃ ) _{2 and the} like, and nitrides having insulation properties typified by AlN, SiN and the like can be mentioned.

Note that in the case where the insulating layer 32 is formed using an inorganic compound, the thickness of the insulating layer is 0.1 nm to 3 nm, preferably 1 nm to 2 nm. When the thickness of the insulating layer is greater than 3 nm, the applied voltage at the time of writing increases.

  When the insulating layer 32 is formed using an organic compound having an insulating property, the organic compound having an insulating property is preferably one in which carrier injection is difficult and has a band gap of 3.5 to 6 eV, preferably 4 eV or more to 5 eV. It is an organic compound. Representative examples include organic materials such as polyimide, acrylic, polyamide, benzocyclobutene, polyester, and other polymer materials, and novolak resins, melamine resins, phenol resins, epoxy resins, silicon resins, furan resins, diallyl phthalate resins, and the like. Resin.

  Note that the insulating layer 32 is preferably formed using an organic compound having a HOMO level different from that of the compound forming the organic compound layer. In the case where the insulating layer 32 is formed of an organic compound, the thickness of the insulating layer is preferably 0.1 nm to 4 nm, more preferably 1 nm to 4 nm.

  Further, the insulating layer 32 may be formed using a plurality of inorganic compounds having the above insulating properties. Alternatively, a plurality of the above organic compounds may be used. Furthermore, you may form by mixing multiple inorganic compounds and the said organic compound which have the said insulating property.

As a method for forming the insulating layer 32, an evaporation method, an electron beam evaporation method, a sputtering method, a CVD method, or the like can be used. A spin coating method, a sol-gel method, a printing method, a droplet discharge method, or the like can be used.

Here, the shape of the insulating layer 32 will be described with reference to FIG. FIG. 3 is a top view in which a first conductive layer 31 and an insulating layer are formed on a substrate 30 having an insulating property. Here, the insulating layer 32 is shown as insulating layers 32a, 32b, and 32c, respectively.

As shown in FIG. 3A, the insulating layer 32a is a discontinuous layer dispersed over the first conductive layer. That is, an island shape covering at least a part of the first conductive layer 31 can be formed. Here, a plurality of insulating layers 32a which are discontinuous layers are randomly dispersed on the surface of the first conductive layer 31 and the insulating substrate 30.

As shown in FIG. 3B, the insulating layer 32b can be a striped discontinuous layer. Here, the insulating layer 32b has a stripe shape extending in a second direction having a predetermined angle (greater than 0 degree and less than 90 degrees) with respect to the first direction in which the first conductive layer 31 extends. The insulating layer 32b may have a stripe shape extending in a direction parallel to the first direction. Furthermore, the stripe shape extended in the direction orthogonal to the 1st direction may be sufficient.

Further, as shown in FIG. 3C, the insulating layer 32c can be a mesh-like discontinuous layer.

Further, as illustrated in FIG. 1C, a continuous layer that covers the surface of the first conductive layer 31 such as the insulating layer 33 may be used instead of the insulating layer 32. In this case, the insulating layer 33 is preferably a monomolecular film. Furthermore, as shown in FIG. 1D, a continuous layer that covers the surface of the first conductive layer 31 such as the insulating layer 34 and has irregularities may be used instead of the insulating layer 32. However, in this case, the thickness of the convex portion of the insulating layer is 1 nm to 4 nm, preferably 2 nm to 4 nm, and the thickness of the concave portion is preferably 0.1 nm to less than 2 nm, and more preferably 1 nm to less than 2 nm. .

In addition, as illustrated in FIG. 1E, insulating particles 35 may be provided between the first conductive layer and the organic compound layer instead of the insulating layer 32. The particle size of the insulating particles at this time is 0.1 nm or more and 4 nm or less.

Further, the insulating layers 32 to 34 or the insulating particles 35 shown in FIGS. 1B to 1E may be provided between the organic compound layer 29 and the second conductive layer 28 (FIG. 2A). reference.). In FIG. 2A, an insulating layer 36 having a shape as shown in FIG. 1B is provided between the organic compound layer 29 and the second conductive layer 28.

2B, the first insulating layer 37 is provided between the first conductive layer 31 and the organic compound layer 29, and the organic compound layer 29 and the second conductive layer 28 are provided. The second insulating layer 38 may be included. At this time, as the first insulating layer 37 and the second insulating layer 38, the insulating layers 32 to 34 and the insulating particles 35 having the shapes shown in FIGS. 1B to 1E can be used as appropriate. Here, each of the first insulating layer 37 and the second insulating layer 38 has a shape similar to that of the insulating layer 32 in FIG.

  Further, in the memory element, an element having a rectifying property may be provided on the side opposite to the organic compound layer 29 with the first conductive layer 31 interposed therebetween (FIG. 2C). The rectifying element is a Schottky diode, a diode having a PN junction, a diode having a PIN junction, or a transistor in which a gate electrode and a drain electrode are connected. Here, a diode 44 including the third conductive layer 41 and the semiconductor layer 42 is provided in contact with the first conductive layer 31. Note that a rectifying element may be provided on the side opposite to the organic compound layer with the second conductive layer interposed therebetween. Further, the rectifying element may be provided between the organic compound layer 29 and the first conductive layer 31. Further, a rectifying element may be provided between the organic compound layer 29 and the second conductive layer 28. Typical examples of the diode include a PN junction diode, a diode having a PIN junction, an avalanche diode, and the like. Moreover, you may use the diode of another structure. As described above, by providing a rectifying element, current flows only in one direction, so that an error is reduced and a read margin is improved. Reference numeral 43 denotes an insulating layer for insulating the diode.

  Further, a thin film transistor (TFT) may be provided over an insulating substrate and the memory element 80 may be provided thereover, or a semiconductor substrate such as Si or an SOI substrate may be used instead of the insulating substrate. Alternatively, a field effect transistor (FET) may be formed, and a memory element 80 may be provided thereon. Note that although the example in which the memory element is formed over a thin film transistor or a field effect transistor is described here, the memory element may be provided by bonding the thin film transistor or the field effect transistor. In this case, the memory element and the thin film transistor or the field effect transistor can be provided by being manufactured in separate steps and then bonded together using a conductive film, an anisotropic conductive adhesive, or the like. Further, any configuration of the thin film transistor or the field effect transistor may be used as long as it is a known one.

  In addition, when there is a concern about the influence of the electric field in the lateral direction between adjacent memory elements, the organic compound layer provided in each memory element is separated to separate the organic compound layer provided in each memory element. A partition wall (insulating layer) may be provided therebetween. Alternatively, an organic compound layer may be selectively provided for each memory cell.

  Typically, when the organic compound layer 29 is provided so as to cover the first conductive layer 31, the step of the organic compound layer 29 caused by the step of the first conductive layer 31 or the lateral direction between the memory cells is formed. In order to prevent the influence of an electric field, a partition wall (insulating layer) 39 may be provided between the first conductive layers 31 (FIG. 2D). Note that in the cross section of the partition wall (insulating layer) 39, the side surface of the partition wall (insulating layer) 39 is inclined at an angle of 10 ° to less than 60 °, preferably 25 ° to 45 ° with respect to the surface of the first conductive layer 31. It is preferable to have an angle. Furthermore, it is preferable that it is curved. Thereafter, the insulating layer 32, the organic compound layer 29, and the second conductive layer 28 are formed so as to cover the first conductive layer 31 and the partition wall (insulating layer) 39.

Alternatively, the partition wall (insulating layer) 39 may be formed after the insulating layer 32 is formed over the first conductive layer 31. In this case, in the step of forming the partition wall (insulating layer) 39 using the etching process, the insulating layer 32 is not etched, and a compound that selectively etches the material forming the partition wall (insulating layer) 39 is used. It is preferable to form the insulating layer 32 and the partition wall (insulating layer) 39.

  When the partition wall (insulating layer) 39 is formed, a residue generated in the step of forming the partition wall (insulating layer) 39 using an etching process may be used as the insulating layer 32.

Further, instead of the partition wall (insulating layer) 39, an interlayer insulating layer 40a covering a part of the first conductive layer 31 on the substrate 30, on the first conductive layer 31 extending in the first direction, A partition wall (insulating layer) 40b provided over the interlayer insulating layer may be provided (FIG. 2E).

The interlayer insulating layer 40 a covering a part of the first conductive layer 31 has an opening for each memory element 80. The partition (insulating layer) 40b is provided in a region where no opening is formed in the interlayer insulating layer. Further, the partition wall (insulating layer) 40 b extends in the second direction similarly to the second conductive layer 28. In addition, the partition wall (insulating layer) 40b has an inclination angle of 95 degrees or more and 135 degrees or less with respect to the interlayer insulating layer surface.

The partition wall (insulating layer) 40b is formed by using a positive photosensitive resin in which an unexposed portion remains, and adjusting the exposure amount or the development time so that the lower part of the pattern is etched more in accordance with a photolithography method. The height of the partition wall (insulating layer) 40 b is set to be larger than the thickness of the organic compound layer 29 and the second conductive layer 28. As a result, only the step of depositing the organic compound layer 29 and the second conductive layer 28 on the entire surface of the substrate 30 is separated into a plurality of electrically independent regions and intersects the first direction. A stripe-shaped organic compound layer 29 and a second conductive layer 28 extending in a straight line can be formed. For this reason, the number of processes can be reduced. Note that the organic compound layer 29c and the conductive layer 28c are also formed on the partition wall (insulating layer) 40b, but these are separated from the organic compound layer 29 and the conductive layer 28.

  When data is written by applying a voltage, one memory cell 21 is selected by the row decoder 24a, the column decoder 26a, and the selector 26c, and then data is written to the memory cell 21 using a write circuit. (See FIG. 5A). When a voltage is applied between the first conductive layer 31 and the second conductive layer 28a of the memory cell, electric charges are charged between the first conductive layer 31 and the insulating layer 32 (see FIG. 4A). . When a voltage equal to or higher than a predetermined voltage is applied between the first conductive layer 31 and the second conductive layer 28a, the charge is injected into the organic compound layer, and a current flows through the organic compound layer 29a. Joule heat is generated at 29a. With the generation of this heat, the temperature of the organic compound layer rises above the glass transition point, the organic compound layer 29a increases in fluidity, and the film thickness becomes nonuniform. As a result, the organic compound layer 29b and the second conductive layer are deformed, the first conductive layer 31 and the second conductive layer 28b are short-circuited, and the electric resistance of the memory element is changed (see FIG. 4B). .) In FIG. 4B, 29b is a deformed organic compound layer. In addition, when data is written to the memory cell, a forward voltage is applied. Further, a reverse voltage may be applied.

  A shorted memory element has a significantly lower electrical resistance than other memory elements. As described above, data is written by applying a change in electric resistance between two conductive layers by applying a voltage.

  Hereinafter, a specific operation when data is written into the organic memory will be described (see FIG. 5).

When writing data “1” to the memory cell 21, first, the memory cell 21 is selected by the row decoder 24a, the level shifter 24b, the column decoder 26a, and the selector 26c. Specifically, a predetermined voltage V2 is applied to the word line W3 connected to the memory cell 21 by the row decoder 24a and the level shifter 24b. Further, the bit line B3 connected to the memory cell 21 is connected to the read / write circuit 26b by the column decoder 26a and the selector 26c. Then, the write voltage V1 is output from the read / write circuit 26b to the bit line B3. Thus, the voltage Vw = V1−V2 is applied between the first conductive layer and the second conductive layer constituting the memory cell 21. By appropriately selecting the voltage Vw, the organic compound layer 29 provided between the conductive layers is changed physically or electrically, and data “1” is written. Specifically, at the read operation voltage, the electrical resistance between the first conductive layer and the second conductive layer in the data “1” state is significantly smaller than that in the data “0” state. It is good to change as follows. For example, it may be appropriately selected from the range of (V1, V2) = (0V, 5-15V), or (3-5V, -12--2V). The voltage Vw may be 5 to 15V, or -5 to -15V.

Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. For example, unselected word lines and unselected bit lines may be set in a floating state. The first conductive layer and the second conductive layer constituting the memory cell must have characteristics such as diode characteristics that can ensure selectivity.

On the other hand, when data “0” is written in the memory cell 21, it is not necessary to apply an electrical action to the memory cell 21. In the circuit operation, for example, as in the case of writing “1”, the memory cell 21 is selected by the row decoder 24a, the level shifter 24b, the column decoder 26a, and the selector 26c, but from the read / write circuit 26b to the bit line B3. Is set to the same level as the potential of the selected word line W3 or the potential of the non-selected word line, and between the first conductive layer and the second conductive layer constituting the memory cell 21, What is necessary is just to apply the voltage (for example, -5-5V) of the grade which does not change an electrical property.

  Next, a specific operation when data is read from the organic memory will be described (FIG. 5B). In reading data, the electrical characteristics between the first conductive layer and the second conductive layer constituting the memory cell are different between the memory cell having data “0” and the memory cell having data “1”. Use it. For example, the effective electrical resistance between the first conductive layer and the second conductive layer constituting the memory cell having data “0” (hereinafter simply referred to as the electrical resistance of the memory cell) is R0 at the read voltage. A method of reading data by using the difference in electric resistance when the electric resistance of the memory cell having data “1” is R1 in the read voltage will be described. Note that R1 << R0. The read / write circuit can be considered to be a read / write circuit 26b using, for example, a resistance element 46 and a differential amplifier 47 shown in FIG. The resistance element 46 has a resistance value Rr, and R1 <Rr <R0. A transistor 48 may be used instead of the resistance element 46, and a clocked inverter 49 may be used instead of the differential amplifier (FIG. 5C). The clocked inverter 49 receives a signal φ or an inverted signal φ that becomes Hi when reading and becomes Lo when not reading. Of course, the circuit configuration is not limited to FIGS. 5B and 5C.

When reading data from the memory cell 21, first, the memory cell 21 is selected by the row decoder 24a, the level shifter 24b, the column decoder 26a, and the selector 26c. Specifically, a predetermined voltage Vy is applied to the word line Wy connected to the memory cell 21 by the row decoder 24a and the level shifter 24b. Further, the bit line Bx connected to the memory cell 21 is connected to the terminal P of the read / write circuit 26b by the column decoder 26a and the selector 26c. As a result, the potential Vp of the terminal P becomes a value determined by resistance division by the resistance element 46 (resistance value Rr) and the memory cell 21 (resistance value R0 or R1). Therefore, when the memory cell 21 has data “0”, Vp0 = Vy + (V0−Vy) × R0 / (R0 + Rr). When the memory cell 21 has data “1”, Vp1 = Vy + (V0−Vy) × R1 / (R1 + Rr). As a result, in FIG. 5B, Vref is selected to be between Vp0 and Vp1, and in FIG. 5C, the change point of the clocked inverter is selected to be between Vp0 and Vp1. Thus, Lo / Hi (or Hi / Lo) is output as the output potential Vout according to the data “0” / “1”, and reading can be performed.

For example, the differential amplifier is operated at Vdd = 3V, and Vy = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9, when the memory cell data is “0”, Vp0 = 2.7 V and Vout is Hi, and when the memory cell data is “1”, Vp1 = 0.3V and Lo is output as Vout. Thus, the memory cell can be read.

According to the above method, the state of the electrical resistance of the organic compound layer 29 is read as a voltage value using the difference in resistance value and resistance division. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. In addition, when the electrical characteristics of the memory cell have data “0” and “1” and diode characteristics with different threshold voltages, reading may be performed using the threshold voltage difference. It is also possible to adopt a method of reading the resistance value of the memory element by replacing it with the magnitude of the current, or a method of precharging the bit line.

  According to this embodiment, an insulating layer having a thickness of 4 nm or less, preferably 2 nm or less is provided between the conductive layer and the organic compound layer, whereby charges are injected into the organic compound layer by a tunnel effect. By the tunnel effect of the insulating layer, variation in applied voltage and current value at the time of writing to the memory element can be reduced. Further, by providing an insulating layer having a thickness of 4 nm or less, preferably 2 nm or less, between the conductive layer and the organic compound layer, even if the organic compound layer of the memory element is thin, a short circuit between the electrodes can be prevented. It is possible to reduce. In addition, the organic compound layer sandwiched between the pair of conductive layers can be formed thick due to the increase in charge injection property. As a result, the roughness of the surface of the first conductive layer causes the memory element before writing. The short circuit between the conductive layers can be prevented, and the reliability of the memory device can be improved. As a result, the reliability of the memory device and the semiconductor device can be improved.

(Embodiment 2)
In this embodiment, a memory device having a structure different from that in Embodiment 1 is described. Specifically, a case where the structure of the memory device is an active matrix type will be described.

  6A shows an example of a structure of the organic memory shown in this embodiment mode. A memory cell array 222 in which memory cells 221 are provided in a matrix, a column decoder 226a, a reading circuit 226b, and a selector 226c are included. A bit line driver circuit 226 having a word decoder; a word line driver circuit 224 having a row decoder 224a and a level shifter 224b; an interface 223 having a write circuit and the like and performing exchange with the outside. Note that the structure of the memory circuit 216 shown here is just an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included, and a writing circuit may be provided in the bit line driver circuit.

  The memory cell 221 includes a first wiring that forms a bit line Bm (1 ≦ m ≦ x), a second wiring that forms a word line Wn (1 ≦ n ≦ y), a transistor 240, and a storage element 241. And have. The memory element 241 has a structure in which an insulating layer and an organic compound layer are sandwiched between a pair of conductive layers.

  Next, an example of a top view and a cross-sectional view of the memory cell array 222 having the above structure is described with reference to FIGS. Note that FIG. 7A illustrates an example of a top view of the memory cell array 222, and FIG. 7B illustrates a cross-sectional view taken along a line AB in FIG. 7A. Note that in FIG. 7A, the partition wall (insulating layer) 249, the insulating layer 242, the organic compound layer 244, and the second conductive layer 245 which are formed over the first conductive layer 243 are omitted. .

  In the memory cell array 222, a plurality of memory cells 221 are provided in a matrix. In addition, the memory cell 221 includes a transistor 240 functioning as a switching element and a memory element 241 connected to the transistor 240 over a substrate 230 having an insulating surface (see FIGS. 7A and 7B). )reference.). The memory element 241 is formed over the first conductive layer 243 formed over the insulating layer 248, a partition wall (insulating layer) 249 that covers part of the first conductive layer, and the first conductive layer 243. An insulating layer 242 having a thickness of 0.1 nm to 4 nm, preferably 1 nm to 4 nm, a first conductive layer 243, a partition wall (insulating layer) 249, an organic compound layer 244 covering the insulating layer 242, a second A conductive layer 245. As the insulating layer 242, the shape of the insulating layers 32 to 38 described in Embodiment 1 can be used as appropriate. Here, a memory element 241 including the insulating layer 242 having the same shape as the insulating layer 32 illustrated in FIG. A thin film transistor is used as the transistor 240. In addition, the insulating layer 246 that covers the second conductive layer 245 and functions as a protective film is provided.

Note that although the insulating layer 242 is formed over the partition wall (insulating layer) 249 and the first conductive layer 243 here, the insulating layer 242 remains on the first conductive layer 243 when the partition wall (insulating layer) 249 is formed. The residue may be used as the insulating layer 242. Specifically, an insulating layer is formed over the insulating layer 248 and the first conductive layer 243, and the insulating layer is etched to form a partition wall (insulating layer) 249. In this step, the first conductive layer 243 is formed. Etching residue remains on the top. This residue is used as the insulating layer 242. In this case, the compounds forming the partition wall (insulating layer) 249 and the insulating layer 242 are the same compound. Further, the insulating layer 242 is formed only over the first conductive layer 243, and the insulating layer 242 is not provided over the partition wall (insulating layer) 249. In the memory device having such a structure, the step of forming the insulating layer 242 can be omitted, so that throughput can be improved.

  One mode of a thin film transistor that can be used for the transistor 240 is described with reference to FIGS. FIG. 16A illustrates an example in which a top-gate thin film transistor is applied. An insulating layer 105 is provided over a substrate 230 having an insulating surface, and a thin film transistor is provided over the insulating layer 105. In the thin film transistor, a semiconductor layer 1302 and an insulating layer 1303 which can function as a gate insulating layer are provided over the insulating layer 105. Over the insulating layer 1303, a gate electrode 1304 is formed corresponding to the semiconductor layer 1302, and an insulating layer 1305 functioning as a protective layer and an insulating layer 248 functioning as an interlayer insulating layer are provided thereover. In addition, a first conductive layer 243 connected to each of the source region and the drain region of the semiconductor layer is formed. Further, an insulating layer functioning as a protective layer may be formed thereon.

  The semiconductor layer 1302 is a layer formed of a semiconductor having a crystal structure, and a non-single-crystal semiconductor or a single-crystal semiconductor can be used. In particular, an amorphous or microcrystalline semiconductor is crystallized by crystallizing a semiconductor that is crystallized by laser light irradiation, a crystallized semiconductor that is crystallized by heat treatment, or a combination of heat treatment and laser light irradiation. It is preferable to apply a crystalline semiconductor. In the heat treatment, a crystallization method using a metal element such as nickel which has an action of promoting crystallization of a silicon semiconductor can be applied.

In the case of crystallization by irradiating with laser light, high repetition frequency with continuous wave laser light irradiation or repetition frequency of 10 MHz or more and pulse width of 1 nanosecond or less, preferably 1 to 100 picoseconds. By irradiating with ultrashort pulse light, crystallization can be performed while continuously moving the molten zone in which the crystalline semiconductor is melted in the irradiation direction of the laser light. By such a crystallization method, a crystalline semiconductor having a large particle diameter and a crystal grain boundary extending in one direction can be obtained. By adjusting the carrier drift direction to the direction in which the crystal grain boundary extends, the field-effect mobility in the transistor can be increased. For example, 400 cm ² / V · sec or more can be realized.

When the crystallization process is performed using a crystallization process at a heat resistant temperature (about 600 ° C.) or lower of the glass substrate, a large-area glass substrate can be used. Therefore, a large amount of semiconductor devices can be manufactured per substrate, and the cost can be reduced.

Alternatively, the semiconductor layer 1302 may be formed by performing a crystallization step by heating at a temperature equal to or higher than the heat resistant temperature of the glass substrate. Typically, a quartz substrate is used as the insulating substrate, and the semiconductor layer 1302 is formed by heating an amorphous or microcrystalline semiconductor at 700 ° C. or higher. As a result, a semiconductor with high crystallinity can be formed. Therefore, a thin film transistor that has favorable characteristics such as response speed and mobility and can operate at high speed can be provided.

The insulating layer 1303 is formed by a single layer or a stacked structure of an insulating film containing silicon nitride, silicon oxide, or other silicon by a thin film formation method such as a plasma CVD method or a sputtering method. The insulating layer 1303 can be formed using an insulating solution by a droplet discharge method, a coating method, a sol-gel method, or the like. Typical examples of the insulating solution include a solution in which fine particles of inorganic oxide are dispersed, polyimide, polyamide, polyester, acrylic, PSG (phosphorus glass), BPSG (boron phosphorus glass), and silicate-based SOG (Spin on Glass). ), SiO ₂ having a Si—CH ₂ bond represented by alkoxysilicate SOG, polysilazane SOG, and polymethylsiloxane can be used as appropriate.

  The gate electrode 1304 can be formed using a metal or a polycrystalline semiconductor to which an impurity of one conductivity type is added. In the case of using a metal, tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), aluminum (Al), or the like can be used. Further, a metal nitride obtained by nitriding the metal can be used. Or it is good also as a structure which laminated | stacked the 1st layer which consists of the said metal nitride, and the 2nd layer which consists of the said metal. In the case of a laminated structure, the end of the first layer may protrude outward from the end of the second layer. At this time, a barrier metal can be formed by using a metal nitride for the first layer. That is, the second layer metal can be prevented from diffusing into the insulating layer 1303 and the semiconductor layer 1302 below the insulating layer 1303.

Sidewalls (sidewall spacers) 1308 are formed on the side surfaces of the gate electrode 1304. The sidewall can be formed by forming an insulating layer made of silicon oxide on the substrate by a CVD method and anisotropically etching the insulating layer by a RIE (Reactive ion etching) method.

  A thin film transistor including a combination of the semiconductor layer 1302, the insulating layer 1303, the gate electrode 1304, and the like can employ various structures such as a single drain structure, an LDD (low concentration drain) structure, and a gate overlap drain structure. Here, a thin film transistor having an LDD structure in which a low concentration impurity region 1310 is formed in a semiconductor layer where sidewalls overlap is shown. In addition, a single gate structure, equivalently a multi-gate structure in which thin film transistors to which a gate voltage of the same potential is applied is connected in series, or a dual gate structure in which a semiconductor layer is sandwiched between gate electrodes can be applied. it can.

  The insulating layer 248 is formed using an inorganic insulating material such as silicon oxide or silicon oxynitride, or an organic insulating material such as an acrylic resin or a polyimide resin. When a coating method such as spin coating or roll coater is used, an insulating layer formed of silicon oxide by heat treatment can be used after applying a liquid insulating film material. For example, an insulating layer containing silicon oxide can be used by applying a material containing a siloxane bond and performing heat treatment at 200 to 400 ° C. By forming the insulating layer 248 by an application method or an insulating layer flattened by reflow, disconnection of wiring formed on the layer can be prevented. It can also be used effectively when forming multilayer wiring.

  The first conductive layer 243 formed over the insulating layer 248 can be provided so as to intersect with a wiring formed in the same layer as the gate electrode 1304, and forms a multilayer wiring structure. A multilayer wiring structure can be formed by stacking a plurality of insulating layers having the same function as the insulating layer 248 and forming wirings on the insulating layers. The first conductive layer 243 includes a stacked structure of titanium (Ti) and aluminum (Al), a stacked structure of molybdenum (Mo) and aluminum (Al), a low-resistance material such as aluminum (Al), and titanium (Ti). And a combination with a barrier metal using a refractory metal material such as molybdenum (Mo).

  FIG. 16B illustrates an example in which a bottom-gate thin film transistor is applied. An insulating layer 105 is formed over a substrate 230 having an insulating surface, and a thin film transistor is provided thereover. The thin film transistor is provided with a gate electrode 1304, an insulating layer 1303 functioning as a gate insulating layer, a semiconductor layer 1302, a channel protective layer 1309, an insulating layer 1305 functioning as a protective layer, and an insulating layer 248 functioning as an interlayer insulating layer. . Further, an insulating layer functioning as a protective layer may be formed thereon. The first conductive layer 243 can be formed over the insulating layer 1305 or the insulating layer 248. Note that in the case of a bottom-gate thin film transistor, the insulating layer 105 is not necessarily formed.

In the case where the substrate 230 having an insulating surface is a flexible substrate, the heat resistant temperature is lower than that of a non-flexible substrate such as a glass substrate. For this reason, the thin film transistor is preferably formed using an organic semiconductor.

Here, a structure of a thin film transistor using an organic semiconductor is described with reference to FIGS. FIG. 16C illustrates an example in which a staggered organic semiconductor transistor is applied. An organic semiconductor transistor is provided over a flexible substrate 1401. The organic semiconductor transistor includes a gate electrode 1402, an insulating layer 1403 functioning as a gate insulating film, a semiconductor layer 1404 overlapping with the insulating layer functioning as the gate electrode and the gate insulating film, and a first conductive layer 243 connected to the semiconductor layer 1404. Is formed. Note that the semiconductor layer is partly sandwiched between the insulating layer 1403 functioning as a gate insulating film and the first conductive layer 243.

The gate electrode 1402 can be formed using a material and a method similar to those of the gate electrode 1304. Alternatively, the gate electrode 1402 can be formed by drying and baking using a droplet discharge method. Alternatively, the gate electrode 1402 can be formed by printing a paste containing conductive fine particles on a flexible substrate by a printing method, followed by drying and baking. As typical examples of the conductive fine particles, fine particles mainly containing any one of gold, copper, an alloy of gold and silver, an alloy of gold and copper, an alloy of silver and copper, and an alloy of gold, silver and copper may be used. Further, fine particles mainly containing a conductive oxide such as indium tin oxide (ITO) may be used.

The insulating layer 1403 functioning as a gate insulating film can be formed using a material and a method similar to those of the insulating layer 1303. However, when the insulating layer is formed by heat treatment after applying the liquid insulating film material, the heat treatment temperature is lower than the heat resistance temperature of the flexible substrate.

Examples of the material of the semiconductor layer 1404 of the organic semiconductor transistor include polycyclic aromatic compounds, conjugated double bond compounds, phthalocyanines, and charge transfer complexes. For example, anthracene, tetracene, pentacene, 6T (hexathiophene), TCNQ (tetracyanoquinodimethane), PTCDA (perylene carboxylic acid anhydride), NTCDA (naphthalene carboxylic acid anhydride) and the like can be used. Examples of the material for the semiconductor layer 1404 of the organic semiconductor transistor include π-conjugated polymers such as organic polymer compounds, carbon nanotubes, polyvinyl pyridine, and phthalocyanine metal complexes. In particular, when a polyacetylene, polyaniline, polypyrrole, polythienylene, polythiophene derivative, poly (3 alkylthiophene), polyparaphenylene derivative or polyparaphenylene vinylene derivative is used, which is a π-conjugated polymer whose skeleton is composed of conjugated double bonds preferable.

  As a method for forming the semiconductor layer of the organic semiconductor transistor, a method capable of forming a film with a uniform thickness on the substrate may be used. The thickness is 1 nm to 1000 nm, preferably 10 nm to 100 nm. As a specific method, a vapor deposition method, a coating method, a spin coating method, an overcoat method, a solution casting method, a dip method, a screen printing method, a roll coater method, or a droplet discharge method can be used.

FIG. 16D illustrates an example in which a coplanar organic semiconductor transistor is used. An organic semiconductor transistor is provided over a flexible substrate 1401. In the organic semiconductor transistor, a gate electrode 1402, an insulating layer 1403 functioning as a gate insulating film, a first conductive layer 243, and a semiconductor layer 1404 overlapping with the insulating layer functioning as a gate electrode and a gate insulating layer are formed. The first conductive layer 243 is partly sandwiched between an insulating layer functioning as a gate insulating layer and a semiconductor layer.

Further, the thin film transistor and the organic semiconductor transistor may be provided in any configuration as long as they can function as a switching element.

  Alternatively, a transistor may be formed using a single crystal substrate or an SOI substrate, and a memory element may be provided thereover. The SOI substrate may be formed using a method called wafer bonding or a method called SIMOX in which an insulating layer is formed inside by implanting oxygen ions into the Si substrate. Here, as shown in FIG. 7C, a memory element 241 is connected to a field-effect transistor 262 provided over a single crystal semiconductor substrate 260. In addition, an insulating layer 250 is provided so as to cover the wiring of the field-effect transistor 262, and the memory element 241 is provided over the insulating layer 250.

Since a transistor formed using such a single crystal semiconductor has favorable characteristics such as response speed and mobility, a transistor that can operate at high speed can be provided. In addition, since the transistor has less variation in characteristics, a semiconductor device that achieves high reliability can be provided.

The memory element 241 includes a first conductive layer 264 formed over the insulating layer 250 and a thickness of 0.1 nm to 4 nm, preferably 1 nm, formed over the first conductive layer 264 and the first conductive layer. The insulating layer 242 has a thickness of 4 nm or less, the partition wall (insulating layer) 249, the organic compound layer 244 that covers the insulating layer 242, and the second conductive layer 245.

  In this manner, the first conductive layer 264 can be freely arranged by providing the insulating layer 250 and forming the memory element 241. In other words, in the structures of FIGS. 7A and 7B, the memory element 241 has to be provided in a region where the wiring of the transistor 240 is avoided; however, with the above structure, for example, the layer 251 including the transistor The memory element 241 can be formed above the provided transistor 262. As a result, the memory circuit 216 can be more highly integrated. That is, some or all of the transistors and the memory circuit 216 may overlap.

  7B and 7C, the organic compound layer 244 is provided over the entire surface of the substrate, but the organic compound layer 244 may be selectively provided only in each memory cell. . In this case, the use efficiency of the material can be improved by selectively providing an organic compound layer by discharging and baking an organic compound using a droplet discharge method or the like.

  The materials and formation methods of the first conductive layers 243 and 264 and the second conductive layer 245 are any of the materials and formation methods of the first conductive layer 81 and the second conductive layer 28 described in Embodiment Mode 1. It can carry out similarly using these.

  The insulating layer 242 and the organic compound layer 244 can be provided using a material and a formation method similar to those of the organic compound layer 29 described in Embodiment Mode 1.

  Further, a rectifying element may be provided between the first conductive layers 243 and 264 and the organic compound layer 244. The element having a rectifying property is a transistor or a diode in which a gate electrode and a drain electrode are connected. Note that the element having a rectifying property may be provided between the organic compound layer 244 and the second conductive layer 245.

Further, after a separation layer is provided over the substrate 230 having an insulating surface and the transistor 253 and the memory element 241 are formed over the separation layer, the transistor 253 and the memory element 241 are separated from the separation layer. A layer 253 having a transistor and a memory element 241 may be attached to the memory element 241 with an adhesive layer 462 interposed therebetween (see FIGS. Note that as a peeling method, (1) a layer having a transistor is provided by providing a metal oxide layer as a peeling layer between a substrate having high heat resistance and a layer having a transistor, and weakening the metal oxide layer by crystallization. (2) An amorphous silicon film containing hydrogen is provided as a peeling layer between a substrate having high heat resistance and a layer having a transistor, and hydrogen gas of the amorphous silicon film is released by laser light irradiation. And a method of peeling a layer having the transistor by providing an amorphous silicon film on a peeling layer and removing the amorphous silicon film by etching, (3 ) A method of mechanically removing a substrate having high heat resistance on which a layer having a transistor is formed or removing by etching with a solution; (4) peeling between a substrate having high heat resistance and a layer having a transistor; The metal layer and metal oxide layer provided as a layer, the metal oxide layer is weakened by crystallization, is etched away by a part of the solution and NF _3, BrF _3, ClF 3 fluoride such as a halogen gas metal layer Then, a method of physically peeling off the weakened metal oxide layer or the like may be used.

  In addition, as the substrate 461, a flexible substrate shown in the substrate 30 described in Embodiment 1, a film showing thermoplasticity, paper made of a fibrous material, or the like can be used, so that the memory device can be made small and thin. It is possible to reduce the weight.

  Next, an operation when data is written to the memory circuit 216 will be described (FIG. 6).

  First, an operation when data is written by voltage application will be described. Here, a case where data is written to the memory cell 221 in the m-th column and the n-th row will be described. In this case, the row decoder 224a, the column decoder 226a, and the selector 226c select the bit line Bm in the m-th column and the word line Wn in the n-th row, and the transistor 240 included in the memory cell 221 in the m-th column and the n-th row Turns on. Subsequently, a predetermined voltage is applied to the bit line Bm in the m-th column by the writing circuit. The voltage applied here is a voltage value at which both electrodes of the memory element 241 are short-circuited, and a voltage higher than usual is applied.

  The voltage applied to the bit line Bm in the m-th column is applied to the first conductive layer 243, and a potential difference is generated between the first conductive layer 243 and the second conductive layer 245 (FIG. 7B). reference.). Then, electric charges are charged between the first conductive layer 243 and the insulating layer 242. When a voltage equal to or higher than a predetermined voltage is applied between the first conductive layer 243 and the second conductive layer 245, the charge is injected into the organic compound layer. As a result, a current flows through the organic compound layer 244 and Joule heat is generated. With the generation of this heat, the temperature of the organic compound layer rises above the glass transition point, the organic compound layer 244 increases in fluidity, and the film thickness of the organic compound layer becomes nonuniform. As a result, the organic compound layer 244 and the second conductive layer are deformed, the first conductive layer 243 and the second conductive layer 245 are short-circuited, and the electric resistance of the memory element is changed. Further, the resistance value of the memory element in which no current flows does not change.

  Next, an operation for reading data by applying a voltage will be specifically described (see FIGS. 6 and 7).

When data “1” is written to the memory cell 221, the memory cell 221 is first selected by the row decoder 224a, the level shifter 224b, the column decoder 226a, and the selector 226c. Specifically, a predetermined voltage V22 is applied to the word line Wn connected to the memory cell 221 by the row decoder 224a and the level shifter 224b. Further, the bit line Bm connected to the memory cell 221 is connected to the read / write circuit 226b by the column decoder 226a and the selector 226c. Then, the write voltage V21 is output from the read / write circuit 226b to the bit line B3.

Thus, the transistor 240 included in the memory cell is turned on, the bit line is electrically connected to the memory element 241, and a voltage of approximately Vw = Vcom−V21 is applied. Note that one electrode of the memory element 241 is connected to a common electrode of the potential Vcom. By appropriately selecting the potential Vw, the organic compound layer 29 provided between the conductive layers is changed physically or electrically, and data “1” is written. Specifically, at the read operation voltage, the electrical resistance between the first conductive layer and the second conductive layer in the data “1” state is significantly smaller than that in the data “0” state. It may be changed as described above, or it may be simply short-circuited. The potential may be appropriately selected from the range of (V21, V22, Vcom) = (5-15V, 5-15V, 0V), or (-12 to 0V, -12 to 0V, 3 to 5V). The voltage Vw may be 5 to 15V, or -5 to -15V.

Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. Specifically, a potential (for example, 0 V) for turning off the transistor of the memory cell to be connected is applied to the non-selected word line, and the non-selected bit line is in a floating state or approximately equal to Vcom. A potential may be applied.

On the other hand, when data “0” is written in the memory cell 221, it is not necessary to apply an electrical action to the memory cell 221. In the circuit operation, for example, as in the case of writing “1”, the memory cell 221 is selected by the row decoder 224a, the level shifter 224b, the column decoder 226a, and the selector 226c, but from the read / write circuit 226b to the bit line B3. Or the bit line B3 is set in a floating state. As a result, a small voltage (for example, −5 to 5 V) is applied to the memory element 241 or no voltage is applied, so that the electrical characteristics do not change and data “0” writing is realized.

Next, an operation when data is read by electrical action will be described. Data is read by utilizing the fact that the electrical characteristics of the memory element 241 are different between the memory cell having the data “0” and the memory cell having the data “1”. For example, the electrical resistance of the memory element constituting the memory cell having data “0” is R0 at the read voltage, and the electrical resistance of the memory element constituting the memory cell having data “1” is R1 at the read voltage. A method of reading using the difference will be described. Note that R1 << R0. As the structure of the reading / writing circuit, for example, a reading / writing circuit 226b using the resistance element 254 and the differential amplifier 247 illustrated in FIG. 6B can be considered. The resistance element has a resistance value Rr, and R1 <Rr <R0.

When data is read from the memory cell 221 in the xth row and the yth column, first, the memory cell 221 is selected by the row decoder 224a, the level shifter 224b, the column decoder 226a, and the selector 226c. Specifically, the level shifter 224b applies a predetermined voltage V24 to the word line Wy connected to the memory cell 221 to turn on the transistor 240. Further, the bit line Bx connected to the memory cell 221 is connected to the terminal P of the read / write circuit 226b by the column decoder 226a and the selector 226c. As a result, the potential Vp of the terminal P becomes a value determined by resistance division of Vcom and V0 by the resistance element 254 (resistance value Rr) and the storage element 241 (resistance value R0 or R1). Therefore, when the memory cell 221 has data “0”, Vp0 = Vcom + (V0−Vcom) × R0 / (R0 + Rr). When the memory cell 221 has data “1”, Vp1 = Vcom + (V0−Vcom) × R1 / (R1 + Rr). As a result, by selecting Vref to be between Vp0 and Vp1, the output potential Vout is output as Lo / Hi (or Hi / Lo) in accordance with the data “0” / “1” and read. It can be performed.

For example, the differential amplifier is operated at Vdd = 3V, and Vcom = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9 and the on-resistance of the transistor 240 can be ignored, when the data in the memory cell is “0”, Vp0 = 2.7V and Vout is output as Hi, When the data of “1” is “1”, Vp1 = 0.3 V and Lo is output as Vout. Thus, the memory cell can be read.

  Next, in the case where a transistor is used instead of the resistance element 254, operation when data is read from the memory element by voltage application will be described with reference to a specific example in FIG.

  FIG. 11 shows a current-voltage characteristic 951 of a memory element in which data “0” is written to the memory element, a current-voltage characteristic 952 of a memory element in which data “1” is written, and a current-voltage characteristic of a transistor. 953. Further, a case where 3 V is applied between the first conductive layer 243 and the second conductive layer 245 as an operation voltage when reading data will be described.

  In FIG. 11, in a memory cell having a memory element in which data of “0” is written, an intersection 954 between the current-voltage characteristic 951 of the memory element and the current-voltage characteristic 953 of the transistor serves as an operating point. The potential of P is V2 (V). The potential of the node P is supplied to the differential amplifier 247. In the differential amplifier 247, the data stored in the memory cell is determined as “0”.

  On the other hand, in a memory cell having a memory element in which data of “1” is written, an intersection 955 between the current-voltage characteristic 952 of the memory element and the current-voltage characteristic 953 of the transistor serves as an operating point. The potential is V1 (V) (V1 <V2). The potential of the node P is supplied to the differential amplifier 247. In the differential amplifier 247, the data stored in the memory cell is determined as “1”.

  As described above, the data stored in the memory cell can be determined by reading the resistance-divided potential in accordance with the resistance value of the memory element 241.

  According to the above method, the voltage value is read by utilizing the difference in resistance value of the memory element 241 and the resistance division. However, the information included in the memory element 241 may be read using a current value.

Note that this embodiment mode can be freely combined with the above embodiment modes.

  According to this embodiment, an insulating layer having a thickness of 4 nm or less, preferably 2 nm or less is provided between the conductive layer and the organic compound layer, whereby the charge injection property is increased by the tunnel effect of the insulating layer, and the memory element It is possible to reduce variations in applied voltage and current value during writing. In addition, since the charge injection property is increased by providing an insulating layer having a thickness of 4 nm or less, preferably 2 nm or less, between the conductive layer and the organic compound layer, the thickness of the organic compound layer of the memory element is increased. It is possible to reduce the short circuit between the electrodes in the initial state. As a result, the reliability of the memory device and the semiconductor device can be improved.

(Embodiment 3)
In this embodiment, an example of a semiconductor device including the memory device described in the above embodiment will be described with reference to drawings.

  The semiconductor device described in this embodiment is characterized in that data can be read and written in a non-contact manner. A data transmission format is an electromagnetic which performs communication by mutual induction with a pair of coils arranged opposite to each other. There are roughly divided into a coupling system, an electromagnetic induction system that communicates using an induction electromagnetic field, and a radio system that communicates using radio waves, but any system may be used. There are two types of antennas used for data transmission. One is provided on a substrate provided with a transistor and a memory element, and the other is provided on a substrate provided with a transistor and a memory element. There is a case where a terminal portion is provided and an antenna provided on another substrate is connected to the terminal portion. Here, as part of a cross section of the semiconductor device, an antenna, a circuit connected to the antenna, and a part of a memory circuit are illustrated.

  First, a structure example of a semiconductor device in the case where an antenna is provided over a substrate provided with a plurality of elements and memory elements will be described with reference to FIGS.

  FIG. 8A illustrates a semiconductor device having a memory circuit formed of a passive matrix type. The semiconductor device includes a layer 351 including transistors 451 and 452 over a substrate 350, a memory element portion 352 formed over the layer 351 including transistors, and a conductive layer 353 functioning as an antenna.

Note that although the case where the memory element portion 352 and the conductive layer 353 functioning as an antenna are provided above the transistor 351 is shown here, the present invention is not limited to this structure, and the memory element portion 352 or the conductive layer 353 functioning as an antenna is provided. May be provided below the layer 351 including a transistor or in the same layer.

  The memory element portion 352 includes a plurality of memory elements 352a and 352b. The memory element 352a includes a first conductive layer 361 formed over the insulating layer 252, a partition wall (insulation layer) 374 that covers part of the first conductive layer, a first conductive layer 361, and a partition wall ( Insulating layer) 374 having a thickness of 0.1 nm to 4 nm, preferably 1 nm to 4 nm, and a first conductive layer 361, a partition wall (insulating layer) 374, and an organic compound layer covering insulating layer 364a 362a and a second conductive layer 363a. The memory element 352b includes a first conductive layer 361 formed over the insulating layer 252, a partition wall (insulating layer) 374 that covers part of the first conductive layer, a first conductive layer 361, and a partition wall ( Insulating layer) 374 having a thickness of 0.1 nm to 4 nm, preferably 1 nm to 4 nm, and a first conductive layer 361, a partition wall (insulating layer) 374, and an organic compound layer covering insulating layer 364b 362b and a second conductive layer 363b.

An insulating layer 366 that functions as a protective film is formed so as to cover the second conductive layers 363a and 363b and the conductive layer 353 that functions as an antenna. In addition, the first conductive layer 361 in which the memory element portion 352 is formed is connected to the wiring of the transistor 452. The memory element portion 352 can be formed using a material or a manufacturing method similar to those of the memory element described in the above embodiment. Further, here, a memory circuit including a passive matrix type is shown; thus, a plurality of insulating layers 364a and 364b, organic compound layers 362a and 362b, a second conductive layer 363a, and the like are formed over the first conductive layer 361. 363b is formed to constitute a plurality of memory elements 352a and 352b. Note that the transistor 452 functions as a switch for controlling the potential of the first conductive layer 361 in the memory element portion 352.

  In the memory element portion 352, as shown in the above embodiment mode, the first conductive layer 361 and the organic compound layers 362a and 362b, or the organic compound layers 362a and 362b and the second conductive layer 363a, An element having a rectifying property may be provided between 363b and 363b. As the rectifying element, the element described above in Embodiment Mode 1 can be used.

  Here, the conductive layer 353 functioning as an antenna is provided over the conductive layer 360 formed using the same layer as the second conductive layers 363a and 363b. Note that a conductive layer functioning as an antenna may be formed in the same layer as the second conductive layers 363a and 363b. The conductive layer 353 functioning as an antenna is connected to the source wiring or the drain wiring of the transistor 451. Note that the transistor 452 forms part of a circuit connected to the antenna.

  As a material of the conductive layer 353 functioning as an antenna, gold (Au), platinum (Pt), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), aluminum (Al ), Manganese (Mn), titanium (Ti), or the like, or an alloy containing a plurality of such elements can be used. As a method for forming the conductive layer 353 functioning as an antenna, various printing methods such as vapor deposition, sputtering, CVD, screen printing, and gravure printing, a droplet discharge method, or the like can be used.

  As the transistors 451 and 452 included in the layer 351 including a transistor, the transistors 240 and 262 described in Embodiment 2 can be used as appropriate.

  In addition, a separation layer, a layer 351 including a transistor, a memory element portion 352, and a conductive layer 353 functioning as an antenna are formed over a substrate, and the layer 351 including a transistor is formed using the separation method described in Embodiment 2 as appropriate. The element portion 352 and the conductive layer 353 functioning as an antenna may be peeled off and attached to another substrate using an adhesive layer. As another substrate, a flexible substrate shown in the substrate 30 of Embodiment 1, a film showing thermoplasticity, paper made of a fibrous material, a base film, or the like is used, so that the memory device is small and thin. It is possible to reduce the weight.

  FIG. 8B illustrates an example of a semiconductor device having an active matrix memory circuit. Note that FIG. 8B will be described with respect to portions different from FIG.

  The semiconductor device illustrated in FIG. 8B includes a layer 351 including transistors 451 and 452 over a substrate 350, and a memory element portion 356 and a conductive layer 353 functioning as an antenna above the layer 351 including the transistor. Note that here, the transistor 452 which functions as a switching element of the memory element portion 356 is provided in the same layer as the transistor 451, and the memory element portion 356 and the conductive layer 353 which functions as an antenna are provided above the layer 351 including the transistor. Although shown, the memory element portion 356 and the conductive layer 353 functioning as an antenna can be provided below the layer 351 including the transistor or in the same layer.

  The memory element unit 356 includes memory elements 356a and 356b. The memory element 356a includes a first conductive layer 371a formed over the insulating layer 252, a partition wall (insulating layer) 374 that covers part of the first conductive layer 371a, a first conductive layer 361, and a partition wall (insulating). Layer) 374 covering a thickness of 0.1 nm to 4 nm, preferably 1 nm to 4 nm, and an organic compound layer 372 covering the first conductive layer 371a, the partition (insulating layer) 374, and the insulating layer 370. And a second conductive layer 373. The memory element 356b includes a first conductive layer 371b formed over the insulating layer 252, a partition wall (insulating layer) 374 that covers part of the first conductive layer 371b, a first conductive layer 361, and a partition wall (insulating). Layer) 374 having a thickness of 0.1 nm to 4 nm, preferably 1 nm to 4 nm, and an organic compound layer 372 covering the first conductive layer 371b, the partition (insulating layer) 374, and the insulating layer 370. And a second conductive layer 373. Here, in order to show an active matrix memory circuit, a first conductive layer 371a and a first conductive layer 371b are connected to wirings of the transistors. That is, each of the first conductive layers of the memory element is connected to a transistor.

Note that the memory elements 356a and 356b can be formed using the material or the manufacturing method described in Embodiments 1 and 2. In the memory elements 356a and 356b, as described above, the rectifying property is provided between the first conductive layers 371a and 371b and the organic compound layer 372 or between the organic compound layer 372 and the second conductive layer 373. You may provide the element which has.

  Further, the transistor layer 351, the memory element portion 356, and the conductive layer 353 functioning as an antenna can be formed by vapor deposition, sputtering, CVD, printing, droplet discharge, or the like as described above. . Note that a different method may be used depending on each place.

  A separation layer, a layer 351 having a transistor, a memory element portion 356, and a conductive layer 353 functioning as an antenna are formed over a substrate, and a layer 351 having a transistor and a memory element portion are appropriately formed using the separation method described in Embodiment 2. 356 and the conductive layer 353 functioning as an antenna may be peeled off and attached to another substrate using an adhesive layer. As another substrate, a flexible substrate shown in the substrate 30 of Embodiment 1, a film showing thermoplasticity, paper made of a fibrous material, a base film, or the like is used, so that the memory device is small and thin. It is possible to reduce the weight.

  Note that a sensor connected to the transistor may be provided. Examples of the sensor include an element that detects temperature, humidity, illuminance, gas (gas), gravity, pressure, sound (vibration), acceleration, and other characteristics by physical or chemical means. Sensors are typically formed of elements such as resistive elements, capacitive coupling elements, inductive coupling elements, photovoltaic elements, photoelectric conversion elements, thermoelectric elements, transistors, thermistors, diode capacitance elements, piezoelectric elements, etc. Is done.

  Next, one structure of a semiconductor device including a layer having a transistor, a terminal portion connected to the transistor, a first substrate having a memory element, and a second substrate on which an antenna connected to the terminal portion is formed An example will be described with reference to FIG. 9 will be described with respect to portions different from FIG.

  FIG. 9A illustrates a semiconductor device having a passive matrix memory circuit. The semiconductor device includes a layer 351 including a transistor formed over a substrate 350, a memory element portion 352 formed above the layer 351 including a transistor, a connection terminal 378 connected to the transistor 451, and a conductive layer functioning as an antenna. The conductive layer 357 and the connection terminal 378 are connected to each other with conductive particles. Note that here, the case where the memory element portion 352 is provided above the layer 351 having a transistor is shown; however, the present invention is not limited to this structure, and the memory element portion 352 is provided below the layer 351 having a transistor or in the same layer. May be.

  The memory element portion 352 can be formed using the memory element portion 352 having the structure illustrated in FIG.

  In addition, the substrate 365 including the transistor 351 and the memory element portion 352 and the substrate 365 provided with the conductive layer 357 functioning as an antenna are attached to each other with a resin 375 having adhesiveness. The layer 351 having a transistor and the conductive layer 358 are electrically connected through conductive particles 359 contained in the resin 375. In addition, a conductive layer such as a silver paste, a copper paste, or a carbon paste or a method of performing solder bonding is used to provide a layer 351 having a transistor and a substrate including a memory element portion 352, and a conductive layer 357 functioning as an antenna. The substrate 365 may be bonded together.

  FIG. 9B illustrates a semiconductor device provided with the memory device described in Embodiment 2, in which a layer 351 including a transistor including transistors 451 and 452 formed over a substrate 350 and a layer including a transistor are formed. 351 includes a memory element portion 356 formed above 351, a connection terminal 378 connected to the transistor 451, and a substrate 365 over which a conductive layer 357 functioning as an antenna is formed. The conductive layer 357 and the connection terminal 378 are conductive. Connected by sex particles. Note that here, a case where the transistor 451 is included in the same layer as the transistor 451 in the layer 351 including the transistor and the conductive layer 357 functioning as an antenna is provided above the layer 351 including the transistor is shown. Without limitation, the memory element portion 356 may be provided below the layer 351 including a transistor or in the same layer.

  The memory element portion 356 can be composed of memory elements 356a and 356b having the structure shown in FIG.

  9B, the substrate 365 including the transistor 351 and the memory element portion 356 and the substrate 365 provided with the conductive layer 357 functioning as an antenna are attached to each other with a resin 375 including conductive particles 359. It is done. Further, the conductive layer 357 and the connection terminal 378 are connected by conductive particles 359.

  Further, a separation layer, a layer 351 having a transistor, and a memory element portion 356 are formed over a substrate, and the separation method described in Embodiment 2 is appropriately used to separate the layer 351 having a transistor and the memory element portion 356 so that another layer You may affix using a contact bonding layer on a board | substrate. As another substrate, a flexible substrate shown in the substrate 30 of Embodiment 1, a film showing thermoplasticity, paper made of a fibrous material, a base film, or the like is used, so that the memory device is small and thin. It is possible to reduce the weight.

Further, the memory element portions 352 and 356 may be provided over the substrate 365 provided with a conductive layer functioning as an antenna. In other words, the first substrate over which a layer including a transistor is formed and the second substrate over which a conductive layer functioning as a memory element portion and an antenna are formed may be bonded to each other with a resin containing conductive particles. Further, similarly to the semiconductor device illustrated in FIGS. 8A and 8B, a sensor connected to the transistor may be provided.

Note that this embodiment can be freely combined with the above embodiment.

  By providing an insulating layer having a thickness of 4 nm or less, preferably 2 nm or less, between the conductive layer and the organic compound layer, the charge injection property is enhanced by the tunnel effect of the insulating layer, the applied voltage at the time of writing to the memory element, and It is possible to reduce variation in current value. In addition, since the charge injection property is increased by providing an insulating layer having a thickness of 4 nm or less, preferably 2 nm or less, between the conductive layer and the organic compound layer, the thickness of the organic compound layer of the memory element may be increased. It is possible to reduce the short circuit between the electrodes in the initial state. As a result, the reliability of the semiconductor device can be improved.

  In this example, current-voltage characteristics when a memory element is manufactured over a substrate and voltage is applied to the memory element to write data will be described with reference to FIGS. Note that here, data is written by applying a voltage to the memory element to cause a short circuit. The memory element is an element in which a first conductive layer, an insulating layer, an organic compound layer, and a second conductive layer are stacked in this order on a substrate. The first conductive layer is titanium, the insulating layer is calcium fluoride, and the organic layer is organic. The compound layer was formed using 4,4′-bis [N- (1-naphthyl) -N-phenylamino] biphenyl (NPB), and the second conductive layer was formed using aluminum. The insulating layer was 2 nm, the organic compound layer was 8 nm, and the second conductive layer was 200 nm. In addition, the first conductive layer was formed by a sputtering method, and the insulating layer, the organic compound layer, and the second conductive layer were formed by an evaporation method. A memory element having this structure and having a top surface of a square shape and a side length of 100 μm is referred to as a sample 1. In addition, a memory element having this structure, having a top surface of a square shape, and a side length of 10 μm is referred to as Sample 2 and Sample 3.

  In addition, as a comparative sample of Samples 1 to 3, an element in which a first conductive layer, an organic compound layer, and a second conductive layer were stacked in that order on a substrate was formed. The first conductive layer was formed using titanium, the organic compound layer was formed using 4,4'-bis [N- (1-naphthyl) -N-phenylamino] biphenyl (NPB), and the second conductive layer was formed using aluminum. The organic compound layer was formed with a thickness of 8 nm, and the second conductive layer was formed with a thickness of 200 nm. The first conductive layer was formed by a sputtering method, and the organic compound layer and the second conductive layer were formed by an evaporation method. A memory element having this structure, having a square top surface, and a side length of 100 μm is referred to as a comparative sample 1. In addition, a memory element having the above structure, having a square top surface shape, and a side length of 10 μm is referred to as a comparative sample 2 and a comparative sample 3.

The voltage-current characteristics when writing is performed by applying a voltage to the memory element (sample 1, comparative sample 1) will be described with reference to FIG. In FIG. 15A, the horizontal axis represents the voltage value and the vertical axis represents the current value.

In FIG. 15A, plot 411a shows the behavior of the current value of sample 1 before writing due to voltage application, and plot 411b shows the behavior of the current value of sample 1 after writing.

The plot 412a shows the behavior of the current value of the comparative sample 1 before writing by voltage application, and the plot 412b shows the behavior of the current value of the comparative sample 1 after writing.

When Sample 1 was written, the voltage was 2.9 V and the current value was 82000 μA. The voltage when the comparative sample 1 was written was 4.9 V, and the current value was 110 μA. Furthermore, the current value at the same potential is higher in the sample 1 than in the comparative sample 1 before writing. From this, it can be seen that the memory element of Sample 1 has a high charge injection property by including an insulating layer between the first conductive layer and the organic compound layer. Since the insulating layer is formed using stable calcium fluoride, it can be seen that this mechanism is tunnel injection. Further, since the charge injection property is enhanced, the applied voltage at the time of writing is lowered.

Next, voltage-current characteristics when voltage is applied to Samples 2 and 3 and Comparative Samples 2 and 3 for writing will be described with reference to FIG. In FIG. 15B, the horizontal axis represents the voltage value and the vertical axis represents the current value.

In FIG. 15B, the plot 401a shows the behavior of the current value of the sample 3 before writing by voltage application, and the plot 401b shows the behavior of the current value of the sample 3 after writing.

The plot 402a shows the behavior of the current value of the sample 3 before writing due to voltage application, and the plot 402b shows the behavior of the current value of the sample 3 after writing.

The plot 403a shows the behavior of the current value of the comparative sample 3 before writing by voltage application, and the plot 403b shows the behavior of the current value of the comparative sample 3 after writing.

The plot 404a shows the behavior of the current value of the comparative sample 3 before writing by voltage application, and the plot 404b shows the behavior of the current value of the comparative sample 3 after writing.

In Sample 2, the voltage at the time of writing was 5.1 V, and the current value was 130 μA. The voltage at the time of writing in Sample 3 was 4.2 V, and the current value was 110 μA. Thus, it can be seen that there is little variation in voltage and current values during writing. From this, it can be seen that by having an insulating layer between the first conductive layer and the organic compound layer, variations in voltage and current values during writing are reduced.

On the other hand, the voltage when writing data in Comparative Sample 2 was 2.0 V, and the current value was 6.8 × 10 ³ μA. Moreover, the voltage at the time of data writing in the comparative sample 3 was 7.9 V, and the current value was 0.45 μA. Thus, it can be seen that there are many variations in voltage and current values during writing.

  Next, voltage-current characteristics of a memory element in which an organic compound layer is formed by a spin coating method will be described with reference to Tables 1 to 3. The memory element is an element in which a first conductive layer, an insulating layer, an organic compound layer, and a second conductive layer are stacked in this order on a substrate. The first conductive layer is titanium, the insulating layer is calcium fluoride, The organic compound layer was formed using polyvinyl carbazole (PVK), and the second conductive layer was formed using aluminum. The insulating layer was 1 nm, the organic compound layer was 15 nm, and the second conductive layer was 200 nm. In addition, the first conductive layer was formed by a sputtering method, the insulating layer and the second conductive layer were formed by an evaporation method, and the organic compound layer was formed by spin coating. Note that, before the insulating layer is deposited on the first conductive layer, a titanium layer is formed as the first conductive layer by a sputtering method, and an aluminum layer having a thickness of 100 nm is formed on the titanium layer. The aluminum layer was removed using tetramethylammonium hydroxide).

  In the memory element having the above structure, a memory element having a top surface of a square shape and a side length of 10 μm is referred to as Sample 4 and Sample 5.

  In addition, as a comparative example of Sample 4 and Sample 5, an element in which a first conductive layer, an organic compound layer, and a second conductive layer were stacked in this order on a substrate was formed. The first conductive layer was formed using titanium, the organic compound layer was formed using polyvinyl carbazole (PVK), and the second conductive layer was formed using aluminum. The organic compound layer was formed with a thickness of 15 nm, and the second conductive layer was formed with a thickness of 200 nm. The first conductive layer was formed by sputtering, the organic compound layer was formed by spin coating, and the second conductive layer was formed by vapor deposition. In the memory element having the above structure, memory elements having a square top shape and a side length of 10 μm are shown as comparative samples 4 to 6.

Table 1 shows the voltages and current values at the time of writing by applying voltages to Samples 4 and 5 and Comparative Samples 4 to 6.

Sample 4 and sample 5 have little variation in voltage and current values at the time of writing. On the other hand, in the comparative samples 4 to 6, the voltage value at the time of writing is high. In addition, the current value varies.

In addition, a memory element having the same stacked structure as Samples 1 to 5, the top surface shape is square, and the length of one side is 5 μm is referred to as Sample 6 and Sample 7. Similarly, Comparative Samples 7 to 10 are memory elements having the same stacked structure as Comparative Samples 1 to 6, the top surface shape is square, and the length of one side is 5 μm.

Table 2 shows the voltage and current values when voltage was applied to Samples 6 and 7 and Comparative Samples 7 to 10 and writing was performed.

Sample 6 and sample 7 have little variation in voltage and current values at the time of writing. On the other hand, the comparative sample 7 and the comparative sample 10 were not written but were insulated. Moreover, in the comparative sample 8 and the comparative sample 9, the voltage and current value at the time of writing are high.

Samples 8 to 10 are storage elements having the same stacked structure as Sample 4 and Sample 5, the top surface shape is square, and the length of one side is 3 μm. Similarly, memory elements having the same stacked structure as Comparative Samples 4 to 6, a top surface shape of square, and a side length of 3 μm are shown as Comparative Samples 11 to 13.

Table 3 shows the voltage and current values when voltage was applied to Samples 8 to 10 and Comparative Samples 11 to 13 for writing.

Samples 8 to 10 have little variation in voltage and current values at the time of writing. On the other hand, in Comparative Samples 11 to 13, no data was written and insulation occurred.

As shown in Tables 1 to 3, in a memory element having an organic compound layer, an insulating layer having a thickness of 4 nm or less, preferably 2 nm or less is provided in the first conductive layer and the organic compound layer, thereby increasing the top surface area of the memory element. Regardless, variations in voltage and current values during writing were reduced.

Here, the structure of the semiconductor device of the present invention will be described with reference to FIG. As shown in FIG. 12A, the semiconductor device 20 of the present invention has a function of communicating data without contact, and includes a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, and other circuits. A control circuit 14 for controlling, an interface circuit 15, a memory circuit 16, a bus 17, and an antenna 18 are included.

Further, as shown in FIG. 12B, the semiconductor device 20 of the present invention has a function of communicating data without contact, and includes a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, and the like. In addition to the control circuit 14 for controlling the circuit, the interface circuit 15, the memory circuit 16, the bus 17, and the antenna 18, the central processing unit 1 may be included.

Further, as shown in FIG. 12C, the semiconductor device 20 of the present invention has a function of communicating data without contact, and includes a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, and the like. In addition to the control circuit 14, the interface circuit 15, the storage circuit 16, the bus 17, the antenna 18, and the central processing unit 1, the detection unit 2 including the detection element 3 and the detection control circuit 4 may be included.

The semiconductor device of this embodiment includes a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, a control circuit 14 for controlling other circuits, an interface circuit 15, and a memory circuit 16 by transistors in a layer having transistors. In addition to the bus 17, the antenna 18, and the central processing unit 1, the detection unit 2 including the detection element 3 and the detection control circuit 4 can be configured to form a small semiconductor device having a sensor function. .

  The power supply circuit 11 is a circuit that generates various power supplies to be supplied to each circuit inside the semiconductor device 20 based on the AC signal input from the antenna 18. The clock generation circuit 12 is a circuit that generates various clock signals to be supplied to each circuit inside the semiconductor device 20 based on the AC signal input from the antenna 18. The data demodulation / modulation circuit 13 has a function of demodulating / modulating data communicated with the reader / writer 19. The control circuit 14 has a function of controlling the memory circuit 16. The antenna 18 has a function of transmitting / receiving electromagnetic waves or radio waves. The reader / writer 19 controls communication and control with the semiconductor device and processing related to the data. The semiconductor device is not limited to the above-described configuration, and may be a configuration in which other elements such as a power supply voltage limiter circuit and hardware dedicated to cryptographic processing are added.

  The memory circuit 16 includes one or a plurality selected from the memory elements described in Embodiment 1 or Embodiment 2. Since a memory element having an organic compound layer can simultaneously achieve downsizing, thinning, and large capacity, providing the memory circuit 16 with a memory element having an organic compound layer makes the semiconductor device smaller and lighter. Can be achieved.

The detection unit 2 can detect temperature, pressure, flow rate, light, magnetism, sound wave, acceleration, humidity, gas component, liquid component, and other characteristics by physical or chemical means. The detection unit 2 includes a detection element 3 that detects a physical quantity or a chemical quantity, and a detection control circuit 4 that converts the physical quantity or the chemical quantity detected by the detection element 3 into an appropriate signal such as an electrical signal. Yes. The detection element 3 is formed of an element such as a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, a diode, a capacitive element, or a piezoelectric element. can do. A plurality of detection units 2 may be provided. In this case, a plurality of physical quantities or chemical quantities can be detected simultaneously.

The physical quantity here refers to temperature, pressure, flow rate, light, magnetism, sound wave, acceleration, humidity, etc., and the chemical quantity refers to chemical substances such as gas components such as gas and liquid components such as ions. Point to. In addition, the chemical amount includes organic compounds such as specific biological substances (for example, blood glucose level contained in blood) contained in blood, sweat, urine and the like. In particular, when a chemical amount is to be detected, a specific substance is necessarily selectively detected. Therefore, a substance that selectively reacts with a substance to be detected is provided in advance in the detection element 3. It is preferable. For example, when detecting a biological substance, it is preferable that an enzyme, an antibody molecule, a microbial cell, or the like that selectively reacts with the biological substance to be detected by the detection element 3 is fixed to a polymer or the like.

  According to the present invention, a semiconductor device functioning as a wireless chip can be formed. Applications of wireless chips are wide-ranging. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 14A), packaging containers (wrapping paper and Bottles, etc., see FIG. 14C), recording media (DVD software, video tape, etc., see FIG. 14B), vehicles (bicycles, etc., see FIG. 14D), personal items (bags, glasses, etc.) ), Products such as foods, plants, clothing, daily necessities, electronic devices, and articles such as luggage tags (see FIGS. 14E and 14F). It can also be pasted or embedded in animals and human bodies. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also simply referred to as televisions, television receivers, television receivers), mobile phones, and the like.

  The semiconductor device 20 of the present invention is fixed to an article by being mounted on a printed board, pasted on a surface, or embedded. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin, and is fixed to each article. Since the semiconductor device 20 of the present invention realizes a small size, a thin shape, and a light weight, the design of the article itself is not impaired even after being fixed to the article. Further, by providing the semiconductor device 2707 of the present invention to bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and forgery can be prevented by utilizing this authentication function. Can do. In addition, by providing the semiconductor device of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved.

Next, one mode of an electronic device in which the semiconductor device of the present invention is mounted will be described with reference to the drawings. The electronic device illustrated here is a mobile phone, and includes housings 2700 and 2706, a panel 2701, a housing 2702, a printed wiring board 2703, operation buttons 2704, and a battery 2705 (see FIG. 13). The panel 2701 is detachably incorporated in the housing 2702, and the housing 2702 is fitted on the printed wiring board 2703. The shape and dimensions of the housing 2702 are changed as appropriate in accordance with the electronic device in which the panel 2701 is incorporated. A plurality of packaged semiconductor devices are mounted on the printed wiring board 2703, and the semiconductor device of the present invention can be used as one of them. The plurality of semiconductor devices mounted on the printed wiring board 2703 have any one function of a controller, a central processing unit (CPU), a memory, a power supply circuit, a sound processing circuit, a transmission / reception circuit, and the like.

The panel 2701 is connected to the printed wiring board 2703 through the connection film 2708. The panel 2701, the housing 2702, and the printed wiring board 2703 are housed in the housings 2700 and 2706 together with the operation buttons 2704 and the battery 2705. A pixel region 2709 included in the panel 2701 is arranged so as to be visible from an opening window provided in the housing 2700.

As described above, the semiconductor device of the present invention is characterized in that it is small, thin, and lightweight, and the limited space inside the housings 2700 and 2706 of the electronic device can be effectively used due to the above characteristics. .

  In addition, since the semiconductor device of the present invention includes a memory element having a simple structure in which an organic compound layer that is changed by external voltage application is sandwiched between a pair of conductive layers, an electronic device using an inexpensive semiconductor device is provided. can do. In addition, since the semiconductor device of the present invention can be easily integrated, an electronic device using the semiconductor device including a large-capacity memory circuit can be provided.

  In addition, a memory device included in the semiconductor device of the present invention writes data by applying voltage from the outside, is nonvolatile, and can additionally write data. With the above feature, forgery due to rewriting can be prevented, and new data can be added and written. Therefore, an electronic device using a semiconductor device that achieves high functionality and high added value can be provided.

Note that the housings 2700 and 2706 are examples of the appearance of a mobile phone, and the electronic device according to the present embodiment can be transformed into various modes depending on the function and application.

  In this embodiment, write characteristics of the memory element will be described with reference to FIGS.

  17A shows the structure of the sample 11 used in this example, and FIG. 17B shows the structure of the comparative sample 14 that is a comparison with the sample 11.

  The sample 11 includes a first conductive layer 51 formed on the substrate 50, an insulating layer 52 formed on the first conductive layer 51, an organic compound formed on the first conductive layer 51 and the insulating layer 52. The memory element 55 includes a layer 53 and a second conductive layer 54 formed on the organic compound layer 53.

  The comparative sample 14 includes a first conductive layer 51 formed on the substrate 50, an organic compound layer 53 formed on the first conductive layer 51, and a second conductive layer 54 formed on the organic compound layer 53. The memory element 56 is configured.

  Note that in the memory elements 55 and 56, the end portion of the first conductive layer 51 is covered with a partition wall (insulating layer) 57.

  In the memory elements 55 and 56, a glass substrate is used as the substrate 50, a 100 nm-thick titanium layer formed by a sputtering method is used as the first conductive layer 51, and a thickness formed by an evaporation method in the organic compound layer 53. NPB having a thickness of 10 nm was used, and an aluminum layer having a thickness of 200 nm formed by vapor deposition on the second conductive layer 54 was used. As the memory element 55, a 1-nm-thick calcium fluoride layer formed on the insulating layer 52 by a vapor deposition method was used. In addition, the upper surface shape where the first conductive layer 51 and the second conductive layer 54 of the memory elements 55 and 56 overlap is a square, and the length of one side thereof is 5 μm.

  FIG. 18 shows the writing characteristics of Sample 11 and Comparative Sample 14. The horizontal axis represents the write voltage, and the vertical axis represents the probability of successful write (write success rate) below the write voltage. The writing time was 100 ms. In addition, 64 memory elements formed in each of the sample 11 and the comparative sample 14 were evaluated. The memory element of Sample 11 started writing at 9V, and the writing success rate reached 100% at 12V. On the other hand, the writing of the comparative sample 14 is started at the time of 5V, but the increase in the writing success rate with respect to the increase in voltage is slow, and the writing voltage of 14V is necessary for the writing success rate to reach 100%.

From the above, it is possible to reduce variation in voltage necessary for writing by providing an insulating layer between the first conductive layer and the organic compound layer so as to be in contact with the first conductive layer. I understand.

  In this embodiment, write characteristics of a memory element using different insulating layers will be described with reference to FIGS.

In Samples 12 to 14 each having a memory element using a lithium halide salt as an insulating layer, the write characteristics depending on the type of the lithium halide salt and the upper surface area of the memory element are shown in FIG.

  Samples 12 to 14 include a first conductive layer 51 formed on a substrate 50 as shown in FIG. 17A, an insulating layer 52 formed on the first conductive layer 51, and a first conductive layer 51. And a memory element 55 including an organic compound layer 53 formed on the insulating layer 52 and a second conductive layer 54 formed on the organic compound layer 53.

  Here, as the memory elements of Samples 12 to 14, a glass substrate is used as the substrate 50, a titanium layer having a thickness of 100 nm formed by a sputtering method is used as the first conductive layer 51, and a vapor deposition method is used as the organic compound layer 53. The TPAQn having a thickness of 10 nm formed by the above method was used, and an aluminum layer having a thickness of 200 nm formed by a vapor deposition method was used for the second conductive layer 54. In addition, each of the samples 12 to 14 has a memory element in which the upper surface shape where the first conductive layer 51 and the second conductive layer 54 overlap each other is a square, and the length of one side is 2 μm or 3 μm.

  Writing was performed by applying a voltage of 8 to 12 V to the memory elements of Samples 12 to 14. The writing time at this time was 10 ms.

  As the memory element of Sample 12, a 1-nm-thick lithium fluoride layer formed on the insulating layer 52 by a vapor deposition method was used. The write success rate with respect to the write voltage at this time is shown in FIG.

  As the memory element of Sample 13, a 1-nm-thick lithium chloride layer formed by vapor deposition on the insulating layer 52 was used. The write success rate with respect to the write voltage at this time is shown in FIG.

  For the memory element of Sample 14, a 1 nm thick lithium bromide layer formed on the insulating layer 52 by vapor deposition was used. The writing success rate with respect to the writing voltage at this time is shown in FIG.

Table 4 shows the configurations of the memory elements of Samples 12 to 14.

  Compared with Sample 13 (FIG. 19B) having an insulating layer using lithium chloride and Sample 14 having an insulating layer using lithium bromide (FIG. 19C), lithium fluoride was used. In Sample 12 having an insulating layer (FIG. 19A), the increase in the writing success rate was steep. Further, the variation in the write success rate with respect to the write voltage was small regardless of the top surface area of the memory element. From this, it can be seen that a memory element using lithium fluoride for the insulating layer can reduce variations in the value of the write voltage between the memory elements.

  Next, FIG. 20 shows write voltages and current values of the memory elements using different insulating layers. In this example, a sample having a memory element using an alkaline earth metal fluoride salt as an insulating layer was evaluated.

  As shown in FIG. 17A, the samples 15 to 20 include a first conductive layer 51 formed on the substrate 50, an insulating layer 52 formed on the first conductive layer 51, and a first conductive layer. 51 and an organic compound layer 53 formed on the insulating layer 52 and a second conductive layer 54 formed on the organic compound layer 53.

  In addition, as samples 15 to 17, a glass substrate was used as the substrate 50, a 100 nm-thick titanium layer formed by a sputtering method was used as the first conductive layer 51, and an organic compound layer 53 was formed by a vapor deposition method. NPB having a thickness of 10 nm was used, and an aluminum layer having a thickness of 200 nm formed by a vapor deposition method was used for the second conductive layer 54. Further, the upper surface shape where the first conductive layer 51 and the second conductive layer 54 overlap each other is a square, and the length of one side is 10 μm.

  As the memory element of Sample 15, magnesium fluoride having a thickness of 1 nm formed on the insulating layer 52 by vapor deposition was used.

  As the memory element of Sample 16, calcium fluoride having a thickness of 1 nm formed on the insulating layer 52 by a vapor deposition method was used.

  For the memory element of sample 17, barium fluoride having a thickness of 1 nm formed on the insulating layer 52 by vapor deposition was used.

Table 5 shows the configuration of the memory elements of Samples 15-17.

  Samples 18 to 20 are memory elements in which the organic compound layer is formed of a material different from that of Samples 15 to 17. Here, SFDCz was used instead of NPB as the organic compound layer. The substrate 50, the first conductive layer 51, and the second conductive layer 54 were the same as those used in the samples 15 to 17.

  The memory element of Sample 18 was formed using 1 nm-thick calcium fluoride formed on the insulating layer 52 by a vapor deposition method and 10 nm thick SFDCz formed on the organic compound layer 53 by a vapor deposition method.

  As the memory element of the sample 19, barium fluoride having a thickness of 0.1 nm formed by the evaporation method was used for the insulating layer 52, and SFDCz having a thickness of 10 nm formed by the evaporation method was used for the organic compound layer 53.

  The memory element of the sample 20 used barium fluoride having a thickness of 1 nm formed by an evaporation method for the insulating layer 52 and SFDCz having a thickness of 10 nm formed by an evaporation method for the organic compound layer 53.

Table 6 shows the configuration of the memory elements of Samples 18-20.

  The write voltage and current values of Samples 15 to 17 are shown in FIG. 20A, and the write voltage and current values of Samples 18 to 20 are shown in FIG. 20A and 20B show isopower curves of 20 μW, 100 μW, and 200 μW, respectively. As a writing method at this time, sweep measurement was performed in which the current value of the sample at each voltage was measured while increasing the voltage from 0V to 0.1V. The application time of each voltage was 100 ms.

  As shown in FIG. 20A, the sample 16 having the memory element using calcium fluoride in the insulating layer is more preferable than the sample 17 having the memory element using barium fluoride in the insulating layer. Although the write voltage is high, the current value is low. For this reason, it turns out that power consumption can be reduced. Note that the memory element of Sample 15 has no plot in FIG. 20A because an initial short circuit occurred. Hereinafter, the state in which the memory element is already written before the voltage is applied to the memory element to perform writing is referred to as an initial short circuit.

  20A and 20B, when SFDCz is used instead of NPB for the organic compound layer, compared with Samples 19 and 20 having a memory element using barium fluoride for the insulating layer, The sample 18 having a memory element using calcium fluoride as the insulating layer had a higher write voltage but a lower current value, and as a result, it was possible to reduce power consumption.

  In addition, as shown in FIG. 20B, when comparing the samples 19 and 20 each having a storage element using barium fluoride as the insulating layer, when the film thickness of the insulating layer is reduced as in the sample 19, the write voltage is reduced. It can be seen that this can be reduced.

  Next, in the memory element of the present invention, the write voltage and current value of the memory element with respect to the thickness of the insulating layer are shown in FIG.

  As shown in FIG. 17A, the samples 21 to 24 include a first conductive layer 51 formed on the substrate 50, an insulating layer 52 formed on the first conductive layer 51, and a first conductive layer. 51 and an organic compound layer 53 formed on the insulating layer 52 and a second conductive layer 54 formed on the organic compound layer 53.

  Here, as the samples 21 to 24, a glass substrate is used as the substrate 50, a titanium layer having a thickness of 100 nm formed by a sputtering method is used as the first conductive layer 51, and an organic compound layer 53 is formed by a vapor deposition method. Further, NPB having a thickness of 10 nm was used, and an aluminum layer having a thickness of 200 nm formed on the second conductive layer 54 by an evaporation method was used.

  As the memory element of the sample 21, calcium fluoride having a thickness of 1 nm formed on the insulating layer 52 by a vapor deposition method was used.

  As the memory element of the sample 22, calcium fluoride having a thickness of 2 nm formed on the insulating layer 52 by a vapor deposition method was used.

  For the memory element of Sample 23, calcium fluoride having a thickness of 3 nm formed on the insulating layer 52 by vapor deposition was used.

  As the memory element of the sample 24, calcium fluoride having a thickness of 5 nm formed on the insulating layer 52 by a vapor deposition method was used.

Table 7 shows the configuration of the memory elements of Samples 21 to 24.

  Next, the method of measurement is shown below. First, a read voltage of 0 to 3 V was applied to each sample, and the presence and location of the memory element that was initially short-circuited in the memory element of each sample was specified.

  Next, writing was performed by applying a voltage to a memory element that was not initially short-circuited. Here, the voltage boosted using the booster circuit was used as the write voltage and applied to the memory element of each sample. The operating frequency of the booster circuit at this time was 5 MHz, and the write voltage was 3V. Next, sweep measurement was performed to measure the current value of the sample at each voltage while increasing the voltage by 0.1V from 0V to 50V. Moreover, the application time of each voltage was 20 ms.

  As shown in FIG. 21, a plot of the write voltage and current value of the sample 21 is surrounded by a broken line 61, a plot of the write voltage and current value of the sample 22 is surrounded by a broken line 62, and a plot of the write voltage and current value of the sample 23 is plotted. A plot of the writing voltage and current value of the sample 24 is enclosed by a broken line 64 and surrounded by a broken line 63. When Samples 21 to 23 and Sample 24 were compared, it was found that a memory element having a thin insulating layer (1 to 3 nm) had a low write voltage and a large current value. However, it can be seen that in Samples 21 to 23, the current-voltage characteristics at the time of writing hardly change. From this, it is understood that the write voltage and current value can be stabilized by setting the thickness of the insulating layer of the memory element to 1 to 3 nm.

  In this example, Tables 8 to 11 and FIG. 22 show measurement results of writing time and writing characteristics of memory elements having different insulating layers.

  As shown in FIG. 17A, the samples 25 to 27 include a first conductive layer 51 formed on the substrate 50, an insulating layer 52 formed on the first conductive layer 51, and a first conductive layer. 51 and an organic compound layer 53 formed on the insulating layer 52 and a second conductive layer 54 formed on the organic compound layer 53.

  Here, as the samples 25 to 27, a glass substrate is used on the substrate 50, a 100 nm-thick titanium layer formed by a sputtering method is used for the first conductive layer 51, and an organic compound layer 53 is formed by a vapor deposition method. The NPB having a thickness of 10 nm was used, and an aluminum layer having a thickness of 200 nm formed on the second conductive layer 54 by an evaporation method was used. Samples 25 to 27 each have a storage element in which the upper surface shape where the first conductive layer 51 and the second conductive layer 54 overlap is a square, and the length of one side is 2 μm, 3 μm, 5 μm, and 10 μm. .

  For the memory element of sample 25, calcium fluoride having a thickness of 1 nm formed on the insulating layer 52 by vapor deposition was used.

  As the memory element of the sample 26, barium fluoride having a thickness of 1 nm formed on the insulating layer 52 by a vapor deposition method was used.

  For the memory element of Sample 27, lithium fluoride having a thickness of 1 nm formed on the insulating layer 52 by vapor deposition was used.

Table 8 shows the structures of the memory elements of Samples 25 to 27.

  Next, the method of measurement is shown below. First, a read voltage of 3 V was applied to each sample, and the presence and location of the memory element initially short-circuited in the memory element of each sample was specified.

  Next, writing was performed by applying a voltage to a memory element that was not initially short-circuited. Here, the voltage boosted using the booster circuit was used as the write voltage and applied to the memory element of each sample. The operating frequency of the booster circuit at this time was 5 MHz, and the write voltage was 3V.

  First, a voltage of 1 ms was applied to the memory element of each sample, and writing was performed by applying a voltage to the memory element that could not be written with a writing time of 2 ms, 5 ms, 10 ms, 20 ms, 50 ms, and 100 ms.

Table 9 shows the evaluation results of writing the sample 25, Table 10 shows the evaluation results of writing the sample 26, and Table 11 shows the evaluation results of writing the sample 27.

As shown in Table 9 and Table 10, the sample 26 having a memory element using barium fluoride for the insulating layer and the sample 25 having a memory element using calcium fluoride for the insulating layer had substantially the same write characteristics. It was. On the other hand, as shown in Tables 9 to 11, the sample 27 having a memory element using lithium fluoride as the insulating layer is a sample 25 having a memory element using calcium fluoride as the insulating layer, or the insulating layer. The writing success rate is higher than that of the sample 26 having a memory element using barium fluoride.

Next, FIG. 22 shows the relationship between the writing success rate of the sample 27 and the writing time with a high writing success rate. If the memory element has a side length of 10 μm, it can be seen that 100% writing is successful with 1 ms writing.

From the above, it was found that the write success rate can be increased by using a memory element using lithium fluoride as an insulating layer. In particular, it can be seen that a memory element using lithium fluoride as an insulating layer is suitable for a semiconductor device that requires high-speed operation because the writing success rate is high even in a short writing time.

  In this example, measurement results of write characteristics of memory elements having different organic compound layers will be described with reference to Tables 12 and 13 and FIG.

  As shown in FIG. 17A, the samples 28 to 33 include a first conductive layer 51 formed on the substrate 50, an insulating layer 52 formed on the first conductive layer 51, and a first conductive layer. 51 and an organic compound layer 53 formed on the insulating layer 52 and a second conductive layer 54 formed on the organic compound layer 53.

  Here, as the samples 28 to 33, a glass substrate is used on the substrate 50, a 100 nm-thick titanium layer formed by a sputtering method is used for the first conductive layer 51, and an insulating layer 52 is formed by an evaporation method. In addition, a calcium fluoride layer having a thickness of 1 nm was used, and an aluminum layer having a thickness of 200 nm formed on the second conductive layer 54 by an evaporation method was used. Further, in Samples 28 to 30, memory elements were formed in which the top surface shape where the first conductive layer 51 and the second conductive layer 54 overlap each other was a square and the length of one side thereof was 5 μm.

  As the memory element of the sample 28, NPB having a thickness of 10 nm formed on the organic compound layer 53 by a vapor deposition method was used.

  As the memory element of the sample 29, t-BuDNA having a thickness of 10 nm formed on the organic compound layer 53 by a vapor deposition method was used.

  As the memory element of Sample 30, TPAQn having a thickness of 10 nm formed on the organic compound layer 53 by a vapor deposition method was used.

Table 12 shows the configuration of the memory elements of Samples 28 to 30.

First, when a read voltage is applied to each sample, a ratio of initial short-circuit in the memory element of each sample (hereinafter referred to as initial short-circuit ratio), and a write voltage from 5 V to 14 V is applied to the memory element that is not initially short-circuited. Table 13 shows the writing success rate. The writing time was performed under two conditions of 10 ms and 100 ms.

  As shown in Table 13, even when NPB, t-BuDNA, and TPAQn were used for the organic compound layer of the memory element, the initial short-circuit rate of each sample was very low.

In addition, the writing success rate from 5V to 14V is higher in the sample 29 having the memory element using t-BuDNA in the organic compound layer and the TPAQn in the organic compound layer than in the sample 28 having the memory element using NPB in the organic compound layer. The sample 30 having the memory element used was higher.

  Next, FIG. 23 shows voltage-current characteristics when writing is performed by applying a voltage to the memory elements of Samples 28-30. Here, the shape of the upper surface of the memory element of each sample was a square, the length of one side was 5 μm, and the writing time was 10 ms.

  As shown in FIG. 23, the write voltage of the sample 30 having the memory element using TPAQn as the organic compound layer is the lowest, then the sample 29 having the memory element using t-BuDNA as the organic compound layer, and NPB as the organic compound. The writing voltage increased in the order of the sample 28 having the memory element used for the layer. By using TPAQn for the organic compound layer, the write voltage of the memory element can be reduced.

  In this example, as in Example 9, the measurement results of the writing voltage and current value when writing is performed by applying a voltage to a memory element having a different organic compound layer, using Table 14 and FIG. Show.

Here, a sample having a memory element using an organic compound layer formed of a different material was manufactured. The results are shown in FIGS. 24 (A) and (B). FIG. 24A shows the write voltage and current values of Samples 31 to 34 each having a memory element using a hole transport material for the organic compound layer, and FIG. 24B uses an electron transport material for the organic compound layer. The write voltage and current values of Samples 35 to 40 having the storage elements were shown.

  As shown in FIG. 17A, the samples 31 to 40 include a first conductive layer 51 formed on the substrate 50, an insulating layer 52 formed on the first conductive layer 51, and a first conductive layer. 51 and an organic compound layer 53 formed on the insulating layer 52 and a second conductive layer 54 formed on the organic compound layer 53.

  Here, as the samples 31 to 40, a glass substrate is used on the substrate 50, a 100 nm-thick titanium layer formed by a sputtering method is used for the first conductive layer 51, and an insulating layer 52 is formed by a vapor deposition method. In addition, a calcium fluoride layer having a thickness of 1 nm was used, and an aluminum layer having a thickness of 200 nm formed on the second conductive layer 54 by an evaporation method was used. Further, in Samples 31 to 43, memory elements in which the top surface shape where the first conductive layer 51 and the second conductive layer 54 overlap are square and the length of one side is 2 μm, 3 μm, 5 μm, and 10 μm are formed. did.

  In the memory element of sample 31, an organic compound layer was formed using NPB having a thickness of 10 nm formed on the organic compound layer 53 by a vapor deposition method.

  In the memory element of Sample 32, an organic compound layer was formed on the organic compound layer 53 using SFDCz having a thickness of 10 nm formed by a vapor deposition method.

  As the memory element of Sample 33, PVK having a thickness of 10 nm formed on the organic compound layer 53 by a vapor deposition method was used.

  As the memory element of the sample 34, TCTA having a thickness of 10 nm formed on the organic compound layer 53 by a vapor deposition method was used.

  As the memory element of the sample 35, InTz having a thickness of 10 nm formed on the organic compound layer 53 by a vapor deposition method was used.

  As the memory element of the sample 36, TPQ having a thickness of 10 nm formed on the organic compound layer 53 by a vapor deposition method was used.

  As the memory element of the sample 37, Alq having a thickness of 10 nm formed on the organic compound layer 53 by a vapor deposition method was used.

  As the memory element of the sample 38, BAlq having a thickness of 10 nm formed on the organic compound layer 53 by a vapor deposition method was used.

  As the memory element of the sample 39, TPAQn having a thickness of 10 nm formed on the organic compound layer 53 by a vapor deposition method was used.

  As the memory element of the sample 40, t-BuDNA having a thickness of 10 nm formed on the organic compound layer 53 by a vapor deposition method was used.

Table 14 shows the configuration of the memory elements of Samples 31 to 40.

As a writing method at this time, sweep measurement was performed in which the current value of the sample at each voltage was measured while increasing the voltage from 0V by 0.1V. The application time of each voltage was 100 ms.

As shown in FIG. 24A, the writing voltage of the sample 34 having a memory element using TCTA for the organic compound layer is significantly increased. On the other hand, a sample 31 having a memory element using NPB for the organic compound layer, a sample 32 having a memory element using SFDCz for the organic compound layer, and a sample 33 having a memory element using PVK for the organic compound layer are 200 μW. Since it plots in the area | region below an isopower curve, it turns out that the power consumption of a semiconductor device can be reduced by using the memory element which has these organic compound layers.

As shown in FIG. 24B, a sample 37 having a memory element using Alq as the organic compound layer and a sample 38 having a memory element using BAlq as the organic compound layer are below the isopower curve of about 200 μW. Is plotted in the region. Sample 35 having a memory element using InTz as an organic compound layer, Sample 36 having a memory element using TPQ as an organic compound layer, Sample 39 having a memory element using TPAQn as an organic compound layer, t-BuDNA A sample 40 having a memory element in which is used for the organic compound layer is plotted in a region below the 100 μW isopower curve. For this reason, it is understood that the power consumption of the semiconductor device can be reduced by using the memory element having these organic compound layers.

  In this example, Table 15 shows measurement results of current-voltage characteristics when writing is performed by applying a voltage to a memory element in which different organic compound layers are stacked.

As shown in FIG. 17A, the sample 41 includes a first conductive layer 51 formed on the substrate 50, an insulating layer 52 formed on the first conductive layer 51, a first conductive layer 51, and A memory element including an organic compound layer 53 formed on the insulating layer 52 and a second conductive layer 54 formed on the organic compound layer 53 was used.

  Here, the memory element of the sample 41 includes a 10 nm thick BCP formed by an evaporation method and an organic compound layer stacked using NPB 10 nm thick formed on the BCP.

  Further, a glass substrate is used on the substrate 50, a titanium layer having a thickness of 100 nm formed by a sputtering method is used for the first conductive layer 51, and a calcium fluoride having a thickness of 1 nm formed by an evaporation method on the insulating layer 52. A 200 nm-thick aluminum layer formed by vapor deposition on the second conductive layer 54 was used.

The shape of the upper surface of each memory element is a square, and Table 15 shows the write voltage and current value of the memory element with respect to the length of one side of the memory element.

  As shown in Table 15, it was possible to perform writing in the memory element in which the organic compound layers were stacked. Moreover, although the write voltage is high, the current value at the time of writing can be reduced. It was also found that the variation in the write voltage was small.

  In this example, changes in the write voltage and current value with respect to the upper surface area of the memory element and the film thickness of the organic compound layer will be described with reference to Table 16 and FIGS.

  As shown in FIG. 17A, the samples 42 to 48 include a first conductive layer 51 formed on the substrate 50, an insulating layer 52 formed on the first conductive layer 51, and a first conductive layer. 51 and an organic compound layer 53 formed on the insulating layer 52 and a second conductive layer 54 formed on the organic compound layer 53.

  As samples 42 to 48, a glass substrate was used on the substrate 50, a titanium layer having a thickness of 100 nm formed by a sputtering method was used for the first conductive layer 51, and an insulating layer 52 was formed by a vapor deposition method. A calcium fluoride layer having a thickness of 1 nm was used, and an aluminum layer having a thickness of 200 nm formed by vapor deposition on the second conductive layer 54 was used.

  As the memory element of the sample 42, NPB having a thickness of 5 nm formed on the organic compound layer 53 by a vapor deposition method was used.

  As the memory element of the sample 43, NPB having a thickness of 10 nm formed on the organic compound layer 53 by a vapor deposition method was used.

  As the memory element of the sample 44, NPB having a thickness of 10 nm formed on the organic compound layer 53 by a vapor deposition method was used.

  As the memory element of the sample 45, NPB having a thickness of 20 nm formed on the organic compound layer 53 by a vapor deposition method was used.

  As the memory element of the sample 46, NPB having a thickness of 30 nm formed on the organic compound layer 53 by a vapor deposition method was used.

  For the memory element of Sample 47, NPB having a thickness of 40 nm formed on the organic compound layer 53 by vapor deposition was used.

  As the memory element of the sample 48, NPB having a thickness of 50 nm formed on the organic compound layer 53 by a vapor deposition method was used.

Table 16 shows the configuration of the memory elements of Samples 42 to 48.

  Further, in the sample 42, the memory elements in which the top surface shape where the first conductive layer 51 and the second conductive layer 54 overlap each other are square and the length of one side is 2 μm, 3 μm, 5 μm, and 10 μm are formed. . As a writing method at this time, sweep measurement was performed in which the current value of the sample at each voltage was measured while increasing the voltage from 0V by 0.1V. The application time of each voltage was 100 ms.

  FIG. 25 shows measurement results of the writing voltage and the writing characteristics of the memory element in Sample 42 in which the length of one side of the memory element is 2 μm, 3 μm, 5 μm, and 10 μm.

  As shown in FIG. 25, the longer the length of one side of the memory element, the better the writing characteristics. Although this tendency is not shown, the same tendency was confirmed in the sample 43 and the results of evaluation with different writing times.

  Next, FIG. 26 and FIG. 27 show measurement results of write voltage and current value and write characteristics when the film thickness of the organic compound layer is changed.

  In FIG. 26, writing voltage and current value when writing is performed by applying a voltage to the memory elements of the samples 44 to 48 are shown. In FIG. 26, a plot surrounded by a broken line 71 is a plot of the sample 44, a plot surrounded by a broken line 72 is a plot of the sample 45, a plot surrounded by a broken line 73 is a plot of the sample 46, and is surrounded by a broken line 74. The plot shown is a plot of the sample 47, and the plot surrounded by the broken line 75 shows the plot of the sample 48. Further, in the dashed ellipse, the measurement results of the memory elements having the same structure and different sizes are plotted. The upper left of the ellipse shows the measurement results of the larger storage elements, and the lower right is the smaller size. The plot of the measurement result of a memory element is shown.

FIG. 26 shows that the write voltage decreases as the film thickness of the organic compound layer decreases, although the current value does not change so much. It can also be seen that, in the memory elements having the same structure, the smaller the upper surface area, the lower the write voltage, but the higher the current value at that time.

  Next, FIG. 27 shows the write voltage and write characteristics of the memory element when the film thickness of the organic compound layer is further reduced. The length of one side of the memory elements of the samples 42 and 43 was 3 μm.

  As shown in FIG. 27, when the length of one side of the memory element is the same, the sample 42 having the memory element with the organic compound layer thickness of 5 nm has the organic compound layer thickness of 10 nm. It was found that the writing success rate at a low voltage was higher than that of the sample 43 having the element. Specifically, the sample 42 can be written with a voltage lower by about 4 V than the sample 43.

4A and 4B are a top view and cross-sectional views illustrating a memory device of the present invention. FIG. 10 is a cross-sectional view illustrating a memory device of the present invention. FIG. 6 is a top view illustrating a memory device of the present invention. FIG. 10 is a cross-sectional view illustrating a memory device of the present invention. 3A and 3B illustrate a memory device of the present invention. 3A and 3B illustrate a memory device of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a memory device of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device of the present invention. 10A and 10B illustrate current-voltage characteristics of a memory element and a resistance element. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 6A and 6B illustrate an electronic device including a semiconductor device of the present invention. 4A and 4B each illustrate a usage pattern of a semiconductor device of the invention. FIG. 11 shows current-voltage characteristics of a memory element. FIG. 10 is a cross-sectional view illustrating a memory device of the present invention. FIG. 6 is a cross-sectional view illustrating the structure of a memory element of the present invention. 4A and 4B illustrate experimental results using the memory element of the present invention. 4A and 4B illustrate experimental results using the memory element of the present invention. 4A and 4B illustrate experimental results using the memory element of the present invention. 4A and 4B illustrate experimental results using the memory element of the present invention. 4A and 4B illustrate experimental results using the memory element of the present invention. 4A and 4B illustrate experimental results using the memory element of the present invention. 4A and 4B illustrate experimental results using the memory element of the present invention. 4A and 4B illustrate experimental results using the memory element of the present invention. 4A and 4B illustrate experimental results using the memory element of the present invention. 4A and 4B illustrate experimental results using the memory element of the present invention.

Claims (3)

A first conductive layer;
A second conductive layer;
An organic compound layer sandwiched between the first conductive layer and the second conductive layer;
An insulating layer provided between the first conductive layer and the organic compound layer ,
The insulating layer has a thickness of 0.1 nm to 4 nm ,
The memory element , wherein the insulating layer contains lithium fluoride . In claim 1,
The memory element, wherein the organic compound layer includes TPAQn. In claim 1,
The memory element, wherein the organic compound layer includes NPB.

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