JPH02246149A - Semiconductor integrated circuit device and method for remedying defect thereof - Google Patents

Abstract

PURPOSE:To simplify and rationalize a layout by a method wherein a circuit having a RAM function is formed as a macrocell and a plurality of macrocells constitute a semiconductor storage circuit of a large storage capacity. CONSTITUTION:In this RAM, a plurality of memory blocks which has been formed as macrocells are arranged in a matrix manner. Sixteen memory blocks of about 4 Mbits each are arranged in four rows and four columns and have a large storage capacity of about 64 Mbits as a whole. One memory block constituted as the macrocell is provided with the following: a row-based address decoder which receives an address signal supplied through a timing/address generation circuit which have been made common; an address selection circuit composed of a word-line drive circuit, a column-based address decoder, a column selection-line drive circuit or the like; a timing generation circuit which generates a time-series timing pulse when an internal operation is required according to a memory array and an operating mode; a timing generation circuit for a selected memory cell; an input/output circuit which executes a write/readout operation of a data for the selected memory cell.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device and a defect relief method thereof, and relates to a dynamic RAM (random access memory) having a large storage capacity of about 64 M pins, for example. )
This article concerns effective technology that can be used to remedy defects.

[Conventional technology]

Dynamic RAM having a large storage capacity of approximately 16 Mbits is being developed.

An example of such a dynamic RAM is "Nikkei Microdevice 1 Magazine, pages 67 to 81, published by Nikkei McGraw-Hill, March 1, 1988.

[Problem to be solved by the invention]

With the increase in storage capacity as described above, memory chips also inevitably become larger. Accordingly, in a dynamic RAM with a large storage capacity such as approximately 64 M pins, the signal transmission speed decreases as the wiring length increases due to miniaturization of elements and routing of wiring. As a result, in a DRAM designed to have a large storage capacity as described above, special consideration must be given to the reduction in operating speed due to the signal delay as described above.

In other words, in order to realize a large storage capacity of approximately 64 Mbits, it is necessary to develop a new technology that is different from the technical methods used for conventional approximately 1 Mbits and approximately 4 Mbits.

An object of the present invention is to provide a semiconductor integrated circuit device including a semiconductor memory circuit with a large storage capacity.

Another object of the present invention is to provide a semiconductor integrated circuit device equipped with a semiconductor memory circuit that realizes a large storage capacity while increasing the speed.

Still another object of the present invention is to provide an efficient method for repairing defects in semiconductor memory circuits that achieve large storage capacity.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a circuit block including a memory array, its address selection circuit, and data input/output circuit is used as a macrocell, and a plurality of macrocells are provided to constitute a semiconductor memory device with a large storage capacity. Bonding pads for external input and output are arranged close to the macrocell, and a common LOC lead frame is extended to the bonding pads that supply the same signal, and bonding is performed using a covered wire.

In the memory cell, the backing wiring of the word line and the bit line are multilayered, and the wiring layers of adjacent wirings are different from each other. Drive circuits and unit sense amplifiers are provided alternately at both ends of the word line and/or bit line. The number of operating circuits and operating time are made different between the normal mode and the refresh mode.

On the condition that no defective bit exists at the same address, the output of the non-defective part of the two memory chips is made valid, or only the non-defective part is accessed. A plurality of chips using only non-defective parts of the defective chips are housed in one puff cage to make it appear to be a working product. Output signals of memory chips or memory blocks consisting of an odd number of three or more memory chips having no defects at the same address are outputted via a majority logic circuit.

[For production]

According to the above-mentioned means, the layout can be simplified and rationalized by converting a memory circuit having a RAM function into a macro cell and configuring a semiconductor memory circuit with a large storage capacity by providing a plurality of macro cells. By extending the LOG IJ-board close to the macrocell and performing bonding with a covered wire, high-speed signal input/output is possible.

For memory cells, high-density arrangement of memory cells can be achieved by multilayering word line backing wiring and bit lines, and by providing drive circuits and unit sense amplifiers alternately at both ends of word lines and/or bit lines. It becomes possible. It is possible to reduce power consumption by varying the number of circuits operating in the normal mode and the operating time in the refresh mode.

Then, by using the non-defective part of the two defective chips, it is possible to form an apparently working memory chip. A defective bit can be invalidated by taking a majority vote of an odd number of bits. By configuring one RAM by housing these defective chips in the same package, the yield of the RAM can be increased.

〔Example〕

FIG. 1 shows a basic block diagram of an embodiment of a dynamic RAM having a large storage capacity of about 64 Mbits to which the present invention is applied.

In this embodiment, the length of various wiring such as control signals and memory array drive signals is increased due to the increase in chip size due to the increase in memory capacity, which inevitably increases the signal propagation delay time. In order to prevent the operation speed from slowing down depending on the
The following measures are taken in the arrangement of the memory array section that constitutes the memory array section and the peripheral section that performs address selection and the like.

Each main circuit block in the figure is drawn in accordance with the geometric arrangement on an actual semiconductor chip.

The RAM of this embodiment is composed of a plurality of macrocell memory blocks arranged in a matrix. One macrocell memory block has a storage capacity of approximately 4M bits. In the embodiment shown in the figure, 16 such macrocell memory blocks are arranged in 4 rows and 4 columns, thereby providing a large storage capacity of approximately 64 Mbits as a whole.

One macro cell memory block includes a row address decoder and word line drive circuit, a column address decoder, a column selection line drive circuit, etc. that receive address signals supplied through a common timing/address generation circuit. an address selection circuit consisting of an address selection circuit, a memory array, a timing generation circuit that generates time-series timing pulses necessary for internal operations according to the operation mode, and a data write/write circuit for a selected memory cell.
It also includes an input/output circuit that performs reading.

Memory blocks as described above are arranged in a matrix, and a control circuit as described above is provided to control the memory blocks. Signals are transmitted between this control circuit and each of the memory blocks through a signal bus.

Therefore, the dynamic RAM of this embodiment looks like a semiconductor memory device with a board configuration in which one macro cell memory block is regarded as one RAM.

However, the RAM of this embodiment is constituted by only one semiconductor integrated circuit, and is greatly different from simply replacing the mounting substrate of the board configuration as described above with a semiconductor substrate. This is because semiconductor integrated circuits involve various technical issues that do not pose problems for board-based semiconductor memory devices, such as chip size constraints, wiring layer constraints, power consumption constraints, and defect relief. This is because.

In other words, by solving various technical problems such as those mentioned above,
This is the first time that it can be configured as a single semiconductor integrated circuit device.

In this embodiment, the overall layout and its control are simplified by converting the memory block having the above memory function into a macro cell. In other words, by designing a macrocell with a storage capacity of about 4M bits, it can be converted into a 4x4 memory cell as described above.
64 Mbit dynamic RA just by arranging them
This is because M can be formed.

Then, in the control circuit, the operation mode is determined and a main timing signal corresponding thereto is formed, and the address signal is divided into an internal address signal to be supplied to each memory block and a decoded memory block selection signal. Macro cells are created through the above signal bus.
Supply to memory block. Further, the control circuit is provided with a refresh control circuit including a refresh address generation circuit for refresh operation.

By adopting such a configuration, a macrocell memory block can have a simplified circuit configuration consisting of memory cells arranged in a matrix, their selection circuits, and data input/output circuits. . That is, in the macro cell memory block of this embodiment, an operation mode determination circuit and a corresponding timing signal generation circuit and refresh address generation circuit are provided, like the individual DRAMs mounted on the board-configured storage device. It is not necessary to provide a refresh control circuit including.

In this embodiment, the power supply voltage is set to a relatively low potential such as about 3.3 V, although not particularly limited, in order to cope with the reduction in breakdown voltage and power consumption of the device due to the increase in the number of ML elements. This power supply voltage is approximately 5V supplied externally.
In addition to a configuration in which a power supply circuit is provided internally to receive a voltage such as 3.3V and step down, the voltage of approximately 3.3V may be supplied externally.In this case, the selection of the word line, etc. For circuits that require a higher level than the power supply voltage, such as a selection signal for selecting a level or shared sense amplifier, use a bootstrap circuit for each circuit or operate it with a pre-boosted voltage. do it.

In order to further reduce power consumption, for example, in response to the above voltage of approximately 3.3V, the internal operating voltage may be reduced to 2V or 5V.
It may be as low as about v. If the circuit is operated at a low voltage such as the above-mentioned approximately 1°5V, battery bank-up can be easily performed.

FIG. 2 shows a block diagram of an embodiment of a dynamic RAM according to the present invention.

Each circuit block in the figure is formed on one semiconductor substrate. The RAM of this embodiment has a large storage capacity of approximately 64 Mbits, as described above, and is constituted by one semiconductor integrated circuit device as described above.

Therefore, the address signal terminal At (
In the address multiplex method, AO-A12),
It consists of a row address strobe signal terminal RAS, a column address strobe signal terminal CAS, a write enable signal terminal WE, and data signal terminals Din and Dout.

The address signal supplied from the address signal terminal Ai is
The signal is supplied to an address control circuit ADC included in the control circuit. The row address strobe signal supplied from the terminal RAS is sent to the row-related pretiming generation circuit RP.
The output signal is taken into the TG, and the output signal is sent to the address control circuit ADC, the operation mode determination circuit RD such as normal mode, refresh mode, counter test mode, etc.
C and a memory block selection signal, a main timing signal generation circuit according to the operation mode, and a control circuit C0NT2 consisting of a refresh address counter circuit. The column address strobe signal supplied from the terminal CAS is taken into the column system pre-timing generation circuit CPTG, and its output signal is supplied to the address control circuit ADC1 operation mode determination circuit RDC and the control circuit C0NT2. The write enable signal supplied from the terminal WE is sent to the write timing generation circuit W.
The signal is taken into PTG, and its output signal is supplied to the address control circuit ADC1 control circuit C0NT2 and the operation mode determination circuit RDC.

The address control circuit ADC uses the address strobe signals RAS and CAS to take in row-related and column-related address signals supplied in time series from the external terminal At, and selects a specific address signal among them. The signal is supplied to the control circuit C0NT1, and the remaining address signals are input to address buffers XAB and YAB. Address buffers XAB and YAB commonly supply an X address and a Y address to each memory block through internal buses XB and YB, respectively.

The control circuit C0NT1 generates the number of operating mats during refresh operation and the address for normal mode.

The operation mode determination circuit RDC determines the CBR from the output signals of the pretiming generation circuits RPTG, CPTG, and WPTG.
Refresh (CAS before RAS refresh)
and WCBR (counter test), and transmits the determination results to the control circuit C0NT2. The control circuit C0NT2 supplies a block selection signal in the normal mode and a main timing signal according to the operation mode through the internal bus CB. In refresh mode (CBR), a refresh address is supplied.

Therefore, in each memory protector, the internal bus
A switching circuit is provided for switching between an address in the normal mode and an address in the refresh mode, which are supplied through the CB and CB. In this refresh mode, the operations of the Y-system selection circuit and the X address buffer are stopped, as will be described later. Counter test mode (W
CBR), in addition to the above refresh operation, Y
The selection circuit of the system is also activated.

The read signal of each memory block is sent to the main amplifier MA.
is transmitted to the output logic circuit through the input/output circuit 1.
It is sent from the terminal Dout through 0B. Note that in the write path, data input from the terminal Din is taken in through the input/output circuit IOB and transmitted to the selected memory block. Although such a write path is omitted in the figure, it should be understood that it is provided parallel to the read path.

In this embodiment, one memory block is made into a macro cell, and a plurality of macro cells are arranged in order to realize a large storage capacity of about 6 Mbits.

Therefore, it is sufficient to develop and design a memory circuit having a storage capacity of, for example, about 4 Mbits, and to provide a plurality of the same circuits, which simplifies circuit design and layout design. Further, as described above, one memory block is provided with a memory cell selection circuit and an input/output circuit so as to constitute one RAM. Therefore, as will be described later, it is possible to activate only the memory block in which the memory cell to be selected exists, thereby reducing power consumption.

As mentioned above, since the operation mode determination circuit and the Freshé control circuit are provided in common for multiple memory blocks, the circuit scale of the memory block itself can be reduced, and the overall circuit scale can be reduced accordingly. Can be made smaller.

FIG. 3 shows a basic layout diagram of another embodiment of external terminals in a semiconductor integrated circuit device according to the present invention.

In the figure, one semiconductor integrated circuit device is made up of a plurality of circuit blocks formed into macro cells.For example, when configuring a dynamic RAM of approximately 64 Mbits as described above, each circuit block is It is said to be a dynamic RAM with a storage capacity of about 4 Mbits. However, in this embodiment, a control circuit commonly used for a plurality of memory blocks as described above is not provided. Therefore, it should be understood that the memory blocks in this embodiment each include an address selection circuit, an input/output circuit, and a control circuit.

In this example, in order to prevent the internal wiring from causing signal delays and slowing down the operation speed when transmitting and receiving signals to and from external terminals in a large-scale integrated circuit, each memory block is Then, bonding pads are arranged near each of them.

For example, bonding pads for address terminals are provided near where the address buffer of each memory block is provided, and bonding pads for RA34) CAS and WE are provided near where the control circuit is provided.
Bonding pads for control signals such as these are arranged as close as possible to bonding pads for data terminals in the input/output circuit. In this embodiment, bonding pads are not provided at the periphery like in conventional semiconductor chips, but are provided near each memory block.

In this case, although there is no particular restriction, a memory block consisting of 4 rows and 4 columns is divided into two vertically and horizontally, and four memory blocks consisting of 2 columns and 2 rows are combined into one memory group. A bonding pad is provided at the center of the memory block so as to correspond to the four memory blocks and to be used in common. By adopting such a configuration, the number of bonding bands can be reduced. In this configuration, there are 4 memory blocks consisting of 16 in total.
For example, when explaining the row address strobe signal RAS, four bonding pads are provided for the four memory groups mentioned above. provided.

In contrast to conventional DRAM chips, in which bonding pads are provided only at the periphery of the chip as described above, and only one bonding pad is provided for one signal, the configuration of this embodiment is They are very different. In other words, as chips become larger, bonding pads are no longer provided in structures such as conventional DRAMs, in which bonding bands are provided only at the periphery of the chip, and only one bonding band is provided for one signal. Since the wiring is routed from one point to the opposing peripheral area, the length of the wiring becomes long.

In this embodiment, in order to increase the operating speed, the above-mentioned restrictions are removed and bonding pads for necessary signals are provided close to each memory block. As a result, the wiring length from the bonding pad to the corresponding internal circuit can be shortened, and high-speed operation can be achieved regardless of the increase in chip size.

However, when bonding pads are provided as described above, a bonding technique different from that of conventional DRAMs is required. Therefore, the following LOC
(lead-on-chip) technology.

FIG. 4 shows a basic layout diagram of an embodiment of the semiconductor integrated circuit device according to the present invention and a corresponding pattern diagram of an embodiment of the LOC lead frame.

The LOC lead frame shown in the figure corresponds to a half area in the longitudinal direction of the chip.

In the LOC lead frame, for example, the lead frame and the surface of the chip are connected to each other using an adhesive via a film-like insulator. This allows each lead to
As shown in the figure, it extends from the long side of the chip and is bent from a certain point at a right angle to the longitudinal direction of the chip. By employing such a LOC lead frame, bonding pads to which the same signal is supplied are wire-bonded to the same LOC lead frame. In this case, the wire used is an insulated wire to prevent electrical contact with other LOC lead frames.

Bonding pads corresponding to the remaining half of the memory blocks in the figure are also provided with LOC leads axially symmetrical to the LOC lead frame and connected in the same way. In this configuration, the LOG IJ-deframes are commonly connected to bonding bands to which the same signal is applied. Therefore, in this embodiment, the LOC
The lead frame is regarded as part of the wiring of the semiconductor integrated circuit device, and constitutes a signal transmission path. Since the LOC lead frame can significantly reduce the resistance value of the wiring line Ia compared to the signal line formed in the semiconductor integrated circuit device, it is possible to speed up the operation.

The above-mentioned LOC lead frame includes one in which a film is interposed as described above, and one in which an insulator is formed on the surface of the semiconductor chip (excluding the bonding pads) and leads are directly bonded to it with an adhesive. Alternatively, the lead frame itself may be covered with a molding resin or the like in areas other than the portions to be bonded and attached to the surface of the semiconductor chip using an adhesive.

It should be noted that a part of the internal bus shown in FIG. 2 may be replaced with a LOC lead frame.

In this case, the signal is divided into an address signal for selecting a memory block and an address signal commonly supplied to each memory block. Address signals to be supplied to each memory block are supplied to bonding pads arranged close to each memory block using the LOC lead frame. Further, an address signal for selecting a memory block is supplied to a bonding pad arranged close to the control circuit C0NT2. Further, the data input/output path is also connected to the bonding pad for the input/output circuit of each memory block using the OC lead frame described above.

By adopting such a configuration, it is possible to simplify the system as described above and to realize faster operation.

5A to 5C show the semiconductor chip and L
A schematic pattern diagram of another embodiment of the OC lead frame is shown.

FIG. 5A shows an example in which the LOC lead frames are arranged in the short direction of the semiconductor chip, and FIG. 5B shows the lengths from the long sides of the semiconductor chip to the center of the semiconductor chip.
An example is shown in which the pattern is such that the OC lead frame is extended, and FIG. 5C shows an example in which the LOC lead frame is made into two layers and a larger number of LOC leads are formed on the chip surface. In this way, the pattern of the LOC lead frame can take various embodiments depending on the arrangement of the bonding pads.

FIG. 6 shows a layout diagram of bonding pads in another embodiment of the macrocell memory block according to the present invention.

This embodiment shows an example in which the four memory blocks consisting of two rows and two columns are treated as one memory group, and bonding pads are arranged around the periphery thereof. In this embodiment, bonding bands are placed close to each circuit in order to make the wiring from the bonding pads to the internal circuits shorter. Therefore, among the bonding pads, a bonding pad formed in a region sandwiched between two memory blocks can be used in common for both memory blocks, but other bonding pads are provided for each memory block. Therefore, in order to share the bonding band as described above, the layout of the internal circuits of the four memory blocks is arranged axially symmetrically with respect to the vertical and horizontal axes of the cross between the memory blocks. It is desirable that

The seventh WJ shows a layout diagram of an embodiment of a semiconductor integrated circuit device using the memory group shown in FIG. 6 above.

The figure shows two columns and two columns, with the memory group as a unit.
Four memory groups are arranged in rows. In this case, the pad provided in the large cross-shaped area between the four memory groups is commonly used in adjacent memory blocks of the two memory groups that are axially symmetrical. This makes it possible to reduce the number of bonding bands. In this case, it is necessary to arrange each memory group axially symmetrically corresponding to the vertical axis and the horizontal axis that constitute the above-mentioned cross area. This is because the common bonding pad requires a corresponding internal circuit to be configured in close proximity thereto.

In a memory block, data is input and output from an input/output node, so it itself constitutes a closed circuit. Therefore, when a memory block with an independent memory function is made into a macro cell as in this embodiment, the corresponding bonding pads are configured to simply connect those to which the same signal is supplied using a LOC lead frame. It is something.

On the other hand, the control circuit C0N as shown in FIG.
T,2 adopts a configuration in which an input signal is logically processed by an internal logic circuit and output. Therefore, the input section, logic circuit section, and output section are arranged according to the signal flow. Therefore, instead of a memory block, a plurality of memory blocks as described above, their control circuits, and logic circuits such as a logic unit that generates data to be stored in a memory block are formed into macro cells to form one semiconductor integrated circuit. When constructing a device, the LOC lead frame can be used as part of the wiring connecting macro cells in the same manner as described above. That is, in this configuration, the LOC lead frame is provided with leads as internal wiring that are not connected to external terminals in addition to normal leads. That is, the lead frame as internal wiring is ultimately housed inside the puff cage and is cut off from the outside.For example, in a DRAM with the configuration shown in FIG.
The refresh address signal, block selection signal, etc. transmitted from the control circuit C0NT2 to each memory block may use a LOC lead frame instead of the internal signal bus CB. In order to differentiate the leads from other leads, it is desirable to have two layers of leads and use one of them as wiring for interconnecting the internal macrocells.By adopting such a configuration, lower power consumption and higher speeds can be achieved. It is possible to aim for That is, power consumption can be reduced by activating only the memory block in which the memory cell to be selected exists.

In this case, in order to perform high-speed access, it is necessary to transmit the block selection signal prior to the address signal supplied to each memory block. As described above, the block selection signal can be transmitted to each memory block at high speed by using the LOC lead frame instead of the internal bus, so it is possible to achieve lower power consumption and higher speed as described above. .

FIG. 8 shows a block diagram of one embodiment of one memory block and part of the in-chip common circuits to be converted into macro cells.

Memory array M-ARY has an X address of 2048,
The Y address is made up of 2048 and has a total storage capacity of about 4 Mbits. In the figure, the memory cell array is shown arranged as 2048x2048, but in reality, the length of the word lines and bit lines (data lines or digit lines) are shortened (in order to It is divided into memory mats.Memory cells are
As described later, it is composed of an address selection MO3FET and an information storage capacitor. The gate of the address selection MOS FET is connected to a word line extending vertically in the figure.

The drain, which is an input/output node of the address selection MOSFET, is connected to a bit line extending in the horizontal direction in the figure.

The word line is selected by a drive circuit based on a selection signal generated by an X decoder XDEC. The drive circuit has a relatively large current driving capability in order to rapidly drive a word line which has a relatively large load capacitance by connecting a large number of memory cells. The selection is made based on the selection signal formed by the decoder YDEC. That is, this Y decoder YDEC forms a selection signal that selects a column switch circuit that connects a bit line to a common input/output line.

The bit line is provided with a sense amplifier that amplifies the read signal of the memory cell. Dynamic memory cells are
When the address selection MOS FET is turned on and the capacitor is connected to the bit line, the storage charge in the storage capacitor is temporarily lost due to charge sharing with the parasitic capacitance of the bit line, but the amplified output of the sense amplifier mentioned above It can be recovered by accepting it as it is. The memory array M-ARY in the figure includes the above-described sense amplifiers and column switch circuits. In addition, the memory array M-ARY is also provided with a bit line precharge circuit and a word clear circuit provided at the end of the word line.

Among the address signals supplied from the outside, those input in synchronization with the row address strobe signal RAS are
It is taken into address buffer XAB. The output signal of the X address buffer XAB and the address signal generated by the refresh address generation circuit RC are selectively supplied to the X decoder XDEC via the multiplexer XMP.

In normal mode, the X address buffer XAB
The address signal taken in is supplied to the X decoder XDEC via the multiplexer XMP. In the refresh mode, the refresh address generation circuit RC
The address signal formed by the multiplexer XMP
The signal is supplied to the X decoder XDEC via the X decoder XDEC.

Among the address signals supplied from the outside, those input in synchronization with the column address strobe signal CAS are
It is taken into the Y address buffer YAB. The output signal of Y address buffer YAB is supplied to Y decoder YDEC.

Row address strobe signal RAS supplied externally
is supplied to the row-related timing circuit RTG. A column address strobe signal CAS supplied from the outside is supplied to a column system timing circuit CTG. The write enable signal WE supplied from the outside is supplied to the timing circuit WTG. These timing circuits R
Although timing signals formed by TG and CTG are omitted in the figure, the timing signals formed by the address buffers XAB,
It is supplied to YAB and used to take in an address signal.

The output signals of each of the timing circuits RTGSCTG and WTG are supplied to the control circuit C0NT, where an internal operation timing signal is formed according to the operation mode determined by the operation mode determination circuit RDC. In the figure, the paths of these timing signals are omitted.

The timing signals formed by the timing circuits RTG, CTG and WTG are sent to the operation mode determination circuit RDC.
is supplied to In this embodiment, in order to reduce power consumption in refresh mode, when the refresh mode is determined, in addition to switching the multiplexer XPM using the signal CBH, each column circuit
For example, Y address buffer YAB, Y decoder YDEC
.

Main amplifier MA and data input/output circuit 10B are rendered inactive. Also, as mentioned above, the X decoder
Since the address signal is supplied from the refresh address generation circuit RC to the X address buffer XAB, the X address buffer XAB is also rendered inactive.

That is, in an information processing system etc. in which the dynamic RAM of this embodiment is implemented, the dynamic RAM
When M is in refresh mode, when the processor sends an address signal onto the address bus to access other memory devices or peripheral devices, the input circuits of the address buffer respond to it, causing current consumption. This is prevented by the signal CBR.

In conventional dynamic RAM with a large storage capacity, memory is refreshed in sequence by operating a column system circuit to confirm the operation of the refresh 7 address counter circuit, and selecting bit lines when refresh is performed. The information stored in the cell is read out to the outside.

On the other hand, in the dynamic RAM of this embodiment, in order to reduce power consumption in the refresh mode, the above-mentioned peripheral circuits that are not related to the original refreshing operation are put into a non-operating state. be. This makes it possible to perform a simultaneous refresh operation on memory cells consisting of more bits in one refresh cycle.

For example, in the case of a large storage capacity of approximately 64 Mbits, if the conventional method is adopted as is, one refresh cycle will refresh approximately 8 bits of memory cells connected to the word line specified by the X address. It will cause the action to take place. With this configuration, it takes about 8 cycles to complete refresh for all memory cells in the RAM.

In this embodiment, in order to perform the refresh operation in about 4 cycles as in a dynamic RAM of about 16 Mbits, the current consumption in the peripheral circuits is reduced as described above, and the bit line charging by the sense amplifier is accordingly increased. By directing the discharge current, a large number of memory cells, such as about 16 bits, can be refreshed in one refresh operation.

In addition to dynamic RAM consisting of a plurality of memory blocks organized into macro cells as in the above embodiment, such a refresh method is also applicable to a conventional dynamic RAM in which the memory cell array is divided into mats appropriately. Needless to say, the present invention can be similarly applied to devices in which peripheral circuits such as decoders and address buffers are appropriately laid out.

FIG. 9 shows a block diagram of another embodiment of one memory block and a part of the chip common circuit to be converted into a macro cell.

In this embodiment, in addition to the block diagram of the embodiment shown in FIG. 8, a normal circuit and a power down circuit as described below are added to the row selection circuit.

Although the explanation is the same as that of the embodiment shown in FIG. 8, the circuit blocks in the same figure are as follows.

Although the memory array M-ARY is not particularly limited, the X address is 2048. The Y address consists of 2048, and the total storage capacity is about 4 Mbits. In the same figure, the memory cell array is shown arranged as 2048x2048, but in reality it is divided into multiple memory mats as appropriate to shorten the length of word lines and bit lines. It consists of

The word line is selected by a word line drive circuit based on a selection signal generated by an X decoder XDEC. This word line driving circuit drives a word line having a relatively large load capacitance by combining a large number of memory cells at high speed. The above bit line is Y
It is selected by the column switch circuit based on the selection signal generated by the decoder YDEC.

The bit line is provided with a sense amplifier that amplifies the read signal of the memory cell. Memory array M-ARY in the same figure
This includes the sense amplifier and column switch circuit as described above. In addition, memory array M-AR
Y is also provided with a bit line precharge circuit and a word clear circuit provided at the end of the word line.

Among the address signals supplied from the outside, those input in synchronization with the row address strobe signal RAS are
It is taken into address buffer XAB. In this embodiment, the output signal of the X address buffer XAB is supplied to the normal circuit in order to further power down and reduce peak current in the refresh mode. The address signal generated by the refresh address generation circuit RC is supplied to the power down circuit. A multiplexer XMP is provided at the output section of the normal circuit and the power down circuit, and the output is supplied to the X decoder XDEC according to its operation mode.

Among the address signals supplied from the outside, those input in synchronization with the column address strobe signal CAS are
It is taken into the Y address buffer YAB. The output signal of Y address buffer YAB is supplied to Y decoder XDEC.

Row address strobe signal RAS supplied externally
is supplied to the row-related timing circuit RTG. A column address strobe signal CAS supplied from the outside is supplied to a column system timing circuit CTG. The write enable signal WE supplied from the outside is supplied to the timing circuit WTG. These timing circuits R
Although timing signals formed by TG and CTG are omitted in the figure, the timing signals formed by the address buffers XAB,
It is supplied to YAB and used to take in an address signal.

The output signals of each of the timing circuits RTG, CTG, and WTG are supplied to the control circuit C0NT, where an internal operation timing signal is formed according to the operation mode determined by the RDC. In the figure, the paths of these timing signals are omitted.

The timing signals formed by the timing circuits RTG, CTG and WTG are sent to the operation mode determination circuit RDC.
supplied to In this embodiment, in order to reduce power consumption in the refresh mode, when the refresh mode is determined, the signal CBH is used to control the column system circuits, such as the Y address buffer YABSY decoder YDEC, main amplifier, etc., as described above. MA, data output circuit, and X address buffer XAB are made inactive.

Furthermore, the multiplexer XMP is switched as described above. This reduces current consumption for word line selection operations and sense amplifier amplification operations in refresh operations.

It also reduces peak currents during word line selection operations and sense amplifier amplification operations. That is, in the figure, the signal passed through the power down circuit is sent to the X decoder XDEC.
However, it should be understood that these power down circuits (including word line drive circuits) and normal circuits are actually configured integrally with the X decoder XDEC. That is, the power down circuit
In a decoder circuit, when an inverter circuit array is provided as a normal circuit in order to drive a relatively large capacitive load, a large drive current is passed through the output inverter circuit, etc. The inverter circuit is put into a non-operating state, and the capacitive load is driven by the inverter circuit that allows only a relatively small drive current to flow through the human power section. Further, the drive circuit that drives the word line at high speed is made inactive, and the word line is driven using a word line drive circuit that has only a relatively small drive capability. Therefore, the multiplexer XPM uses a clocked inverter circuit in addition to the logic gate circuit provided at the output section of the decoding section and the drive circuit, and utilizes a three-state output function including an output high-impedance state, and has the current drive capability described above. Numerous embodiments can be adopted, such as one in which switching is performed.

This makes it possible to reduce the current consumption of the selection circuit and sense amplifier drive circuit that are used to select the word line for the refresh operation, so the current consumption in the refresh mode is reduced, and the peak current value is also reduced accordingly. . In addition, by allocating this current reduction to the charging/discharging current of the bit line for refresh operation, 1
More memory cells can be refreshed in one refresh operation. In other words, the refresh operation can be completed in approximately 2 cycles.

Note that if the operating current of the X decoder and the word line drive current can be reduced as described above, the actual selection operation of the word line will be delayed accordingly. However, in the refresh mode of this embodiment, there is no need to output the stored information of the memory cell selected by refresh to the outside, and only the word line selection operation and the sense amplifier amplification operation are performed. Since the entire memory cycle period can be allocated to the word line selection operation and the sense amplifier amplification operation, there is no problem even if the power down circuit as described above is used.

In addition to dynamic RAM consisting of a plurality of memory blocks organized into macro cells as in the above embodiment, such a refresh method is also applicable to a conventional dynamic RAM in which the memory cell array is divided into mats appropriately. Needless to say, the present invention can be similarly applied to devices in which peripheral circuits such as decoders and address buffers are appropriately laid out.

FIG. 10 shows a schematic waveform diagram in the DRAM.

In normal mode, row address strobe signal RA
S becomes low level, and accordingly, a row-related address signal is taken in and a row-related selection operation is performed. In this case, a peak current flows during a word line selection operation or a sense amplifier operation.

On the other hand, in CBR mode (refresh mode), if you select, for example, four times as many word lines as in the normal mode, and perform the word line selection operation in a time-sharing manner to reduce the peak current, the current peak The value can be the same as the normal mode above.

In addition, if the word line selection operation and sense amplifier current are limited using the power-down circuit as described above, the peak current value will decrease even though four word lines and four corresponding sense amplifiers are operated. can be the same as the normal mode above. However, in any of the above refresh cases, the total current consumption remains approximately four times that in the normal mode.

FIG. 11 shows the dynamic type RA shown in FIG.
A block diagram for explaining one embodiment of address allocation of M is shown.

In this embodiment, although not particularly limited, in order to activate only one memory block formed into a macro cell in order to reduce power consumption, the upper 4 bits of the address signals X9 to X12 of the make use of,
In the figure, addresses as shown in binary numbers (0000 to 1111) are assigned. That is, for a total of 16 memory blocks arranged in a 4x4 arrangement, horizontal addresses are designated by XO and XIO, and vertical addresses are designated by Xll and X12.

Also, one memory block has 2048 memory blocks as described above.
It has a storage capacity of 2048 bits, so if 4 bits are used for the X address as described above, the address signal assigned to one memory block must be 9 bits from XO to Since only 11,512 addresses can be specified by the addresses X0 to x8, one memory block has a memory area divided into four, and one word line is selected in each area by the address signals X0 to X8. Therefore, four word lines are simultaneously specified in one entire memory block. As a result, a memory cell consisting of 2048×4 bits is selected by the row (X) system selection operation.

The four divided memory areas are selected by Y-system upper two bit address signals Yll and Y12.

That is, addresses are assigned in the order of binary numbers (00, 01, 10, and 11) starting from the left memory area of the memory block by designation using two bits of Y address signals Yll and Y12.

Then, using the remaining 11 bits of Y-based address signals YO to YIO, 1/2048th address is selected from one word line of one memory area in one memory block specified above. .

In this configuration, the row address strobe signal RAS and the column address strobe signal CAS are used to use the row address signal supplied earlier among the row address signals and column address signals supplied in time series. ,
Only one memory block formed into a macro cell as described above is activated. In this configuration, since only one memory block is activated, it is possible to reduce power consumption. Incidentally, when 2-bit X addresses and 2-bit Y addresses are assigned to memory blocks, it is necessary to activate four memory blocks in row-related selection operations. On the contrary,
When address assignment is performed as in this example, only one memory block is activated, so the current consumption in circuits such as address buffers and decoder circuits is reduced to approximately 17%.
This can be reduced to 4. Note that the number of sense amplifiers and the number of word lines are the same in the case of activating the four memory blocks described above and in the case of activating only one memory block as in this embodiment, so theoretically There is no reduction in current consumption in that part.

This figure explains address allocation, and it is important to note that the 2048 memory cells described above are not connected to one word line or bit line formed in an actual memory block. Please be careful. In other words, the word lines and bit lines formed in each macro cell memory block for high-speed operation etc. are divided into multiple memory mats as in the known dynamic RAM of about 4 Mbits. be. However, from the perspective of address selection operation, the above number of memory cells are selected for a specific address designation.

As shown above, the memory block address allocation is
In addition to the one that uses the row) system address signal, it is also possible to create a new Z system address signal.For the input of these two address signals, the WC
BR timing can be used. That is,
When changing the row address strobe signal RAS from a high level to a low level, both the column address strobe signal CAS and the write enable signal WE are set to a low level (.The address signal supplied at this timing is taken internally as a Z address, and the above Used as an address signal to specify a memory block.

When the WCBR is used in the counter test mode, etc., the write enable signal WE is set to low level during the precharge period when the row address strobe signal RAS is high level, and the address signal supplied at that time is set to the Z address signal. You can import it as . In addition, numerous embodiments can be adopted, such as one in which the Z address signal is supplied from the data terminal in synchronization with the change of the row address strobe signal RAS from high level to low level. By creating such a Z address signal, there is no need to divide one memory block into four memory areas as in the previous embodiment. Accordingly, in one memory block to be activated, the number of word lines to be selected and the number of sense amplifiers to be operated can be reduced, resulting in lower power consumption than when using the above-mentioned X address signal. become something that can be done.

FIG. 12 shows a block diagram for explaining one embodiment of the refresh operation of the dynamic RAM having the above configuration.

In this embodiment, in order to simplify the circuit, a refresh address counter RC is provided in common, and an address signal is supplied via a signal bus formed inside the chip. By adopting such a configuration, refresh-related circuits can be shared, and the circuit can be simplified. Since the refresh operation does not require high-speed access as described above, there is no problem in adopting a configuration in which address signals are supplied using an internal bus having a relatively long signal propagation delay time as described above.

In this embodiment, in order to reduce the number of refresh cycles, although not particularly limited, two bits of the X address specifying a memory block are degenerated. For example, if the upper 2 bits of the X address signals X11 and X12 are degenerated, the refresh as shown by the dotted line in the figure will occur in the four memory blocks specified by the lower 2 bits of the address signals X9 and XlO. will be held.

In one memory block, four word lines (2048x4) are refreshed as described above, so if four memory blocks are refreshed at the same time as in this embodiment, one refresh cycle will refresh 2048X4X4- Refreshing is performed in memory cells with 32,768 pins. Therefore, in a dynamic RAM of approximately 64 Mbits as in this embodiment, it takes 2048 cycles to complete refresh for all memory cells. Instead of this,
If the most significant bit of the address signal X12 of the refresh address signal formed by the refresh address counter circuit RC is degenerated, the refresh operation will be performed in two memory blocks at a time.
The number of refresh cycles is 4096 cycles. This is equal to the number of refresh cycles of a dynamic RAM that is currently being developed and has a storage capacity of approximately 16 Mbits.

In order to reduce the number of refresh cycles, it is sufficient to increase the number of memory blocks on which refresh operations are performed simultaneously. However, if the number of memory blocks to be refreshed simultaneously is increased in this way, the number of sense amplifiers operating will also increase accordingly, resulting in an increase in current consumption. Therefore, as mentioned above, during the refresh operation in each memory block, the column system selection circuit, data output circuit, and column system address buffer are made inactive, and as explained next, the X The current consumption in the memory block that is refreshed is reduced by using a power down circuit that reduces the drive current of the decoder and drive circuit.

Therefore, reducing current consumption in refresh operation and
The number of memory blocks to be activated in one refresh operation is selected in consideration of the increase in current due to the number of memory blocks refreshed simultaneously. In the case of 4×4 memory blocks as in this embodiment, the number of memory blocks to be refreshed simultaneously is 2, 4, 8, etc. as described above. Good too.

Further, in order to reduce the peak current during refresh operation, the memory blocks may be shifted from each other.

That is, in the block diagram of FIG. 12, when performing a refresh operation in the four memory blocks indicated by dotted lines in the same figure, from the memory block (1111) near the refresh address counter circuit RC to (I Q l
1), (Ol 11), and (0011), the refresh operation, particularly the word line drive and sense amplifier operation timings, are sequentially delayed with a time difference.

Such a time difference may utilize a signal propagation delay time of a refresh address signal supplied to each memory block through an internal bus.

Due to the above-mentioned deviation in the operation timing of the four memory blocks, the current consumption generated in the refresh operation can be averaged. This allows 2048X4 at the same time
The peak value of the current required to refresh (rewrite) x4 bits of memory cells at the same time is 1.
The peak value can be reduced to /4. As a result, noise generated in the internal power supply line can also be significantly reduced.

The refresh address counter circuit RC forms a memory block selection signal specifying a memory block to be refreshed, and supplies it and a refresh address signal to each memory block through the internal bus.

Instead of this configuration, the refresh address counter circuit may generate only a refresh address signal, and the memory block itself may have a decoder circuit for decoding the designation of the memory block.

There are no particular restrictions on specifying the refresh mode, but the CAS signal must be at low level at the timing when RAS falls from high level to low level (CA
S before RAS). In addition to the circuit built into the refresh address counter circuit RC, the circuit for determining the refresh mode is
It may be provided in each memory block. However, when the determination circuit is provided in each memory block, its determination output is made valid/invalid by a decoder output of a memory block selection signal or an equivalent address signal. Only in the valid memory block will a refresh address signal be taken in and a refresh operation performed in accordance with the refresh address signal. In addition, in the configuration in which a control circuit is provided as in the embodiment shown in FIG. 1, a common operation mode determination circuit as described above is provided.

FIG. 13 shows a specific circuit diagram of one embodiment of the power down circuit shown in FIG. 9.

On the normal circuit side, C whose driving capacity is increased in order
It is configured by cascading MOS inverter circuits. On the other hand, the power-down circuit side is composed of one CMOS inverter circuit with a small driving capacity.

A switching gate circuit is provided on the input side of both circuits, and a 3-state output circuit is provided on the output side, and each of the circuits is switched by a power down control circuit PDC.

In the 0M03 circuit, current consumption occurs during charge amplifier and discharge of the capacitive load when the output signal changes.

Therefore, in this configuration, in the refresh mode, the inverter circuits consisting of a large number of large current drive capacities are placed in a non-operating state, and only the inverter circuits with small current drive capacities are operated, so that a power-down operation can be performed. becomes.

Note that the loads in the figure are word lines and decoder circuits. Therefore, the input capacitance of the address buffer and the X decoder circuit becomes a load for the black and white CB as signal sources.

FIG. 14 shows a cross-sectional view of an element structure of an embodiment of a memory cell used in a dynamic RAM according to the present invention. This figure shows a cross-sectional view along the bit line direction.

In order to increase the storage capacity of a dynamic RAM, it is necessary to increase the density of the memory circuit itself, in addition to making each circuit block common as described above. That is, if the memory block shown in FIG. 3 is the same as a known dynamic RAM of about 4 Mbits, then in order to configure a dynamic RAM of about 64 Mbits as in this embodiment, the semiconductor chip The size of the dynamic RAM is about 16 times larger than that of a dynamic RAM semiconductor chip of about 4 Mbits. Even if it were possible to form such a large semiconductor chip, it would not result in an attractive product because the product yield would be significantly lowered and the package would be larger.

Therefore, it is necessary to form one memory block itself significantly smaller than a known dynamic RAM having an equivalent storage capacity.

Therefore, in this embodiment, the backing wiring for performing a word shunt, which is provided for the purpose of lowering the wiring resistance of the word line, which is one of the causes that hinder the miniaturization and higher density of memory cell arrays, is replaced with the backing wiring that performs the word shunt, which is one of the reasons that prevent the miniaturization and high density of memory cell arrays. It is not a single layer, but a two-layer structure, as in the case of For example, it is provided corresponding to the rightmost word vAWL1 made of a polysilicon layer formed integrally with the gate of the MOS FET for address selection. The word shunt wiring WL1'' is the 31st aluminum layer A.
Formed by L3. As the word shunt wiring WL 2' provided corresponding to the word line WL2 arranged adjacent to the left side of this word line WLI, the third
A second aluminum layer A is formed below the aluminum AL3 layer through a glabella insulating film.
Use L2. The third aluminum layer AL3 is used as the word shunt wiring WL3' provided corresponding to the word line WL3 arranged adjacent to the left side of the word line WL2.

Furthermore, the second layer of aluminum AL2 is used as the word shunt wiring 1WL4° provided corresponding to the word line WL4 arranged adjacent to the left side of the word line WL3.

In this way, by using metal layers of different layers for adjacent word shunt wirings with an interlayer insulating film interposed therebetween, there is no need for space for insulation between adjacent wiring layers. That is,
As shown in the figure, word shunt wiring can be formed at high density without providing any horizontal space. In the case of higher density, adjacent word shunt wiring may be partially overlapped with the glabella insulating film interposed therebetween.

In addition, in the same figure, the first layer of aluminum JiA
L1 is used to configure a bit line. This bit line may use silicide instead of the first aluminum layer ALI.

In this way, when silicide is used as the bit line, the word shunt wiring is formed by the first aluminum layer and the '2nd aluminum layer. Alternatively, the bit line is formed of silicide as described above,
The first metal layer as described above constitutes a column selection line extending in the same direction as the bit line, and the second and third metal layers are used as the word shunt wiring. In the configuration in which the column selection line extends above the memory cell array parallel to the bit line as described above, the Y decoder is commonly used for a plurality of memory mats. Therefore, in a configuration in which a Y address decoder is provided for each memory mat, it is possible to form column selection lines using the first metal layer or silicide.

FIG. 15 shows a pattern diagram of an embodiment of the connection portion between the word line and the word shunt wiring portion.

In the same figure, winter is indicated by a thick dashed line.
The word shunt wiring made of the second metal layer is indicated by a thick solid line, and the word shunt wiring made of the third metal layer is indicated by a thick solid line. The black opening is a through hole for swapping the word shunt wiring up and down. The shaded openings are word shunt contacts, and the word lines made of polysilicon shown by thin dotted lines are connected to the word shunt wiring. By using the wiring pattern as in this embodiment, a contact portion c between a word line made of a polysilicon layer and a word shunt metal layer provided thereon.

NT will be established. In addition, by using the word shunt sections provided at regular intervals to replace the upper and lower word shunt wiring, higher density can be achieved because the continuity of the pattern will not be lost at the contact section. .

FIG. 16 shows a schematic circuit diagram of an embodiment of a memory cell array according to the present invention. In the figure, 2
A bit line pair, a sense amplifier unit corresponding to the bit line pair, one column selection line arranged in parallel thereto, and four word lines are exemplarily shown.

In this example, the unit sense amplifiers USAI and USA
2 is a bit line pair BO exemplarily shown as a representative.
, BO, Bl, and Bl are arranged at one end side (the right end in the figure).

The sense amplifier USAi USA2 of the above unit is configured to be mutually visible, and is composed of a pair of CMOS inverter circuits in the form of a latch whose inputs and outputs are cross-connected, although this is not particularly limited.

When using a latch-type CMOS inverter circuit, if a relatively large pitch is required and this impedes the miniaturization of the bit line pitch as described later, the gate and drain may be cross-connected as a unit sense amplifier. Alternatively, a latch type N-channel MO3FET may be used.

In this configuration, the unit sense amplifier can be composed of only two N-channel MOS FETs, so the CM
The area occupied can be reduced compared to the case where an O3 circuit is used. However, when a latch-type N-channel MOS FET is used, the level of the bit line on the high level side decreases due to its amplification operation, so active restoration is required to restore it to the original high level. This requires a circuit.

In the same figure, two pairs of bit lines BO, BO and B1, B1
In between, a column selection line YS is arranged in parallel thereto, and word lines WLO to WL3, which are representatively shown, are arranged perpendicularly thereto. Bit line pair B arranged in parallel with the word lines WLO to WL3
One bit line BO, B of O, BO and Bl, Bl
MOSFE for address selection at the intersection with l or BO, Bl
A memory cell consisting of a T and an information storage capacitor is arranged. In other words, the address selection MOS
The gate of the FET is connected to the corresponding word line, and the drain, which is its input/output node, is connected to the corresponding bit line.

In this embodiment, in order to increase the density of the memory cell array, the wiring A layer for bit line pairs BO, BO, Bl, B1, etc. and the column selection line YS, which is formed to run parallel thereto, are formed using separate metal layers. Configure.

For example, when an aluminum layer is used as the first metal layer for the bit m-line pairs BO, BO and B, B1, etc., the column selection line YS is placed between the eyebrows on the first metal layer. An aluminum layer is used as a second metal layer formed with an insulating film interposed therebetween. In place of this configuration, when silicide is used for the bit line pairs BO, BO and B1, B1, etc., the first metal layer is used as the column selection line YS. In this embodiment, the term "metal layer" refers not only to the aluminum layer described above, but also to a metal wiring layer such as a tungsten layer.

Furthermore, instead of the above embodiment, the even-numbered bit lines BO, BO in the figure are made of the first metal layer (or silicide), and the odd-numbered bit lines Bl, Bl are made of the second layer. It may be a metal layer (or a first metal layer). In this configuration, two adjacent bit line pairs BO, BO and Bl, Bl are insulated by the glabella insulating film. Since it is a single wire, the space for both wirings can be shortened to zero. However, if this is done, the unbalance in the coupling noise between the bit line pairs becomes larger, so the known bit line method in which the bit line pairs are replaced at regular intervals to equalize the mutual coupling between the bit lines It is desirable to adopt the crossing method.

Column selection YS may be arranged so as to overlap bit line pair BO, BO and bit line pair B1, B1 at a constant interval using the two metal layers as described above.

For example, using the metal layer in which bit lines B and 81 are formed, bit lines BO and BO are formed by different metal layers.
The metal layer may be formed so as to overlap with the bit lines B and B1 by a certain length, and the metal layer may be formed so as to overlap with the bit lines B and B1 by the same length.

Furthermore, the wiring layers may be different between the bit line pairs BO and BO and between B1 and B1.
For example, to explain the bit lines BO and BO, bit *BO may be the first metal layer (or silicide), and bit line BO may be the second metal layer. In this configuration, bit line pair 80, 8
0 is insulated by an interlayer insulating film, the space between the two wirings can be shortened to zero (it is possible to shorten the space between the two wirings to zero. However, if an unbalance occurs in the parasitic capacitance of the bit line itself, the above bit line crossing By adopting this method, mutual coupling noise between bit lines can be reduced and the wiring capacitance thereof can be balanced.

Note that memory cells are connected to the above-mentioned focus lines, and the minimum pitch of the bit lines may be determined depending on the layout of the memory cells.

In this case, the other embodiments described above are employed to realize a high density memory cell array.

FIG. 17 shows a schematic circuit diagram of another embodiment of the memory cell array according to the present invention.

In the same figure, two bit line pairs BO, BO and B are shown in the same manner as above.
l, Bl and corresponding unit sense amplifier USA,
USA2, one column selection line YS arranged parallel to USA2, and 41 word lines WLO to WL3 arranged perpendicular to the bit lines and the like are exemplarily shown.

In this example, in order to increase the density of the memory cell array,
Unit sense amplifiers are arranged alternately at both ends of the bit lines.
For BO, there is a unit sense amplifier US on the right side.
Place AI. This bit line pair BO, a bit line pair Bl exemplarily shown as a representative of the remaining adjacent bit lines to BO.
.

For B1, there is a unit sense amplifier US on the left end side.
This is where A2 is placed. Although not shown in the figure, similarly, for even-numbered bit line pairs, the above-mentioned sense amplifier USAI is placed on the right side, and for odd-numbered bit pairs, the above-mentioned sense amplifier USAI is placed on the right side. Amplifier USA2
Place it on the left side like this.

In the figure, the two pairs of bits vABO, BO and B,
A column selection line YS is arranged between and parallel to B1, and word lines WLO to WL3, which are exemplarily shown as the above representative, are arranged perpendicularly thereto.

At the intersection of the word lines WLO to WL3 and one bit line BO, B1 or BO, Bl of the bit line pair BO, BO and B, Bl arranged in parallel, there is a MO3FET for address selection and an information A memory cell consisting of a storage capacitor is arranged.

The sense amplifiers USA1 and USA2 of the above unit are each configured with ml (Gj), and are composed of a pair of CMOS inverter circuits whose inputs and outputs are cross-connected, although this is not particularly limited. In order to rapidly amplify minute signals read from memory cells to bit lines, the element size is relatively large.Therefore, in order to configure these 0MO3 sense amplifiers, relatively large occupancy is required. Area is required.

Therefore, in the configuration in which the sense amplifier is provided at one end of the bit line, as in the above-mentioned embodiment and the conventional DRAM, even if it is possible to miniaturize the wiring width and the memory cell elements, the layout of the sense amplifier side Due to the constraints, there is a limit to the high integration of memory cell arrays. On the other hand, in the configuration in which unit sense amplifiers are alternately arranged at both ends of a bit line as in this embodiment, the unit sense amplifiers USA can be arranged using the pitch of two pairs of bit lines. This allows the pitch of the bit lines to be made as small as possible, making it possible to increase the density of the memory cell array.

In this case, in order to arrange the word lines at a high density, the backing wiring of the word lines is made of a two-layer metal layer as in the above embodiment, and the layers of the backing wiring of adjacent word lines are alternated. to be different. This makes it possible to increase the bit line density and word line density, thereby reducing the area occupied by the memory cell array.

If there is sufficient space for the word line backing wiring, the bit lines are formed into two layers. For example, the even-numbered bit lines BO,
BO may be the first metal layer (or silicide), and odd-numbered bit lines B and B1 may be the second metal layer. In this configuration, two bit pairs B
Since O, BO and Bl, B1 are insulated by the glabella insulating film, the rewiring space can be shortened to zero (as in the case of word lines, but if you do this, the bit line Since the unbalance in coupling noise between pairs becomes larger, a known bit line crossing method may be used in which bit line pairs are exchanged at regular intervals so that the mutual compression between bit lines becomes equal.

Although column selection YS is not particularly limited, bit line pairs BO are arranged at regular intervals using two metal layers.

It may be arranged so as to overlap with BO and bit line pair B, B1. For example, bit line Bl.

(2) A metal layer on which bit lines BO and BO are formed is formed so as to overlap by a certain length with bit lines BO and BO formed by different metal layers, and a metal layer on which bit lines BO and BO are formed by the same length. It is only necessary to switch to the bit lines Bl and form them so as to overlap with the bit lines Bl.

FIG. 18 shows a sectional view of an element structure of an embodiment in which bit lines are multilayered as in the above embodiment. This figure is a structural cross-sectional view along the direction of the word line.

The bit line BLI is made of the first aluminum layer as described above, and the bit line BL2 adjacent to it is made of the first aluminum layer.
It is composed of a second aluminum layer formed on the first aluminum layer with a glabella insulating film interposed therebetween. The word shunt wiring WL' is composed of a third aluminum layer formed with a glabella insulating film interposed between the second aluminum layer and the second aluminum layer.

Word line WL is MO3FE for memory cell address selection
It consists of a polysilicon layer formed integrally with the gate electrode of T. The word line WL and the word shunt wiring are connected to each other by a contact portion as shown in the pattern diagram.

FIG. 19A shows a schematic circuit diagram of an embodiment of the layout of word lines and their driving circuits in the memory cell array. In the figure, four word lines and corresponding drive circuits are exemplarily shown as representatives.

In the same figure, the word line 2 drawn with a dashed-dotted line is the backing wiring made of the second layer of aluminum as shown in the embodiment of FIG. 14, and the word line 1 drawn with a solid line consists of the third aluminum layer as described above. In this way, by alternately arranging the backing wiring of word lines adjacent to each other using two metal layers as described above, high-density packaging of word lines becomes possible.

FIG. 19B shows a schematic circuit diagram of another embodiment of the layout of word lines and their driving circuits in the memory cell array. In the figure, six word lines and their corresponding drive circuits are exemplarily shown.

In order to drive a word line, which has a large load capacity by combining a large number of memory cells, at high speed, the circuit size of a driver for driving the word line becomes relatively large.

As a result, even if the pitch of the word lines in the memory cell array is reduced as shown in FIG. 19A, drivers cannot be formed in accordance with the pinch.

Therefore, in this embodiment, the word drivers are arranged in two stages as shown in the figure, and the output line of the word driver farthest from the memory array is connected to the memory array using the word line 1 made of the third metal layer. It is formed to run above the word driver closer to the array. In this configuration, a selection/non-selection level is applied to the word line extending from the polysilicon layer to which the memory cell is connected via the word shunt backing wiring. With such a two-stage arrangement of word drivers, the pinch of the word driver can be substantially increased to twice the word line pitch. As a result, it is possible to layout a word driver that enables high-speed driving while achieving high-density packaging of word lines.

The word line consisting of two layers may have upper and lower layers interchanged as necessary.

Further, when the bit line is formed of silicide as described above, the backing wiring of the word line is formed by the first metal layer and the second metal layer. Note that when the scale of the word driver is increased to increase the speed, etc., and there is a margin for the backing wiring for the word shunt, it is not necessary to use the multilayer metal wiring layer as described above.

FIG. 20A shows a schematic circuit diagram of another embodiment of the layout of word lines and their driving circuits in the memory cell array. In the figure, six word lines and their corresponding drive circuits are exemplarily shown.

In the same figure, the word line drawn with a dashed line in the same way as before is the backing wiring made of the second layer of aluminum layer as shown in the embodiment of FIG. 14, and the word line drawn with a solid line consists of the third aluminum layer as described above. In this way, by alternately arranging the backing wiring of word lines adjacent to each other using two metal layers as described above, high-density packaging of word lines becomes possible.

In this embodiment, word drivers are arranged separately above and below a memory cell array (memory mat) in order to accommodate such a high-density word line pitch and arrange word drivers with large driving capacity. That is, word drivers corresponding to word lines made of the second metal layer are placed above the memory cell array, and word drivers corresponding to word lines made of the third metal layer are placed below the memory cell array. Placed. In other words, word drivers are arranged alternately at both ends of the word line. By doing so, the word driver pitch can be substantially increased to twice the word line pitch. As a result, it is possible to layout a word driver that enables high-speed driving while achieving high-density packaging of word lines. Note that, if necessary, the upper and lower layers of the word line may be swapped as described above. In addition, when the scale of the word driver increases to increase speed, etc., the word line backing wiring for the word shunt may be replaced. When there is a margin, it is not necessary to use a multilayer metal wiring layer as described above.

FIG. 20B shows a schematic circuit diagram of another embodiment of the layout of word lines and their driving circuits in the memory cell array. In the figure, 12 word lines and corresponding drive circuits are exemplarily shown as representatives.

In the same figure, the word line drawn with a dashed line in the same way as before is the backing wiring made of the second layer of aluminum layer as shown in the embodiment of FIG. 14, and the word line drawn with a solid line consists of the third aluminum layer as described above. In this way, by alternately arranging the backing wiring of word lines adjacent to each other using two metal layers as described above, high-density packaging of word lines becomes possible. In order to arrange drivers corresponding to such word lines arranged in high density, in this embodiment, the 19B
As shown in the figure, a two-stage structure is used at both ends of the memory cell array, one near the word line and one far from the word line. Note that, if necessary, the upper and lower layers of the word line may be interchanged as described above. Note that when the scale of the word driver is increased to increase speed, etc., and when there is a margin for the backing wiring for the word shunt, there is no particular need to use the multilayer metal wiring layer as described above.

FIG. 20C shows a schematic circuit diagram of another embodiment of the layout of word lines and their driving circuits in the memory cell array. In (A) of the same figure, drivers may be provided at both ends of one word line. In this case, one word line is driven by two word drivers from both ends, so the word line The driving capacity of one word driver provided at one end can be reduced by half. With such a layout, it is possible to layout word drivers that enable high-speed driving while achieving high-density packaging of word lines. Note that when the scale of the word driver is increased to increase speed, etc., and when there is a margin for the backing wiring for the word shunt, there is no particular need to use the multilayer metal wiring layer as described above. In FIG. 19B, one word line is used as a driver at both ends, and the word lines corresponding to adjacent word lines have a two-stage structure similar to the embodiment shown in FIG. 19B. Even with this configuration, it is possible to layout word drivers that enable high-speed driving while achieving high-density packaging of word lines. Note that when the scale of the word driver is increased to increase speed, etc., and when there is a margin for the backing wiring for the word shunt, it is not particularly necessary to use the multilayer metal wiring layer as described above.

In addition, in FIGS. 2A and 2B, if the operating timings of the drivers provided at both ends of one word line are shifted, there is a problem that direct current will flow. Therefore, the word lines may be separated at their midpoints. By adopting such a configuration, the load on the word line is reduced to 1/2 (thereby, the word line selection operation is the same as in the above case).

The multilayer structure of word lines and bit lines, and the configurations of word drive circuits and sense amplifiers explained with reference to FIGS. 14 to 20C can be applied to a large-scale semiconductor memory device of approximately 64 Mbits as in the embodiment described above. Needless to say, in addition to those used in the constituent memory blocks, the present invention can be similarly applied to semiconductor memory devices having a relatively small storage capacity, such as about 1M bits or about 4M bits, compared to the RAM of the above embodiment. Probably not.

FIG. 21 shows a schematic block diagram for explaining an embodiment of the semiconductor integrated circuit defect relief method according to the present invention.

In this embodiment, one semiconductor memory device is constructed using a two-chip mounting method. This two-chip mounting method uses two chips with defects and mounts them in one package to form one semiconductor memory device.

A conventional defect relief method is to provide a spare memory cell array in the memory cell array and switch memory access to the defective portion to the spare memory cell array. For this reason, a redundant address comparison circuit is provided. When a row system and a column system are prepared as a spare memory cell array, redundant address comparison circuits are provided for each.

The defect remedial method described above can only remediate defects within the limits of the number of redundant word lines and redundant bit lines in the spare memory cell array and the number of redundant address comparison circuits. If this occurs, it becomes impossible to repair and the chip is discarded as a defective chip.

This embodiment attempts to create substantially one good chip by combining two defective chips that could not be repaired by conventional defect repair methods. In other words, by using the multi-chip mounting technology described below, the two chips with defective parts as described above are housed in one package, and are treated as a single non-defective semiconductor memory device from the outside. This is to make it possible to do so.

The figure shows an example in which a memory chip CHIP 1 and a memory chip CHIP 2 are housed in one package. Both chips CHIPI, 2 each have a defect teaching function using a redundant circuit, and regardless of the defect relief, each memory array has a defect in the shaded area in the figure. However, both memory chips C
A chip is selected such that the addresses of the defective parts of HIPI, 2 do not overlap.

Although not particularly limited, instead of discarding defective chips with more defects than redundant circuits as in the conventional method, select and combine two chips from among them without using redundant circuits and whose defective parts do not overlap. . If the defective parts overlap, the redundant circuit of one memory chip is used to repair the defect.Even if all the redundant circuits provided in one chip are used as described above,
If overlapping defective parts still remain, the redundant circuit provided in the other chip is used to repair the defect. In this way, each redundant circuit of the two memory chips can be used to repair only the overlapping defective parts. By using this method, it is possible to repair most defective chips in which defects exist in the memory array portion.

Although not particularly limited, the memory chip CHIPI and the memory chip CHIP2 in the figure are operated in parallel. That is, reading/writing is performed in parallel to both memory chips. Both memory chips are provided with an address comparison circuit ACMP that detects memory access to the remaining defective part, and when an access to the defective address is detected, the detection signal DOE controls each output circuit DOB to output Set to high impedance state. As mentioned above, the defective parts of both memory chips do not overlap, so if a memory access is made to the defective part and the output of one memory chip is prohibited as described above, the other memory chip, which has been read normally, will A read signal from is output as an output signal Do. When reading from normal memory cells in both memory chips, the same signal DO is output from both output circuits DOB.

By using two memory chips with such defective parts, it is possible to create a device that looks the same as a fully operational product. This makes it possible to obtain semiconductor memory devices of good quality from memory chips that were conventionally discarded, thereby achieving the effect of increasing the substantial product yield.

In particular, as mentioned above, the dynamic type R with a focus of about 64M
Memory chips with large storage capacities, such as AM, are relatively thick (this means that the number of memory chips that can be formed from a single semiconductor wafer decreases, and as the chip size increases, Because more defects occur in
Although defect relief methods using redundant circuits such as those of the prior art have limitations in improving yield, by adopting the relief method of this embodiment, it is expected that yields will be significantly improved.

When two chips of memory are operated in parallel as in this embodiment, a parity check circuit may be provided to inhibit the operation of the output control circuit on the memory chip side where a parity error has occurred. This makes it possible to repair not only the hard errors described above but also soft errors, so that a highly reliable semiconductor memory device can be obtained.

FIG. 22 shows a schematic block diagram for explaining another embodiment of the method for relieving defects in semiconductor integrated circuits according to the present invention.

In the above defect relief method, two memory chips C) 11P
Since I and 2 are operated in parallel, current consumption increases accordingly. Also, one memory chip CHI
If there is a memory access to a defective part in PI or C)IIP2, the output of the output control circuit becomes a high impedance state and the output current is halved. Conversely, when reading data from both memory chips CHIP,2 in parallel, the output current is from one memory chip CHIP,2.
It is twice as large as when there is a defect in PI or CHIP2. A problem arises in that the output current changes between memory accesses to addresses for which defect relief has been performed and addresses for which defect relief has not been performed.

In this embodiment, a priority determination circuit RDC2 is provided in the memory chip CHIPI. This priority determination circuit RDC2 yields priority to the other memory chip CHIP when it detects memory access to a defective portion as described above.

For example, if the memory chip CHIPI is set to be given priority by bonding or the like, when a memory access occurs, the row-related address circuits of both chips become operational. In this case, although not particularly limited, the memory chips CHI P l and 2 are used until address input and address comparison operations.
Both are done in parallel. In this address comparison operation, the memory chip CHIPI to which priority is given
If the access is not to a defective portion, the memory chip has priority and continues the subsequent memory access operation, and the other memory chip CHIP2 immediately becomes inactive in response to its output signal φR2. In this address comparison operation, if the access is to a defective part in the memory chip CHIPI to which priority has been given, the signal φR2 is generated, and the priority is transferred from the memory chip CHIP1 to the memory chip CHIP2.
The subsequent memory access operation continues, and the one memory chip CHIPI which has lost the above-mentioned priority is immediately brought into a non-operating state by the signal φR1.

In dynamic RAM, when a word line is selected, the storage charge held in the capacitor is lost due to charge sharing with the bit line charge, so it is necessary to rewrite using the amplified output of the sense amplifier. There is. Therefore, it is important to perform the above-mentioned address comparison operation and priority determination accordingly before the word lines of both memory chips C) (lPl and CHIP2 rise).

Therefore, the address buffer and address comparison operations described above are performed in parallel on both chips, resulting in low power consumption. In other words, in a dynamic RAM, selection of the word line with the highest current consumption, sense amplifier amplification, etc. are performed only in one memory chip, so the current consumption of a fully functioning product consisting of one memory chip is can be made the same. In this configuration, although two memory chips are provided unlike the previous embodiment, only the data output circuit of one memory chip is always in operation, so the output current does not change.

Address multiplex type RAM where X-system address signals and Y-system address signals are input in chronological order.
In this case, 2
When controlling the operation of one memory chip, it is limited to cases where a defect remains only in the X system. That is,
If it is determined for the first time by Y-system address comparison that the access is to a defective part, the word line and sense amplifier start operating, so this method cannot be applied.

Therefore, when it is necessary to perform Y-system address comparison in this manner, the operation of the memory chip that is rendered inactive is stopped from the column selection operation or the main amplifier selection operation. In this case, since only the output sofa of one memory chip operates at any time, the output current does not change.

In a DRAM in which X-system and Y-system address signals are supplied in parallel from independent terminals, the defect relief method described above can be employed regardless of the defective addresses of the X and Y systems.

As described above, the defect relief method sets priority to one memory chip and enables the operation of the other memory chip when memory access is performed to a defective part of that memory chip. The current consumption will be different depending on whether there is a defective part in the Y system or if there is a defective part in the Y system. Therefore, it is only necessary to treat them as different types depending on the location of the defect.

In the system of accessing only the macrocell memory block having address allocation as shown in the embodiment of FIG. 11, an X-based address signal is used as an address signal for specifying a memory block. therefore,
For each memory block, two memory chips whose defects do not overlap with each other are combined, and the defect relief method of this embodiment is applied to register the address of the memory block in which the defect exists. In this way, the above-mentioned priority can always be passed by comparing the addresses of the X system, so that power consumption can be reduced regardless of the defect location.

The address registration (program) for the above defective part is as follows:
Although not particularly limited, the same means as the address registration circuit used in the redundant address comparison circuit can be used, such as selectively irradiating a laser beam or the like to cut the fuse means made of a polysilicon layer or the like.

By using two memory chips with defective parts such as these, it is possible to create a device that has the same external appearance as a fully operational product, as described above. As a result, good quality semiconductor memory devices can be obtained from memory chips that were conventionally discarded, so that the actual product yield can be increased. especially,
As mentioned above, memory chips with large storage capacities such as approximately 64 Mbit dynamic RAM are relatively large in size, and the number of memory chips that can be formed from one semiconductor wafer is reduced. As the size increases, the number of defects inevitably increases, so there is a limit to the improvement in yield with conventional defect relief methods that use redundant circuits, but with the defect relief method of this embodiment, redundant circuits Rather than repairing all defects, it is sufficient to repair defects by leaving only the defects, so a significant improvement in yield can be expected.

FIG. 23 shows a schematic block diagram for explaining another embodiment of the method for relieving defects in semiconductor integrated circuits according to the present invention.

The defect relief method shown in FIG. 22 requires a priority determination circuit, which increases the circuit scale accordingly.

In this embodiment, one of the two memory chips CHIP, 2 has a defect (F
A I L), and the other memory chip CHIP2 has a defect (FAIL) in the left half area of the memory array as indicated by diagonal lines in the same figure, so that defect relief is performed using each redundant circuit. . In other words, in one memory chip CHI P 1, defects are repaired only in the left half using the redundancy circuit provided therein, and defects existing in the right half are ignored. On the other hand, in the other memory chip CHIP2, defect relief is performed only on the right half using the redundant circuit provided therein, and the defect existing on the left half is ignored.

From this, regarding memory chips with defects,
The number of defects in each of the left and right halves is checked and defect relief is performed for the area with fewer defects.

For example, the address of the most significant bit of the X system is selected as the address that divides the memory area to be divided into two. By using this address signal as a chip selection signal for the memory chips 1 and 2, memory access can be performed only to the memory chip CHIP 1 or CHIP2.

In this case, since a priority determination circuit and the like are not required, the circuit can be simplified and the control can be simplified compared to the embodiment shown in FIG. 2L.

When a memory array is divided into halves as described above, defects may be concentrated on the right or left side depending on a certain manufacturing loft. In such a case, the number of memory chips that use the left or right side increases, and it may not be possible to combine the two memory chips.

Therefore, each memory chip is provided with a function of inverting the address selectively inputted by the fuse means. As a result, the chip selection address for one of the two memory chips using physically the same right (or left) half is inverted by cutting the fuse. Thereby, this memory chip can be used as a memory chip that equivalently makes use of the left (or right) half, which is the opposite area to the above-mentioned physical area. As a result, one semiconductor memory device using a pair of equivalent left and right half areas can be obtained.

In the system of accessing only the macrocell memory block having address allocation as shown in the embodiment of FIG. 11, an X-based address signal is used as an address signal for specifying a memory block. therefore,
For each memory block, two memory chips that make use of 8 out of 16 chips are combined, and the defect relief method of this embodiment is applied to register the address of the memory block in which no defects exist. The chip may be activated by accessing the address.

In this case, the number of focuses of the addresses divided into eight memory blocks as described above can be set to 3 bits or 2 bits, in addition to all 4 bits. If it is set to 1 bit, it becomes substantially equivalent to the above embodiment.

Furthermore, in the case of a RAM system in which X-system and Y-system address signals are supplied in parallel, the Y-system address signal can also be used as the address signal for dividing memory areas.

By using two memory chips that still have such defective parts, it is possible to create a device that has the same external appearance as a fully operational product, as described above. As a result, good quality semiconductor memory devices can be obtained from memory chips that were conventionally discarded, so that the actual product yield can be increased.

In particular, as mentioned above, about 64 Mbit dynamic type R
Memory chips with large storage capacities, such as AM, are relatively large in size, and the number of memory chips that can be formed from one semiconductor wafer is reduced, and as the chip size increases, defects inevitably occur. Because it occurs more frequently,
Although there is a limit to the improvement in yield with conventional defect relief methods that use redundant circuits, the defect relief method of this embodiment does not use redundant circuits to relieve all defects, but only defects that remain and are repaired. Since it is only necessary to carry out this process, a significant improvement in yield can be expected.

In Fig. 24, for the main memory consisting of multiple chips,
Although not particularly limited, two spare memories are provided.

These are supplied with address signals and control signals in parallel, and I10 selectors are provided for input/output lines. This I10 selector is switched by switching information stored in a PROM (programmable ROM) that stores defective addresses, although this is not particularly limited. The RAM chip constituting the main memory has a defective bit. The condition is that the number of defective bits at the same address is within the number of spare memories. As a result, among data consisting of multiple bits written/read from multiple main memories, if up to 2 bits are defective, the spare memory is accessed according to the defective address switching information stored in FROM. . The RAM chip, spare memory, FROM, and I10 selector described above may be packaged as one module, or may be configured on a mounting board.

By using the spare memory and creating conditions in which the defective portion is not accessed as described above, it is possible to treat a RAM chip having a defective bit as an apparently good product.

FIG. 25 shows a block diagram of an embodiment of the defect relief method using the majority decision method.

In this embodiment, three memory chips CI (IP) are used.Address signals and control signals are supplied to the three memory chips CHIPI to 3 in parallel. output through the circuit.

Each of the three memory areas CHI P 1 to CHI P 3 is selected so that the defective parts do not overlap with each other. In other words, the defective addresses to be relieved by the redundant circuits of each memory chip CHIP 3 are to be relieved so that the defective parts do not overlap. With this configuration, even if a soft error occurs in one chip at a portion other than the defective address, it has an automatic correction function.

The defect relief method based on majority vote in this embodiment may be applied to one dynamic RAM. For example, if the storage capacity is approximately 64 Mbits as in this embodiment, it is divided into four areas, redundant circuits are used to repair defects so that defects do not overlap in three of the memory areas, and the 3-bit signal is processed by majority logic. Make it output through the circuit. By adopting such a configuration, it can be used as an approximately 16 Mbit RAM.

Even in this case, even if a soft error occurs in one of the bits, it can be repaired if the remaining other bits are read correctly, so there is an advantage that reliability can be increased.

The defect relief method described above is applicable not only to large-scale semiconductor memory devices such as approximately 16 Mbits and approximately 64 Mbits as described above, but also to semiconductor memories with relatively small storage capacities such as approximately 4 Mbits and approximately 1 Mbits. It goes without saying that the invention can be similarly applied to devices.

FIG. 26 shows a plan view and a corresponding cross-sectional view for explaining an embodiment of a stacked multi-chip package used in the defect relief method as described above. FIG. 27 shows an enlarged perspective view thereof.

As is clear from the figure, a plurality of semiconductor chips are stacked and mounted using a lead frame as a base with film-like spacers interposed therebetween. By using such multi-chip packaging technology, one semiconductor memory device can be obtained without changing its external dimensions.

The effects obtained from the above examples are as follows. That is, (1) A large-scale semiconductor memory circuit is constructed by forming a circuit block including a memory array, its address selection circuit, and an input/output circuit for reading/writing to/from memory cells into macro cells. This configuration has the effect that the design layout and control of a large-scale semiconductor memory device can be easily simplified by combining macro cells.

(2) The semiconductor memory device includes a memory circuit including a plurality of the macrocells, a selection signal for selecting one of the plurality of macrocells, and a control system for generating main timing signals necessary for its operation. It consists of a circuit. In this configuration, since each control circuit can be used in common, the macro cell circuit can be made smaller, and the overall circuit scale can be made smaller.

(3) The above control circuit includes an address control circuit that distributes an address signal that specifies a memory cell in a macro cell and an address signal that specifies the macro cell itself, and a refresh that is commonly used for a plurality of macro cells. It is an address counter circuit.

This makes it possible to simplify the memory circuit made up of macro cells, resulting in the effect that the overall circuit scale can be reduced.

(4) A macro cell consisting of a plurality of cells having a specific circuit function is provided, and a bonding pad for signals input from the outside is provided close to the corresponding macro cell, and the bonding pad has an L extending to the vicinity thereof.
Bonding is performed using the OC lead and coated wire.

This configuration has the advantage that signals to be supplied from the outside to each macrocell can be transmitted at high speed.

(5) The layout of a large-scale semiconductor memory device can be simplified by making the macrocell, which is provided with bonding pads and LOC leads, as described above, consisting of each circuit that itself constitutes one semiconductor memory circuit. This has the effect of making it possible to increase speed and speed.

(6) By using the above LOC lead as part of the wiring that connects bonding pads that supply the same signal provided corresponding to multiple macro cells, it is possible to speed up the operation of large-scale integrated circuits. You can get the effect of

(7) By using the LOC lead as part of the signal wiring transmitted between multiple macrocells,
This has the effect of making it possible to speed up the operation.

(8) By multilayering the backing wiring of the word lines arranged side by side on the same plane in the memory array, and by making the backing wiring used for the adjacent word lines different from each other, the word line The effect is that a substantially high-density layout becomes possible.

(9) The above-mentioned backing wiring is made up of two metal wiring layers, and by exchanging the upper and lower layers at the word shunt section, it is possible to eliminate imbalances in wiring capacitance and coupling. .

(10) By multi-layering the bit lines arranged in the memory array and using the adjacent bit lines as wiring in different layers, it is possible to realize a high-density layout of the bit lines.

(11) A high-density bit line layout is achieved by forming the above bit lines using two metal wiring layers and arranging adjacent bit lines in each sense amplifier so that they are alternately placed in the upper and lower layers. You can get the effect that you can.

(12) By configuring the above-mentioned bit lines as a pair of complementary bit lines arranged in parallel using upper and lower layer wiring for every other line, it is possible to achieve the effect of realizing a high-density bit line layout. .

(13) By exchanging the upper and lower layers of the two-layered bit lines in the middle, it is possible to eliminate the unbalance of the bit line capacitance and coupling noise.

(14) Backing wirings corresponding to adjacent word lines are alternately arranged using two layers of metal wiring, and drivers are arranged to drive the word lines from both ends of the word lines. In this configuration, since the driving capacity of the driver can be reduced by half, it is possible to achieve the effect of high-density packaging of word lines and correspondingly arrangement of drivers with substantially increased driving capacity.

(15) Backing wiring corresponding to adjacent word lines is arranged alternately using two layers of metal wiring, and an odd word line driver is arranged at one end of the word line, and an even number is placed at the other end of the word line. By arranging a word line driver, the word line pinch seen from the driver side can be doubled, which has the effect of allowing high density packaging of word lines and the placement of drivers with a correspondingly large driving capacity. can get.

(16) Backing wiring corresponding to adjacent word lines is arranged alternately using two layers of metal wiring, and a driving circuit for driving the backing wiring is arranged near the word line,
By using a two-stage configuration with one placed far away and using the upper layer metal wiring as the output line of the drive circuit placed far away, the word line pitch seen from the driver side can be doubled. The advantage is that the lines can be mounted at a high density and drivers with correspondingly large driving capacities can be arranged.

(17) By arranging a sense amplifier corresponding to one end of an odd-numbered bit line among a plurality of bit line pairs and arranging a corresponding sense amplifier at the other end of an even-numbered bit line, the sense amplifier can be This has the effect of increasing the amplification factor and realizing a high-density bit line layout.

(18) By alternately arranging the odd-numbered bit line pairs and the even-numbered bit pairs using two metal wiring layers, it is possible to achieve a high-density layout of the bit lines.

(19) By configuring the backing wiring of the word line arranged orthogonally to the bit line with two layers of metal wiring,
The effect is that a high-density layout of the memory cell array becomes possible.

(20) In normal mode, drive the bit lines and word lines that you want to access, as well as the sense amplifier rows, and in refresh mode, switch the number of simultaneously selected word lines and sense amplifier rows to be an integer multiple of the number in the normal mode. , it is possible to achieve the effects of lower power consumption and a reduction in the number of refresh cycles.

(21) A semiconductor memory circuit in which macrocells are circuit blocks including a memory array, its address selection circuit, and an input/output circuit that reads/writes to the memory cells, and in the refresh mode, the semiconductor memory circuit formed into macrocells By deactivating the column-related circuits, it is possible to reduce current consumption in refresh operations.

(22) Counter test mode uses a set/reset method different from the refresh mode described above, and the column system circuit is activated and read data is output only in counter test mode, thereby reducing low power consumption during refresh operation. The effect is that the counter operation can be tested while reducing power consumption.

(23) A semiconductor memory circuit in which a macrocell is a circuit block including a memory array, its address selection circuit, and an input/output circuit that reads/writes to the memory cells, and drives word lines for normal mode in refresh mode. The effect of reducing current consumption and peak current in the refresh mode is that the circuit is rendered inactive and the word line selection operation is performed by a circuit with a small drive capacity that receives a selection signal from its input section. can get.

(24) A semiconductor memory circuit is provided in which a macrocell is a circuit block including a memory array, its address selection circuit, and an input/output circuit that reads/writes to the memory cell, and the sense amplifier current is set to normal mode when in refresh mode. By providing the function of reducing the size compared to the current size, it is possible to reduce the current consumption and peak current in the refresh mode.

(25) A semiconductor memory circuit is provided in which a macro cell is a circuit block including a memory array, its address selection circuit, and an input/output circuit that reads/writes to the memory cell, and the word line selection operation time is shorter than that of a normal cycle. Or, by providing the sense amplifier with a function of increasing the amplification time, it is possible to reduce current consumption in the refresh mode.

(26) A semiconductor memory circuit is provided in which a circuit block including a memory array, its address selection circuit, and an input/output circuit that reads/writes to/from memory cells is used as a macrocell, and the peak currents of the sense amplifiers are shifted from each other. By refreshing a plurality of macro cells with a time difference, it is possible to reduce the peak current of the power supply in the refresh mode.

(27) A semiconductor memory circuit in which a circuit block including a memory array, its address selection circuit, and an input/output circuit that reads/writes to/from memory cells is used as a macrocell, and in normal mode, one or more macrocells are used. By activating a plurality of circuit blocks and activating an integer multiple of circuit blocks in refresh mode as in normal mode, it is possible to achieve the effect of lowering power consumption and reducing the number of refresh cycles.

(28) In a memory array that constitutes a semiconductor storage circuit, two memory chips whose defective parts do not overlap each other are housed in one package, and only the good parts of the two memory chips are accessed. This has the effect that working products can be obtained from defective chips that were conventionally discarded.

(29) The memory arrays of the two memory chips mentioned above are each divided into two memory areas by the address of a specific bit consisting of one or more, and the address signal specifying each memory area indicates that there is no defective chip among the two chips. By selectively accessing a chip having one memory area, it is possible to repair a defective chip without increasing current consumption.

(30) Among the two memory chips, priority is assigned to one of the memory chips, and when a defective part of one of the memory chips is accessed, the other memory chip is switched to be accessed. It is possible to obtain the effect that a defective chip can be repaired without increasing the current consumption unlike that for chips.

(31) The above two memory chips are both kept in an active state until the address determination before the word line selection operation is started, and the operation of the memory chip that is not accessed according to the address determination is immediately stopped. As a result, it is possible to prevent an increase in current consumption while saving a defective chip.

(32) The above memory chip is equipped with a defect relief circuit based on a redundant circuit system, and the defect relief circuit is used to create a fixed memory area free of defects, so that the redundant circuit can be used efficiently. effect'
is obtained.

(33) Three or more memory chips that are made free of defects at the same address, or one memory chip that has a memory block divided into three or more parts, are housed in one package, and those memory chips or By performing memory access to the memory blocks in parallel and outputting the read signal through the majority logic circuit, it is possible to achieve the effect that defects can be repaired using a defective chip.

(34) By preparing a spare memory chip for the main memory chip that stores data consisting of multiple bits, and when an access to a defective bit in the main memory chip is detected, the spare memory chip is accessed instead. , an effect can be obtained in that defect relief can be performed using a memory chip in which defective bits exist.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, instead of using the address multiplex method in which row-related address signals and column-related address signals are input in chronological order as in the above embodiment, a dynamic RAM configured as a macro cell uses a row-related address signal and a column-related address signal. In such a non-address multiplex system, a chip select signal or a chip enable signal is used instead of the address strobe signal, and the chip select signal or the chip enable signal is used in place of the address strobe signal. Various timing generation circuits are provided. Alternatively, the storage capacity of one memory block may be approximately 1M bits, and 4x4 blocks may be arranged to obtain a semiconductor memory device of approximately 16M bits.
A semiconductor memory device having a storage capacity of 32 M bits may be obtained by combining 8 M bits or the like. In this way, the combination of the storage capacity of one memory block and the total storage capacity can take various embodiments.

One memory block includes dynamic RAM,
Static RAM + EEPROM or EFRO
Programmable ROM (read-only) like M
(memory) or a combination of the above dynamic RAM and static RAM. That is, the static type memory described above may be used as a cache memory section. In this way, the memory block can take various embodiments.

The defect relief method may be applied to a plurality of semiconductor integrated circuit devices configured on a mounting board such as a printed circuit board, in addition to the one packaged as described above.

In addition to the above-mentioned large-scale semiconductor storage device, the present invention can also be used as a macrocell circuit block, such as a memory circuit, a microprocessor, and its peripheral circuits, such as a high-performance, multifunctional one-chip microcomputer, etc. It may constitute various semiconductor integrated circuit devices such as.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, a circuit block including a memory array, its address selection circuit, and an input/output circuit that reads/writes to the memory cell is converted into a macrocell, and a selection signal for selecting one of the plurality of macrocells and a selection signal for its operation are provided. By providing control circuitry to generate the necessary key timing signals, large scale storage devices can be obtained. It is equipped with a plurality of macrocells with specific circuit functions, and bonding pads for externally input signals are provided close to the corresponding macrocells, and the bonding band has an L that extends to the vicinity.
By bonding the OC lead and the coated wire, it is possible to speed up the transmission of signals to be supplied from the outside to each macro cell, and the LOC lead can be connected to a bonding pad that supplies the same signal and is provided corresponding to a plurality of macro cells. By using it also as part of the wiring connecting between the two, it becomes possible to speed up the operation of large-scale integrated circuits. Multi-layering the backing wiring of word lines arranged side by side on the same plane in a memory array, making the backing wiring used for the adjacent word lines wires in different layers, or exchanging the upper and lower layers at the word shunt part. By doing so, it is possible to increase the density of word lines and eliminate imbalances in wiring capacitance and coupling. A high-density bit line layout can be realized by multilayering the bit lines arranged in the memory array and configuring every other sense amplifier or bit line using upper and lower layer wiring. Then, by switching the bit line up and down midway, it is possible to eliminate the unbalance of the bit line capacitance and coupling noise. A word line driver is placed at both ends of a word line and driven from both ends of the word line, and an odd word line driver is placed at one end of a word line consisting of a plurality of word lines, and an odd word line driver is placed at the other end of the word line. By arranging drivers for even word lines, high-speed word line driving and high-density layout can be realized. Of the multiple bit line pairs,
By placing a corresponding sense amplifier at one end of the odd-numbered bit line and placing a corresponding sense amplifier at the other end of the even-numbered bit line, the amplification factor of the sense amplifier can be increased (and the bit line height can be increased). A density layout can be realized.The above odd bit line pairs and even bit line pairs are
The alternating arrangement of the metal wiring layers enables a high-density layout of the bit lines. In normal mode, the bit lines and word lines to be accessed and sense amplifier rows are driven, and in refresh mode, the number of word lines and sense amplifier rows to be simultaneously selected and operating sense amplifier rows is switched to an integer multiple of the number in normal mode, which reduces power consumption. The number of power consumption and refresh cycles can be reduced. In addition, in the refresh, the current consumption of the refresh operation can be reduced by inactivating the column circuit of the semiconductor memory circuit formed into a macro cell, and the counter test mode is set using a set/reset method different from the refresh mode. By activating the column-related circuit and outputting read data, it is possible to test the counter operation while reducing power consumption in the refresh operation. In the above refresh mode, the word line drive circuit is rendered inactive, and the word line selection operation is performed by a circuit with a small drive capacity that receives the selection signal of the input section, and the sense amplifier current is compared with that in the normal mode. The word line selection operation time and/or the sense amplifier amplification time should be made longer than the normal cycle, and the time difference should be given to multiple macro cells so that the peak currents of the sense amplifiers are shifted from each other. By performing refresh with refresh mode, current consumption in refresh mode can be reduced, and the number of memory cells to be refreshed at one time can be increased accordingly.In normal mode, one or more circuit blocks configured as macro cells can be refreshed. By activating the circuit blocks in the refresh mode and activating the number of circuit blocks that is an integer multiple of the number in the normal mode, it is possible to reduce power consumption and the number of refresh cycles. By putting two memory chips that have been processed into one package and accessing only the non-defective part of the two memory chips, it is possible to obtain a working product from the defective chip that was conventionally discarded. The memory arrays of the two memory chips are each divided into two memory areas based on the address of a specific bit consisting of one or more memory areas, and the memory area of the one of the two chips with no defects is divided by the address signal specifying each memory area. By selectively accessing a chip with a memory chip that has When a defective part is accessed, by switching to access the other memory chip, the defective chip can be repaired without increasing the current consumption as it would for two chips. A redundant circuit can be used efficiently by providing a defect relief circuit and using the defect relief circuit to create a fixed memory area free of defects.

[Brief explanation of drawings]

FIG. 1 is a basic block diagram showing an embodiment of a dynamic RAM with approximately 64 M pinpoints to which the present invention is applied. FIG. 2 is a block diagram showing another embodiment of the dynamic RAM according to the present invention. 3 is a basic layout diagram showing an example of the arrangement of circuit blocks and corresponding bonding pads in a semiconductor integrated circuit device to which the present invention is applied, and FIG. The basic layout diagram and the corresponding pattern diagram of one embodiment of the LOC lead, Figures 5A to 5C, show the above semiconductor chip and the L
FIG. 6 is a schematic pattern diagram showing another embodiment of the OG IJ-card; FIG. 6 is a bonding band layout diagram showing another embodiment of the macro cell memory block according to the present invention; FIG. , a basic layout diagram showing an embodiment of a semiconductor integrated circuit device using the memory group shown in FIG. 7, FIG. 8 is a block diagram showing an embodiment of one memory block to be converted into a macro cell, FIG. 9 is a block diagram showing another embodiment of one memory block to be made into a macro cell, FIG. 10 is a schematic waveform diagram for explaining the refresh operation, and FIG. FIG. 12 is a block diagram for explaining one embodiment of the address allocation of the RAM according to the embodiment; FIG. 12 is a block diagram for explaining one embodiment of the refresh operation of the dynamic RAM according to the present invention; FIG. , a specific circuit diagram showing one embodiment of the power down circuit shown in FIG. 9, FIG. FIG. 15 is a pattern diagram showing an embodiment of the connection between the word line and the word shunt wiring section, FIG. 16 is a schematic circuit diagram showing an embodiment of the memory cell array according to the present invention, and FIG. , a schematic circuit diagram showing another embodiment of the memory cell array according to the present invention, FIG. 18 is a cross-sectional view of an element structure showing another embodiment of the memory cell, and FIG. 19A is a memory cell array according to the present invention. FIG. 19B is a layout diagram showing another embodiment of the word line and its driver in the memory cell array according to the present invention; FIG. 20A is a layout diagram showing another embodiment of the word line and its driver in the memory cell array according to the present invention; 20B is a layout diagram showing another embodiment of the word line and its driver in the memory cell array according to the present invention. FIG. 20B is a layout diagram showing another embodiment of the word line and its driver in the memory cell array according to the present invention. FIG. 20C is a layout diagram showing another embodiment of the word line and its driver in a memory cell array according to the present invention, and FIG. 21 is a schematic block diagram for explaining an embodiment of the defect relief method according to the present invention. 22 is a schematic block diagram for explaining another embodiment of the defect relief method according to the present invention, and FIG. 23 is a schematic block diagram for explaining another embodiment of the defect relief method according to the present invention. FIG. 24 is a schematic block diagram for explaining still another embodiment of the defect relief method according to the present invention, and FIG. 25 is a schematic block diagram for explaining still another embodiment of the defect relief method according to the present invention. FIG. 26 is a schematic block diagram for explaining one embodiment, FIG. 26 is a plan view showing one embodiment of a stacked multi-package, and FIG. 27 is an enlarged perspective view thereof. ADC: Address control circuit, RPTG: Row pretiming generation circuit, CPTO: Column pretiming generation circuit, WPTG: Pretiming generation circuit, RDC: Operation mode determination circuit, C0NTL,
C0NT2...Control circuit, XB...X address bus, Y
B...Y address bus, CB...control bus, XAB...
X address buffer, YAB...Y address buffer,
MA...main amplifier, IOB...input/output circuit, RC...
・Refresh address counter, RTG: Row timing generation circuit, CTG: Column timing generation circuit, WTG: Timing generation circuit, XDEC: X
Decoder, YDBC...Y decoder, XMP...multiplexer, PDC...power down control circuit,
CB... Clock buffer, WLI to WL4... Word line (polysilicon) WLI' to Wf, 4'... Wiring for word shunt (backing wiring), USAI, US
A2...Sense amplifier

Claims (1)

[Claims] 1. A semiconductor memory circuit formed by macrocelling a circuit block including a memory array in which memory cells are arranged in a matrix, its address selection circuit, and an input/output circuit that reads/writes to the memory cells. A semiconductor integrated circuit device comprising: 2. The semiconductor memory circuit includes a memory circuit provided with a plurality of the macrocells, and a control circuit that generates a selection signal for selecting one of the plurality of macrocells and a main timing signal necessary for its operation. 2. A semiconductor integrated circuit device according to claim 1, comprising: 3. The control circuit includes an address control circuit that distributes an address signal that specifies a memory cell in a macro cell and an address signal that specifies the macro cell itself, and a refresh address that is commonly used for a plurality of macro cells. 3. The semiconductor integrated circuit device according to claim 2, further comprising a counter circuit. 4. A macro cell consisting of a plurality of cells having a specific circuit function is provided, and a bonding pad for a signal input from the outside is provided close to the corresponding macro cell, and the bonding pad has an LO that extends to the vicinity.
3. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device is bonded to a C lead frame and a covered wire. 5. The macrocell is characterized in that it includes a memory array that itself operates as a semiconductor memory circuit, its address selection circuit, and a data input/output circuit that reads/writes to/from the memory cell. A semiconductor integrated circuit device according to claim 4. 6. Claim 1, wherein the LOC lead frame is also used as a part of wiring connecting bonding pads that supply the same signal and are provided corresponding to a plurality of macro cells. 6. The semiconductor integrated circuit device according to item 2, 4, or 5. 7. The semiconductor integrated circuit device according to claim 6, wherein the LOC lead frame is also used as a part of signal wiring transmitted between a plurality of macro cells. 8. A semiconductor memory circuit is provided in which the backing wiring of the word lines arranged side by side on the same plane arranged in the memory array is multilayered, and the backing wiring used for the adjacent word lines is a wiring of a different layer. A semiconductor integrated circuit device characterized by: 9. The semiconductor integrated circuit device according to claim 8, wherein the backing wiring is composed of two metal wiring layers, and the upper and lower layers are exchanged at the word shunt section. 10. The semiconductor integrated circuit according to claim 8 or 9, wherein the backing wiring for the common source line of the sense amplifier is formed by a metal wiring layer formed in the same manner as the backing wiring. circuit device. 11. Multilayering the bit lines arranged in the memory array,
A semiconductor integrated circuit device comprising a semiconductor memory circuit in which the adjacent bit lines are wired in different layers. 12. The bit line is composed of two metal wiring layers, and adjacent bit lines are arranged in an upper layer and a lower layer alternately in units of sense amplifiers, as set forth in claim 11. semiconductor integrated circuit devices. 13. The above-mentioned bit line is configured by using upper layer and lower layer wiring for every other pair of complementary bit lines arranged in parallel. semiconductor integrated circuit devices. 14. The semiconductor integrated circuit device according to claim 12 or 13, wherein the two-layered bit line is vertically switched in the middle thereof. 15. A semiconductor integrated circuit comprising a semiconductor memory circuit having a two-stage configuration in which unit circuits for selecting word lines are arranged close to the word lines and those arranged far away from the word lines. Device. 16. In the word line, the backing wiring corresponding to adjacent word lines is arranged alternately using two metal wiring layers, and the output line of the unit circuit placed far away connects to the upper metal wiring layer. 16. A semiconductor integrated circuit device according to claim 15, characterized in that the semiconductor integrated circuit device is configured using a semiconductor integrated circuit device. 17. A semiconductor memory circuit including a unit selection circuit for odd word lines arranged at one end of the word line and a unit selection circuit for even numbered word lines arranged at the other end of the word line. A semiconductor integrated circuit device characterized by: 18. A semiconductor integrated circuit device comprising a semiconductor memory circuit in which word line drivers are arranged at both ends of a word line to drive the word line from both ends. 19. The semiconductor integrated circuit device according to claim 18, wherein the word lines are electrically isolated at their midpoints. 20. Unit circuits that select mutually adjacent word lines are:
Claims 17, 18, or 19 are characterized in that they are arranged in two stages, one arranged close to the corresponding word line and the other arranged far away. Semiconductor integrated circuit device. 21. Claims 17 and 18, characterized in that the backing wirings corresponding to mutually adjacent word lines are arranged alternately using two metal wiring layers.
The semiconductor integrated circuit device according to item 19 or 21. 22. Of a plurality of bit line pairs, a semiconductor memory circuit is provided in which a corresponding sense amplifier is arranged at one end of the odd bit line and a corresponding sense amplifier is arranged at the other end of the even bit line. A semiconductor integrated circuit device characterized by: 23. The semiconductor integrated circuit device according to claim 22, wherein the odd bit line pairs and the even bit pairs are alternately arranged in two metal wiring layers. 24. The word line arranged orthogonally to the bit line is:
Claim 22 or 2, characterized in that the backing wiring is composed of two layers of metal wiring.
3. The semiconductor integrated circuit device according to item 3. 25. In normal mode, drive the bit line and word line you want to access and the sense amplifier rows corresponding to them, and in refresh mode, switch the number of word lines and sense amplifier rows to be simultaneously selected and operating sense amplifier rows to an integer multiple of the number in the above normal mode. A semiconductor integrated circuit device comprising a functional semiconductor memory circuit. 26. A semiconductor integrated circuit device having a built-in dynamic RAM and having a function of deactivating column circuits in its refresh mode. 27. The dynamic RAM has read/write functions for the memory array, its address selection circuit, and memory cells.
27. The semiconductor integrated circuit device according to claim 26, wherein the semiconductor integrated circuit device is configured as a macro cell and includes an input/output circuit that performs writing. 28. The counter test mode adopts a set/reset method different from the refresh mode described above, and is equipped with a dynamic RAM in which the column circuit is activated and read data is output only in the counter test mode. A semiconductor integrated circuit device according to claim 26 or 27, characterized in that: 29. In the refresh mode, the word line drive circuit for normal mode is put into a non-operating state, and the word line selection operation is performed by the word line drive circuit for refresh mode, which has a small drive capacity and receives a selection signal from its input part. Dynamic type R with drive capacity switching function
A semiconductor integrated circuit device characterized by having a built-in AM. 30. A semiconductor integrated circuit device comprising a dynamic RAM having a function of reducing a sense amplifier current in a refresh mode compared to a normal mode. 31. A semiconductor integrated circuit device comprising a dynamic RAM having a function of reducing the operating current of circuits other than the sense amplifier drive circuit and the word line drive circuit in the refresh mode compared to the normal mode. . 32. A semiconductor integrated circuit device comprising a dynamic RAM whose cycle time in refresh mode is set longer than the cycle time in normal mode. 33. A semiconductor integrated circuit device comprising a dynamic RAM in which the refresh operation of a memory mat is controlled so that the rise timing of a word line and/or the peak current of a sense amplifier are shifted from each other. 34. A semiconductor characterized by comprising a dynamic RAM that activates one or more memory mats in normal mode and activates a larger number of memory mats in refresh mode than in normal mode. Integrated circuit device. 35. The above-mentioned dynamic RAM performs read/write operations on the memory array, its address selection circuit, and memory cells.
The semiconductor integrated circuit device according to claim 30, 31, 32, 33, or 34, characterized in that the semiconductor integrated circuit device is configured as a macro cell and includes an input/output circuit that performs writing. 36. Among the memory arrays constituting the semiconductor memory circuit,
A defect relief method characterized in that only a non-defective part of two memory chips whose defective parts are prevented from overlapping each other is accessed. 37. The memory arrays of the above two memory chips each have two memory arrays according to the address of one or more specific bits.
Claim 1, wherein the chip is divided into two memory areas, and the chip having the memory area free of defects is selectively accessed by an address signal specifying each memory area. 36
Deficiency Remedy Law as described in Section 1. 38. Among the two memory chips, priority is assigned to one of the memory chips, and when a defective part of one of the memory chips is accessed, the other memory chip is switched to be accessed. A method for relieving defects according to claim 36. 39. The above two memory chips are both kept in an operating state until the address is determined before the word line selection operation is started, and the operation of the memory chip that is not accessed according to the address determination is immediately stopped. A defect relief method according to claim 38, characterized in that: 40. Claim 36, wherein the memory chip is provided with a defect relief circuit based on a redundant circuit system, and the defect relief circuit is used so that defects do not overlap at the same address. 37th, 38th
or the Defect Remedy Act described in Section 39. 41. Claim 36, wherein the memory chip is housed in one package.
, 37th, 38th, 39th or 40th defect relief method. 42. Parallel memory access to a memory chip consisting of an odd number of three or more or three or more odd memory blocks configured in one memory chip so that no defects exist at the same address A defect relief method characterized in that the readout signal is outputted via a majority logic circuit. 43.A memory chip consisting of an odd number of three or more chips is
43. The defect relief method according to claim 42, characterized in that the defect relief method is contained in one package. 44. A main memory chip consisting of a plurality of chips storing data consisting of a plurality of bits, a spare memory consisting of a number equal to the maximum number of defective bits at a specific address of the main memory chip, and storing the address of the defective bit, A defect relief method characterized in that a spare memory chip is accessed in place of a main memory chip in which a defective bit exists.