JPH09270192A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit device which can change bit constitution without increasing the driving capacity of transistors and is easily manufacturable without increasing the burden at the time of design. SOLUTION: Input pads DQ0-DQ3 and input bufferes DIB0-BID3 are connected by wiring La or Lb. When the memory cell array is made to have x4 bit constitution, the respective input terminals of the input pads DQ0-DQ3 and the input bufferes DIB0-DIB3 are connected by the wiring La. In the case of x1 bit constitution, the respective input terminals of the input pads DQ0 and the input buffers DIB0-DIB3 are connected by the wiring Lb. Since the constitution from input buffers DIB0-DIB3 to the memory cell array is unchanged between x4 bit and x1 bit, the increase of the driving capacity of transistors in the input buffers DIB0-DIB3 is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device such as a dynamic RAM (DRAM) or a synchronous DRAM.

[0002]

2. Description of the Related Art FIG. 7 shows the structure of a general DRAM chip. A row decoder 2 for selecting a word line is provided between adjacent memory cell arrays 1 of the plurality of memory cell arrays 1. Each memory cell array 1 includes a column decoder 3 for selecting a bit line, a write driver for writing the input data into the memory cell, and a write driver including a read amplifier for outputting the data read from the memory cell.
A read amplifier group 4 is arranged. A control circuit group 5 is arranged between the plurality of column decoders 3, and an input / output line RWD for transmitting input data and output data is arranged along the write driver / read amplifier group 4. These I / O lines RWD are provided with pads (not shown) for inputting / outputting data. These input / output lines RWD are connected to the write driver / read amplifier group 4 and the control circuit group 5.

FIG. 8 is a circuit showing a part of FIG. 7 in detail. In the memory cell array 1, the word lines WL are arranged in the vertical direction and the bit lines BL are arranged in the horizontal direction, and memory cells (not shown) are arranged at the intersections of the word lines WL and the bit lines BL. The word line WL is selected by the row decoder 2 and the bit line BL is selected by the column decoder 3. In order to suppress the bit line capacity, the memory cell array 1 is divided into a plurality of sub arrays 11. The bit lines BL, / BL (/ indicates an inverted signal) in each sub-array 11 are selected by the column selection signals CSL (A), CSL (A + 1) ... Output from the column decoder 3 and arranged in each sub-array. Data line DQ, / D
Connected to Q. The data lines DQ and / DQ are connected to the input / output lines (denoted as RWDn (n = 0 to 3)) via the write driver DQWD and the read amplifier DQRA. Input buffers DIB0 to DIB3 for inputting data and output buffers DOB0 to DOB3 for outputting data are connected to the input / output line RWDn, and these input buffers DIB0 to DIB3 and output buffers DOB0 to DOB3 have pads DQ0. -DQ3 are respectively connected.

When writing data, pads DQ0 to DQ
The data supplied to the input buffers DIB0 to DIB3 via the I / O line 3 are supplied to the write driver DQWD via the I / O line RWDn, and the data on the I / O line RWDn is supplied to the data line DQ, /
Transferred to DQ. Data on the data lines of the data lines DQ and / DQ is written in the selected memory cell.

On the other hand, when reading data, the signal read from the selected memory cell is supplied to the read amplifier DQRA via the data lines DQ and / DQ. The signal output from the read amplifier DQRA is the input / output line RW.
The signal of the input / output line RWDn transferred to Dn is output via the output buffers DOB0 to DOB and the pads DQ0 to DQ3.

[0006]

By the way, this kind of D
The bit configuration of the RAM can be selected as, for example, x1 bit or x4 bit. 9 and 10 are x1 bits,
It shows a configuration in which a × 4 bit configuration is integrated into one chip. For convenience of description, FIGS. 9 and 10 show pads DQ0 to DQ.
Only the write data path from 3 to the memory cell array is schematically shown.

FIG. 9 shows a write data path of x4 bit structure. In this case, each input buffer DIB0
The output end of the DIB 3 and the input end of each write driver DQWD are connected to the corresponding input / output line RWDn (n = 0-3). The 4-bit data input to the pads DQ0 to DQ3 is transmitted to the input / output line RWDn via the input buffers DIB0 to DIB3. I / O line RWDn
Data is supplied to the memory cell selected by the predetermined address Add via the write driver DQWD.

FIG. 10 shows a write data path having a x1 bit structure. In this case, each input buffer DIB0
The output ends of the DIB3 to DIB3 are connected to the corresponding input / output lines RWDn, and the input end of each write driver DQWD is 1.
It is connected to one input / output line RWD0. In the x1 bit configuration, if data is input from the pad DQ0, the 1-bit data input to the pad DQ0 is transmitted to the input / output line RWD0 via the input buffer DIB0. The data of the input / output line RWD0 is supplied to the memory cell selected by the predetermined address Add via each write driver DQWD.

As described above, in the conventional DRAM, by changing the wiring connection between the write driver and the input / output line, x1
Bit, × 4 bit configuration is realized in one chip. For this reason, there are usually input / output lines RWDn having an integral multiple of the bit configuration in one chip. For example, four input / output lines RW
Assuming that there is D, in the case of the x4 bit configuration, each write driver is connected to each input / output line, and the write driver is driven by the input buffer for the bit configuration. In the case of the 1-bit configuration, all write drivers are connected to one input / output line and driven by one input buffer.

Specifically, in the case of FIG. 9 and FIG.
For example, 16 write drivers DQWD, 4 input / output lines RWDn, 4 input buffers DIBn (n = 0-
Assuming that 3) is used, in the case of the x4 bit configuration, four write drivers are connected to each input / output line, and therefore the number of write drivers connected to one input buffer is four. On the other hand, in the case of the x1 bit configuration, as shown in FIG. 10, since 16 write drivers are connected to one input / output line, the number of write drivers connected to one input buffer is 16. It becomes the number (4 times). Therefore, if the drive capability of the input buffer is the same as in the x4 bit configuration, the drive capability will be reduced.

Normally, in the case of the x1 bit structure, the driving capability of the input buffer is the same as that in the x4 bit structure, and therefore a large driving capability is required. Therefore, a transistor having a pattern with a large gate width is used for the input buffer, which causes a problem of increasing the chip size.

Moreover, when setting x1 bit or x4 bit, the write driver DQWD and the input / output line RWDn are set.
The wiring connection of is changing. The input / output line RWDn and the wiring connecting the pads DQ0 to DQ3 and the input ends of the input buffers DIB0 to DIB3 are formed with the same mask.
The wiring connecting the input / output line RWDn and the write driver DQWD is formed by a mask different from the mask.
For this reason, the load on the design of the circuit and the mask increases. This problem becomes more serious when the bit configuration that can be switched by one chip increases to x8, x16, x32, ....

The present invention is intended to solve the above problems, and an object thereof is to change the bit configuration without increasing the driving capability of a transistor, and to increase the load at the time of designing. It is an object of the present invention to provide a semiconductor integrated circuit device that can be easily manufactured.

[0014]

According to the present invention, a plurality of terminals for inputting and outputting a signal, a plurality of buffer circuits arranged corresponding to these terminals, and these buffer circuits are respectively connected, A plurality of wirings connected to the selected memory cell and transmitting a signal, at least one of the terminals and the plurality of buffer circuits, and a plurality of wirings that are changed according to the bit configuration of the memory cell It has and.

Further, according to the present invention, a plurality of input terminals for receiving an input signal, a plurality of buffer circuits arranged corresponding to these input terminals, and output terminals of these buffer circuits are connected, and these buffer circuits are connected. A decoder for decoding the input signal supplied as a signal, a circuit means whose selection position is changed by the output signal of the decoder, and at least one of the input terminals and at least one of the buffer circuits, and the circuit means. And at least one wiring whose connection position is changed according to the selected position.

Further, according to the present invention, a plurality of input terminals for receiving an input signal, a plurality of buffer circuits arranged corresponding to these input terminals, and a plurality of transmission lines to which output terminals of these buffer circuits are connected respectively. And a input circuit connected to each of the transmission lines, for writing a signal supplied to each of the transmission lines into a selected memory cell, the input terminal and the buffer circuit are connected, and a semiconductor integrated circuit And at least one wiring whose connection position is changed according to the bit configuration of the memory cell.

Further, according to the present invention, a plurality of input terminals for receiving an input signal, a plurality of buffer circuits arranged corresponding to these input terminals, and output terminals of these buffer circuits are connected and supplied from the buffer circuit. A decoder that decodes the address signal, a memory cell array that is selected by the output signal of the decoder, and forms a plurality of banks, the input terminal and the buffer circuit, and the connection is made according to the bank configuration of the memory cell array. And at least one wire whose position is changed.

Further, according to the present invention, a plurality of input terminals for receiving an address signal, a plurality of buffer circuits arranged corresponding to these input terminals, and output terminals of these buffer circuits are connected and supplied from the buffer circuit. A row decoder for decoding the address signal, a memory cell selected by the output signal of the row decoder, the input terminal and a buffer circuit are connected, and the connection position is changed according to the refresh cycle of the memory cell. And at least one wiring.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention and shows a case where a x1 bit and a x4 bit configuration is realized by one chip. In FIG.
The same parts as those in FIGS. 8 to 10 are designated by the same reference numerals, and different parts will be described. In FIG. 1, a circuit for reading data is omitted.

In FIG. 1, each write driver DQWD
Input terminals and output terminals of the input buffers DIB0 to DIB3 are connected to corresponding input / output lines RWDn. Assuming that the number of write drivers DQWD is 16, four write drivers DQWD are connected to each input / output line. Pads DQ0 to DQ3 and input buffer DI
Wiring to each input terminal of B0 to DIB3 is formed according to the bit configuration.

A wiring La shown by a broken line in FIG. 1 shows a case where this semiconductor memory device has a × 4 bit configuration, and a wiring Lb shown by a dashed line in FIG. 1 makes this semiconductor memory device a × 1 bit configuration. The case is shown. That is, in the case of the x4 bit configuration, the input pad DQ0
To DQ3 and input buffers DIB0 to DIB3 are connected to each other and have a × 1 bit configuration, one input pad DQ0 and one input buffer D are connected by the wiring Lb.
Input terminals of IB0 to DIB3 are connected. Figure 2 shows
The 1-bit configuration is specifically shown.

In the above-mentioned × 1 bit configuration, when writing data to a memory cell (not shown), the 1-bit data supplied to the input pad DQ0 is stored in the four input buffers DQ0.
It is supplied to IB0 to DIB3 and these input buffers DI
It is supplied to each input / output line RWDn via B0 to DIB3. The data supplied to these input / output lines RWDn are written into one write driver DQWD decoded by the address signal Add and the selected memory cell via the data line.

FIG. 3 shows an example of the write driver DQWD. In FIG. 3, input / output lines RWD, / R
WD is supplied to the input terminals of the AND circuits 31 and 32 together with the address signal Add. / RWD is RWD
Of the signal RWD, which is generated by inverting the signal RWD by an inverter circuit (not shown). The output terminals of these AND circuits 31, 32 are N-channel transistors 33, 3
4 and the input terminals of the inverter circuits 35 and 36, respectively. The output terminals of the inverter circuits 35 and 36 are P-channel transistors 37 and 3, respectively.
8 gates connected. The current paths of the P-channel transistors 37 and 38 are the same as the N-channel transistor 3
3 and 34 are connected to the current paths, and these connection points are connected to the data lines / DQ and DQ, respectively.

The write driver DQWD having the above structure transmits the data of the input / output line RWD to the data lines / DQ and DQ when the input conditions of the AND circuits 31 and 32 are satisfied.
Note that the data write operation and data read operation in the x4 bit configuration are the same as in the conventional art, and therefore will be omitted.

FIGS. 4A and 4B show an example of wiring between the pad and the input buffer. Since each pad and the input buffer have the same structure, the input buffer DIB
Only 0 and the pad DQ0 will be described.

The input buffer DIB0 is provided on the semiconductor substrate 41.
Is formed.
An insulating film 43 is provided on the MOS transistor 42, and a plurality of first-layer wirings 44 are provided in the insulating film 43. A contact hole 45 is formed in the insulating film 43 so as to correspond to the gate of the MOS transistor 42, and the second-layer wiring 46 as the wirings La and Lb is connected to the gate through the contact hole 45. It A pad D is provided at one end of the second-layer wiring 46.
Q0 is connected. When changing the bit configuration, the formation position of the wiring 46 of the second layer is changed.

According to the above-described embodiment, the input pads DQ0-DQ0.
The bit configuration of the semiconductor memory device is changed by the wiring connecting the DQ3 and each input terminal of the input buffers DIB0 to DIB3. For this reason, the input buffer DIB is configured depending on the x1 bit configuration and the x4 bit configuration.
The configuration from 0 to DIB3 to the memory cell does not change.
Therefore, the driving capability of the input buffers DIB0 to DIB3 can be made the same in the x1 bit configuration and in the x4 bit configuration, so that the transistors forming the input buffer are in the x4 bit configuration. The current driving capacity of That is, even when two or more kinds of bit configurations can be set, the transistors forming the input buffer have the current driving capability in the maximum bit configuration. Therefore, a transistor having a small size can be used, and an increase in pattern area can be prevented.

The bit configuration of the semiconductor memory device is changed by changing the wiring connecting the input pads DQ0 to DQ3 and the input terminals of the input buffers DIB0 to DIB3. Therefore, only the wiring between the input pads DQ0 to DQ3 and the input ends of the input buffers DIB0 to DIB3 need be verified. Therefore, it is not necessary to verify the wiring at a plurality of locations as in the conventional case, and the verification can be facilitated.

Further, the wiring connecting the input pads DQ0 to DQ3 and the input terminals of the input buffers DIB0 to DIB3 is the uppermost wiring of the semiconductor memory device. That is, this wiring is a wiring formed in the final step of manufacturing the semiconductor memory device, and only this wiring needs to be changed. Therefore, unlike the conventional case, it is not necessary to change the wiring in the manufacturing process in the middle, so that the mask can be easily designed. Moreover, since the number of masks can be reduced, mask management can be facilitated. Further, since only the final wiring needs to be changed, the manufacturing process of the semiconductor memory device can be shortened as compared with the conventional case by performing the steps before this and performing the final wiring according to the bit configuration.

FIG. 5 shows a second embodiment of the present invention, and shows an example in which the present invention is applied, for example, when the bank configuration of a synchronous DRAM (hereinafter referred to as SDRAM) is switched. The SDRAM has a plurality of independent memory banks composed of a plurality of memory cell arrays in one chip. When this SDRAM is used as a cache memory, it is possible to avoid a so-called cache miss in which the address and data required by the CPU are not in the memory. This type of memory is designed so that the bank structure in the chip can be changed, and the required bank structure is set at the time of manufacture.

In FIG. 5, a plurality of memory cell arrays 51a, 51b, 51c, 51d forming a memory bank.
The output terminal of the decoder 52 is connected to the. The output ends of the address buffers 53 and 54 are connected to the input end of the decoder 52. These address buffers 53,
The input end of 54 and the pads 55 and 56 to which the bank addresses Am and An are supplied are appropriately connected by wiring. That is, the input end of the address buffer 53 and the pad 55 are connected by the wiring 57 regardless of the bank structure, and the wiring of the input end of the address buffer 54 is changed according to the bank structure. For example, when the SDRAM has a 4-bank structure, the pad 5 is formed by the wiring 58 shown by a broken line in FIG.
6 and the input end of the address buffer 54 are connected. When the SDRAM has a two-bank structure, the pad 55 and the input end of the address buffer 54 are connected by a wiring 59 shown by a dashed line in the figure. These wiring 5
Reference numerals 7 and 58 are, for example, second-layer wirings, which are manufactured in the final step.

According to the second embodiment described above, the pads 55,
The bank configuration can be easily switched by switching the wiring between 56 and the input ends of the address buffers 53 and 54. Moreover, the address buffers 53, 5
4 and the memory cell arrays 51a to 51d have the same configuration in each bank configuration, it is possible to equalize the performance at the time of address transition in each bank configuration.

FIGS. 6 (a) to 6 (d) show a third embodiment of the present invention.
The case where the present invention is applied to the switching of the AM refresh cycle is shown.

In FIG. 6A, the memory cell array 6
1 row decoder 62 has address buffers 63, 6
The output terminals of 4, 65 are connected. The input ends of these address buffers 63, 64, 65 and the addresses Am, A
The pads 66, 67, and 68 to which n and Ao are supplied are appropriately connected by wiring. That is, the wiring 69 connects the pad 68 and the address buffer 65 when the refresh cycle is 2k, 4k, or 8k.

The wiring 70 has a refresh cycle of 8k.
And 4k, pad 67 and address buffer 64
And connect. The wiring 71 has a refresh cycle of 8
In the case of k, the pad 68 and the address buffer 65 are connected.

The wiring 72 has a refresh cycle of 4k.
In this case, the pad 67 and the address buffer 65 are connected. The wiring 73, 74 has a refresh cycle of 2k
In this case, the pad 66 is connected to the address buffers 64 and 65.

These wirings 69, 70, 71, 72, 7
Reference numerals 3 and 74 are, for example, second-layer wirings, which are manufactured in the final step. As described above, the address buffers 63 and 6
As shown in FIGS. 6B, 6C, and 6D, by connecting the input terminals of Nos. 4, 65 and the pads 66, 67, 68,
A refresh area can be set according to the addresses Am, An, Ao. In FIG. 6B, the refresh cycle is 8k.
6C, the refresh cycle is 4 times.
FIG. 6D shows the case where the refresh cycle is 2k.

Moreover, in the case of the third embodiment, only the wiring connecting the address buffers 63, 64 and 65 and the pads 66, 67 and 68 is changed, and the address buffer 6
The wiring between 3, 64 and 65 and the memory cell is not changed. Therefore, the performance in each refresh cycle can be made uniform.

Although the above embodiments have been described with respect to DRAM and SDRAM, the present invention is not limited to these, and can be applied to semiconductor integrated circuit devices other than memories such as logic integrated circuits.

[0040]

As described above in detail, according to the present invention, the bit configuration can be changed without increasing the driving ability of the transistor, and the designing load can be easily increased. A manufacturable semiconductor integrated circuit device can be provided.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a main part showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a main part showing a first embodiment of the present invention.

FIG. 3 is a circuit diagram specifically showing a write driver DQWD.

4A is a plan view showing an example of wiring between a pad and an input buffer, and a cross-sectional view taken along line 4b-4b of FIG. 4A.

FIG. 5 is a configuration diagram showing a second embodiment of the present invention.

FIG. 6 (a) is a configuration diagram showing a third embodiment of the present invention, and FIGS. 6 (b), (c) and (d) respectively show refresh cycles of 8k, 4k, 2k in FIG. 6 (a). The figure shown in order to demonstrate operation | movement in the case of.

FIG. 7 is a plan view showing a chip configuration of a RAM.

FIG. 8 is a circuit diagram specifically showing a part of FIG.

FIG. 9 is a configuration diagram showing a conventional write data path having a × 4 bit configuration.

FIG. 10 is a configuration diagram showing a conventional write data path of × 1 bit configuration.

[Explanation of symbols]

 DQWD ... Write driver, DIB0-DIB3 ... Input buffer, RWDn ... I / O line, DQ0-DQ3 ... Pad, La, Lb ... Wiring, DQ, / DQ ... Data line, 51a-51d ... Memory cell array, 52 ... Decoder, 53 , 54 ... Address buffer, 55, 56 ... Pad, 57, 58, 59 ... Wiring, 61 ... Memory cell array, 62 ... Row decoder, 63, 64, 65 ... Address buffer, 66, 67, 68 ... Pad, 69, 70 , 71, 72, 73, 74 ... Wiring.

Claims (12)

[Claims] 1. A plurality of terminals for inputting / outputting a signal, a plurality of buffer circuits arranged corresponding to these terminals, and these buffer circuits are respectively connected to a selected memory cell. A plurality of transmission paths for transmitting a signal, and a plurality of wirings that connect at least one of the terminals and the plurality of buffer circuits and are changed according to a bit configuration of the memory cell. Integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the wiring is a second layer wiring. 3. The semiconductor integrated circuit device according to claim 1, wherein the terminal is an input terminal. 4. The semiconductor integrated circuit device according to claim 1, further comprising a plurality of write circuits each of which is connected to the transmission line and writes data in the selected memory cell. 5. A plurality of input terminals for receiving an input signal, a plurality of buffer circuits arranged corresponding to these input terminals, and output terminals of these buffer circuits are connected and supplied through these buffer circuits. A decoder that decodes the input signal, a circuit unit whose selection position is changed by an output signal of the decoder, and at least one of the input terminals and at least one of the buffer circuits are connected to each other, A semiconductor integrated circuit device comprising: at least one wiring whose connection position is changed accordingly. 6. The semiconductor integrated circuit according to claim 5, wherein said circuit means is a plurality of memory cell arrays forming a plurality of banks, and said decoder selects at least one bank according to an input signal. Circuit device. 7. The circuit means is a memory cell array, the decoder is a row decoder for selecting a word line of the memory cell array, and a refresh cycle of the memory cell array connects the input terminal to a buffer circuit. The semiconductor integrated circuit device according to claim 5, wherein the semiconductor integrated circuit device is changed by changing a connection position of the wiring. 8. A plurality of input terminals for receiving an input signal, a plurality of buffer circuits arranged corresponding to these input terminals, a plurality of transmission lines to which output terminals of these buffer circuits are respectively connected, and these transmission circuits. Each input end is connected to a path, a write circuit for writing the signal supplied to each transmission path into a selected memory cell, the input terminal and the buffer circuit are connected, and the uppermost part of the semiconductor integrated circuit is connected. A semiconductor integrated circuit device, comprising: at least one wiring, the connection position of which is changed according to the bit configuration of the memory cell. 9. A plurality of input terminals for receiving an input signal, a plurality of buffer circuits arranged corresponding to these input terminals, output terminals of these buffer circuits are connected, and the address signal is supplied from the buffer circuit. And a memory cell array which is selected by an output signal of the decoder and constitutes a plurality of banks, and which connects the input terminal and the buffer circuit, and the connection position is changed according to the bank configuration of the memory cell array. A semiconductor integrated circuit device, comprising: 10. A plurality of input terminals for receiving an address signal, a plurality of buffer circuits arranged corresponding to these input terminals, and output terminals of these buffer circuits are connected to the address signal supplied from the buffer circuit. A row decoder for decoding the memory cell, a memory cell selected by an output signal of the row decoder, the input terminal and a buffer circuit, and at least one connection position of which is changed according to a refresh cycle of the memory cell. A semiconductor integrated circuit device comprising: a wiring. 11. The current drive capability of the buffer circuit is
The semiconductor integrated circuit device according to any one of claims 1, 8, 9, and 10, wherein the current driving capability is set to the maximum bit configuration. 12. The wiring is manufactured in a final manufacturing process of a semiconductor integrated circuit.
9. The semiconductor integrated circuit device according to any one of 9 and 10.