JP2006165535A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that is nonvolatile and easily manufactured, and has a rewritable storage circuit. <P>SOLUTION: The semiconductor device has a plurality of transistors, conductive layers acting as source lines or drain lines of the transistors, a storage element provided on one of the plurality of transistors, and a conductive layer acting as an antenna; wherein the storage element includes a first conductive layer, an organic compound layer or a phase change layer, and a second conductive layer stacked in this order, and the conductive layer acting as the antenna and the conductive layers acting as the source lines or the drain lines of the transistors are provided on the same layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device capable of transmitting and receiving data and a manufacturing method thereof.

  In recent years, development of semiconductor devices having various functions in which a plurality of circuits are integrated on an insulating surface has been promoted. In addition, development of a semiconductor device capable of transmitting and receiving data wirelessly by providing an antenna is in progress. Such a semiconductor device is called a wireless chip (also referred to as an ID tag, an IC tag, an IC chip, an RF (Radio Frequency) tag, a wireless tag, an electronic tag, or an RFID (Radio Frequency Identification) tag). Has been introduced in the market.

  When a memory circuit for storing data (also simply referred to as a memory) is provided as various circuits integrated on the substrate, a semiconductor device with higher functions and higher added value can be provided. Memory circuits include DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory Memory), FeRAM (Ferroelectric Random Access Memory Memory), Mask ROM (Mask Read Only Memory). Examples include Erasable and Programmable Read Only Memory) and flash memory. Among these, DRAM and SRAM are volatile storage circuits, and data is erased when the power is turned off. Therefore, it is necessary to write data every time the power is turned on. FeRAM is a non-volatile memory circuit, but a manufacturing process increases because a capacitor element including a ferroelectric layer is used. Although the mask ROM has a simple structure, it is necessary to write data in the manufacturing process and cannot be additionally written. Although EPROM, EEPROM, and flash memory are non-volatile memory circuits, the number of manufacturing steps increases because an element including two gate electrodes is used.

  In view of the above circumstances, an object of the present invention is to provide a semiconductor device having a memory circuit that is nonvolatile, easy to manufacture, and additionally writable, and a manufacturing method thereof.

  One embodiment of the present invention includes a transistor provided over an insulating layer, a conductive layer that functions as a source wiring or a drain wiring of the transistor, a memory element that overlaps with the transistor, and a conductive layer that functions as an antenna. The memory element is an element in which a first conductive layer, an organic compound layer or a phase change layer, and a second conductive layer are sequentially stacked. The memory element functions as an antenna and includes a plurality of transistors. The conductive layer functioning as a source wiring or a drain wiring is a semiconductor device provided in the same layer.

  One embodiment of the present invention includes a transistor provided over an insulating layer, a memory element overlapping with the transistor, and a conductive layer functioning as an antenna. The memory element includes a first conductive layer, an organic compound, and the like. An element in which a layer or a phase change layer and a second conductive layer are sequentially stacked, wherein the conductive layer functioning as an antenna and the first conductive layer are provided in the same layer. It is a semiconductor device.

  One embodiment of the present invention includes a transistor provided over an insulating layer, a memory element overlapping with the transistor, and a conductive layer functioning as an antenna. The memory element includes a first conductive layer, an organic compound, and the like. An element in which a layer or a phase change layer and a second conductive layer are sequentially stacked, wherein the conductive layer functioning as an antenna and the second conductive layer are provided in the same layer. It is a semiconductor device.

  According to one aspect of the present invention, a first element formation layer, a second element formation layer, an adhesive layer that adheres the first element formation layer and the second element formation layer and includes conductive particles are provided. And the first element formation layer includes a transistor provided over an insulating layer, a conductive layer functioning as a source wiring or a drain wiring of the transistor, and a conductive layer functioning as an antenna provided over the transistor And the second element formation layer includes a memory element in which a first conductive layer, an organic compound layer or a phase change layer, and a second conductive layer are stacked. The conductive layer or the second conductive layer and the conductive layer functioning as a source wiring or a drain wiring of the transistor are connected to each other through conductive particles.

  One aspect of the present invention includes an element formation layer, a substrate provided with a conductive layer functioning as an antenna, and an adhesive layer that adheres the element formation layer and the substrate and includes conductive particles. The formation layer overlaps with the first and second transistors provided on the insulating layer, a conductive layer functioning as a source wiring or a drain wiring of the first transistor, the second transistor, and a first layer A memory element in which one conductive layer, an organic compound layer or a phase change layer, and a second conductive layer are stacked; the conductive layer functioning as an antenna; and the source wiring or drain wiring of the first transistor The conductive layer functioning as a semiconductor device is a semiconductor device that is connected through conductive particles.

  According to one aspect of the present invention, a first element formation layer, a second element formation layer, an adhesive layer that adheres the first element formation layer and the second element formation layer and includes conductive particles are provided. And the first element formation layer includes: first and second transistors provided on an insulating layer; a first conductive layer functioning as a source wiring or a drain wiring of the first transistor; A second conductive layer functioning as a source wiring or a drain wiring of the second transistor, and the second element formation layer includes a first conductive layer, an organic compound layer, a phase change layer, and a second conductive layer. A memory element in which a conductive layer is stacked; a conductive layer that functions as an antenna; the conductive layer that functions as an antenna; and a first conductive layer that functions as a source wiring or a drain wiring of the first transistor; Through the conductive particles The first conductive layer or the second conductive layer of the memory element and the second conductive layer functioning as a source wiring or a drain wiring of the second transistor are connected to each other through the conductive particles. A semiconductor device is connected.

  According to one embodiment of the present invention, a first transistor includes a transistor provided over a substrate, a conductive layer functioning as a source wiring or a drain wiring of the transistor, and a conductive layer functioning as an antenna provided over the plurality of transistors. An element formation layer and the substrate or the first element formation layer are provided via an adhesive layer, and the first conductive layer, the organic compound layer or the phase change layer, and the second conductive layer are stacked. A second element formation layer having a memory element, a first conductive layer of the memory element or the second conductive layer, and a conductive layer functioning as a source wiring or a drain wiring of the transistor, The semiconductor device is connected through the conductive member.

  One of the present invention includes an element formation layer, a substrate provided with a conductive layer functioning as an antenna, an adhesive layer that adheres the element formation layer and the substrate and includes conductive particles, and the element The formation layer includes the first and second transistors provided on the insulating layer, an interlayer insulating layer covering the first and second transistors, and an opening provided in the interlayer insulating layer. A source of the first transistor connected to a source region or a drain region of the first transistor and exposed to a back surface of the element formation layer through an opening provided in each of the insulating layer and the interlayer insulating layer; A conductive layer functioning as a wiring or a drain wiring, the second transistor, the second transistor, a first conductive layer, an organic compound layer or a phase change layer, and a second conductive layer overlapping with the second transistor. Laminated A conductive layer that functions as the antenna, and an exposed portion of the conductive layer that functions as a source wiring or a drain wiring of the first transistor through the conductive particles of the adhesive layer. A semiconductor device is characterized by being connected.

  According to one aspect of the present invention, a first element formation layer, a second element formation layer, an adhesive layer that adheres the first element formation layer and the second element formation layer, and has conductive particles, The first element formation layer includes a transistor provided on an insulating layer, an interlayer insulating layer covering the transistor, and a source region of the transistor through an opening provided in the interlayer insulating layer. Alternatively, a conductive layer connected to the drain region and functioning as a source wiring or a drain wiring of the transistor exposed to the back surface of the first element formation layer through an opening provided with the insulating layer and the interlayer insulating layer. A memory element in which a first conductive layer, an organic compound layer or a phase change layer, and a second conductive layer are stacked. And a first of the storage elements The conductive layer or the second conductive layer is electrically connected to the exposed portion of the conductive layer functioning as a source wiring or a drain wiring of the transistor through the conductive particles of the adhesive layer. It is a semiconductor device.

  According to one aspect of the present invention, a first element formation layer, a second element formation layer, an adhesive layer that adheres the first element formation layer and the second element formation layer, and has conductive particles, And the first element formation layer is provided on the insulating layer, the first and second transistors provided on the insulating layer, the interlayer insulating layer covering the first and second transistors, and the interlayer insulating layer. The first element is formed through the opening provided with the insulating layer and the interlayer insulating layer, and connected to the source region or the drain region of the first and second transistors through the formed opening. A first conductive layer and a second conductive layer functioning as a source wiring or a drain wiring of the first and second transistors exposed on the back surface of the layer, and the second element formation layer serves as an antenna A functional conductive layer and a first conductive layer, an organic compound layer or A memory element on which the change layer and the second conductive layer are stacked, and function as the first conductive layer or the second conductive layer of the memory element and the source wiring or the drain wiring of the first transistor The exposed portion of the first conductive layer is electrically connected via the conductive particles of the adhesive layer, and functions as the source wiring or drain wiring of the conductive layer functioning as the antenna and the second transistor. The exposed portion of the second conductive layer is a semiconductor device that is connected through the conductive particles of the adhesive layer.

  According to one aspect of the present invention, a first element formation layer, a second element formation layer, the first element formation layer, and the second element formation layer are bonded to each other, and the first element formation layer includes conductive particles. An adhesive layer; a substrate having a conductive layer that functions as an antenna; and a second adhesive layer that adheres the second element formation layer and the substrate and has conductive particles. The element formation layer includes a memory element in which a first conductive layer, an organic compound layer or a phase change layer, and a second conductive layer are stacked, and the second element formation layer is provided on the insulating layer. The first and second transistors, the interlayer insulating layer covering the first and second transistors, and the source or drain region of the first transistor through the opening provided in the interlayer insulating layer Connected as the source wiring or drain wiring of the first transistor A first conductive layer that functions as well as an opening provided in the interlayer insulating layer and connected to a source region or a drain region of the second transistor, and the insulating layer and the interlayer insulating layer are provided. And a second conductive layer functioning as a source wiring or a drain wiring of the transistor exposed on the back surface of the first element formation layer through the opening, and the first conductive layer or the second conductive layer of the memory element The conductive layer and the first conductive layer functioning as a source wiring or a drain wiring of the first transistor are electrically connected through the conductive particles of the first adhesive layer as the antenna. The functioning conductive layer and the exposed portion of the second conductive layer functioning as the source wiring or drain wiring of the second transistor are connected via the second conductive particles of the adhesive layer, Do A conductor arrangement.

  In the semiconductor device of the present invention having the above structure, a transistor is connected to the memory element. Further, the transistor connected to the memory element is a MOS transistor, a thin film transistor, or an organic semiconductor transistor.

The memory element overlaps with part or all of the transistor, the first transistor, or the second transistor.

  The insulating layer is a silicon oxide layer.

In the memory element, when the organic compound layer is made of a conjugated polymer material doped with a photoacid generator, an electron transport material, or a hole transport material, the memory element is irreversible due to an optical action or an electrical action. The electrical resistance changes, and the electrode spacing distance of the memory element changes. The film thickness of the organic compound layer before changing the electric resistance is 5 to 60 nm, preferably 10 to 20 nm.

The phase change layer included in the memory element includes a material that reversibly changes between a crystalline state and an amorphous state, a material that reversibly changes between a first crystalline state and a second crystalline state, Or it consists of a material which changes only from an amorphous state to a crystalline state.

  In addition, the semiconductor device of the present invention having the above-described structure includes one or more selected from a power supply circuit, a clock generation circuit, a data demodulation / modulation circuit, a control circuit, and an interface circuit.

  The semiconductor device of the present invention includes a memory element that overlaps with a plurality of transistors. With the above characteristics, a small and highly integrated semiconductor device can be provided.

  Further, the semiconductor device of the present invention has a structure in which a substrate having a memory element or a substrate having a conductive layer functioning as an antenna is bonded to an element formation layer having a plurality of transistors. A small semiconductor device can be provided.

  In addition, the present invention is characterized in that it has a memory element with a simple structure in which an organic compound layer or a phase change layer is sandwiched between a pair of conductive layers. A semiconductor device and a manufacturing method thereof can be provided. In addition, since high integration is easy, a semiconductor device having a large-capacity memory circuit and a manufacturing method thereof can be provided.

  In addition, in the memory circuit included in the semiconductor device of the present invention, in the case where a memory element in which an organic compound layer is sandwiched between a pair of conductive layers is included, data is written by an optical action or an electrical action, and is nonvolatile And, it is possible to add data. With the above feature, forgery due to rewriting can be prevented, and new data can be added and written. That is, a semiconductor device including a memory circuit that cannot be rewritten can be provided.

  In addition, in the memory circuit included in the semiconductor device of the present invention, in the case where the memory element includes a phase change layer sandwiched between a pair of conductive layers, the memory element is nonvolatile, and thus a battery for retaining data is incorporated. There is no need to provide a small, thin, and lightweight semiconductor device. If an irreversible material is used for the phase change layer, data cannot be rewritten. Therefore, it is possible to provide a semiconductor device that prevents forgery and ensures security.

  Accordingly, it is possible to provide a semiconductor device that achieves high functionality and high added value and a manufacturing method thereof.

  Embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.

(Embodiment 1)
The configuration of the semiconductor device of this embodiment will be described with reference to FIGS. As shown in FIG. 15, the semiconductor device 20 of the present invention has a function of communicating data without contact, and controls to control a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, and other circuits. The circuit 14 includes an interface circuit 15, a memory circuit 16, a data bus 17, and an antenna (antenna coil) 18.

  The power supply circuit 11 is a circuit that generates various power supplies to be supplied to each circuit inside the semiconductor device 20 based on the AC signal input from the antenna 18. The clock generation circuit 12 is a circuit that generates various clock signals to be supplied to each circuit inside the semiconductor device 20 based on the AC signal input from the antenna 18. The data demodulation / modulation circuit 13 has a function of demodulating / modulating data communicated with the reader / writer 19. The control circuit 14 has a function of controlling the memory circuit 16. The antenna 18 has a function of transmitting and receiving an electromagnetic field or a radio wave. The reader / writer 19 controls communication and control with the semiconductor device and processing related to the data. The semiconductor device is not limited to the above-described configuration, and may be a configuration in which other elements such as a power supply voltage limiter circuit and hardware dedicated to cryptographic processing are added.

  The memory circuit 16 includes a memory element in which an organic compound layer or a phase change layer is sandwiched between a pair of conductive layers. Note that the memory circuit 16 may include only a memory element in which an organic compound layer or a phase change layer is sandwiched between a pair of conductive layers, or may include a memory circuit having another structure. The memory circuit having another configuration corresponds to, for example, one or more selected from DRAM, SRAM, FeRAM, mask ROM, PROM, EPROM, EEPROM, and flash memory.

  A perspective view of the semiconductor device 20 of the present embodiment will be described with reference to FIG. As shown in FIG. 7A, the semiconductor device of this embodiment has a configuration in which a plurality of circuits are integrated on a substrate. Here, an element formation layer 101a including a plurality of transistors is formed over a substrate 100a. The element formation layer 101a including a plurality of transistors typically includes regions 102 and 103 each including a plurality of TFTs and a memory element. And a conductive layer 105 functioning as an antenna provided around the regions 102 and 103 having a plurality of TFTs and the region 104 having a memory element.

  In the following embodiments, an example in which the element formation layer having a plurality of transistors is configured by the regions 102 and 103 having TFTs is shown, but is not limited to TFTs, and is not limited to TFTs. An element formation layer having a plurality of transistors can be formed using a transistor formed over a crystal substrate. In this case, the substrate 100a is a semiconductor single crystal substrate. Alternatively, an SOI (silicon on insulator) substrate in which an insulating layer and a single crystal semiconductor layer are stacked can be used. Furthermore, an element formation layer having a plurality of transistors can be formed using an organic semiconductor transistor.

  The regions 102 and 103 having a plurality of TFTs constitute various circuits. As a typical example of the region 102 having a plurality of TFTs, a communication circuit that processes an electromagnetic wave received by an antenna such as a power supply circuit, a clock generation circuit, and a data demodulation / modulation circuit is provided. A typical example of the region 103 having a plurality of TFTs includes a control circuit for controlling other circuits, an interface circuit, and the like.

  In addition, the conductive layer 105 functioning as an antenna is connected to a region 102 including a plurality of TFTs that form a communication circuit.

  The region 104 including a memory element forms a memory circuit that stores data, and includes a memory element, a circuit that operates the memory element, and the like. A region 104 including a memory element is connected to a region 103 having a plurality of TFTs that constitute a control circuit, an interface circuit, and the like.

  Next, a cross-sectional structure of the semiconductor device having the structure illustrated in FIG. 7A will be described with reference to FIG. An element formation layer 101a including a plurality of transistors is formed over the substrate 100a. Here, as the element formation layer 101a having a plurality of transistors, a TFT 111 (part of the region 104 having the memory element in FIG. 7A) that forms a circuit for operating the memory element, and a TFT 112 for switching the memory element ( TFT 113 which constitutes a circuit for processing a signal received by an antenna such as a power supply circuit, a clock generation circuit, and a data demodulation / modulation circuit (FIG. 7A). The TFT 114 (part of the region 103 having a plurality of TFTs in FIG. 7A) constituting a circuit such as a control circuit and an interface is shown.

  These TFTs can be configured by appropriately combining p-channel TFTs, n-channel TFTs, and the like. Here, TFTs constituting each circuit are shown as n-channel TFTs.

  The TFTs 111 to 114 are provided on the substrate 100a with an insulating layer 115 interposed therebetween. The TFT includes a semiconductor region, gate insulating films 116a to 116d, gate electrodes 117a to 117d, and sidewalls 118a to 118d provided on the side walls of the gate electrode. The semiconductor layer includes source and drain regions 119a to 119d, low-concentration impurity regions 120a to 120d, and channel formation regions 121a to 121d. The low concentration impurity regions 120a to 120d are covered with the sidewalls 118a to 118d. Further, an insulating layer 122 that covers the TFTs 111 to 114 is formed. The insulating layer 122 functions as a passivation film, has an effect of blocking impurities from the outside, typically contaminants such as alkali gold, and the TFTs 111 to 114 have improved reliability without being contaminated. Can be provided. Note that as the passivation film, a silicon nitride film, a silicon nitride oxide film, a silicon oxynitride film, or the like can be given.

Note that the semiconductor layer of the TFTs 111 to 114 may use any semiconductor such as an amorphous semiconductor, a microcrystalline semiconductor, a polycrystalline semiconductor, and an organic semiconductor as an active layer, but in order to obtain a transistor with favorable characteristics, A semiconductor layer crystallized using a metal element as a catalyst or a semiconductor layer crystallized by a laser irradiation method may be used. In addition, a semiconductor layer formed by a plasma CVD method using SiH ₄ / F ₂ gas or SiH ₄ / H ₂ gas (Ar gas), or a semiconductor layer that has been subjected to laser irradiation may be used as the semiconductor layer. .

The TFTs 111 to 114 are crystalline semiconductor layers (low-temperature polysilicon layers) that are crystallized at a temperature of 200 to 600 degrees (preferably 350 to 550 degrees) or crystals that are crystallized at a temperature of 600 degrees or more. A quality semiconductor layer (high-temperature polysilicon layer) can be used. When a high-temperature polysilicon layer is formed on a substrate, a quartz substrate may be used because a glass substrate may be vulnerable to heat. A concentration of 1 × 10 ¹⁹ atoms / cm ³ to 1 × 10 ²² atoms / cm ³ , preferably 1 × 10 ¹⁹ atoms / cm ^{3 to} 5 × 10, is applied to the semiconductor layer (particularly the channel formation region) of the TFTs 111 to 114. Hydrogen or a halogen element is preferably added at a concentration of ²⁰ atoms / cm ³ . If it does so, the active layer with few defects and being hard to produce a crack can be obtained.

  The thickness of the semiconductor layer of the TFTs 111 to 114 is 20 nm to 200 nm, preferably 40 nm to 170 nm, more preferably 45 nm to 55 nm, and still more preferably 50 nm. Then, it is possible to provide the element formation layer 101a that is unlikely to crack even when bent.

In addition, crystals constituting the semiconductor layers of the TFTs 111 to 114 are preferably formed so as to have a crystal grain boundary extending in parallel with the carrier flow direction (channel length direction). The S value (subthreshold value) of the TFTs 111 to 114 is preferably 0.35 V / sec or less (preferably 0.09 to 0.25 V / sec) and has a mobility of 10 cm ² / Vs or more. Such a semiconductor layer can be formed by irradiating the semiconductor layer with a continuous wave laser or a pulsed laser operating at 10 MHz or higher, preferably 60 to 100 MHz.

  An element imparting p-type or n-type conductivity is added to the low-concentration impurity region, the source region, and the drain region. Here, the source and drain regions 119a to 119d and the low-concentration impurity regions 120a to 120d are formed by adding an impurity element imparting n-type conductivity in a self-aligned manner by an ion implantation method or an ion doping method. can do.

  Note that here, a configuration in which the TFTs 111 to 114 include low-concentration impurity regions 120a to 120d and sidewalls 118a to 118d is shown; however, the present invention is not limited to this configuration. If not necessary, the low-concentration impurity region and the sidewall need not be provided.

  Moreover, a well-known organic-semiconductor material can be used suitably as a semiconductor layer. As a typical example, a π-electron conjugated polymer material whose skeleton is composed of conjugated double bonds is desirable. Typically, a soluble polymer material such as polythiophene, poly (3-alkylthiophene), a polythiophene derivative, or pentacene can be used.

  In addition, a semiconductor layer can be formed by processing after forming a soluble precursor. Examples of the organic semiconductor material that passes through such a precursor include polythienylene vinylene, poly (2,5-thienylene vinylene), polyacetylene, a polyacetylene derivative, and polyarylene vinylene.

    When converting the precursor into an organic semiconductor, a reaction catalyst such as hydrogen chloride gas is added as well as heat treatment. Typical solvents for dissolving these soluble organic semiconductor materials include toluene, xylene, chlorobenzene, dichlorobenzene, anisole, chloroform, dichloromethane, γ-butyllactone, butyl cellosolve, cyclohexane, NMP (N-methyl-2 -Pyrrolidone), cyclohexanone, 2-butanone, dioxane, dimethylformamide (DMF), THF (tetrahydrofuran), or the like can be applied.

  In addition, an insulating layer 123 is provided so as to cover the TFTs 111 to 114 and the insulating layer 122 functioning as a passivation film, and these insulating layers 123 are provided to planarize the surface. The conductive layers 124 a to 124 d functioning as source wirings or drain wirings are in contact with the source and drain regions 119 a to 119 d and fill contact holes provided in the insulating layers 122 and 123. In addition, a conductive layer 125a functioning as an antenna is formed with the conductive layers 124a to 124d functioning as source wirings or drain wirings. The conductive layer 125 a is connected to the conductive layer 124 c that functions as a source wiring or a drain wiring of the TFT 113. Insulating layers 126 and 127 are provided so as to cover the conductive layers 124 a to 124 d and 125. These insulating layers 126 and 127 are provided for the purpose of flattening the surface and for protecting the TFTs 111 to 114 and the conductive layers 124 a to 124 d and 125.

  In the TFTs 111 to 114, at least the TFTs 113 and 114 have characteristics of 1 MHz or higher, preferably 10 MHz or higher (at 3 to 5 V) at the ring oscillator (9-stage inverter) level. Alternatively, the frequency characteristic per gate is 100 kHz or more, preferably 1 MHz or more (at 3 to 5 V).

  Note that, as will be described later, depending on the structure of the memory element 134 stacked over the TFTs 111 to 114, data is written by an optical action using laser light. In that case, in order to protect the TFTs 111 to 114 from laser light, the insulating layer 127 and the insulating layer 135 to be formed later are formed using an insulating material having a light-blocking property. The insulating material having a light-shielding property is, for example, a material obtained by adding carbon particles, metal particles, pigments, coloring agents, and the like to a known insulating material and stirring, and then performing filtration as necessary, or It is a material to which a surfactant or a dispersant is added so that carbon particles and the like are uniformly mixed. Such an insulating material is preferably formed by a spin coating method.

  In addition, the memory element 134 is provided over the insulating layer 127. The memory element is characterized in that it overlaps part or all of the TFT 112. With this structure, memory elements can be integrated with high density in a semiconductor device with a small area.

  A first conductive layer 131, an organic compound layer or phase change layer 132, and a second conductive layer 133 are sequentially stacked over the insulating layer 127, and this stacked body corresponds to the memory element 134. An insulating layer 135 is provided between adjacent organic compound layers or phase change layers 132. The first conductive layer 131 is connected to the conductive layer 124 b that functions as a source wiring or a drain wiring of the TFT 112. An insulating layer 136 is provided over the second conductive layer 133. Note that the TFT 112 functions as a TFT for switching the memory element.

  Next, a cross section of a semiconductor device having a passive memory circuit instead of a memory circuit in which a switching TFT is provided in each memory element in FIG. 1A, that is, a semiconductor device having an active matrix memory circuit. The structure will be described with reference to FIG. More specifically, a cross-sectional structure of a semiconductor device in which the structure of the memory element 134 and the TFT connected to the memory element 134 are different from those of the semiconductor device illustrated in FIG.

  A first conductive layer 151 is provided over the insulating layer 127 so as to be connected to the conductive layer 124 a functioning as a source wiring or a drain wiring of the TFT 111, and an organic compound layer or a phase is in contact with the first conductive layer 151. A change layer 152 is provided, and a second conductive layer 153 is provided so as to be in contact with the organic compound layer or the phase change layer 152. A stacked body of the first conductive layer 151, the organic compound layer or phase change layer 152, and the second conductive layer 153 corresponds to the memory element 154. An insulating layer 155 is provided between adjacent organic compound layers or phase change layers 152. An insulating layer 156 is provided over the memory element 154.

Note that the first conductive layer 151 functions as a common electrode, and the plurality of memory elements 154 are formed using the first conductive layer 151.

  In the memory element 154 illustrated in FIG. 1B, the switching TFT is not connected to each memory element 154, and is directly connected to the TFT 111 that forms a circuit for operating the memory element.

1A and 1B illustrate a cross-sectional view of a semiconductor device in which an element formation layer 101a including a plurality of transistors is formed over a substrate, the invention is not limited to this. For example, after a separation layer is provided over a substrate and an element formation layer 101a including a plurality of transistors is formed over the separation layer, the element formation layer 101a including a plurality of transistors is separated from the separation layer, and FIG. As illustrated, an element formation layer 101a including a plurality of transistors may be attached to the substrate 200a with an adhesive layer 201 interposed therebetween. As a peeling method, (1) a metal oxide film is provided between a substrate and an element formation layer having a plurality of transistors, the metal oxide film is weakened by crystallization, and an element formation layer having the plurality of transistors is formed. (2) An amorphous silicon film containing hydrogen is provided between a substrate and an element formation layer having a plurality of transistors, and the amorphous silicon film is removed by laser light irradiation or etching. (3) A method for removing the element formation layer having a plurality of transistors, (3) a method for mechanically removing the substrate on which the element formation layer having a plurality of transistors is formed, or removing the substrate by etching with a solution; 4) A peeling layer and a metal oxide film are provided between the substrate and an element formation layer having a plurality of transistors, the metal oxide film is weakened by crystallization, and a part of the peeling layer is dissolved in a solution or After removing by etching with gas F _3, etc., may be used a method in which physically separated in the metal oxide film which is weakened.

  The substrate 200a is preferably a flexible, thin and light plastic substrate. Specifically, PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PES (polyethersulfone), polypropylene A substrate made of polypropylene sulfide, polycarbonate, polyetherimide, polyphenylene sulfide, polyphenylene oxide, polysulfone, polyphthalamide, or the like can be used. Adhesive synthesis with laminate film (made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, etc.), paper made of fibrous materials, base film (polyester, polyamide, inorganic vapor deposition film, paper, etc.) A laminated film with a resin film (acrylic synthetic resin, epoxy synthetic resin, or the like) can also be used.

  The laminate film is subjected to sealing treatment with the object to be processed by thermocompression bonding. When the sealing treatment is performed, the laminate film is provided on the outermost layer of the laminate film or on the outermost layer. The layer (not the adhesive layer) is melted by heat treatment and bonded by pressure. An adhesive layer may be provided on the surface of the substrate 200a, or an adhesive layer may not be provided.

  The adhesive layer 201 is a layer including an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, and a resin additive.

  As described above, when the element formation layer 101a including a plurality of peeled transistors is bonded to a flexible, thin and light plastic substrate, a semiconductor device that is thin, light, and difficult to break even when dropped is obtained. Can be provided. In addition, it can be bonded on a curved surface or an irregular shape, realizing a wide variety of uses. For example, the semiconductor device of the present invention can be closely attached to a curved surface such as a medicine bottle. Furthermore, if the substrate is reused, an inexpensive semiconductor device can be provided.

  Alternatively, as illustrated in FIG. 2B, a conductive layer 215a functioning as an antenna may be formed using the conductive layer formed at the same time as the first conductive layer 131 of the memory element 134. At this time, the conductive layer 215 functioning as an antenna is connected to the conductive layer 124c functioning as a source wiring or a drain wiring.

  Further, as illustrated in FIG. 2C, a conductive layer 225a functioning as an antenna may be formed using a conductive layer formed at the same time as the second conductive layer 133 of the memory element 134. At this time, the conductive layer 225a functioning as an antenna is connected to the conductive layer 124c functioning as a source wiring or a drain wiring through the conductive layer 214.

  Note that the semiconductor device illustrated in FIGS. 2A to 2C includes a passive matrix memory circuit including a memory element in which a switching TFT is not provided in each memory element as illustrated in FIG. It is also possible to apply to a semiconductor device having

  The semiconductor device of the present invention has a structure in which a memory element is stacked over an element formation layer having a plurality of TFTs. With the above characteristics, a small semiconductor device can be provided. In addition, since the conductive layer functioning as an antenna is formed at the same time as the source wiring or drain wiring of the TFT or the conductive layer of the memory element, the number of steps can be reduced and throughput can be improved. is there.

  In the semiconductor device having the above structure, the memory element has a simple structure in which an organic compound layer or a phase change layer is sandwiched between a pair of conductive layers (a first conductive layer and a second conductive layer). And With the above characteristics, since the manufacturing is simple, an inexpensive semiconductor device and a manufacturing method thereof can be provided. In addition, since high integration is easy, a semiconductor device having a large-capacity memory circuit and a manufacturing method thereof can be provided.

  Further, a memory circuit included in the semiconductor device of the present invention writes data by an optical action or an electrical action, is nonvolatile, and can additionally write data. With the above feature, forgery due to rewriting can be prevented, and new data can be added and written. Accordingly, it is possible to provide a semiconductor device that achieves high functionality and high added value and a manufacturing method thereof.

(Embodiment 2)
In this embodiment mode, a structure of a semiconductor device of the present invention which is different from that of the above embodiment mode will be described with reference to FIGS.

  As shown in FIG. 7B, the semiconductor device of this embodiment includes an element formation layer 301a having a plurality of transistors formed over a first substrate 100a and an antenna formed over a second substrate 300a. And the element formation layer 302a including the conductive layer 105 functioning as an adhesive layer.

  Here, the element formation layer 301a having a plurality of transistors is typically formed of regions 102 and 103 having a plurality of TFTs and a region 104 having a memory element. In addition, the conductive layer 105 functioning as an antenna formed in the element formation layer 302a is connected to a region 102 including a plurality of TFTs included in the communication circuit formed in the element formation layer 301a with conductive particles (not shown). ing.

  A cross-sectional structure of the semiconductor device of the present invention having the structure shown in FIG. 7B is described with reference to FIG.

  As shown in FIG. 3A, the semiconductor device of this embodiment is formed on the second substrate 300a and the element formation layer 301a including a plurality of transistors and memory elements formed on the first substrate 100a. The element formation layer 302a including the conductive layer 303a functioning as the antenna is bonded to the adhesive layer 306.

  The element formation layer 301a including a plurality of TFTs and memory elements includes TFTs 111 to 114. The structures of these TFTs 111 to 114 are as described above, and the memory element 134 can be formed using the same structure as the memory element 134 illustrated in FIG. By superimposing all of them, memory elements can be integrated with high density in a semiconductor device with a small area.

  An element formation layer 301 a having a plurality of TFTs 111 to 114 and a memory element 134 formed on the substrate 100 a and an element formation layer 302 a having a conductive layer 303 formed on the substrate 300 a are bonded to an adhesive layer 306 containing conductive particles 305. Are pasted together. In addition, the conductive layer 124 c functioning as a source wiring or a drain wiring of the TFT 113 is connected to the conductive layer 224 through the conductive layer 214. The conductive layer 224 functions as a connection terminal. The conductive layer 214 is a conductive layer formed at the same time as the first conductive layer 131 of the memory element 134. The conductive layer 224 is a conductive layer formed at the same time as the second conductive layer 133 of the memory element 134. Further, the conductive layer 224 functioning as a connection terminal and the conductive layer 303 functioning as an antenna are electrically connected through conductive particles 305.

  Note that the second substrate 300a provided with the conductive layer 303 functioning as an antenna can be a substrate similar to the substrate 200a. Alternatively, the insulating layer 307 may be formed on the surfaces of the substrate 300a and the conductive layer 303. However, the conductive layer 303 is exposed in a region connected to the conductive layer 224 functioning as a connection terminal of the TFT 113.

    The adhesive layer 306 includes an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, and a resin additive, and the conductive particles 305 are dispersed. Such an adhesive is called an anisotropic conductive adhesive. The conductive particles 305 are formed of one element or a plurality of elements selected from gold, silver, copper, palladium, or platinum. Moreover, the particle | grains which have the multilayer structure of these elements may be sufficient. When the diameter of the conductive particles 305 is 1 to 100 nm, preferably 5 to 50 nm, one or a plurality of conductive particles 305 and the conductive layers 303 and 224 are connected. In this case, the distance between the conductive layer 303 and the conductive layer 224 is maintained by one or a plurality of conductive particles 305.

  As shown in FIG. 37, an adhesive layer 306 including conductive particles 308 having a diameter of 0.5 to 10 μm, preferably 1 to 5 μm may be used. In this case, the conductive layer 303 and the conductive layer 224 are connected by conductive particles 309 having a shape squeezed in the vertical direction. At this time, the space between the conductive layer 303 and the conductive layer 224 is held by the crushed conductive particles 309.

Alternatively, conductive particles in which a thin film formed of one element selected from gold, silver, copper, palladium, or platinum or a plurality of elements may be used on the surface of particles formed of resin. . Furthermore, instead of the anisotropic conductive adhesive, an anisotropic conductive film formed in a film shape on the base film may be transferred and used. In the anisotropic conductive film, conductive particles similar to the anisotropic conductive adhesive are dispersed.

  In the memory element 134 illustrated in FIG. 3A, a switching TFT 112 is provided in each memory element 134. In other words, the semiconductor device includes an active matrix memory circuit. Note that as illustrated in FIG. 3B, a memory element 154 including a first conductive layer 151, an organic compound layer or phase change layer 152, and a second conductive layer 153 can be provided. In this structure, as in FIG. 1B, each switching TFT is not connected to the memory element 154 but is directly connected to the TFT 111. In addition, the first conductive layer 151 functions as a common electrode, a plurality of memory elements 154 are formed using the first conductive layer 151, and is a semiconductor device having a passive matrix memory circuit.

  Furthermore, also in this embodiment, as illustrated in FIG. 2A, an element formation layer 301a including a plurality of transistors may be provided over the substrate 200a with the adhesive layer 201 interposed therebetween.

  The semiconductor device of the present invention has a structure in which a layer including a memory element is stacked over an element formation layer having a plurality of TFTs. With the above characteristics, a small semiconductor device can be provided. In addition, the step of forming an element formation layer having a plurality of transistors and memory elements and the step of forming a conductive layer functioning as an antenna can be performed independently and in parallel. Therefore, the present invention can manufacture a semiconductor device efficiently in a short time. In addition, when each of the element formation layers having a plurality of transistors and the antennas are formed, the performance of each circuit is confirmed and selected to electrically connect the element formation layers having a plurality of transistors and the antennas. A semiconductor device can be completed. Therefore, the rate at which defective products are produced can be suppressed, and the yield can be improved.

(Embodiment 3)
In this embodiment, a cross-sectional structure of a semiconductor device of the present invention, which is different from the structure of the above embodiment, will be described with reference to FIGS. More specifically, as compared with the semiconductor device illustrated in FIGS. 3A and 3B, a cross-sectional structure of a semiconductor device in which a substrate on which an element formation layer 402a including a memory element is formed is attached instead of a conductive layer having an antenna explain.

  As shown in FIG. 7C, the semiconductor device of this embodiment includes an element formation layer 401a including a plurality of transistors formed over the first substrate 100a and a memory formed over the second substrate 400a. An element formation layer 402a including elements is bonded to each other with an adhesive layer.

  Here, the element formation layer 401a including a plurality of transistors typically includes regions 102 and 103 each including a plurality of TFTs, and a conductive layer 125a functioning as an antenna. In addition, the element formation layer 402a including a memory element includes a region 104 including a memory element. In addition, the region 104 having a memory element is connected to a region 103 including a plurality of TFTs constituting a control circuit, an interface, and the like by conductive particles (not shown).

  A cross-sectional structure of the semiconductor device of the present invention having the structure shown in FIG. 7C is described with reference to FIGS.

  As shown in FIG. 4A, an element formation layer 401a including a conductive layer functioning as an antenna and a plurality of transistors is formed over a substrate 100a, and an element formation including a conductive layer functioning as an antenna and a plurality of transistors is formed. The layer 401a includes TFTs 111, 113, and 114, and the structure of these TFTs is as described above. In addition, an element formation layer 402a including a memory element is formed over the substrate 400a. In FIG. 4A, switching TFTs 412a and 412b are connected to the memory elements 434a and 434b, respectively. In other words, the first conductive layers 431a and 431b of the memory element are connected to one of the source wiring and the drain wiring of the switching TFTs 412a and 412b. The other of the source wiring and the drain wiring of the switching TFTs 412a and 412b is connected to a conductive layer formed at the same time as the first conductive layer or the second conductive layer of the memory element. Here, the other of the conductive layer 424 functioning as a source wiring or a drain wiring is connected to the conductive layer 426 through the conductive layer 425. Note that the conductive layer 425 is a conductive layer formed at the same time as the first conductive layers 431a and 431b of the memory element, and the conductive layer 426 is a conductive layer formed at the same time as the second conductive layers 433a and 433b of the memory element. Is a layer.

In addition, an element formation layer 401 a including a plurality of transistors and an element formation layer 402 a including a memory element are bonded to each other with an adhesive layer 306.

  The conductive layer 424 functioning as a source wiring or a drain wiring of the TFT 412a for switching the memory element and the conductive layer 124a functioning as a source wiring or a drain wiring of the TFT 111 constituting a circuit for operating the memory element are conductive. The particles 305 and the conductive layers 421, 425, and 426 are electrically connected to each other.

  Note that depending on the structure of the memory element, data may be written to the element formation layer 402a including the memory element by an optical action using a laser beam. In such a case, in the element formation layer 402a having a memory element, it is necessary to perform layout so that the switching TFTs 412a and 412b and the memory elements 434a and 434b each have a non-overlapping region.

Memory elements 434a and 434b shown in FIG. 4A are connected to switching TFTs 412a and 412b, respectively. That is, an active matrix semiconductor device. Note that as illustrated in FIG. 4B, a substrate including a memory element 454 including a first conductive layer 451, an organic compound layer or phase change layer 452, and a second conductive layer 453 can be attached. It is. The first conductive layer 451, the organic compound layer or phase change layer 452, and the second conductive layer 453 include the first conductive layer 151 described in Embodiment 1, the organic compound layer or phase change layer 152, and A structure similar to that of the second conductive layer 153 can be used. In this structure, as in FIG. 1B, each switching TFT is not connected to the memory element 454, and is connected to the TFT 111 constituting a circuit for operating the memory element via the conductive particles 305. Yes. In addition, the first conductive layer 451 functions as a common electrode, a plurality of memory elements 454 are formed using the first conductive layer 451, and is a semiconductor device having a passive matrix memory circuit.

  In the above embodiment, a circuit for operating a memory element is formed in the element formation layer 401a including a plurality of transistors; however, the present invention is not limited to this. For example, a circuit for operating a memory element may be formed in the element formation layer 402a including the memory element. Specifically, as illustrated in FIG. 8A, the TFT 811 which forms a circuit for operating the memory element is formed over the substrate 400a together with the memory elements 434a and 434b, and then an element formation layer 402a including the memory element is formed. Alternatively, the element formation layer 401 a including a plurality of transistors may be bonded to the adhesive layer 306 including the conductive particles 305. At this time, one of the conductive layers 424 functioning as a source wiring or a drain wiring of the TFT 811 constituting a circuit for operating the memory element and one of the conductive layers 124a functioning as a source wiring or a drain wiring of the TFT 114 are electrically conductive particles. 305 and the conductive layers 825, 826, and 827 are electrically connected. Note that the conductive layer 826 is connected to one of the conductive layers 424 functioning as a source wiring or a drain wiring of the TFT 811 through the conductive layer 825. The conductive layer 826 is a conductive layer formed at the same time as the second conductive layer of the memory element, and the conductive layer 825 is a conductive layer formed at the same time as the first conductive layer of the memory element.

  4A, the element formation layer 402a including a memory element has a structure formed over the substrate 400a. However, as illustrated in FIG. 8B, the adhesive layer 834 is formed over the substrate 800a. An element formation layer 402a including a memory element may be attached to the substrate.

  The semiconductor device of the present invention has a structure in which a layer including a memory element is bonded to an element formation layer having a plurality of transistors and a conductive layer that functions as an antenna. Can be provided. In addition, the step of forming an element formation layer having a plurality of transistors and the step of forming an element formation layer having a memory element can be performed independently and in parallel. Therefore, the present invention can manufacture a semiconductor device efficiently in a short time. In addition, when each of the element formation layer having a plurality of transistors and the memory element is formed, the performance of each element is confirmed and selected, and the element formation layer having a plurality of transistors and the memory element are electrically connected. A semiconductor device can be completed. Therefore, the rate at which defective products are produced can be suppressed, and the yield can be improved.

(Embodiment 4)
In this embodiment, a cross-sectional structure of the semiconductor device of the present invention, which is different from the structure of the above embodiment, will be described. More specifically, a cross-sectional structure of a semiconductor device in which a substrate including a layer including a memory element and an antenna is bonded to an element formation layer including a plurality of transistors will be described with reference to FIGS. .

  As shown in FIG. 7D, the semiconductor device of this embodiment includes an element formation layer 501a having a plurality of transistors formed over the first substrate 100a and a memory formed over the second substrate 500a. An element formation layer 502a including an element and an antenna has a structure in which the adhesive layer is attached to the element formation layer 502a.

  Here, the element formation layer 501a including a plurality of transistors typically includes regions 102 and 103 each including a plurality of TFTs. In addition, the element formation layer 502a including a memory element and an antenna includes a region 104 including a memory element and a conductive layer 105 functioning as an antenna. In addition, the region 104 having a memory element is connected to a region 103 including a plurality of TFTs constituting a control circuit, an interface, and the like by conductive particles (not shown). In addition, the conductive layer 105 functioning as an antenna is connected to a region 102 including a plurality of TFTs constituting a communication circuit with conductive particles (not shown).

  A cross-sectional structure of the semiconductor device of the present invention having the structure shown in FIG. 7D is described with reference to FIGS.

  As shown in FIG. 5A, an element formation layer 501a having a plurality of TFTs has TFTs 111, 113, and 114, and the structure of these TFTs is as described above. In addition, an element formation layer 502 including a memory element 434 and a conductive layer 525 functioning as an antenna is formed over the substrate 500a. In FIG. 5A, a switching TFT 412 is connected to the memory element 434. That is, the first conductive layer of the memory element 434 is connected to one of the source wiring and the drain wiring of the switching TFT 412.

  The other of the source wiring and the drain wiring of the switching TFT 412 is connected to a conductive layer 425 formed at the same time as the first conductive layer or the second conductive layer of the memory element. Here, the other of the conductive layer 424 functioning as a source wiring or a drain wiring is connected to the conductive layer 426 through the conductive layer 425. Note that the conductive layer 426 is a conductive layer formed at the same time as the second conductive layer of the memory element 434 and functions as a connection terminal.

  Further, the conductive layer 424 functioning as a source wiring or a drain wiring of the TFT 412 and the conductive layer 124a functioning as a source wiring or a drain wiring of the TFT 111 are electrically connected through the conductive layers 421, 425, and 426 and the conductive particles 305. Has been.

  In addition, a conductive layer 525 functioning as an antenna is formed at the same time as the first conductive layer or the second conductive layer of the memory element 434. The conductive layer 525 is electrically connected to the conductive layer 124 c functioning as a source wiring or a drain wiring of the TFT 113 through the conductive particles 305 and the conductive layer 521. In addition, the conductive layer 521 functions as a connection terminal for connecting to the conductive layer 525 functioning as an antenna.

  Note that depending on the structure of the memory element, data may be written to the memory element 434 by an optical action using a laser beam. In such a case, in the element formation layer 502a including the memory element and the antenna, it is necessary to perform layout so that the switching TFT 412 and the memory element 434, and the conductive layer 424 and the memory element 434 have regions that do not overlap with each other. It is.

  A memory element 434 illustrated in FIG. 5A is connected to the switching TFT 412. That is, an active matrix semiconductor device. Note that as illustrated in FIG. 5B, a substrate 500 including a memory element 454 including a first conductive layer 451, an organic compound layer or phase change layer 452, and a second conductive layer 453 may be attached. Is possible. The first conductive layer 451, the organic compound layer or phase change layer 452, and the second conductive layer 453 include the first conductive layer 151 described in Embodiment 1, the organic compound layer or phase change layer 152, and A structure similar to that of the second conductive layer 153 can be used. In this structure, as in FIG. 1B, the semiconductor device includes a passive matrix memory circuit.

  In addition, the TFT 111 which forms a circuit for operating the memory element is formed in the element formation layer 501a including a plurality of transistors; however, the structure is not limited thereto. A circuit for operating the memory element may be formed in the element formation layer including the memory element and the antenna. In FIG. 5A, an element formation layer 502a having a memory element and an antenna has a structure formed over a substrate 500a. However, an element having a memory element and an antenna is formed over the substrate through an adhesive layer. The formation layer 502a may be attached. Further, although the element formation layer 501a including a plurality of transistors is formed over the substrate 100a, as illustrated in FIG. 2A, the element formation layer 501a including a plurality of transistors is formed over the substrate 200a with an adhesive layer interposed therebetween. May be pasted together.

  A semiconductor device according to the present invention has a structure in which an element formation layer including a memory element and an antenna is stacked via an adhesive layer on an element formation layer having a plurality of TFTs. An apparatus can be provided. In addition, the step of forming an element formation layer having a plurality of transistors and the step of forming an element formation layer having a memory element and an antenna can be performed independently and in parallel. Therefore, the present invention can manufacture a semiconductor device efficiently in a short time. In addition, when each of the element formation layer having a plurality of transistors, the storage element, and the antenna is formed, the performance of each element is confirmed and selected to electrically connect the element formation layer, the storage element, and the antenna having a plurality of transistors. Thus, the semiconductor device can be completed. Therefore, the rate at which defective products are produced can be suppressed, and the yield can be improved.

(Embodiment 5)
In this embodiment, a cross-sectional structure of the semiconductor device of the present invention, which is different from the structure of the above embodiment, will be described. More specifically, a cross-sectional structure of a semiconductor device in which an element formation layer 602a including a memory element is mounted over a substrate 100a over which an element formation layer 601a including a plurality of transistors is formed is described with reference to FIGS. explain.

  As shown in FIG. 7E, the semiconductor device of this embodiment includes an element formation layer 601a having a plurality of transistors formed over a substrate 100a and an element formation layer 602a having a memory element over the substrate 100a. It has a structure in which the adhesive layer 611 is attached.

  Here, the element formation layer 601a including a plurality of transistors is typically formed using regions 102 and 103 each including a plurality of TFTs and a conductive layer 105 functioning as an antenna. In addition, the element formation layer 602a including a memory element includes a region 104 including a memory element. In addition, the region 104 having a memory element is electrically connected to a region 103 including a plurality of TFTs constituting a control circuit, an interface, and the like using a conductive member 631.

  A cross-sectional structure of the semiconductor device of the present invention having the structure shown in FIG. 7E is described with reference to FIGS.

  As shown in FIG. 6A, the element formation layer 601a having a plurality of TFTs has TFTs 111, 113, and 114, and the structure of these TFTs is as described above. In addition, a substrate 621a over which an element formation layer 602a including a memory element is formed is mounted over the substrate 100a using an adhesive layer 611. In FIG. 6A, a switching TFT 112 is connected to the memory element 634. That is, the first conductive layer of the memory element is connected to one of the source wiring and the drain wiring of the switching TFT 112. The other of the source wiring and the drain wiring of the switching TFT 112 is connected to a conductive layer formed simultaneously with the first conductive layer or the second conductive layer of the memory element. Here, the other of the conductive layer 124 b functioning as a source wiring or a drain wiring is connected to the conductive layer 626 through the conductive layer 625. Note that the conductive layer 625 is a conductive layer formed at the same time as the first conductive layer of the memory element, and the conductive layer 626 is a conductive layer formed at the same time as the second conductive layer of the memory element. Function as.

  Further, a switching TFT 112 of the memory element 634 formed in the element formation layer 602a having a memory element, and a TFT 111 constituting a circuit for operating the memory element formed in the element formation layer 601a having a plurality of TFTs, They are electrically connected by a conductive member 631. Here, the conductive member 631 is a wire and the TFT 111 and the TFT 112 are connected by a wire bonding method. However, after the conductive film is formed, the conductive member 631 may be formed by etching into a desired shape. Good. Furthermore, a connection method such as a printing method can be used.

  A memory element 634 illustrated in FIG. 6A is connected to the switching TFT 112. That is, an active matrix semiconductor device. Note that as illustrated in FIG. 6B, a substrate 622 over which a memory element 654 including the first conductive layer 651, the organic compound layer or phase change layer 652, and the second conductive layer 653 is formed is bonded. It is also possible to mount on the substrate 100a using the layer 611. In this structure, the semiconductor device includes a passive matrix memory circuit.

  In this embodiment, the element formation layer 602a having a memory element is mounted over the substrate 100a. However, the present invention is not limited to this, and the element formation layer having a memory element and an antenna or the element formation layer having an antenna is attached to the substrate 100a. It may be mounted on top.

  The semiconductor device of the present invention includes an element formation layer having a plurality of TFTs and a layer including a memory element over the same substrate. With the above characteristics, a small semiconductor device can be provided. In addition, the step of forming an element formation layer having a plurality of transistors and the step of forming an element formation layer having a memory element can be performed independently and in parallel. Therefore, the present invention can manufacture a semiconductor device efficiently in a short time. In addition, when each of the element formation layer having a plurality of transistors and the memory element is formed, the performance of each element is confirmed and selected, and the element formation layer having a plurality of transistors and the memory element are electrically connected. A semiconductor device can be completed. Therefore, the rate at which defective products are produced can be suppressed, and the yield can be improved.

(Embodiment 6)
In this embodiment, a method for manufacturing a semiconductor device will be described with reference to drawings. Here, a method for manufacturing the semiconductor device illustrated in FIG. 2A of Embodiment 1 is described; however, this embodiment can be appropriately applied to each semiconductor device described in each embodiment.

  As shown in FIG. 9A, release layers 1101 and 1102 are formed on one surface of a substrate 1100.

  As the substrate 1100, a glass substrate, a quartz substrate, a metal substrate, a stainless steel substrate with an insulating layer formed on one surface, a heat-resistant plastic substrate that can withstand the processing temperature in this step, or the like is used. Since there is no restriction on the size or shape of the substrate 1100 listed above, for example, if a substrate having a side of 1 meter or more and a rectangular shape is used as the substrate 1100, productivity is remarkably improved. Can do. This advantage is a great advantage compared to the case of using a circular silicon substrate.

  In addition, the element formation layer including a plurality of transistors provided over the substrate 1100 is peeled off from the substrate 1100 later. Therefore, the element formation layer having a plurality of transistors may be newly formed over the substrate 1100 by reusing the substrate 1100. As a result, cost can be reduced. Note that a quartz substrate is preferably used as the substrate 1100 to be reused.

  The peeling layers 1101 and 1102 are formed by forming a thin film over one surface of the substrate 1100 and then selectively etching the resist using a resist mask formed by a photolithography method. The separation layers 1101 and 1102 are formed by sputtering, plasma CVD, or the like using tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), or cobalt (Co). , An element selected from zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), lead (Pb), osmium (Os), iridium (Ir), silicon (Si), or the element A layer made of an alloy material containing the main component or a compound material containing the element as a main component is formed as a single layer or stacked layers. The crystal structure of the layer containing silicon may be any of amorphous, microcrystalline, and polycrystalline.

  In the case where the separation layers 1101 and 1102 have a single-layer structure, a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum is preferably formed. Alternatively, a layer containing tungsten oxide or oxynitride, a layer containing molybdenum oxide or oxynitride, or a layer containing an oxide or oxynitride of a mixture of tungsten and molybdenum is formed. Note that the mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum.

  In the case where the separation layers 1101 and 1102 have a stacked structure, preferably, a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum is formed as a first layer, and tungsten, molybdenum, or tungsten and molybdenum is formed as a second layer. An oxide, nitride, oxynitride or nitride oxide of the mixture is formed.

In the case where a stacked structure of a layer containing tungsten and a layer containing an oxide of tungsten is formed as the separation layers 1101 and 1102, a layer containing tungsten is formed, and a layer containing silicon oxide is formed thereover. The fact that a layer containing an oxide of tungsten is formed at the interface between the layer and the silicon oxide layer may be utilized. Further, the surface of the layer containing tungsten is subjected to thermal oxidation treatment, oxygen plasma treatment, N ₂ O plasma treatment, treatment with a solution having strong oxidizing power such as ozone water, and the like to form a layer containing tungsten oxide. May be. The same applies to the case where a layer containing tungsten nitride, oxynitride, and nitride oxide is formed. After a layer containing tungsten is formed, a silicon nitride layer, a silicon oxynitride layer, and a silicon nitride oxide layer are formed thereon. A layer may be formed.

The oxide of tungsten is represented by WOx. X is in the range of 2 ≦ X ≦ 3, when x is 2 (WO ₂ ), when x is 2.5 (W ₂ O ₅ ), when x is 2.75 (W ₄ O ₁₁ ) X is 3 (WO ₃ ). In forming the tungsten oxide, the value of X mentioned above is not particularly limited, and may be determined based on the etching rate. However, the layer having the best etching rate is a layer containing tungsten oxide (WOx, 0 <X <3) formed by a sputtering method in an oxygen atmosphere. Therefore, in order to shorten the manufacturing time, a layer containing a tungsten oxide is preferably formed as the separation layer by a sputtering method in an oxygen atmosphere.

  Further, according to the above steps, the release layers 1101 and 1102 are formed so as to be in contact with the substrate 1100, but the present invention is not limited to this step. An insulating layer serving as a base may be formed so as to be in contact with the substrate 1100 and the peeling layers 1101 and 1102 may be provided so as to be in contact with the insulating layer.

  Next, as illustrated in FIG. 9B, an insulating layer 1105 serving as a base is formed so as to cover the separation layers 1101 and 1102. The insulating layer 1105 is formed as a single layer or a stacked layer including a silicon oxide or a silicon nitride by a known means (such as a sputtering method or a plasma CVD method). The silicon oxide material is a substance containing silicon (Si) and oxygen (O), and corresponds to silicon oxide, silicon oxynitride, silicon nitride oxide, or the like. The silicon nitride material is a substance containing silicon and nitrogen (N), and corresponds to silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. The insulating layer serving as a base functions as a blocking film that prevents impurities from entering from the substrate 1100.

  Next, an amorphous semiconductor layer (eg, a layer containing amorphous silicon) is formed over the insulating layer 1105. This amorphous semiconductor layer is formed with a thickness of 25 to 200 nm (preferably 30 to 150 nm) by a known means (sputtering method, LPCVD method, plasma CVD method or the like). Subsequently, a known crystallization method (laser crystallization method, thermal crystallization method using an RTA or furnace annealing furnace, thermal crystallization method using a metal element that promotes crystallization, and crystallization are promoted. A crystalline semiconductor layer is formed by crystallization by a combination of a thermal crystallization method using a metal element to be combined and a laser crystallization method). After that, the obtained crystalline semiconductor layer is etched into a desired shape to form crystalline semiconductor layers 1127 to 1130. Note that in the case where the separation layers 1101 and 1102 are tungsten, an oxide of tungsten can be formed at the interface between the separation layers 1101 and 1102 and the insulating layer 1105 by the heat treatment.

  As a specific example of a manufacturing process of the crystalline semiconductor layers 1127 to 1130, first, an amorphous semiconductor layer having a thickness of 66 nm is formed by a plasma CVD method. Next, after a solution containing nickel, which is a metal element for promoting crystallization, is held on the amorphous semiconductor layer, the amorphous semiconductor layer is subjected to dehydrogenation treatment (500 ° C., 1 hour), heat Crystallization treatment (550 ° C., 4 hours) is performed to form a crystalline semiconductor layer. After that, laser light is irradiated as necessary to improve crystallinity, and etching is performed using a resist mask formed by a photolithography method, so that crystalline semiconductor layers 1127 to 1130 are formed.

Note that when the crystalline semiconductor layers 1127 to 1130 are formed by a laser crystallization method, a continuous wave or pulsed gas laser or solid laser is used. As the gas laser, excimer laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, Ti: sapphire laser, or the like is used. As the solid-state laser, a laser using a crystal such as YAG, YVO ₄ , YLF, or YAlO ₃ doped with Cr, Nd, Er, Ho, Ce, Co, Ti, or Tm is used.

  In addition, when an amorphous semiconductor layer is crystallized using a metal element that promotes crystallization, it is possible to crystallize at a low temperature for a short time and the crystal orientation is aligned. Remains in the crystalline semiconductor layer, resulting in an increase in off-current and unstable characteristics. Therefore, an amorphous semiconductor layer functioning as a gettering site is preferably formed over the crystalline semiconductor layer. Since the amorphous semiconductor layer serving as a gettering site needs to contain an impurity element such as phosphorus or argon, it is preferably formed by a sputtering method in which argon can be contained at a high concentration. After that, heat treatment (RTA method or thermal annealing using a furnace annealing furnace) is performed to diffuse the metal element in the amorphous semiconductor layer, and then the amorphous semiconductor layer containing the metal element is removed. To do. Then, the content of the metal element in the crystalline semiconductor layer can be reduced or removed.

  Next, an insulating layer covering the crystalline semiconductor layers 1127 to 1130 is formed. The insulating layer is formed by a single layer or a stack of layers containing silicon oxide or silicon nitride by a plasma CVD method, a sputtering method, or the like. Specifically, a layer containing silicon oxide, a layer containing silicon oxynitride, or a layer containing silicon nitride oxide is formed as a single layer or a stacked layer.

  Next, a first conductive layer and a second conductive layer are stacked over the insulating layer. The first conductive layer is formed with a thickness of 20 to 100 nm by a plasma CVD method or a sputtering method. The second conductive layer is formed with a thickness of 100 to 400 nm by a known means. The first conductive layer and the second conductive layer include tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium ( Nd) or the like or an alloy material or a compound material containing these elements as a main component. Alternatively, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus is used.

  Examples of combinations of the first conductive layer and the second conductive layer include a tantalum nitride (TaN) layer and a tungsten (W) layer, a tungsten nitride (WN) layer and a tungsten layer, and a molybdenum nitride (MoN) layer. A molybdenum (Mo) layer etc. are mentioned. Since tungsten and tantalum nitride have high heat resistance, heat treatment for thermal activation can be performed after the formation of the first conductive layer and the second conductive layer.

  Next, a resist mask is formed using a photolithography method, etching treatment for forming a gate electrode is performed, and conductive layers functioning as gate electrodes (sometimes referred to as gate electrode layers) 1107 to 1110 Form.

  Next, an impurity element imparting N-type conductivity is added to the crystalline semiconductor layers 1127 to 1130 at a low concentration by ion doping or ion implantation to form N-type impurity regions. The impurity element imparting N-type may be an element belonging to Group 15, for example, phosphorus (P) or arsenic (As). Further, an impurity element imparting P-type may be added to form a P-type impurity region. For example, boron (B) is used as the impurity element imparting P-type.

  Next, an insulating layer is formed so as to cover the insulating layer and the conductive layers 1107 to 1110. The insulating layer is formed by a known means (plasma CVD method or sputtering method) such as a layer containing an inorganic material of silicon, silicon oxide or silicon nitride (sometimes referred to as an inorganic layer), or an organic resin. A layer containing an organic material (sometimes referred to as an organic layer) is formed as a single layer or a stacked layer. Preferably, a layer made of an oxide of silicon is formed as the insulating layer.

  Next, the insulating layer is selectively etched by anisotropic etching mainly in the vertical direction to form insulating layers (hereinafter referred to as sidewall insulating layers) 1115 to 1118 in contact with the side surfaces of the conductive layers 1107 to 1110. It is formed (see FIG. 9B). The sidewall insulating layers 1115 to 1117 are used as doping masks for forming a source region and a drain region later.

  Note that the insulating layer is also etched by the etching step for forming the sidewall insulating layers 1115 to 1118 to form gate insulating layers 1119 to 1122. The gate insulating layers 1119 to 1122 overlap with the conductive layers 1107 to 1110 and the sidewall insulating layers 1115 to 1118. Thus, the gate insulating layer is etched because the etching rates of the materials of the gate insulating layer and the sidewall insulating layers 1115 to 1118 are the same. FIG. 9B shows such a case. Yes. Accordingly, when the gate insulating layer and the sidewall insulating layers 1115 to 1118 have different etching rates, the insulating layer may remain even after an etching process for forming the sidewall insulating layers 1115 to 1118. .

  Subsequently, an impurity element imparting N-type conductivity is added to the crystalline semiconductor layers 1127 to 1130 using the sidewall insulating layers 1115 to 1118 as masks, so that first N-type impurity regions (also referred to as LDD regions) 1123a to 1123d. And second N-type impurity regions (also referred to as source region and drain region region) 1124a to 1124d are formed. The concentration of the impurity element contained in the first N-type impurity regions 1123a to 1123d is lower than the concentration of the impurity element in the second N-type impurity regions 1124a to 1124d.

  Note that in order to form the first N-type impurity regions 1123a to 1123d, the gate electrode has a stacked structure of two or more layers, and etching or anisotropic etching is performed so that the gate electrode has a tapered portion. There are a method using a lower conductive layer constituting the gate electrode as a mask and a method using a sidewall insulating layer as a mask. A thin film transistor formed by adopting the former method has a GOLD (Gate Overlapped Lightly Doped Drain) structure. In the present invention, either the former method or the latter method may be used. However, the use of the latter method using the sidewall insulating layer as a mask has an advantage that the LDD region can be reliably formed and the width of the LDD region can be easily controlled.

  Through the above steps, n-type TFTs 1131 to 1134 are completed.

  The n-type TFTs 1131 to 1134 have an LDD structure, and include a first n-type impurity region (also referred to as an LDD region), a second n-type impurity region (also referred to as a source region and a drain region), and a channel formation region. An active layer, a gate insulating layer, and a conductive layer functioning as a gate electrode.

  Next, an insulating layer is formed as a single layer or a stacked layer so as to cover the TFTs 1131 to 1134. The insulating layer covering the TFTs 1131 to 1134 is formed by known means (SOG method, droplet discharge method, etc.), inorganic materials such as silicon oxide and silicon nitride, polyimide, polyamide, benzocyclobutene, acrylic, epoxy, A single layer or a stacked layer is formed using an organic material such as siloxane. With a siloxane-based material, for example, siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  The cross-sectional structure shown in the figure shows a case where two insulating layers are stacked so as to cover the TFTs 1131 to 1134, and a layer containing silicon nitride is formed as the first insulating layer 1142, and the second insulating layer is formed. A layer containing silicon oxide is formed as the layer 1141. Further, a layer containing silicon oxide may be formed over the second insulating layer 1141 as the third insulating layer.

  Note that before the insulating layers 1141 and 1142 are formed or after one or more thin films of the insulating layers 1141 and 1142 are formed, the crystallinity of the semiconductor layer is restored and the activity of the impurity element added to the semiconductor layer is increased. Heat treatment for the purpose of hydrogenation of the semiconductor layer is preferably performed. For the heat treatment, thermal annealing, laser annealing, RTA, or the like is preferably applied.

  Next, as shown in FIG. 9C, the insulating layers 1141 and 1142 are etched by photolithography to form contact holes 1143 to 1150 that expose the second N-type impurity regions 1124a to 1124d.

  Next, as illustrated in FIG. 9D, a conductive layer is formed so as to fill the contact holes 1143 to 1150, and the conductive layer is patterned to form conductive layers 1154 to 1162. The conductive layers 1155 to 1162 function as a source wiring or a drain wiring of the TFT, and the conductive layer 1154 functions as an antenna.

  The conductive layers 1154 to 1162 are formed of an element selected from titanium (Ti), aluminum (Al), and neodymium (Nd) by a plasma CVD method, a sputtering method, or the like, or an alloy material or a compound material containing these elements as a main component Thus, a single layer or a stacked layer is formed. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon.

  The conductive layers 1154 to 1162 employ, for example, a stacked structure of a barrier layer, an aluminum silicon (Al—Si) layer and a barrier layer, a barrier layer, an aluminum silicon (Al—Si) layer, a titanium nitride (TiN) layer, and a barrier layer. Good. Note that the barrier layer corresponds to a layer formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum silicon are suitable materials for forming the conductive layers 1154 to 1162 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. When a lower barrier layer is provided, good contact between aluminum or aluminum silicon and the crystalline semiconductor layer can be obtained. Titanium is a highly reducible element. Therefore, when a barrier layer made of titanium is formed, even if a thin natural oxide film is formed on the crystalline semiconductor layer, this natural oxide film is reduced and crystalline. Good contact can be made with the semiconductor layer.

  Next, as illustrated in FIG. 9E, an insulating layer 1163 is formed as a single layer or a stacked layer so as to cover the conductive layers 1154 to 1162. The insulating layer 1163 covering the conductive layers 1154 to 1162 can be formed using a method and a material similar to those of the insulating layer 1142 covering the thin film transistor. Next, a contact hole is formed in the insulating layer 1163 covering the conductive layers 1154 to 1162, and the first conductive layer 1164 is formed. The conductive layer 1164 functions as a first conductive layer of a memory element to be formed later. Note that the first conductive layer is formed so as to cover the thin film transistor 1132.

  Next, an insulating layer 1165 is formed so as to cover an end portion of the first conductive layer 1164, and then an organic compound layer or phase change layer 1166 and a second conductive layer 1167 are formed. The first conductive layer 1164, the organic compound layer or phase change layer 1166, and the second conductive layer 1167 form a memory element 1169. After that, an insulating layer 1168 may be formed. The insulating layer 1168 corresponds to a layer containing carbon such as DLC (diamond-like carbon), a layer containing silicon nitride, a layer containing silicon nitride oxide, a layer containing an organic material (preferably an epoxy resin), or the like. Note that the insulating layer functions as a protective layer, and may not be formed if not necessary. In addition, when the insulating layer 1168 is formed of a thick layer (typically 5 to 100 μm, preferably 5 to 50 μm, more preferably 5 to 10 μm) of an organic compound, the separation layers 1101 and 1102 are removed. Even after that, a plurality of elements on the substrate 1100 are weighted to prevent scattering from the substrate 1100, and further, without being wound, the element can be prevented from being broken or damaged. Hereinafter, an element formation layer 1170 including a plurality of transistors including the TFTs 1131 to 1134 and the memory element 1169 is described.

  Further, the organic compound layer of the memory element may be formed by a droplet discharge method typified by inkjet. By using a droplet discharge method, it is possible to provide a method for manufacturing a semiconductor device in which the material use efficiency is improved and the manufacturing process is simplified. In addition, a method for manufacturing a semiconductor device that can reduce manufacturing time and manufacturing cost can be provided.

  Next, as illustrated in FIG. 10A, the insulating layers 1105, 1141, 1142, 1163, 1165, and 1168 are etched by a photolithography method so that the separation layers 1101 and 1102 are exposed, whereby openings 1171, 1172 is formed.

Next, as illustrated in FIG. 10B, an etchant is introduced into the openings 1171 and 1172 to remove the peeling layers 1101 and 1102. If the etching agent is wet etching, a mixture of hydrofluoric acid diluted with water or ammonium fluoride, a mixture of hydrofluoric acid and nitric acid, a mixture of hydrofluoric acid, nitric acid and acetic acid, a mixture of hydrogen peroxide and sulfuric acid, hydrogen peroxide And a mixed solution of ammonium water and water, a mixed solution of hydrogen peroxide, hydrochloric acid, and water. In the case of dry etching, a gas containing a halogen atom or molecule such as fluorine or a gas containing oxygen is used. Preferably, a gas or liquid containing halogen fluoride or an interhalogen compound is used as an etchant. For example, chlorine trifluoride (ClF ₃ ) is used as a gas containing halogen fluoride.

  Next, as illustrated in FIG. 10C, the element formation layer 1170 including a plurality of transistors is bonded to the base 1181 after the surface where the memory element is formed, and then the element formation layer 1170 including the plurality of transistors. Is completely peeled from the substrate 1100 (see the cross-sectional view of FIG. 11A).

  The base 1181 can be formed using a material similar to that of the substrate 200a described in Embodiment 1.

Next, as illustrated in FIG. 11B, the other surface of the element formation layer 1170 including a plurality of transistors is bonded to a substrate 1183a with an adhesive 1182a.

  For the substrate 1183a, a material similar to that of the substrate 200a described in Embodiment 1 can be used.

  Next, a structure in which the element formation layer 1170 including a plurality of transistors is bonded to the base 1181 is cut using a slicing device, a laser irradiation device, or the like.

  Through the above steps, a semiconductor device having a function of communicating data without contact is completed.

    In this embodiment mode, the element formation layer 1170 having a plurality of transistors and the substrate 1183 are bonded, and then divided to form a semiconductor device. However, the present invention is not limited to this step. After the element formation layer 1170 including a plurality of transistors and the base 1181 are bonded and divided, the substrate 1183 may be bonded to the element formation layer 1170 including a plurality of transistors.

As described above, since the semiconductor device of the present invention is small, thin, lightweight, and flexible, it can be used in a wide variety of applications, and even when attached to an article, the design of the article may be impaired. Absent.
(Embodiment 7)
The configuration of the semiconductor device of this embodiment will be described with reference to FIGS.

  A perspective view of the semiconductor device of this embodiment is described with reference to FIG. As shown in FIG. 26A, the semiconductor device of this embodiment has a structure in which a plurality of transistors are integrated on a substrate. Here, an element formation layer 101b including a plurality of transistors and an element formation layer 107b including an antenna provided over a substrate 108b are formed. The element formation layer 101b including a memory element and a plurality of transistors is typically Consists of regions 102 and 103 having a plurality of TFTs, and a region 104 having a memory element. Further, an element formation layer 107b including the conductive layer 105 functioning as an antenna is formed over the substrate 108b, and the conductive layer 105 and the adhesive layer are attached to the back surface of the element formation layer 101b including a plurality of transistors. It has a configuration. Here, the back surface of the element formation layer 101b including a plurality of transistors refers to the surface where the insulating layer is exposed.

  Next, a cross-sectional structure of the semiconductor device having the structure illustrated in FIG. 26A will be described with reference to FIG. An element formation layer 101b including a plurality of transistors is provided over the substrate 100b. Here, as the element formation layer 101b having a plurality of circuits, a TFT 111 (a part of the region 104 having the memory element in FIG. 26A) that forms a circuit for operating the memory element, and a TFT 112 for switching the memory element ( TFT 113 which constitutes a circuit for processing a signal received by an antenna such as a power supply circuit, a clock generation circuit, a data demodulation / modulation circuit, etc. (FIG. 26A). The TFT 114 (part of the region 103 having a plurality of TFTs in FIG. 26A) forming a circuit such as a control circuit and an interface is shown.

The element formation layer 101b including a plurality of transistors and the element formation layer 107b including an antenna are attached to each other with an adhesive layer 106. Specifically, the insulating layer 115 and the element formation layer 107 b having an antenna are attached to each other with an adhesive layer 106. In addition, the conductive layer 124c functioning as a source wiring or a drain wiring of the TFT 113 of the element formation layer 101b and the conductive layer 125b functioning as an antenna of the element formation layer 101b are electrically connected through the conductive particles 109 of the adhesive layer 106. It is connected.

  The TFTs 111 to 114 are provided between the substrate 100 b and the insulating layer 115, and an insulating layer 122 that covers the TFTs 111 to 114 is formed.

  In addition, an insulating layer 123 is provided so as to cover the TFTs 111 to 114 and the insulating layer 122 functioning as a passivation film, and these insulating layers 123 are provided to planarize the surface. The conductive layers 124 a to 124 d functioning as source wirings or drain wirings are in contact with the source and drain regions 119 a to 119 d and fill contact holes provided in the insulating layer 123. In addition, one of the conductive layers 124 c functioning as a source wiring or a drain wiring of the TFT 113 passes through the insulating layers 115, 122, and 123 and is exposed on the back surface of the element formation layer 101.

  In addition, insulating layers 126 and 127 are provided so as to cover the conductive layers 124a to 124d and 125b. These insulating layers 126 and 127 are provided for the purpose of flattening the surface and for protecting the TFTs 111 to 114 and the conductive layers 124a to 124d and 125b.

  In addition, the memory element 134 is provided over the insulating layer 127.

  A first conductive layer 131, an organic compound layer or phase change layer 132, and a second conductive layer 133 are sequentially stacked over the insulating layer 127, and this stacked body corresponds to the memory element 134. An insulating layer 135 is provided between adjacent organic compound layers or phase change layers 132. The first conductive layer 131 is connected to the conductive layer 124 b that functions as a source wiring or a drain wiring of the TFT 112. An insulating layer 136 is provided over the conductive layer 133. Note that the TFT 112 functions as a TFT for switching the memory element. In addition, a switching TFT is provided in each of the other memory elements. In this structure, the semiconductor device has an active matrix memory circuit.

  A substrate 100b is provided over the insulating layer 136.

  Next, a cross-sectional structure of a semiconductor device including a memory element that does not include a switching transistor, that is, a semiconductor device including a passive matrix memory circuit, instead of the memory element provided with the transistor in FIG. 27 (B). More specifically, a cross-sectional structure of a semiconductor device in which the structure of the memory element 154 is different from that of the semiconductor device illustrated in FIG.

  A first conductive layer 151 is provided over the insulating layer 127 so as to be connected to the conductive layer 124 a functioning as a source wiring or a drain wiring of the TFT 111, and an organic compound layer or a phase is in contact with the first conductive layer 151. A change layer 152 is provided, and a second conductive layer 153 is provided so as to be in contact with the organic compound layer or the phase change layer 152. A stacked body of the first conductive layer 151, the organic compound layer or phase change layer 152, and the second conductive layer 153 corresponds to the memory element 154. An insulating layer 155 is provided between adjacent organic compound layers or phase change layers 152. An insulating layer 156 is provided over the memory element 154.

  In the semiconductor device of the present invention, the step of forming an element formation layer including a memory element and a plurality of transistors and the step of forming a conductive layer functioning as an antenna can be independently performed in parallel. Therefore, the present invention can manufacture a semiconductor device efficiently in a short time. In addition, when each of the element formation layer having the memory element and the plurality of transistors and the antenna is formed, the performance of each circuit is confirmed and selected to electrically connect the element formation layer having the plurality of transistors and the antenna. Thus, the semiconductor device can be completed. Therefore, the rate at which defective products are produced can be suppressed, and the yield can be improved.

(Embodiment 8)
In this embodiment, a cross-sectional structure of the semiconductor device of the present invention, which is different from the structure of the above embodiment, will be described. More specifically, compared with the semiconductor device illustrated in FIG. 27, a cross-sectional structure of a semiconductor device in which a substrate 200b over which an element formation layer 202b including a memory element is formed is bonded instead of a conductive layer including an antenna Will be described.

  As shown in FIG. 26B, the semiconductor device of this embodiment includes an element formation layer 201b having a plurality of transistors provided over a first substrate 100b and a memory formed over a second substrate 200b. The element formation layer 202b including an element has a structure in which a resin layer is attached.

  Here, the element formation layer 201b including a plurality of transistors typically includes regions 102 and 103 each including a plurality of TFTs, and a conductive layer 105 functioning as an antenna. In addition, the element formation layer 202b including a memory element includes a region 104 including a memory element. In addition, the region 104 having a memory element is connected to a region 103 including a plurality of TFTs constituting a control circuit, an interface, and the like by conductive particles of an adhesive layer (not shown).

  A cross-sectional structure of the semiconductor device of the present invention having the structure shown in FIG. 26B is described with reference to FIG.

  As shown in FIG. 28A, a substrate 100b is provided over an element formation layer 201b including a plurality of transistors having a conductive layer functioning as an antenna, and the element formation layer 201b including a plurality of transistors includes TFTs 111, 113, and 114. The structure of these TFTs is as described above. Further, the conductive layer 124a functioning as the source wiring or drain wiring of the TFT 111 is exposed on the back surface.

  In addition, an element formation layer 202b including a memory element is formed over the substrate 200b. The element formation layer 201 b including a plurality of transistors and the element formation layer 202 b including a memory element are attached to each other with an adhesive layer 106. Specifically, the insulating layer 115 and the element formation layer 202b including a memory element are attached to each other with an adhesive layer 106. In FIG. 28A, switching TFTs 212a and 212b are connected to the memory elements 234a and 234b, respectively. In other words, the first conductive layers 231a and 231b of the memory element are connected to one of the source wiring and the drain wiring of the switching TFTs 212a and 212b. The other of the source wiring and the drain wiring of the switching TFTs 212a and 212b is connected to a conductive layer formed simultaneously with the first conductive layer or the second conductive layer of the memory element. Here, the other of the conductive layer 223 functioning as a source wiring or a drain wiring is connected to the conductive layer 226 through the conductive layer 225b. Note that the conductive layer 225b is a conductive layer formed at the same time as the first conductive layers 231a and 231b of the memory elements 234a and 234b, and the conductive layer 226 is a second conductive layer 233a and 233b of the memory elements 234a and 234b. It is a conductive layer formed at the same time.

  The conductive layer 223 that functions as a source wiring or a drain wiring of the TFT 212a for switching the memory element and the conductive layer 124a that functions as a source wiring or a drain wiring of the TFT 111 that constitutes a circuit for operating the memory element are an adhesive layer. They are electrically connected through conductive particles 109 in 106.

  Note that depending on the structure of the memory element, data may be written to the element formation layer 202b including the memory element by an optical action using a laser beam. In such a case, in the element formation layer 202b having a memory element, it is necessary to make a layout so that the switching TFTs 212a and 212b and the memory elements 234a and 234b each have a non-overlapping region.

  Memory elements 234a and 234b illustrated in FIG. 28A each indicate a memory element in which switching TFTs 212a and 212b are provided in the memory elements 234a and 234b. In this structure, the semiconductor device has an active matrix memory circuit. Note that as shown in FIG. 28B, a substrate having a memory element 254 including a first conductive layer 251, an organic compound layer or phase change layer 252, and a second conductive layer 253 can be attached. It is. FIG. 28B shows a passive matrix memory circuit in which each memory element is not provided with a switching TFT. Note that the first conductive layer 251, the organic compound layer or phase change layer 252, and the second conductive layer 253 are the first conductive layer 151, the organic compound layer or phase change layer 152 described in Embodiment 1, and A structure similar to that of the second conductive layer 153 can be used.

  In the above embodiment, a circuit for operating a memory element is formed in the element formation layer 201b including a plurality of transistors; however, the invention is not limited to this. For example, the TFT 111 that constitutes a circuit for operating the memory element may be formed in the element formation layer 202b including the memory element. Specifically, as illustrated in FIG. 31A, after the TFT 511 that forms a circuit for operating the memory element is formed over the substrate 500b together with the memory elements 234a and 234b, an element formation layer including the memory element and the antenna is formed. 502b, an element formation layer 501b including an antenna and a plurality of transistors, and an adhesive layer 106 including conductive particles 109 may be attached to each other. At this time, the conductive layer 526 connected to one of the source wiring or the drain wiring 524 of the TFT 511 and the one of the source wiring or the drain wiring 124d of the TFT 114 which form a circuit for operating the memory element are connected to each other through the conductive particles 109. Electrically connected. Note that the conductive layer 526 is connected to one of the source wiring and the drain wiring 524 of the TFT 511 through the conductive layer 525. The conductive layer 526 is a conductive layer formed at the same time as the second conductive layer of the memory element, and the conductive layer 525 is a conductive layer formed at the same time as the first conductive layer of the memory element.

  In FIG. 28A, the element formation layer 202b having a memory element has a structure formed over the substrate 200b. However, as shown in FIG. 31B, the adhesive layer 513 is formed over the substrate 512b. An element formation layer 202b having a memory element may be attached to the substrate. Specifically, after a separation layer is provided over a substrate and an element formation layer 202b including a plurality of transistors is formed over the separation layer, the element formation layer 202b including a plurality of transistors is separated from the separation layer, and FIG. As shown in B), an element formation layer 202b having a plurality of transistors may be bonded to the substrate 512b with an adhesive layer 513 interposed therebetween. Note that as the peeling method, the peeling method described in Embodiment 1 can be used as appropriate.

  For the substrate 512b, a material similar to that of the substrate 200a can be used. The adhesive layer 513 corresponds to a layer containing an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, or a resin additive.

  As described above, a semiconductor device that is thin, light, and hard to crack even when dropped is provided by bonding an element formation layer having a plurality of peeled transistors to a flexible, thin and light plastic substrate. can do. In addition, it can be bonded onto a curved or irregularly shaped object, realizing a wide variety of uses. For example, the semiconductor device of the present invention can be closely attached to a curved surface such as a medicine bottle. Furthermore, if the substrate is reused, an inexpensive semiconductor device can be provided.

  In the semiconductor device of the present invention, the step of forming an element formation layer having a plurality of transistors and the step of forming an element formation layer having a memory element can be independently performed in parallel. Therefore, the present invention can manufacture a semiconductor device efficiently in a short time. In addition, when each of the element formation layer having a plurality of transistors and the memory element is formed, the performance of each element is confirmed and selected, and the element formation layer having a plurality of transistors and the memory element are electrically connected. A semiconductor device can be completed. Therefore, the rate at which defective products are produced can be suppressed, and the yield can be improved.

(Embodiment 9)
In this embodiment, a cross-sectional structure of the semiconductor device of the present invention, which is different from the structure of the above embodiment, will be described. More specifically, a cross-sectional structure of a semiconductor device in which a substrate having a layer in which a memory element and an antenna are formed is bonded to the back surface of an element formation layer having a plurality of transistors will be described.

  As shown in FIG. 26C, the semiconductor device of this embodiment includes an element formation layer 301b including a plurality of transistors provided over a substrate 100b, a memory element and an antenna formed over the second substrate 300b. The element formation layer 302b has a structure in which an adhesive layer is attached to the element formation layer 302b.

  Here, the element formation layer 301b including a plurality of transistors typically includes regions 102 and 103 each including a plurality of TFTs. The element formation layer 302b including a memory element and an antenna includes a region 104 including a memory element and a conductive layer 105 functioning as an antenna. In addition, the region 104 having a memory element is connected to a region 103 including a plurality of TFTs constituting a control circuit, an interface, and the like by conductive particles (not shown). In addition, the conductive layer 105 functioning as an antenna is connected to a region 102 including a plurality of TFTs constituting a communication circuit by conductive particles of an adhesive layer (not shown).

  A cross-sectional structure of the semiconductor device of the present invention having the structure shown in FIG. 26C is described with reference to FIGS.

  As shown in FIG. 29A, an element formation layer 301b having a plurality of TFTs has TFTs 111, 113, and 114, and the structure of these TFTs is as described above. In addition, an element formation layer 302b including a memory element 334 and a conductive layer 325 functioning as an antenna is formed over the substrate 300b. In FIG. 29A, a switching TFT 312 is connected to the memory element 334. In other words, the first conductive layer of the memory element 334 is connected to one of the conductive layers 324 functioning as a source wiring or a drain wiring of the switching TFT 312 to form an active matrix memory circuit.

  The other of the source wiring and the drain wiring of the switching TFT 312 is connected to a conductive layer formed simultaneously with the first conductive layer or the second conductive layer of the memory element. Here, the other of the conductive layer 324 functioning as a source wiring or a drain wiring is connected to the conductive layer 326 through the conductive layer 225b. Note that the conductive layer 225b is a conductive layer formed at the same time as the first conductive layer of the memory element, and the conductive layer 326 is a conductive layer formed at the same time as the second conductive layer of the memory element. Function as.

  Further, the back surface of the element formation layer 301 b having a plurality of TFTs and the element formation layer 302 b having a memory element and an antenna are bonded to each other with an adhesive layer 106 having conductive particles 109. That is, the insulating layer 115 and the element formation layer 302 b including a memory element and an antenna are bonded to each other with the adhesive layer 106 including the conductive particles 109. Further, the conductive layer 124c functioning as the source wiring or drain wiring of the TFT 113 is exposed on the back surface. Therefore, the conductive layer 124 a that functions as the source wiring or the drain wiring of the TFT 111 is electrically connected to the conductive layer 325 that functions as an antenna through the conductive particles 109.

  In addition, a conductive layer 325 functioning as an antenna is formed at the same time as the first conductive layer or the second conductive layer of the memory element 334. The conductive layer 325 is electrically connected to the conductive layer 124 c functioning as a source wiring or a drain wiring of the TFT 113 through the conductive particles 109. Note that the conductive layer 325 is formed at the same time as the conductive layer 326.

  Note that depending on the structure of the memory element, data may be written to the memory element 334 by an optical action using a laser beam. In such a case, in the element formation layer 302b including a memory element, it is necessary to perform layout so that the switching TFT 312 and the memory element 334, and the conductive layer 325 and the memory element 434 have regions that do not overlap with each other. .

  A memory element 334 illustrated in FIG. 29A is a memory element in which a switching TFT 312 is provided in each memory element. Note that as shown in FIG. 29B, a memory element 354 including a first conductive layer 351, an organic compound layer or phase change layer 352, and a second conductive layer 353 and a conductive layer 525 functioning as an antenna are provided. It is also possible to attach the substrate 300b having the same.

  In addition, although the TFT 111 which forms a circuit for operating the memory element is formed in the element formation layer 301b having a plurality of transistors, the invention is not limited to this. A TFT that constitutes a circuit for operating the memory element may be formed in the element formation layer 302b including the memory element. In FIG. 29A, an element formation layer 302b including a memory element and an antenna has a structure formed over a substrate 300b. The element formation layer 302b includes a memory element and an antenna over the substrate 300b with an adhesive layer interposed therebetween. The element formation layer 302b may be attached.

In the semiconductor device of the present invention, the step of forming an element formation layer having a plurality of transistors and the step of forming an element formation layer having a memory element and an antenna can be performed independently and in parallel. Therefore, the present invention can manufacture a semiconductor device efficiently in a short time. In addition, when each of the element formation layer having a plurality of transistors, the storage element, and the antenna is formed, the performance of each element is confirmed and selected to electrically connect the element formation layer, the storage element, and the antenna having a plurality of transistors. Thus, the semiconductor device can be completed. Therefore, the rate at which defective products are produced can be suppressed, and the yield can be improved.

(Embodiment 10)
In this embodiment, a cross-sectional structure of the semiconductor device of the present invention, which is different from the structure of the above embodiment, will be described. In more detail, FIG. 26 and FIG. 30 are used for a cross-sectional structure of a semiconductor device in which an element formation layer 401b including a plurality of transistors is sandwiched between a substrate over which an antenna is formed and a substrate over which a memory element is formed. I will explain.

  As shown in FIG. 26D, the semiconductor device of this embodiment includes an element formation layer 107b having a conductive layer functioning as an antenna formed over a substrate 108b and an element having a memory element formed over the substrate 200b. The element formation layer 401b including a plurality of transistors is interposed between the formation layer 202b and the formation layer 202b. Note that the element formation layer 401b including a plurality of transistors and the element formation layer 202b including a conductive layer functioning as an antenna are attached to each other with an adhesive layer. The element formation layer 401b including a plurality of transistors and the antenna An element formation layer 107b having a functioning conductive layer is also attached to the adhesive layer.

  Here, the element formation layer 401b including a plurality of transistors typically includes regions 102 and 103 including a plurality of TFTs. In addition, the element formation layer 202b including a memory element includes a region 104 including a memory element. In addition, the region 104 having a memory element is connected to a region 103 including a plurality of TFTs constituting a control circuit, an interface, and the like by conductive particles in an adhesive layer (not shown).

  In addition, the conductive layer 105 functioning as an antenna is connected to a region 102 including a plurality of TFTs constituting a communication circuit by conductive particles in an adhesive layer (not shown).

  A cross-sectional structure of the semiconductor device of the present invention having the structure shown in FIG. 26D is described with reference to FIGS.

  As shown in FIG. 30A, an element formation layer 202b having a memory element is formed over a substrate 200b. The element formation layer 401 b including a plurality of transistors and the element formation layer 202 b including a memory element are attached to each other with an adhesive layer 406 including conductive particles 109. The element formation layer 401b having a plurality of transistors includes TFTs 111, 113, and 114, and the structure of these TFTs is as described above. A connection wiring connected to the conductive layer 124a functioning as a source wiring or a drain wiring of the TFT 111 is exposed on the surface of the element formation layer 401b including a plurality of thin film transistors. Further, the conductive layer 124c functioning as the source wiring or drain wiring of the TFT 111 is exposed on the back surface of the element formation layer 401b having a plurality of thin film transistors.

  In FIG. 30A, switching TFTs 212a and 212b are connected to the memory elements 234a and 234b, respectively. In other words, the first conductive layers 231a and 231b of the memory element are connected to one of the source wiring and the drain wiring of the switching TFTs 212a and 212b. The other of the source wiring and the drain wiring of the switching TFTs 212a and 212b is connected to conductive layers 225b and 226 that are formed at the same time as the first conductive layer or the second conductive layer of the memory element. Here, the other of the conductive layer 223 functioning as a source wiring or a drain wiring is connected to the conductive layer 226 through the conductive layer 225b.

  The conductive layer 223 functioning as a source wiring or a drain wiring of the TFT 212a for switching the memory element and the conductive layer 124a functioning as a source wiring or a drain wiring of the TFT 111 constituting a circuit for operating the memory element are conductive. It is electrically connected through the particle 109 and the conductive layer.

  In addition, the element formation layer 401 b including a plurality of transistors and the element formation layer 107 b including the conductive layer 125 b formed over the substrate 108 b are attached to each other with an adhesive layer 406 including conductive particles 109. In addition, the conductive layer 124 c functioning as a source wiring or a drain wiring of the TFT 113 is electrically connected to the conductive layer 125 b functioning as an antenna through the conductive particles 109 in the adhesive layer 407.

  In the memory elements 234a and 234b illustrated in FIG. 30A, switching TFTs 212a and 212b are provided. That is, an active matrix memory circuit. Note that as illustrated in FIG. 30B, a substrate having a memory element 254 including the first conductive layer 251, the organic compound layer or phase change layer 252, and the second conductive layer 253 can be attached. It is. Such a memory element constitutes a passive matrix memory circuit.

  In the above embodiment, a circuit for operating a memory element is formed in the element formation layer 401b having a plurality of transistors; however, the invention is not limited to this. For example, a circuit for operating the memory element may be formed in the element formation layer 202b including the memory element.

  In FIG. 30A, the element formation layer 202b having a memory element has a structure formed over the substrate 200b, but the element formation layer 202b having a memory element is pasted over the substrate through an adhesive layer. May be combined.

  In the semiconductor device of the present invention, the step of forming an element formation layer having a plurality of transistors, the step of forming an element formation layer having a memory element, and the step of forming a conductive layer functioning as an antenna are performed in parallel. It can be carried out. Therefore, the present invention can manufacture a semiconductor device efficiently in a short time. In addition, when an element formation layer having a plurality of transistors, a storage element, and a conductive layer functioning as an antenna are formed, the performance of each element is confirmed and selected, and an element formation layer having a plurality of transistors or a storage layer is stored. A conductive layer functioning as an element or an antenna can be electrically connected to complete the semiconductor device. Therefore, the rate at which defective products are produced can be suppressed, and the yield can be improved.

(Embodiment 11)
In this embodiment, a cross-sectional structure of the semiconductor device of the present invention, which is different from the structure of the above embodiment, will be described. More specifically, a structure in which an element formation layer 601b having a plurality of transistors is provided over a substrate 108b having an element formation layer 107b having a conductive layer functioning as an antenna, and an element formation layer 602b having a memory element is mounted thereon. A cross-sectional structure of the semiconductor device will be described with reference to FIGS.

  As shown in FIG. 26E, the semiconductor device of this embodiment has a structure in which an element formation layer 601b having a plurality of transistors and a substrate 108b on which an antenna is formed are attached to each other with an adhesive layer. In addition, the element formation layer 602b including a memory element is bonded to the element formation layer 601b including a plurality of transistors with an adhesive layer.

  Here, the element formation layer 601b including a plurality of transistors is typically formed using regions 102 and 103 each including a plurality of TFTs and a conductive layer 105 functioning as an antenna. In addition, the element formation layer 602 including a memory element includes a region 104 including a memory element. Further, the region 104 having a memory element is electrically connected to a region 103 including a plurality of TFTs constituting a control circuit, an interface, and the like.

  A cross-sectional structure of the semiconductor device of the present invention having the structure shown in FIG. 26E is described with reference to FIG.

  As shown in FIG. 32, the element formation layer 601b having a plurality of TFTs has TFTs 111, 113, and 114, and the structure of these TFTs is as described above. In addition, an insulating layer 621b over which an element formation layer 602b including a memory element is formed is mounted over the insulating layer 615 with the use of an adhesive layer 611.

The element formation layer 601b including a plurality of transistors and the element formation layer 107b including an antenna are attached to each other with an adhesive layer 106. Specifically, the insulating layer 115 and the element formation layer 107 b having an antenna are attached to each other with an adhesive layer 106. In addition, the conductive layer 124c functioning as a source wiring or a drain wiring of the TFT 113 of the element formation layer 601b including a plurality of transistors and the conductive layer 125b functioning as an antenna of the element formation layer 107b include the conductive particles 109 of the adhesive layer 106. Is electrically connected.

In FIG. 32, a switching TFT 112 is connected to the memory element 634. That is, the first conductive layer of the memory element 634 is connected to one of the source wiring and the drain wiring of the switching TFT 112. The other of the source wiring and the drain wiring of the switching TFT 112 is connected to a conductive layer formed simultaneously with the first conductive layer or the second conductive layer of the memory element. Here, the other of the conductive layer 124 b functioning as a source wiring or a drain wiring is connected to the conductive layer 626 through the conductive layer 625. Note that the conductive layer 625 is a conductive layer formed at the same time as the first conductive layer of the memory element, and the conductive layer 626 is a conductive layer formed at the same time as the second conductive layer of the memory element. Function as.

  In addition, a switching TFT 112 of the memory element 634 formed in the element formation layer 602 having a memory element, and a TFT 111 constituting a circuit for operating the memory element formed in the element formation layer 601b having a plurality of TFTs, They are electrically connected by a conductive member 631.

  A memory element 634 illustrated in FIG. 32 is a memory element in which a switching TFT 112 is provided in each memory element. 33, a memory element 654 including a first conductive layer 651, an organic compound layer or phase change layer 652, and a second conductive layer 653 is formed instead of the memory element having a TFT. The substrate 622 can be mounted on the substrate 103b with the use of the adhesive layer 611.

  In this embodiment, the element formation layer 602 having a memory element is mounted on the element formation layer 601. However, the present invention is not limited to this, and an element formation layer having a memory element and an antenna or an element formation layer having an antenna is provided. It may be mounted on the element formation layer 601.

  The semiconductor device of the present invention has a structure in which a layer including a memory element is stacked over an element formation layer having a plurality of TFTs. With the above characteristics, a small semiconductor device can be provided. In addition, the step of forming an element formation layer having a plurality of transistors, the step of forming an element formation layer having a memory element, and the step of forming a conductive layer functioning as an antenna can be independently performed in parallel. Therefore, the present invention can manufacture a semiconductor device efficiently in a short time. In addition, when an element formation layer having a plurality of transistors, a storage element, and a conductive layer functioning as an antenna are formed, the performance of each element is confirmed and selected, and an element formation layer having a plurality of transistors or a storage layer is stored. Elements can be electrically connected to complete a semiconductor device. Therefore, the rate at which defective products are produced can be suppressed, and the yield can be improved.

Embodiment 12
In this embodiment, a method for manufacturing a semiconductor device will be described with reference to drawings. Here, a method for manufacturing the semiconductor device illustrated in FIG. 27A of Embodiment 7 is described; however, this embodiment can be appropriately applied to each semiconductor device described in each embodiment.

  As shown in FIG. 34A, separation layers 1101 and 1102 are formed on one surface of a substrate 1100 as in Embodiment 6.

  Next, as illustrated in FIG. 34B, as in Embodiment 6, an insulating layer 1105 serving as a base is formed so as to cover the separation layers 1101 and 1102. Next, after an amorphous semiconductor layer is formed over the insulating layer 1105, the amorphous semiconductor layer is crystallized by a known crystallization method to form a crystalline semiconductor layer. After that, the obtained crystalline semiconductor layer is etched into a desired shape to form crystalline semiconductor layers 1127 to 1130. Next, a gate insulating layer covering the crystalline semiconductor layers 1127 to 1130 is formed. Next, a first conductive layer and a second conductive layer are stacked over the gate insulating layer. Next, a resist mask is formed using a photolithography method, and etching treatment for forming a gate electrode is performed, so that the conductive layers 1107 to 1110 are formed. Next, an impurity element imparting N-type conductivity is added to the crystalline semiconductor layers 1127 to 1130 at a low concentration by ion doping or ion implantation to form N-type impurity regions. Next, the insulating layer 1141 is formed so as to cover the insulating layer and the conductive layers 1107 to 1110.

Next, as in Embodiment 6, the insulating layer is selectively etched by anisotropic etching mainly in the vertical direction, so that the sidewall insulating layers 1115 to 1118 in contact with the side surfaces of the conductive layers 1107 to 1110 are formed. Form. Note that the insulating layer is also etched by the etching step for forming the sidewall insulating layers 1115 to 1118 to form gate insulating layers 1119 to 1122. Subsequently, an impurity element imparting N-type conductivity is added to the crystalline semiconductor layers 1127 to 1130 using the sidewall insulating layers 1115 to 1118 as masks, so that first N-type impurity regions (also referred to as LDD regions) 1123a to 1123d. And second N-type impurity regions (also referred to as source and drain regions) 1124a to 1124d are formed. The concentration of the impurity element contained in the first N-type impurity regions 1123a to 1123d is lower than the concentration of the impurity element in the second N-type impurity regions 1124a to 1124d.

  Through the above steps, n-type TFTs 1131 to 1134 are completed.

  Next, an insulating layer 1142 is formed as a single layer or a stacked layer so as to cover the TFTs 1131 to 1134.

  Next, as shown in FIG. 34C, as in the sixth embodiment, the insulating layers 1141 and 1142 are etched by a photolithography method to expose the N-type impurity regions 1124a to 1124d, so that the contact holes 1143 to 1150 are exposed. Form. At this time, the contact hole 1151 also etches the insulating layer 1105 together with the insulating layers 1141 and 1142, and part of the substrate 1100 is exposed.

  Next, as illustrated in FIG. 34D, a conductive layer is formed so as to fill the contact holes 1143 to 1151, and the conductive layer is patterned to form conductive layers 1155 to 1162. The conductive layers 1155 to 1162 function as a source wiring or a drain wiring of the TFT. Further, the conductive layer 1159 reaches the substrate surface. The conductive layer 1159 is not in contact with the separation layers 1101 and 1102 but is in contact with the insulating layers 1105, 1141, and 1422. This is to prevent the conductive layer 1159 from being removed by the etching agent when the peeling layers 1101 and 1102 are removed by the etching agent.

  Next, as illustrated in FIG. 34E, as in Embodiment 6, an insulating layer 1163 is formed as a single layer or a stacked layer so as to cover the conductive layers 1155 to 1162. The insulating layer 1163 covering the conductive layers 1154 to 1162 can be formed using a method and a material similar to those of the insulating layer 1142 covering the thin film transistor. Next, a contact hole is formed in the insulating layer 1163 covering the conductive layers 1154 to 1162, and the conductive layer 1164 is formed. The conductive layer 1164 functions as a first conductive layer of a memory element to be formed later.

  Next, an insulating layer 1165 is formed so as to cover an end portion of the conductive layer 1164, and then an organic compound layer or a phase change layer 1166 and a conductive layer 1167 are formed. The memory element 1169 includes the conductive layer 1164, the organic compound layer or phase change layer 1166, and the conductive layer 1167. The conductive layer 1164 functions as a second conductive layer of the memory element 1169. After that, an insulating layer 1168 may be formed.

  Next, as illustrated in FIG. 35A, the insulating layers 1105, 1141, 1142, 1163, and 1168 are etched by photolithography so that the separation layers 1101 and 1102 are exposed, as in Embodiment 6. Thus, openings 1171 and 1172 are formed.

  Next, as illustrated in FIG. 35B, as in Embodiment 6, an etching agent is introduced into the opening portions 1171 and 1172 to remove the separation layers 1101 and 1102.

  Next, as illustrated in FIG. 35C, as in Embodiment 6, the surface on which the memory element is formed in the element formation layer 1170 including a plurality of transistors is bonded to the base 1181, so that After the element formation layer 1170 including a transistor and the base 1181 are bonded, the element formation layer 1170 including a plurality of transistors is completely peeled from the substrate 1100 (see a cross-sectional view in FIG. 36A).

  Next, as illustrated in FIG. 36B, as in Embodiment 6, the other surface of the element formation layer 1170 including a plurality of transistors is bonded to a substrate 1183 provided with a conductive layer 1182. At this time, bonding is performed using an adhesive layer 1191 including conductive particles 1900. In addition, the element formation layer 1170 including a plurality of transistors and the substrate 1183b are formed so that the conductive layer 1159 functioning as a source wiring or a drain wiring of the TFT 1133 and the conductive layer 1182b over the substrate 1183b are in contact with each other with conductive particles 1190. Adhere.

  Next, the element formation layer 1170 having a plurality of transistors and the bases 1181 and 1183b are separated using a slicing device, a laser irradiation device, or the like.

  Through the above steps, a semiconductor device having a function of communicating data without contact is completed.

  In this embodiment mode, the element formation layer 1170 having a plurality of transistors and the substrate 1183b having a conductive layer are bonded, and then divided to form a semiconductor device; however, the present invention is not limited to this step. After the element formation layer 1170 including a plurality of transistors and the base 1181 are bonded and divided, the substrate 1183b including the conductive layer 1182 may be bonded to the element formation layer 1170 including a plurality of transistors.

  As described above, since the semiconductor device of the present invention is small, thin, lightweight, and flexible, it can be used in a wide variety of applications, and even when attached to an article, the design of the article may be impaired. Absent.

(Embodiment 13)
Next, the structure and operation of the memory circuit included in the semiconductor device of the present invention will be described with reference to the drawings. The memory circuit of the present invention includes a memory cell array 22 in which memory cells 21 are provided in a matrix, decoders 23 and 24, a selector 25, and a read / write circuit 26. The memory cell 21 includes a memory element 30 (see FIG. 12A).

  The memory element 30 includes a first conductive layer 27 constituting the word line Wy (1 ≦ y ≦ n), a second conductive layer 28 constituting the bit line Bx (1 ≦ x ≦ m), The conductive layer 27 includes an organic compound layer or a phase change layer 29a provided between the second conductive layer 28 (see FIG. 13A). As shown in FIG. 13B, an insulating layer 33 is provided between adjacent organic compound layers or phase change layers 29a. In addition, an insulating layer 34 is provided over the memory element 30. The first conductive layer 27 constituting the word line Wy is provided to extend in the first direction, and the second conductive layer 28 constituting the bit line Bx is a second layer perpendicular to the first direction. It is provided extending in the direction. That is, the first conductive layer 27 and the second conductive layer 28 are provided in stripes so as to cross each other.

  Depending on the configuration of the organic compound layer or the phase change layer 29a, data may be written to the memory element 30 by an optical action. In that case, one or both of the first conductive layer 27 and the second conductive layer 28 needs to have a light-transmitting property. The light-transmitting conductive layer is formed using a transparent conductive material such as indium tin oxide (ITO), or formed with a thickness that allows light to pass even if it is not a transparent conductive material. To do.

  The equivalent circuit diagram shown in FIG. 12A is a passive type, but an active type in which a transistor 31 is provided in the memory cell 21 may be employed (see FIG. 14). In that case, the gate electrode of the switching transistor 31 is connected to the word line Wy (1 ≦ y ≦ n), and one of the source electrode and the drain electrode is connected to the bit line Bx (1 ≦ x ≦ m). The other of the drain electrode and the drain electrode is connected to one conductive layer of the memory element 30.

  As a representative example of the organic compound layer or the phase change layer 29a, an organic compound material can be given. Hereinafter, a layer formed of an organic compound material is referred to as an organic compound layer.

As a typical example of the organic compound layer, 4,4′-bis [N- (1-naphthyl) -N-phenylamino] -biphenyl (abbreviation: α-NPD), 4,4′-bis [N- ( 3-methylphenyl) -N-phenylamino] -biphenyl (abbreviation: TPD), 4,4 ′, 4 ″ -tris (N, N-diphenylamino) -triphenylamine (abbreviation: TDATA), 4,4 ', 4''-tris [N- (3-methylphenyl) -N-phenylamino] -triphenylamine (abbreviation: MTDATA) and 4,4′-bis (N- (4- (N, N-di) -M-Tolylamino) phenyl) -N-phenylamino) biphenyl (abbreviation: DNTPD) and other aromatic amine-based compounds (that is, having a benzene ring-nitrogen bond), phthalocyanine (abbreviation: H ₂ Pc), copper Phthalocyanine (abbreviation: A substance having a high hole transporting property such as a phthalocyanine compound such as CuPc) or vanadyl phthalocyanine (abbreviation: VOPc) can be used.

In addition, a material having a high electron transporting property can be used as the organic compound material, for example, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation). : Almq ₃ ), bis (10-hydroxybenzo [h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), etc. A material made of a metal complex having a skeleton or a benzoquinoline skeleton, bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) ) Benzothiazolate] zinc (abbreviation: Zn (BTZ) ₂ ) and other oxazoles and thiazoles A material such as a metal complex having a ligand can also be used. In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- ( 4-biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2, Compounds such as 4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), and the like can be used.

In addition, as other organic compound materials, 4-dicyanomethylene-2-methyl-6- (1,1,7,7-tetramethyljulolidyl-9-enyl) -4H-pyran (abbreviation: DCJT), 4-dicyanomethylene-2-tert-butyl-6- (1,1,7,7-tetramethyljulolidyl-9-enyl) -4H-pyran, perifrantene, 2,5-dicyano-1,4-bis (10-methoxy-1,1,7,7-tetramethyljulolidyl-9-enyl) benzene, N, N′-dimethylquinacridone (abbreviation: DMQd), coumarin 6, coumarin 545T, tris (8-quinolinolato) Aluminum (abbreviation: Alq ₃ ), 9,9′-bianthryl, 9,10-diphenylanthracene (abbreviation: DPA) and 9,10-bis (2-naphthyl) anthracene (abbreviation: D) NA), 2,5,8,11-tetra-t-butylperylene (abbreviation: TBP) and the like. As a base material for forming a layer in which the light emitting material is dispersed, an anthracene such as 9,10-di (2-naphthyl) -2-tert-butylanthracene (abbreviation: t-BuDNA) is used. Derivatives, carbazole derivatives such as 4,4′-bis (N-carbazolyl) biphenyl (abbreviation: CBP), bis [2- (2-hydroxyphenyl) pyridinato] zinc (abbreviation: Znpp ₂ ), bis [2- (2 Metal complexes such as -hydroxyphenyl) benzoxazolate] zinc (abbreviation: ZnBOX) can be used. In addition, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), 9,10-bis (2-naphthyl) anthracene (abbreviation: DNA), bis (2-methyl-8-quinolinolato) -4-phenylphenolato- Aluminum (abbreviation: BAlq) or the like can be used.

In addition, an oxide semiconductor or a metal oxide may be added to the organic compound. Specific examples of the oxide semiconductor or metal oxide include molybdenum oxide (MoO _x ), vanadium oxide (VO _x ), ruthenium oxide (RuO _x ), tungsten oxide (WO _x ), and cobalt oxide (Co _x ), nickel oxide (NiO _x ), copper oxide (CuO _x ), and the like. In addition, indium tin oxide (ITO), zinc oxide (ZnO), or the like can be used.

For the organic compound layer, a material whose electrical resistance is changed by an optical action can be used. For example, a conjugated polymer doped with a compound that generates an acid by absorbing light (a photoacid generator) can be used. As the conjugated polymer, polyacetylenes, polyphenylene vinylenes, polythiophenes, polyanilines, polyphenylene ethynylenes, and the like can be used. As the photoacid generator, arylsulfonium salts, aryliodonium salts, o-nitrobenzyl tosylate, arylsulfonic acid p-nitrobenzyl esters, sulfonylacetophenones, Fe-allene complex PF ₆ salts, and the like can be used. .

  Next, an operation when data is written to the memory circuit having the above structure is described. Data is written by optical action or electrical action. Note that the optical action is to irradiate light from the outside, and the electric action is to apply a voltage higher than a predetermined voltage to the first conductive layer and the second conductive layer of the memory element.

When data “1” is written in the memory cell 21, first, the memory cell 21 is selected by the decoders 23 and 24 and the selector 25. Specifically, the decoder 24 applies a predetermined voltage V2 to the word line W3 connected to the memory cell 21. Further, the bit line B 3 connected to the memory cell 21 is connected to the read / write circuit 26 by the decoder 23 and the selector 25. Then, the write voltage V1 is output from the read / write circuit 26 to the bit line B3. Thus, the voltage Vw = V1−V2 is applied between the first conductive layer and the second conductive layer constituting the memory cell 21. By appropriately selecting the potential Vw, the organic compound layer or the phase change layer 29 provided between the conductive layers is changed physically or electrically, and data “1” is written. Specifically, at the read operation voltage, the electrical resistance between the first conductive layer and the second conductive layer in the data “1” state is significantly smaller than that in the data “0” state. It is good to change as follows. For example, it may be appropriately selected from the range of (V1, V2) = (0V, 5-15V), or (3-5V, -12--2V). The voltage Vw may be 5 to 15V, or -5 to -15V.

Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. For example, unselected word lines and unselected bit lines may be set in a floating state. The first conductive layer and the second conductive layer constituting the memory cell must have characteristics such as diode characteristics that can ensure selectivity.

On the other hand, when data “0” is written in the memory cell 21, it is not necessary to apply an electrical action to the memory cell 21. In the circuit operation, for example, as in the case of writing “1”, the memory cell 21 is selected by the decoders 23 and 24 and the selector 25, but the output potential from the read / write circuit 26 to the bit line B3 is selected. The potential of the word line W3 or the potential of the non-selected word line is set to the same level, and the electrical characteristics of the memory cell 21 are not changed between the first conductive layer and the second conductive layer constituting the memory cell 21. A voltage (for example, −5 to 5 V) may be applied.

  Next, the case where data is written by an optical action is described (see FIG. 13B). In this case, data is written by irradiating the organic compound layer with laser light by the laser irradiation device 32 from the light-transmitting conductive layer side (here, the second conductive layer 28). More specifically, the organic compound layer included in the selected memory element 30 is irradiated with laser light to destroy the organic compound layer. The destroyed organic compound layer is insulated, and its resistance value is greatly increased as compared with other memory elements 30. In this manner, data is written by utilizing the change in the electrical resistance of the memory element 30 due to laser light irradiation. For example, when the memory element 30 that is not irradiated with laser light is set to “0” data, the electric resistance is increased by writing the data “1” by irradiating the memory element 30 with laser light and destroying it. Is possible.

  Note that the present invention is not limited to the mode of writing data by irradiating the memory element 30 with laser light and insulating the organic compound layer, and adjusts the element structure of the memory element 30 and the intensity of the laser light. Thus, the data may be written by irradiating the memory element 30 with laser light, causing the organic compound layer to break down, and changing the resistance value of the memory element 30. In this case, the resistance of the memory element 30 in which the pair of conductive layers are short-circuited is significantly lower than that of the other memory elements 30. In this manner, data may be written using the change in the resistance value of the memory element 30 by applying an optical action.

  In addition, when a conjugated polymer doped with a compound that generates an acid by absorbing light (photoacid generator) is used as the organic compound layer, when the laser beam is irradiated, the electric resistance value of the irradiated portion is It changes, and the electrical resistance value does not change in the unirradiated part. Also in this case, data is written by utilizing the change in the resistance value of the memory element 30 by irradiating the selected organic compound layer with laser light. For example, when the memory element 30 that has not been irradiated with the laser beam is set to “0” data, the selected memory element 30 is irradiated with the laser beam to change the electrical resistance value and write the data “1”. Is possible.

  Next, an operation for reading data will be described (see FIG. 12). In reading data, the electrical characteristics between the first conductive layer and the second conductive layer constituting the memory cell are different between the memory cell having data “0” and the memory cell having data “1”. Use it. For example, the effective electrical resistance between the first conductive layer and the second conductive layer constituting the memory cell having data “0” (hereinafter simply referred to as the electrical resistance of the memory cell) is R0 at the read voltage. A method of reading data by using the difference in electric resistance when the electric resistance of the memory cell having data “1” is R1 in the read voltage will be described. Note that R1 << R0. As the read / write circuit, for example, a circuit 26 using a resistance element 46 and a differential amplifier 47 shown in FIG. The resistance element 46 has a resistance value Rr, and R1 <Rr <R0. A transistor 48 may be used instead of the resistance element 46, and a clocked inverter 49 may be used instead of the differential amplifier (FIG. 12C). The clocked inverter 49 receives a signal or an inverted signal that becomes Hi when reading and becomes Lo when not reading. Of course, the circuit configuration is not limited to FIG.

When reading data from the memory cell 21, first, the memory cell 21 is selected by the decoders 23 and 24 and the selector 25. Specifically, the decoder 24 applies a predetermined voltage Vy to the word line Wy connected to the memory cell 21. Further, the bit line Bx connected to the memory cell 21 is connected to the terminal P of the read / write circuit 26 by the decoder 23 and the selector 25. As a result, the potential Vp of the terminal P becomes a value determined by resistance division by the resistance element 46 (resistance value Rr) and the memory cell 21 (resistance value R0 or R1). Therefore, when the memory cell 21 has data “0”, Vp0 = Vy + (V0−Vy) × R0 / (R0 + Rr). When the memory cell 21 has data “1”, Vp1 = Vy + (V0−Vy) × R1 / (R1 + Rr). As a result, in FIG. 12B, Vref is selected to be between Vp0 and Vp1, and in FIG. 12C, the change point of the clocked inverter is selected to be between Vp0 and Vp1. Thus, Lo / Hi (or Hi / Lo) is output as the output potential Vout according to the data “0” / “1”, and reading can be performed.

For example, the differential amplifier is operated at Vdd = 3V, and Vy = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9, when the memory cell data is “0”, Vp0 = 2.7 V and Vout is Hi, and when the memory cell data is “1”, Vp1 = 0.3V and Lo is output as Vout. Thus, the memory cell can be read.

According to the above method, the state of the electrical resistance of the organic compound layer or the phase change layer 29 is read as a voltage value using the difference in resistance value and resistance division. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. In addition, when the electrical characteristics of the memory cell have data “0” and “1” and diode characteristics with different threshold voltages, reading may be performed using the threshold voltage difference.

  The same applies to the case where data is written by irradiating the organic compound layer with laser light. The resistance value of the memory element 30 to which the optical action is not applied and the resistance value of the memory element 30 to which the optical action is added are the same. Data is read by electrically reading the difference in values.

  The same applies to the case where a conjugated polymer doped with a compound that generates an acid by absorbing light (photoacid generator) is used in the organic compound layer, and the memory element 30 to which no optical action is applied. Data is read by electrically reading the difference between the resistance value and the resistance value of the memory element to which an optical action is applied.

  A phase change layer may be used as a representative example of the organic compound layer or the phase change layer 29. Here, the phase change layer is a material that reversibly changes between a crystalline state and an amorphous state, and the phase change layer is a material that reversibly changes between a first crystalline state and a second crystalline state. Or a material that changes only from an amorphous state to a crystalline state. It is called a layer formed of such a material.

  Note that in the case of using a reversible material, data reading and data writing can be performed. On the other hand, when an irreversible material is used, only data reading can be performed. Thus, depending on the type of material, the phase change memory can be a read-only memory or a read / write memory. Therefore, a material used for the phase change layer is appropriately selected according to the use of the semiconductor device.

In the phase change layer, materials that reversibly change between a crystalline state and an amorphous state include germanium (Ge), tellurium (Te), antimony (Sb), sulfur (S), tellurium oxide (TeOx), A material having a plurality selected from Sn (tin), gold (Au), gallium (Ga), selenium (Se), indium (In), thallium (Tl), Co (cobalt), and silver (Ag), For example, Ge—Te—Sb—S, Te—TeO ₂ —Ge—Sn, Te—Ge—Sn—Au, Ge—Te—Sn, Sn—Se—Te, Sb—Se—Te, Sb—Se, Ga -Se-Te, Ga-Se-Te-Ge, In-Se, In-Se-Tl-Co, Ge-Sb-Te, In-Se-Te, and Ag-In-Sb-Te-based materials can be given.

In the phase change layer, materials that reversibly change between the first crystal state and the second crystal state are silver (Ag), zinc (Zn), copper (Cu), aluminum (Al), nickel ( Ni), indium (in), antimony (Sb), a material having a plurality selected from selenium (Se) and tellurium (Te), for _{example, Te-TeO 2, Te-} TeO 2 -Pd, Sb 2 Se ₃ / _Bi 2 Te ₃ and the like. In this material, the phase change takes place between two different crystalline states.

  In the phase change layer, the material that changes only from the amorphous state to the crystalline state is a plurality selected from tellurium (Te), tellurium oxide (TeOx), antimony (Sb), selenium (Se), and bismuth (Bi). Examples thereof include Ag—Zn, Cu—Al—Ni, In—Sb, In—Sb—Se, and In—Sb—Te.

  A memory element having a simple structure including a phase change material between a pair of conductive layers has a simple manufacturing process and can provide an inexpensive semiconductor device. In addition, since the phase change memory is a non-volatile memory, it is not necessary to incorporate a battery for holding data, and a small, thin, and lightweight semiconductor device can be provided. If an irreversible material is used for the phase change layer, data cannot be rewritten. Then, it is possible to provide a semiconductor device that prevents forgery and ensures security.

  Next, an operation when data is written to a memory element having a phase change layer will be described. Similarly to the memory element using the organic compound layer, data is written by applying a voltage between the first conductive layer 27 and the second conductive layer 28 to change the phase of the phase change material.

  Next, the case where data is written by light is described (see FIG. 13B). In this case, the phase change layer is irradiated with laser light from the side of the light-transmitting conductive layer (here, the second conductive layer 28). The phase change layer undergoes a crystallographic phase change in its structure when irradiated with laser light. In this manner, data writing is performed by utilizing the fact that the phase of the phase change layer changes due to laser light irradiation.

  For example, when data “1” is written, the phase change layer is irradiated with laser light, heated to a temperature equal to or higher than the crystallization temperature, and then gradually cooled to bring the phase change layer into a crystalline state. On the other hand, when writing “0” data, the phase change layer is irradiated with laser light, heated to a temperature higher than the melting point, melted, and then rapidly cooled to make the phase change layer amorphous.

Although the phase change of the phase change layer depends on the size of the memory cell 21, it is realized by laser light irradiation with a diameter of the order of μm. For example, when a laser beam having a diameter of 1 μm passes at a speed of 10 m / sec, the time during which the phase change layer included in one memory cell 21 is irradiated with laser light is 100 nsec. In order to change the phase within a short time of 100 nsec, the laser power is preferably 10 mW and the power density is 10 kW / mm ² , for example.

  Note that the laser beam irradiation to the phase change layer may be performed on all the memory cells 21 or may be performed selectively. For example, in the case where the phase change layer just formed is in an amorphous state, laser light is preferably not irradiated when the amorphous state is kept, and laser light is irradiated when the phase change layer is changed to a crystalline state. That is, data may be written by selectively irradiating laser light. In this manner, in the case of selectively irradiating laser light, a pulsed laser irradiation apparatus may be used.

  As described above, the structure of the present invention in which data is written by laser light irradiation can easily produce a large number of semiconductor devices. Therefore, an inexpensive semiconductor device can be provided.

  Subsequently, the operation when data is read from the memory element having the phase change layer is the same as that of the memory element having the organic compound layer, and the voltage or current changes from the resistance change accompanying the phase state of the phase change layer. Can be read.

  Further, as a configuration different from the above configuration, a rectifying property is provided between the first conductive layer 27 and the organic compound layer or phase change layer 29a, or between the second conductive layer 28 and the organic compound or phase change layer 29. An element including the above may be provided (see FIG. 13C). The rectifying element is typically a Schottky diode, a diode having a PN junction, a diode having a PIN junction, or a transistor in which a gate electrode and a drain electrode are connected. Of course, other configurations of diodes may be used. Here, a case where a PN junction diode including semiconductor layers 44 and 45 is provided between the first conductive layer and a layer including an organic compound is shown. One of the semiconductor layers 44 and 45 is an N-type semiconductor and the other is a P-type semiconductor. By providing an element having a rectifying action in this manner, the selectivity of the memory cell can be improved and the operation margin for reading and writing can be improved.

  As described above, the memory circuit included in the semiconductor device of the present invention includes a memory element having a simple structure in which an organic compound layer or a phase change layer is sandwiched between a pair of conductive layers. Since it is simple, an inexpensive semiconductor device and a manufacturing method thereof can be provided. In addition, since high integration is easy, a semiconductor device having a large-capacity memory circuit and a manufacturing method thereof can be provided.

Further, a memory circuit included in the semiconductor device of the present invention writes data by an optical action or an electrical action, is nonvolatile, and can additionally write data. With the above feature, new data can be added and written while preventing forgery due to rewriting and ensuring security. Accordingly, it is possible to provide a semiconductor device that achieves high functionality and high added value and a manufacturing method thereof.
(Embodiment 14)
Next, the structure and operation of the memory circuit included in the semiconductor device of the present invention will be described with reference to the drawings. The memory cell 21 includes a first conductive layer constituting the bit line Bx (1 ≦ x ≦ m), a second conductive layer constituting the word line Wy (1 ≦ y ≦ n), a transistor 31, and a memory Element 30. The memory element 30 has a structure in which an organic compound layer is sandwiched between a pair of conductive layers. The gate electrode of the transistor is connected to the word line, either the source electrode or the drain electrode is connected to the bit line, and the other is connected to one of the two terminals of the memory element. The remaining one terminal of the memory element is connected to a common electrode (potential Vcom).

  Next, an operation when data is written to the memory cell 21 will be described (FIG. 14).

  First, an operation when data is written by electrical action will be described. Writing is performed by changing the electrical characteristics of the memory cell. The initial state of the memory cell (the state where no electrical action is applied) is data “0”, and the state where the electrical characteristic is changed is “1”. To do.

Here, a case where data is written to the memory cell 21 in the x column and the y row will be described. When data “1” is written in the memory cell 21, first, the memory cell 21 is selected by the decoders 23 and 24 and the selector 25. Specifically, the decoder 24 applies a predetermined voltage V22 to the word line Wy connected to the memory cell 21. Further, the bit line Bx connected to the memory cell 21 is connected to the read / write circuit 26 by the decoder 23 and the selector 25. Then, the write voltage V21 is output from the read / write circuit 26 to the bit line Bx.

Thus, the transistor 31 included in the memory cell is turned on, the bit line is electrically connected to the memory element 30, and a voltage of approximately Vw = Vcom−V21 is applied. Note that one electrode of the memory element 30 is connected to a common electrode having the potential Vcom. By appropriately selecting the potential Vw, the organic compound layer provided between the conductive layers is changed physically or electrically, and data “1” is written. Specifically, at the read operation voltage, the electrical resistance between the first conductive layer and the second conductive layer in the data “1” state is significantly smaller than that in the data “0” state. It may be changed as described above, or it may be simply short-circuited. The potential may be appropriately selected from the range of (V21, V22, Vcom) = (5-15V, 5-15V, 0V), or (-12 to 0V, -12 to 0V, 3 to 5V). The voltage Vw may be 5 to 15V, or -5 to -15V.

Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. Specifically, a potential (for example, 0 V) for turning off the transistor of the memory cell to be connected is applied to the non-selected word line, and the non-selected bit line is in a floating state or approximately equal to Vcom. A potential may be applied.

On the other hand, when data “0” is written in the memory cell 21, it is not necessary to apply an electrical action to the memory cell 21. In the circuit operation, for example, as in the case of writing “1”, the memory cell 21 is selected by the decoders 23 and 24 and the selector 25, but the output potential from the read / write circuit 26 to the bit line Bx is the same as Vcom. Or the bit line Bx is in a floating state. As a result, a small voltage (for example, −5 to 5 V) is applied to the memory element 30 or no voltage is applied, so that the electrical characteristics do not change and data “0” writing is realized.

  Note that the case of writing data by optical action is the same as that in Embodiment 13.

Next, an operation when data is read by electrical action will be described. Data is read using the fact that the electrical characteristics of the memory element 30 are different between the memory cell having the data “0” and the memory cell having the data “1”. For example, the electrical resistance of the memory element constituting the memory cell having data “0” is R0 at the read voltage, and the electrical resistance of the memory element constituting the memory cell having data “1” is R1 at the read voltage. A method of reading using the difference will be described. Note that R1 << R0. As the structure of the reading / writing circuit, for example, the circuit 26 using the resistance element 246 and the differential amplifier 247 illustrated in FIG. 14B can be considered. The resistance element 246 has a resistance value Rr, and R1 <Rr <R0. A transistor 248 may be used instead of the resistance element 246, and a clocked inverter 249 may be used instead of the differential amplifier 247 (FIG. 14C). Of course, the circuit configuration is not limited to FIG.

When data is read from the memory cell 21 at the y-th row and the x-th column, first, the memory cell 21 is selected by the decoders 23 and 24 and the selector 25. Specifically, the decoder 24 applies a predetermined voltage V24 to the word line Wy connected to the memory cell 21 to turn on the transistor 31. Further, the bit line Bx connected to the memory cell 21 is connected to the terminal P of the read / write circuit 26 by the decoder 23 and the selector 25. As a result, the potential Vp of the terminal P becomes a value determined by resistance division by the resistance element 246 (resistance value Rr) and the memory element 30 (resistance value R0 or R1). Therefore, when the memory cell 21 has data “0”, Vp0 = Vcom + (V0−Vcom) × R0 / (R0 + Rr). When the memory cell 21 has data “1”, Vp1 = Vcom + (V0−Vcom) × R1 / (R1 + Rr). As a result, in FIG. 14B, Vref is selected to be between Vp0 and Vp1, and in FIG. 14C, the change point of the clocked inverter is selected to be between Vp0 and Vp1. Thus, Lo / Hi (or Hi / Lo) is output as the output potential Vout according to the data “0” / “1”, and reading can be performed.

For example, the differential amplifier is operated at Vdd = 3V, and Vcom = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9 and the on-resistance of the transistor 31 can be ignored, when the data in the memory cell is “0”, Vp0 = 2.7V and Vout is output as Hi, When the data of “1” is “1”, Vp1 = 0.3 V and Lo is output as Vout. Thus, the memory cell can be read.
According to the above method, the output is read with the voltage value by utilizing the difference in the resistance value of the memory element 30 and the resistance division. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. In addition, when the electrical characteristics of the memory cell have data “0” and “1” and diode characteristics with different threshold voltages, reading may be performed using the threshold voltage difference.

  In this example, a result of an experiment in which a memory element is manufactured over a substrate and current-voltage characteristics are examined when data is written to the memory element by an electric action will be described. The memory element is an element in which a first conductive layer, a first organic compound layer, a second organic compound layer, and a second conductive layer are stacked in this order on a substrate. Indium tin oxide compound (sometimes abbreviated as ITSO), the first organic compound layer is 4,4′-bis [N- (3-methylphenyl) -N-phenylamino] biphenyl (abbreviated as TPD) The second organic compound layer may be 4,4′-bis [N- (1-naphthyl) -N-phenylamino] biphenyl (sometimes abbreviated as α-NPD), The second conductive layer was formed of aluminum. The first organic compound layer was formed with a thickness of 10 nm, and the second organic compound layer was formed with a thickness of 50 nm.

First, measurement results of current-voltage characteristics of a memory element before data writing by an electrical action and after data writing by an electrical action are described with reference to FIGS. In FIG. 16, the horizontal axis represents the voltage value, the vertical axis represents the current value, the plot 261 represents the current-voltage characteristics of the memory element before writing data by electrical action, and the plot 262 represents the memory element after data written by electrical action. The current-voltage characteristics are shown. From FIG. 16, there is a large change in the current-voltage characteristics of the memory element before and after data writing. For example, at an applied voltage of 1 V, the current value before data writing is 4.8 × 10 ⁻⁵ mA, whereas the current value after data writing is 1.1 × 10 ² mA. After the data writing, the current value has changed by 7 digits. As described above, the resistance value of the memory element changes before and after the data is written. When the change in the resistance value of the memory element is read by the voltage value or the current value, the memory circuit can be obtained. Can function.

  Next, in Sample 1 to Sample 6 in which memory elements are similarly formed on the substrate, the results of experiments in which current-voltage characteristics were examined when data was written to the memory elements by electrical action are shown in FIGS. It explains using. Here, writing was performed by applying a voltage to the organic memory element to short-circuit the organic memory element. 22 to 24, the horizontal axis represents the voltage value, the vertical axis represents the current density value, the circled plot represents the current-voltage characteristics of the memory element before data is written by the electrical action, and the square mark represents the electrical action. Shows current-voltage characteristics of the memory element after data is written. Moreover, the magnitude | size in the horizontal surface of the samples 1-6 is 2 mm x 2 mm.

  As Sample 1, an element in which a first conductive layer 701, a first organic compound layer 702, and a second conductive layer 703 are stacked in this order is illustrated in FIG. The first conductive layer 701 was formed of ITSO, the first organic compound layer 702 was formed of TPD, and the second conductive layer 703 was formed of aluminum. The first organic compound layer was formed with a thickness of 50 nm. The current-voltage characteristics of Sample 1 are shown in FIG.

  Further, as Sample 2, an element in which a first conductive layer 701, a first organic compound layer 711, and a second conductive layer 703 are stacked in this order is illustrated in FIG. The first conductive layer is ITSO, and the first organic compound layer is 2,3,5,6-tetrafluoro-7,7,8,8, -tetracyanoquinodimentane (abbreviated as F4-TCNQ). And the second conductive layer was formed of aluminum. Moreover, the thickness of the first organic compound layer was set to 50 nm, and F4-TCNQ was added at a ratio of 0.01 wt. The current-voltage characteristics of Sample 2 are shown in FIG.

  FIG. 25C illustrates a sample 3 in which a first conductive layer 701, a first organic compound layer 721, a second organic compound layer 722, and a second conductive layer 703 are stacked in this order. The first conductive layer was formed of ITSO, the first organic compound layer was TPD, the second organic compound layer was F4-TCNQ, and the second conductive layer was formed of aluminum. In addition, the thickness of the first organic compound layer TPD was set to 50 nm, and the second organic compound layer F4-TCNQ was formed to a thickness of 1 nm. The current-voltage characteristics of Sample 3 are shown in FIG.

  FIG. 25D illustrates a sample 4 in which a first conductive layer 701, a first organic compound layer 731, a second organic compound layer 732, and a second conductive layer 703 are stacked in this order. The first conductive layer was formed of ITSO, the first organic compound layer was formed of F4-TCNQ, the second organic compound layer was formed of TPD, and the second conductive layer was formed of aluminum. In addition, F4-TCNQ that is the first organic compound layer was formed with a thickness of 1 nm, and TPD that was the second organic compound layer was formed with a thickness of 50 nm. The current-voltage characteristics of Sample 4 are shown in FIG.

  FIG. 25E illustrates a sample 5 in which a first conductive layer 701, a first organic compound layer 741, a second organic compound layer 742, and a second conductive layer 703 are stacked in this order. The first conductive layer was formed of ITSO, the first organic compound layer was formed of TPD to which F4-TCNQ was added, the second organic compound layer was formed of TPD, and the second conductive layer was formed of aluminum. In addition, the first organic compound layer was formed to a thickness of 40 nm, and F4-TCNQ was added at a ratio of 0.01 wt. The second organic compound layer was formed with a thickness of 40 nm. The current-voltage characteristics of Sample 5 are shown in FIG.

  FIG. 25F illustrates a sample 6 in which a first conductive layer 701, a first organic compound layer 751, a second organic compound layer 752, and a second conductive layer 703 are stacked in this order. The first conductive layer was formed of ITSO, the first organic compound layer was formed of TPD, the second organic compound layer was formed of TPD added with F4-TCNQ, and the second conductive layer was formed of aluminum. The first organic compound layer was formed with a thickness of 40 nm. In addition, the second organic compound layer was formed to a thickness of 10 nm by adding F4-TCNQ in a 0.01 wt ratio. The current-voltage characteristics of Sample 6 are shown in FIG.

  Also from the experimental results shown in FIGS. 22 to 24, in Samples 1 to 6, there is a large change in the current-voltage characteristics of the memory element before data writing and before and after the memory element writing. Moreover, in the memory elements of these samples, the voltage at which each memory element is short-circuited was also reproducible, and the error was within 0.1V.

Next, Table 1 shows the writing voltage of Sample 1 to Sample 6 and the characteristics before and after writing.

  In Table 1, the write voltage (V) indicates an applied voltage value when each memory element is short-circuited. R (1 V) is a value obtained by dividing the current density after writing of the memory element at the applied voltage of 1 V by the current density before writing. Similarly, R (3V) is a value obtained by dividing the current density after writing of the memory element at the applied voltage of 3V by the current density before writing. That is, it shows a change in current density that flows after writing to the memory element. It can be seen that when 1 V is applied compared to the applied voltage of 3 V, the difference in the current density of the organic memory element is as large as 10 4 or more.

  Note that in the case where the memory element as described above is used as a memory circuit, a predetermined voltage value (a voltage value that does not cause a short circuit) is applied to the memory element every time data is read, and the resistance value is read. Is called. Therefore, the current-voltage characteristics of the memory element must have characteristics that do not change even if the read operation is repeated, that is, a predetermined voltage value is repeatedly applied. Therefore, measurement results of current-voltage characteristics of the memory element after the data read operation are described with reference to FIGS. Note that in this experiment, the current-voltage characteristics of the memory element were measured each time the data reading operation was performed once. Since the data reading operation was performed five times in total, the current-voltage characteristics of the memory element were measured five times in total. In addition, the measurement of the current-voltage characteristics was performed on two memory elements, that is, a memory element in which data was written by an electrical action and a resistance value was changed, and a memory element in which the resistance value was not changed. .

  In FIG. 17, the horizontal axis represents the voltage value, the vertical axis represents the current value, the plot 271 represents the current-voltage characteristics of the memory element in which the resistance value has been changed by writing data by electrical action, and the plot 272 represents the resistance value. The current-voltage characteristic of the memory element which is not shown is shown. As can be seen from the plot 271, the current-voltage characteristic of the memory element whose resistance value has not changed exhibits particularly good reproducibility when the voltage value is 1 V or more. Similarly, as can be seen from the plot 272, the current-voltage characteristic of the memory element whose resistance value has changed shows particularly good reproducibility when the voltage value is 1 V or more. From the above results, even when the data read operation is repeated a plurality of times, the current-voltage characteristics do not change greatly and the reproducibility is good. The above memory element can be used as a memory circuit.

  In this embodiment, a laser irradiation apparatus used when data is written to a memory circuit by an optical action will be described with reference to the drawings.

A laser irradiation apparatus 1001 includes a computer 1002 that executes various controls when irradiating laser light, a laser oscillator 1003 that outputs laser light, a power source 1004, an optical system 1005 that attenuates laser light, and laser light. An acousto-optic modulator 1006 for modulating the intensity of the light, an optical system 1007 composed of a lens for reducing the cross section of the laser light, a mirror for changing the optical path, and the X-axis stage and the Y-axis stage. A moving mechanism 1009, a D / A converter 1010 that converts control data output from the computer 1002, and a driver 1011 that controls the acousto-optic modulator 1006 in accordance with an analog voltage output from the D / A converter. A driver 1012 that outputs a signal for driving the moving mechanism 1009, and laser light on the object to be irradiated. And a auto-focus mechanism 1013 for adjusting the point (see Figure 18). As the laser oscillator 1003, a laser oscillator that can oscillate ultraviolet light, visible light, or infrared light can be used. Specifically, an excimer laser oscillator such as ArF, KrF, XeCl, or Xe, He , He—Cd, Ar, He—Ne, HF and other gas laser oscillators, YAG, GdVO ₄ , YVO ₄ , YLF, YAlO ₃ and other crystals with Cr, Nd, Er, Ho, Ce, Co, Ti, or Tm A solid-state laser oscillator using a doped crystal or a semiconductor laser oscillator such as GaN, GaAs, GaAlAs, InGaAsP can be used.

  Next, the operation of the laser irradiation apparatus 1001 having the above configuration will be described. First, when the substrate 1014 is mounted on the moving mechanism 1009, the computer 1002 detects the position of the memory element that emits the laser light by a camera (not shown). Next, the computer 1002 generates movement data for moving the movement mechanism 1009 based on the detected position data. Subsequently, the computer 1002 controls the output light amount of the acousto-optic modulator 1006 via the driver 1011, so that the laser light output from the laser oscillator 1003 is attenuated by the optical system 1005 and then the acousto-optic modulator. The amount of light is controlled by 1006 so as to obtain a predetermined amount of light. On the other hand, the laser light output from the acousto-optic modulator 1006 is changed in optical path and beam spot shape by the optical system 1007, condensed by a lens, and then irradiated onto the substrate 1014. At this time, the movement mechanism 1009 is controlled to move in the X direction and the Y direction according to the movement data generated by the computer 1002. As a result, laser light is irradiated to a predetermined place, the light energy density of the laser light is converted into thermal energy, and the memory element provided over the substrate 1014 is selectively irradiated with the laser light. Note that, according to the above description, an example in which the laser beam is irradiated by moving the moving mechanism 1009 is shown; however, the laser beam may be moved in the X direction and the Y direction by adjusting the optical system 1007. .

  The present invention in which data is written by irradiating a laser beam using the laser irradiation apparatus as described above can be easily written by being incorporated in a reader / writer. Therefore, a large amount of data can be written in a short time.

  Although the application of the semiconductor device of the present invention is wide-ranging, specific examples of the application will be described below. The semiconductor device 20 of the present invention includes, for example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident card, etc., see FIG. 19A), packaging containers (wrapping paper and bottles, etc.) 19 (B)), recording medium (DVD software, video tape, etc., see FIG. 19 (C)), vehicles (bicycles, etc., see FIG. 19 (D)), personal items (bags, glasses, etc.) (See FIG. 19 (E)), and can be used by being provided in articles such as foods, clothes, daily necessities, and electronic devices. An electronic device refers to a liquid crystal display device, an EL display device, a television device (also simply called a television, or a television receiver or a television receiver), a mobile phone, or the like.

  The semiconductor device 20 of the present invention is fixed to an article by being mounted on a printed board, pasted on a surface, or embedded. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin, and is fixed to each article. Since the semiconductor device 20 of the present invention is small, thin, and lightweight, it does not impair the design of the article itself even after being fixed to the article. In addition, by providing the semiconductor device 20 of the present invention on bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and if this authentication function is utilized, forgery can be prevented. Can do. In addition, by providing the semiconductor device of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved.

  Next, one mode of an electronic device in which the semiconductor device of the present invention is mounted will be described with reference to the drawings. The electronic device illustrated here is a mobile phone, which includes housings 2700 and 2706, a panel 2701, a housing 2702, a printed wiring board 2703, operation buttons 2704, and a battery 2705 (see FIG. 20). The panel 2701 is detachably incorporated in the housing 2702, and the housing 2702 is fitted on the printed wiring board 2703. The shape and dimensions of the housing 2702 are changed as appropriate in accordance with the electronic device in which the panel 2701 is incorporated. A plurality of packaged semiconductor devices are mounted on the printed wiring board 2703, and the semiconductor device of the present invention can be used as one of them. The plurality of semiconductor devices mounted on the printed wiring board 2703 have any one function of a controller, a central processing unit (CPU), a memory, a power supply circuit, a sound processing circuit, a transmission / reception circuit, and the like.

  The panel 2701 is bonded to the printed wiring board 2703 through the connection film 2708. The panel 2701, the housing 2702, and the printed wiring board 2703 are housed in the housings 2700 and 2706 together with the operation buttons 2704 and the battery 2705. A pixel region 2709 included in the panel 2701 is arranged so as to be visible from an opening window provided in the housing 2700.

  As described above, the semiconductor device of the present invention is characterized in that it is small, thin, and lightweight, and the limited space inside the housings 2700 and 2706 of the electronic device can be effectively used due to the above characteristics. .

  In addition, since the semiconductor device of the present invention has a structure in which a layer including a memory element is stacked over a layer including a TFT, an electronic device using a small semiconductor device can be provided.

  In addition, since the semiconductor device of the present invention includes a memory element with a simple structure in which an organic compound layer or a phase change layer is sandwiched between a pair of conductive layers, an electronic device using an inexpensive semiconductor device can be provided. . In addition, since the semiconductor device of the present invention can be easily integrated, an electronic device using the semiconductor device including a large-capacity memory circuit can be provided.

  Further, a memory circuit included in the semiconductor device of the present invention writes data by an optical action or an electrical action, is nonvolatile, and can additionally write data. With the above feature, forgery due to rewriting can be prevented, and new data can be added and written. Therefore, an electronic device using a semiconductor device that achieves high functionality and high added value can be provided.

  Note that the housings 2700 and 2706 are examples of the appearance of a mobile phone, and the electronic device according to the present embodiment can be transformed into various modes depending on the function and application.

  Next, an example of a system using the semiconductor device of the present invention will be described. First, the reader / writer 295 is provided on the side surface of the portable terminal including the display portion 294, and the semiconductor device 20 of the present invention is provided on the side surface of the article 297 (see FIG. 21A). In addition, information such as the raw material and origin of the article 297 and the history of the distribution process are stored in the semiconductor device 20 in advance. If the information included in the semiconductor device 20 is displayed on the display unit 294 at the same time as holding the semiconductor device 20 over the reader / writer 295, a system with excellent convenience can be provided. As shown in FIG. 21B, a reader / writer 295 is provided on the side of the belt conveyor. Then, a system capable of performing inspection of the article 297 very easily can be provided. In this manner, by utilizing the semiconductor device of the present invention for an article management or distribution system, the system can be improved in functionality and convenience can be improved.

6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 3A and 3B each illustrate a memory circuit of the present invention. 3A and 3B each illustrate a memory element of the present invention. 3A and 3B each illustrate a memory circuit of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. FIG. 11 shows current-voltage characteristics of a memory element. FIG. 11 shows current-voltage characteristics of a memory element. The figure explaining laser irradiation equipment 4A and 4B each illustrate a usage pattern of a semiconductor device of the invention. 4A and 4B each illustrate an electronic device using a semiconductor device of the present invention. 4A and 4B each illustrate a usage pattern of a semiconductor device of the invention. FIG. 11 shows current-voltage characteristics of a memory element. FIG. 11 shows current-voltage characteristics of a memory element. FIG. 11 shows current-voltage characteristics of a memory element. FIG. 9 illustrates a structure of a memory element. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention.

Claims (25)

A transistor provided over the insulating layer;
A conductive layer functioning as a source wiring or a drain wiring of the transistor;
A memory element superimposed on the transistor;
A conductive layer that functions as an antenna,
The memory element is an element in which a first conductive layer, an organic compound layer or a phase change layer, and a second conductive layer are sequentially stacked.
The semiconductor device, wherein the conductive layer functioning as an antenna and the conductive layer functioning as a source wiring or a drain wiring of the plurality of transistors are provided in the same layer. A transistor provided over the insulating layer;
A memory element superimposed on the transistor;
A conductive layer that functions as an antenna,
The memory element is an element in which a first conductive layer, an organic compound layer or a phase change layer, and a second conductive layer are sequentially stacked.
The semiconductor device, wherein the conductive layer functioning as an antenna and the first conductive layer are provided in the same layer. A transistor provided over the insulating layer;
A memory element superimposed on the transistor;
A conductive layer that functions as an antenna,
The memory element is an element in which a first conductive layer, an organic compound layer or a phase change layer, and a second conductive layer are sequentially stacked.
The semiconductor device, wherein the conductive layer functioning as an antenna and the second conductive layer are provided in the same layer.   4. The semiconductor device according to claim 1, wherein the memory element overlaps with part of the transistor. A first element forming layer; a second element forming layer; an adhesive layer that adheres the first element forming layer and the second element forming layer and includes conductive particles;
The first element formation layer includes a transistor provided over an insulating layer, a conductive layer functioning as a source wiring or a drain wiring of the transistor, and a conductive layer functioning as an antenna provided over the transistor. And
The second element formation layer includes a memory element in which a first conductive layer, an organic compound layer or a phase change layer, and a second conductive layer are stacked.
The semiconductor device, wherein the first conductive layer or the second conductive layer and the conductive layer functioning as a source wiring or a drain wiring of the transistor are connected through conductive particles. An element forming layer, a substrate provided with a conductive layer functioning as an antenna, and an adhesive layer that adheres the element forming layer and the substrate and includes conductive particles;
The element formation layer includes first and second transistors provided on an insulating layer;
A conductive layer functioning as a source wiring or a drain wiring of the first transistor;
A storage element that overlaps with the second transistor and in which the first conductive layer, the organic compound layer, or the phase change layer, and the second conductive layer are stacked;
The semiconductor device, wherein the conductive layer functioning as an antenna and the conductive layer functioning as a source wiring or a drain wiring of the first transistor are connected through conductive particles. A first element forming layer; a second element forming layer; an adhesive layer that adheres the first element forming layer and the second element forming layer and includes conductive particles;
The first element formation layer includes first and second transistors provided on an insulating layer;
A first conductive layer that functions as a source wiring or a drain wiring of the first transistor; and a second conductive layer that functions as a source wiring or a drain wiring of the second transistor;
The second element formation layer includes a first conductive layer, an organic compound layer or a phase change layer, a memory element in which the second conductive layer is stacked, and a conductive layer functioning as an antenna.
The conductive layer functioning as an antenna and the first conductive layer functioning as a source wiring or a drain wiring of the first transistor are connected via the conductive particles,
The first conductive layer or the second conductive layer of the memory element is connected to the second conductive layer functioning as a source wiring or a drain wiring of the second transistor through the conductive particles. A semiconductor device. A transistor provided over a substrate, a conductive layer functioning as a source wiring or a drain wiring of the transistor, a first element formation layer having a conductive layer functioning as an antenna provided over the plurality of transistors;
The memory element is provided on the substrate or the first element formation layer through an adhesive layer, and the first conductive layer, the organic compound layer or the phase change layer, and the second conductive layer are stacked. A second element forming layer,
The semiconductor, wherein the first conductive layer or the second conductive layer of the memory element is connected to the conductive layer functioning as a source wiring or a drain wiring of the transistor through the conductive member. apparatus. An element forming layer, a substrate provided with a conductive layer functioning as an antenna, and an adhesive layer that adheres the element forming layer and the substrate and has conductive particles;
The element formation layer includes first and second transistors provided on an insulating layer;
An interlayer insulating layer covering the first and second transistors;
The first transistor is connected to a source region or a drain region through an opening provided in the interlayer insulating layer, and the opening is provided in each of the insulating layer and the interlayer insulating layer. A conductive layer functioning as a source wiring or a drain wiring of the first transistor exposed on the back surface of the element formation layer;
A storage element that overlaps with the second transistor and is stacked with the first conductive layer, the organic compound layer or the phase change layer, and the second conductive layer;
The semiconductor, wherein the conductive layer functioning as the antenna and the exposed portion of the conductive layer functioning as the source wiring or drain wiring of the first transistor are connected through the conductive particles of the adhesive layer apparatus. A first element forming layer; a second element forming layer; an adhesive layer that adheres the first element forming layer and the second element forming layer and has conductive particles;
The first element formation layer includes a transistor provided over an insulating layer;
An interlayer insulating layer covering the transistor;
The first element is formed through an opening provided in each of the insulating layer and the interlayer insulating layer, and connected to a source / drain region of the transistor through an opening provided in the interlayer insulating layer. A conductive layer functioning as a source wiring or a drain wiring of the transistor exposed on the back surface of the layer;
And a conductive layer that functions as an antenna,
The second element formation layer has a memory element in which a first conductive layer, an organic compound layer or a phase change layer, and a second conductive layer are stacked.
The first conductive layer or the second conductive layer of the memory element and the exposed portion of the conductive layer functioning as a source wiring or a drain wiring of the transistor are electrically connected through the conductive particles of the adhesive layer. A semiconductor device which is connected. A first element forming layer; a second element forming layer; an adhesive layer that adheres the first element forming layer and the second element forming layer and has conductive particles;
The first element formation layer includes first and second transistors provided on an insulating layer;
An interlayer insulating layer covering the first and second transistors;
An opening provided in each of the insulating layer and the interlayer insulating layer is connected to a source region or a drain region of the first and second transistors through an opening provided in the interlayer insulating layer. A first conductive layer and a second conductive layer functioning as a source wiring or a drain wiring of the first and second transistors exposed on the back surface of the first element formation layer,
The second element formation layer includes a conductive layer functioning as an antenna, and a memory element in which the first conductive layer, the organic compound layer or the phase change layer, and the second conductive layer are stacked.
The first conductive layer or the second conductive layer of the memory element and the exposed portion of the first conductive layer functioning as a source wiring or a drain wiring of the first transistor are the conductive particles of the adhesive layer Electrically connected through
The conductive layer functioning as the antenna and the exposed portion of the second conductive layer functioning as the source wiring or drain wiring of the second transistor are connected through the conductive particles of the adhesive layer. Semiconductor device. A first element formation layer, a second element formation layer, the first element formation layer, the first element formation layer, the first adhesion layer having conductive particles, and an antenna A substrate having a functional conductive layer; and a second adhesive layer having conductive particles adhered to the second element formation layer and the substrate;
The first element formation layer includes a memory element in which a first conductive layer, an organic compound layer or a phase change layer, and a second conductive layer are stacked.
The second element formation layer includes first and second transistors provided on an insulating layer;
An interlayer insulating layer covering the first and second transistors;
A first conductive layer connected to a source region or a drain region of the first transistor through an opening provided in the interlayer insulating layer and functioning as a source wiring or a drain wiring of the first transistor;
The second transistor is connected to a source region or a drain region through an opening provided in the interlayer insulating layer, and the first transistor is connected to the second transistor through an opening provided in each of the insulating layer and the interlayer insulating layer. A second conductive layer functioning as a source wiring or a drain wiring of a transistor exposed on the back surface of the first element formation layer,
The first conductive layer or the second conductive layer of the memory element and the first conductive layer functioning as a source wiring or a drain wiring of the first transistor are the conductive particles of the first adhesive layer. Electrically connected through
The conductive layer functioning as the antenna and the exposed portion of the second conductive layer functioning as the source wiring or drain wiring of the second transistor are connected through the conductive particles of the adhesive layer. Semiconductor device.   13. The semiconductor device according to claim 1, wherein the transistor connected to the memory element, the first transistor, or the second transistor is a thin film transistor.   14. The semiconductor device according to claim 1, wherein the transistor connected to the memory element is an organic semiconductor transistor.   The semiconductor device according to claim 1, wherein the insulating layer is a silicon oxide layer.   16. The semiconductor device according to claim 1, wherein an electric resistance value of the memory element is changed by an optical action.   16. The semiconductor device according to claim 1, wherein a resistance value of the memory element is changed by an electrical action.   15. The semiconductor device according to claim 14, wherein the organic compound layer is made of a conjugated polymer material doped with a photoacid generator.   18. The semiconductor device according to claim 17, wherein the organic compound layer is made of an electron transport material or a hole transport material.   16. The semiconductor device according to claim 1, wherein the phase change layer includes a material that reversibly changes between a crystalline state and an amorphous state.   The phase change layer according to claim 20, wherein the phase change layer is a material having a plurality selected from germanium, tellurium, antimony, sulfur, tin, gold, gallium, selenium, indium, thallium, cobalt, or silver. Semiconductor device.   16. The semiconductor device according to claim 15, wherein the phase change layer includes a material that reversibly changes between a first crystal state and a second crystal state.   23. The semiconductor device according to claim 22, wherein the phase change layer is a material having a plurality selected from silver, zinc, copper, aluminum, nickel, indium, antimony, selenium, or tellurium.   16. The semiconductor device according to claim 15, wherein the phase change layer includes a material that changes only from an amorphous state to a crystalline state. 25. The semiconductor device according to claim 24, wherein the phase change layer is a material having a plurality selected from tellurium, tellurium oxide, antimony, selenium, or bismuth.

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