JP5227536B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit formed by stacking semiconductor elements.

Development of a technique for achieving high integration of a semiconductor integrated circuit by stacking semiconductor substrates on which integrated circuits are formed has been underway. A semiconductor integrated circuit formed by stacking such semiconductors is manufactured by sequentially stacking semiconductor substrates on which integrated circuits are formed. A semiconductor integrated circuit formed by stacking semiconductors is formed by forming an integrated circuit on each semiconductor substrate, and laminating the semiconductor substrate. (For example, refer to Patent Documents 1 and 2).
JP-A-6-61418 JP 2001-189419 A

  However, in the conventional method of manufacturing a semiconductor integrated circuit formed by stacking semiconductors, an opening is formed in a part of a semiconductor substrate by etching or the like, and then the semiconductor substrate is polished from the back surface to form a through-hole (through-hole). A hole). And the integrated circuit formed in each semiconductor substrate is connected by forming wiring in the through-hole by vapor deposition or plating.

  As described above, the process of forming a through hole in the semiconductor substrate or the process of polishing the semiconductor substrate from the back surface takes a very long time and becomes a factor of reducing productivity. In addition, the process of forming a through hole in the semiconductor substrate or the process of polishing from the back surface is a factor that generates dust and thereby causes a failure in the integrated circuit. In addition, a semiconductor integrated circuit formed by stacking semiconductors has a structure in which semiconductor substrates are stacked, and thus has a thick structure and poor mechanical flexibility.

  An object of the present invention is to improve the productivity of an integrated circuit formed by stacking semiconductors. Another object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit having mechanical flexibility by reducing the thickness of an integrated circuit formed by stacking semiconductors.

  In the present invention, a release layer is formed on a plurality of substrates, and an opening for a semiconductor element and a through wiring is formed on the release layer. Then, the gist of the invention is to fabricate a semiconductor integrated circuit by peeling a layer having a semiconductor element from a substrate, stacking them on top of each other, and filling a conductive material in an opening to form a through wiring. Note that in this specification, the opening is formed so as to penetrate a layer having a semiconductor element. In addition, a part of the layer having a semiconductor element located under the opening has conductivity. Furthermore, the side surface of the opening may have conductivity. Forming a through wiring (also simply referred to as a wiring) means filling an opening with a conductive material and electrically connecting layers having upper and lower semiconductor elements.

According to a method for manufacturing a semiconductor integrated circuit of the present invention, a first element formation layer including a semiconductor element formed of a semiconductor layer sandwiched between upper and lower insulating layers is formed on a first substrate, and a second substrate is formed. A peeling layer is formed thereon, and a second element formation layer having a semiconductor element formed of a semiconductor layer sandwiched between upper and lower insulating layers and an opening is formed on the peeling layer, The element formation layer is peeled off from the second substrate, bonded to the first element formation layer, a wiring is formed in the opening, and the first element formation layer and the second element formation layer are electrically connected. It is characterized by connecting to.
It is characterized by.

In the method for manufacturing a semiconductor integrated circuit according to the present invention, a first element formation layer having a semiconductor element formed of a semiconductor layer sandwiched between upper and lower insulating layers is formed on a first substrate, and the second element formation layer is formed. A second element having a first release layer formed on the substrate, a semiconductor element formed of a semiconductor layer sandwiched between upper and lower insulating layers on the first release layer, and an opening Forming a formation layer, peeling the second element formation layer from the second substrate, bonding the first element formation layer on the first element formation layer, and forming a wiring in an opening provided in the second element formation layer; Then, the first element formation layer and the second element formation layer are electrically connected to each other, a second separation layer is formed on the third substrate, and the insulating layer is formed above and below the second separation layer. Forming a third element forming layer having a semiconductor element formed of a semiconductor layer sandwiched between and an opening, and forming the third element forming layer from the third substrate. The first element formation layer and the third element formation layer are electrically connected to each other by forming a wiring in an opening provided in the third element formation layer. Features.

In the method for manufacturing a semiconductor integrated circuit according to the present invention, a first element formation layer having a semiconductor element formed of a semiconductor layer sandwiched between upper and lower insulating layers is formed on a first substrate, and the second element formation layer is formed. A second element having a first release layer formed on the substrate, a semiconductor element formed of a semiconductor layer sandwiched between upper and lower insulating layers on the first release layer, and an opening Forming a formation layer, separating the second element formation layer from the second substrate, bonding the first element formation layer on the first element formation layer, forming a second separation layer on the third substrate, A third element formation layer having a semiconductor element formed of a semiconductor layer sandwiched between upper and lower insulating layers and an opening is formed on the second release layer, and the third element formation layer is a third element formation layer. The second part is peeled off from the substrate, and the opening provided in the second element formation layer and the opening provided in the third element formation layer substantially coincide with each other. Bonding is performed on the element formation layer, and wiring is formed in the opening provided in the second element formation layer and the opening provided in the third element formation layer, thereby forming the first to third elements. The layers are electrically connected.

The semiconductor integrated circuit according to the present invention includes a first element forming layer having a semiconductor element formed of a semiconductor layer sandwiched between upper and lower insulating layers, and a semiconductor element formed of a semiconductor layer sandwiched between upper and lower insulating layers. And a second element formation layer having an opening, and a wiring is formed in the opening.

The semiconductor integrated circuit of the present invention is formed of a first element formation layer having a semiconductor element formed of a semiconductor layer sandwiched between upper and lower insulating layers, and a semiconductor layer sandwiched between upper and lower insulating layers. A second element formation layer having a semiconductor element and an opening; a semiconductor element formed of a semiconductor layer sandwiched between upper and lower insulating layers; and a third element formation layer having an opening; Are stacked, and the first to third element formation layers are bonded so that the opening provided in the second element formation layer and the opening provided in the third element formation layer substantially coincide with each other. Each opening is formed with a wiring.

  Note that in this specification, a peeling layer means a layer that facilitates peeling of a layer having a plurality of semiconductor elements from a substrate.

  The present invention provides an integrated circuit formed by stacking semiconductors by forming an integrated circuit including a semiconductor element formed of a semiconductor layer sandwiched between insulating layers on a substrate, and then stacking it after peeling it from the substrate. The circuit can be thinned. In addition, by manufacturing the semiconductor integrated circuit of the present invention over a flexible substrate such as plastic, a thin, light, and flexible semiconductor device can be formed.

  In addition, since the step of forming a through hole in a semiconductor substrate having a thickness of several micrometers to several hundred micrometers is omitted, productivity can be improved. That is, since it is not necessary to polish the semiconductor substrate in order to form a through hole in the semiconductor substrate, generation of dust can be suppressed and contamination of the semiconductor integrated circuit can be prevented.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the following embodiments. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In the semiconductor integrated circuit according to this embodiment, a layer having a semiconductor element (hereinafter also referred to as an element formation layer) is formed on each of a plurality of substrates. The semiconductor integrated circuit according to this embodiment is manufactured by peeling off the layer having the semiconductor element and stacking the layers on one substrate. In order to peel a layer having a semiconductor element from a substrate, a peeling layer is formed over the substrate, and a layer having a semiconductor element is formed over the peeling layer. In addition, the layer having the semiconductor elements stacked and bonded is electrically connected to the upper layer or the lower layer by through wiring.

  In this embodiment mode, an outline of a method for manufacturing a semiconductor integrated circuit of the present invention will be described with reference to FIGS.

  As shown in FIG. 1A, a first element formation layer 602 including a semiconductor element is formed over a first substrate 601. The first element formation layer 602 is a lowermost layer of a semiconductor integrated circuit formed by stacking layers having semiconductor elements. In the case of manufacturing a semiconductor integrated circuit over the first substrate 601, the first element formation layer 602 can be formed without providing a separation layer over the first substrate 601. In the case where the first element formation layer 602 is peeled off from the first substrate 601 and attached to another substrate to form a semiconductor integrated circuit, the first element formation layer 602 and the first element formation layer 602 are separated from each other. A release layer is formed between them. In this embodiment, an example in which the first element formation layer 602 is formed without providing a separation layer over the first substrate 601 is described.

  Next, as illustrated in FIG. 1B, a separation layer 604 and a second element formation layer 605 including a semiconductor element are formed over the second substrate 603. The second element formation layer 605 has an opening 606 for through wiring. Similarly, a separation layer 604 and a third element formation layer 608 including a semiconductor element are formed over the third substrate 607. Similar to the second element formation layer 605, the third element formation layer 608 has an opening 606 for through wiring.

  In this way, as many element formation layers as necessary for forming a semiconductor integrated circuit are formed. For example, when three element formation layers are stacked, a third element formation layer is formed from the first element formation layer on each of the first substrate, the second substrate, and the third substrate. Note that the second element formation layer and the third element formation layer have openings for through wiring.

  In this embodiment, the first element formation layer 602 to the nth element formation layer 610 are formed over the first substrate 601 to the nth (n ≧ 2) substrate 609, respectively, so that n layers of elements are formed. An example of manufacturing a semiconductor integrated circuit by stacking formation layers is shown (see FIG. 1B). Here, the separation layer 604 is formed over the second substrate 603 to the nth substrate 609, and then the second element formation layer 605 to the nth element formation layer 610 are formed. Further, the second element formation layer 605 to the n-th element formation layer 610 have openings 606 for through wirings.

  Next, as illustrated in FIG. 1C, the second element formation layer 605 to the nth element formation layer 610 formed over the second substrate 603 to the nth substrate 609 are peeled off.

  Then, as illustrated in FIG. 2A, the second element formation layer 605 which is separated from the second substrate 603 is attached to the first element formation layer 602. Then, as shown in FIG. 2B, an opening 606 provided in the second element formation layer 605 is filled with a conductive material. In this embodiment mode, a conductive paste 611 is used as a conductive material and is dropped into the opening 606. A through wiring 612 is formed in the opening 606 into which the conductive paste 611 is dropped (FIG. 2C) to electrically connect the first element formation layer 602 and the second element formation layer 605. .

  Similarly, as illustrated in FIG. 2C, the third element formation layer 608 which is separated from the third substrate 607 is attached to the second element formation layer 605. Then, as shown in FIG. 2D, through wiring 612 is formed by dropping conductive paste 611 into the opening 606 provided in the third element formation layer 608, and the second element formation layer 605 is formed. Are electrically connected to the third element formation layer 608.

  The above steps are repeated, and finally, as shown in FIG. 2E, the n-th element formation layer 610 peeled from the n-th substrate 609 is bonded onto the n−1-th element formation layer 613. Then, as shown in FIG. 2F, through wiring 612 is formed by dropping a conductive paste 611 into an opening 606 provided in the n-th element formation layer 610, and the n-th element formation layer 610 is formed. And the (n−1) th element formation layer 613 are electrically connected to each other, so that a semiconductor integrated circuit 614 in which layers each including a plurality of semiconductor elements are stacked and attached can be manufactured (see FIG. 2G). ). Note that in this specification, being connected is synonymous with being electrically connected.

  The peeling layer 604 that creates a boundary for peeling off the second element formation layer 605 from the second substrate 603 is a film having a lamination relationship that is physically low in lamination, or heating, laser light irradiation, ultraviolet irradiation For example, a film whose properties are changed and weakened by some treatment, or a film which can reduce the adhesion between stacked films is used. Then, the second substrate 603 and the second element formation layer 605 can be peeled from the interface of the film with reduced adhesion. For example, it is known that a metal film that is difficult to oxidize, such as a noble metal, and an oxide film (for example, an oxide film of silicon) have low adhesion. By utilizing this, a metal film and a silicon oxide film are stacked on the second substrate 603 as a peeling layer 604, and a second element formation layer 605 is formed thereon, whereby a metal film and a silicon oxide film are formed. The second element formation layer 605 can be peeled from the second substrate 603 at the interface.

  Examples of the material for the separation layer 604 formed over the second substrate 603 and the method for separating the second element formation layer 605 from the second substrate 603 can include the following examples.

(1) A single-layer or stacked metal oxide film is provided as the separation layer 604 over the second substrate 603. Then, the metal oxide film that is the separation layer 604 is weakened by heating, laser light irradiation, or the like, and the second substrate 603 and the second element formation layer 605 are separated. Here, when a light-transmitting substrate such as a glass substrate or a quartz substrate is used as the second substrate 603, laser irradiation can be performed from the back surface of the substrate. It is considered that the metal oxide film is weakened by heating or laser irradiation because the metal oxide film is crystallized.

(2) An amorphous silicon film containing hydrogen is provided as the separation layer 604 over the second substrate 603. Then, the second substrate 603 and the second element formation layer 605 are separated by weakening the separation layer 604 by heating or laser light irradiation, or by removing the separation layer 604 by etching.

(3) A second element formation layer 605 is provided over the second substrate 603 (without providing the peeling layer 604). Then, the second substrate 603 is polished from the back surface to be thinned or removed, or the substrate is removed by etching, whereby the second element formation layer 605 is obtained. For example, when a quartz substrate is used as the second substrate 603, the substrate can be removed by etching using an HF solution, HF vapor, CHF ₃ , or a mixed gas of C ₄ F ₈ and H ₂ . When a silicon substrate is used as the second substrate 603, the substrate can be removed by etching with a halogen fluoride gas such as NF ₃ , BrF ₃ , or ClF ₃ .

(4) A metal film and a metal oxide film are stacked over the second substrate 603 as the separation layer 604. Then, the metal oxide film is weakened by heating or laser irradiation, and then part of the peeling layer 604 is removed by etching, and physically peeled off at the interface between the weakened metal oxide film and the metal film. For example, when the release layer 604 is formed using a metal such as tungsten (W) or molybdenum (Mo), a chlorine-based gas typified by a solution such as ammonia perwater, CCl ₄ , Alternatively, a mixed gas of fluorine gas and O ₂ typified by CF ₄ , SF _6, NF _3, or the like can be used. In the case where the separation layer 604 is formed using a metal such as aluminum (Al) or titanium (Ti), an acidic solution or a Cl ₂ gas can be used for etching. Note that the metal oxide film or the amorphous silicon film formed as the separation layer 604 can be physically separated without undergoing a step of weakening or etching the separation layer 604.

  As a method for physically peeling the peeling layer, for example, a cut is made at the end portion of the second substrate 603 to make a peeling between the second substrate 603 and the second element formation layer 605. From there, the second element formation layer 605 can be peeled off.

  Here, the peeling layer 604 and the second element formation layer 605 formed over the second substrate 603 have been described. In addition, by applying the above method, a separation layer 604 and a second element formation layer 605 to an nth element formation layer 610 are formed over the second substrate 603 to the nth substrate 609, respectively. The second element formation layer 605 to the nth element formation layer 610 can be peeled off.

  In addition, the method in which the second element formation layer 605 is bonded to the first element formation layer 602 and the nth element formation layer 610 is bonded to the (n−1) th element formation layer 613 is obtained by opening the adhesive layer to the opening. It can be selectively formed in a portion other than 606 and the upper and lower layers can be bonded. As the adhesive layer, an insulating inorganic compound, organic compound, or the like can be used, and it can be used in a single layer or a stacked structure. Furthermore, it is also possible to use a material whose main raw material is an organic compound such as polyimide, epoxy or acrylic (for example, a permanent thick film resist whose main raw material is used). An anisotropic conductive material may be used as the adhesive layer. In the case where an anisotropic conductive material is used, it is preferable that an adhesive layer is not selectively formed.

  As described above, the opening 606 is formed to drop the conductive paste 611 to electrically connect the upper and lower layers and form the through wiring 612. Accordingly, a conductive layer is formed around the opening 606 of the n-th element formation layer 610 and on the outermost surface of the n−1th element formation layer 613 located below the opening 606 of the n-th element formation layer 610. Then, when the conductive paste 611 is dropped, the shape and structure are such that the upper and lower layers are electrically connected.

  Further, as a method that can be most easily considered as the dropping of the conductive paste 611, there is a method in which the entire surface of the layer is applied using a spin coating method. When applying this method, if necessary, after applying the conductive paste 611 by the spin coat method, a step of wiping the applied surface and removing the unnecessary conductive paste 611 may be added. Alternatively, a method of selectively dropping the conductive paste 611 into the opening 606 by using a droplet discharge method typified by inkjet, a screen printing method, or the like can be used.

  Here, the conductive paste 611 refers to a conductive particle having a particle size of several tens of micrometers or less dissolved or dispersed in an organic resin. As conductive particles, silver (Ag), copper (Cu), aluminum (Al), gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo) And metal particles such as titanium (Ti), silver halide fine particles, carbon black, or the like can be used. In addition, as the organic resin contained in the conductive paste, one or more selected from an organic resin that functions as a binder of metal particles, a solvent, a dispersant, and a coating material can be used. Typically, an organic resin such as an epoxy resin, a phenol resin, or a silicone resin can be given. Further, in forming the through wiring 612, it is preferable to fire after the conductive paste 611 is dropped into the opening 606. For example, in the case where fine particles containing silver as a main component (for example, particles having a particle diameter of 1 nm to 100 nm) are used as the material of the conductive paste 611, the conductive paste 611 is cured by baking at a temperature range of 150 to 300 ° C. Thus, the through wiring 612 can be formed.

  In the above-described steps, the example in which the layers are bonded and the step of dropping the conductive paste 611 is repeated. However, the present invention is not limited to this method. The through-wiring 612 may be formed by dropping the conductive paste 611. Specifically, as illustrated in FIG. 3A, second element formation layers 605 to nth element formation layers 610 are formed over the second substrate 603 to the nth substrate 609, respectively. As shown in FIG. 3B, the second element formation layer 605 to the nth element formation layer 610 are peeled. Then, as shown in FIG. 3C, the second element formation layer 605 to the nth element formation layer 610 are all formed over the first element formation layer 602 formed over the first substrate 601. to paste together. Then, as shown in FIG. 3D, a through wiring 612 is formed by dropping a conductive paste 611 into the opening 606 formed in the second element formation layer 605 to the n-th element formation layer 610. In addition, all the stacked layers can be electrically connected.

  In this case, as shown in FIG. 3, when the second element formation layer 605 to the nth element formation layer 610 are overlapped, the openings 606 provided in the respective layers are substantially aligned. Has been. In this specification, the term “substantially coincides” refers to an alignment error when the element formation layers are overlapped, and is a range in which the lower element formation layer and the upper element formation layer are electrically connected. In the inside, there may be a deviation in the overlap of the openings provided in each layer.

  As described above, by manufacturing the semiconductor integrated circuit using the method described above, the through wiring can be formed without the process of forming the through hole penetrating the substrate or the process of polishing the back surface of the substrate. Therefore, throughput can be improved. Further, since the back surface of the substrate is not polished, generation of dust can be suppressed and contamination of the semiconductor element and the semiconductor integrated circuit can be prevented.

  Further, a substrate for forming a layer having a plurality of semiconductor elements is formed without peeling through the substrate or forming a plurality of layers having a plurality of semiconductor elements from the substrate without polishing the back surface. Can be reused. This is one method for manufacturing a semiconductor integrated circuit at a low cost.

  In addition, since the layer having a plurality of semiconductor elements is separated from the substrate and stacked, the thickness of the semiconductor integrated circuit can be reduced. Further, a semiconductor integrated circuit is manufactured over a flexible substrate, or a semiconductor device that is thin, light, and flexible can be manufactured by using a structure in which the semiconductor integrated circuit does not include a substrate. .

(Embodiment 2)
In this embodiment mode, a method for manufacturing the first to n-th element formation layers constituting the semiconductor integrated circuit described in Embodiment Mode 1 and a semiconductor integrated circuit are manufactured by stacking these element formation layers. The method will be described with reference to FIGS. 4 to 9 are sectional views of the substrate, and FIG. 10 is a top view of the substrate.

  First, a method for manufacturing the second to nth element formation layers in Embodiment Mode 1 will be described. First, the first insulating layer 101 is formed on one surface of the substrate 100. Next, the separation layer 102 is formed over the first insulating layer 101. Subsequently, a second insulating layer 103 is formed over the separation layer 102 (see FIG. 4A).

  The substrate 100 is a substrate having an insulating surface, such as a glass substrate, a quartz substrate, a resin (plastic) substrate, a sapphire substrate, a silicon wafer having an insulating film on the upper surface, a metal plate, or the like. Preferably, a glass substrate or a plastic substrate is used as the substrate 100. A glass substrate or a plastic substrate having a side of 1 meter or more and a desired shape such as a square shape can be easily manufactured. For example, when a glass substrate or a plastic substrate having a quadrangular shape and a side of 1 meter or more is used, productivity can be significantly improved because a semiconductor integrated circuit to be manufactured has a quadrangular shape. Such an advantage is a great advantage as compared with the case of using a silicon substrate having a circular shape and a diameter of about 30 centimeters at the maximum.

  The first insulating layer 101 and the second insulating layer 103 include silicon oxide, silicon nitride, silicon oxide containing nitrogen, and oxygen by a vapor deposition method (CVD method), a sputtering method, or the like. Silicon nitride or the like is formed as a material. Further, the first insulating layer 101 and the second insulating layer 103 may have a stacked structure. The first insulating layer 101 serves to prevent an impurity element from the substrate 100 from entering the upper layer. Note that the first insulating layer 101 is not necessarily formed if not necessary.

  The release layer 102 is formed by sputtering or the like using tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium (Zr), Mainly selected from elements selected from zinc (Zn), ruthenium (Ru), rhodium (Rh), palladium (Pd), platinum (Pt), osmium (Os), iridium (Ir), silicon (Si), etc. A single layer or a stack of layers including a compound material including an alloy material or an alloy as a component is formed. Note that silicon contained in the layer containing silicon may be amorphous, microcrystalline, or polycrystalline.

  When the separation layer 102 has a single-layer structure, preferably, tungsten, molybdenum, a mixture of tungsten and molybdenum, tungsten oxide, tungsten nitride, tungsten oxynitride, tungsten nitride oxide, molybdenum oxide, Molybdenum nitride, molybdenum oxynitride, molybdenum nitride oxide, tungsten-molybdenum mixture oxide, tungsten-molybdenum nitride, tungsten-molybdenum oxynitride, tungsten-molybdenum mixture A layer containing any of the nitride oxides is formed.

In the case where the separation layer 102 is formed to have a stacked structure, for example, any one layer of tungsten, molybdenum, or a mixture containing a mixture of tungsten and molybdenum is formed as a first layer, and tungsten oxide or nitride is formed as a second layer. Oxide, nitride, oxynitride, molybdenum oxide, nitride, oxynitride, or nitride oxide, or mixture of tungsten and molybdenum, nitride, oxynitride, or oxynitride Things can be formed. These oxides and oxynitrides can be formed by performing oxygen plasma treatment or N ₂ O plasma treatment on the surface of the first layer.

  In the case where a stacked structure of a layer containing a metal such as tungsten and a layer containing an oxide of the metal is formed as the separation layer 102, a metal oxide is included by forming a layer containing silicon oxide over the layer containing a metal. You may utilize that the layer containing the said metal oxide is formed in the interface of a layer and the layer containing silicon oxide.

  In addition, the surface of the layer containing a metal such as tungsten is subjected to a thermal oxidation treatment, an oxygen plasma treatment, or a treatment with a strong oxidizing power such as ozone water, and the oxide containing the metal is contained on the layer containing the metal. After the layer is formed, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer can be formed thereover. The same applies to the case of forming a layer containing the metal nitride, oxynitride, and nitride oxide. Note that for the separation layer 102, a material that can have a selection ratio of etching to a conductive layer formed in a later step is preferably selected.

  Next, a plurality of semiconductor elements 96 are formed over the second insulating layer 103. Examples of the semiconductor element include a transistor, a diode, a capacitor, and a bipolar transistor. Here, as an example, a case where a plurality of thin film transistors is formed as a semiconductor element is shown (see FIG. 4B).

  Each of the plurality of semiconductor elements 96 includes a semiconductor layer 90, a gate insulating layer 91, and a first conductive layer 92 (also referred to as a gate electrode). The semiconductor layer 90 includes impurity regions 93 and 94 that function as a source or a drain and a channel formation region 95. An impurity element imparting N-type (for example, phosphorus (P) or arsenic (As)) or an impurity element imparting P-type (for example, boron (B)) is added to the impurity regions 93 and 94. The impurity region 94 is a low concentration impurity region (LDD: Light Doped Drain region). By providing the low concentration impurity region, generation of off current can be suppressed.

  In this embodiment, each of the plurality of semiconductor elements 96 has a top gate structure in which a gate insulating layer 91 is provided over a semiconductor layer 90 and a first conductive layer 92 is provided over the gate insulating layer 91. Show. However, the configuration of the plurality of semiconductor elements 96 is not limited to a specific configuration and can take various forms. For example, a bottom gate type in which a gate insulating layer 91 is provided on the first conductive layer 92 and a semiconductor layer 90 is provided on the gate insulating layer 91, or a conductive layer above and below the semiconductor layer 90 with a gate insulating layer interposed therebetween. May be provided. As described above, the structure in which the first conductive layer 92 is provided above and below the semiconductor layer 90 increases the channel region, so that the current value is increased or a depletion layer is easily formed. can do. One or more semiconductor elements selected from the plurality of semiconductor elements 96 may be multi-gate semiconductor elements having two or more gate electrodes and two or more channel formation regions. With a multi-gate structure, the off-state current is reduced, the breakdown voltage of the transistor is improved to improve reliability, or the drain and source voltage changes even when the voltage between the drain and source changes during operation in the saturation region. There is an effect that the current between the sources does not change so much and the characteristics are flat. Further, a source electrode or a drain electrode may overlap with a channel formation region (or a part thereof). With the structure in which the source electrode and the drain electrode overlap with the channel formation region (or a part thereof), it is possible to prevent electric charges from being accumulated in a part of the channel formation region and unstable operation.

  Note that although an example in which a thin film transistor is manufactured as the plurality of semiconductor elements 96 is described in this embodiment, various types of transistors can be applied to the transistor in the present invention, and there is no limitation on the type of applicable transistor. Therefore, a thin film transistor (TFT) using a non-single-crystal semiconductor film typified by amorphous silicon or polycrystalline silicon, a transistor formed using a semiconductor substrate or an SOI substrate, a MOS transistor, a junction transistor, or a bipolar transistor Etc. can be applied. Alternatively, a transistor using a compound semiconductor such as ZnO or a-InGaZnO, a transistor using an organic semiconductor or a carbon nanotube, or another transistor may be used. Note that the non-single-crystal semiconductor film may contain hydrogen or halogen.

  The plurality of semiconductor elements 96 constituting the semiconductor integrated circuit constitute a circuit in which a transistor, a diode (such as a PN diode, a PIN diode, a Schottky diode, or a diode-connected transistor) is combined. For example, when a transistor is used as a switch included in a logic circuit, the polarity (conductivity type) of the transistor is not particularly limited. However, when it is desirable that the off-state current is small, it is desirable to use a transistor having a polarity with a small off-state current. As a transistor with low off-state current, there are a transistor provided with an LDD region, a transistor having a multi-gate structure, and the like.

  Further, when the transistor operated as a switch operates at a source terminal potential close to a low potential power source (Vss, GND, 0 V, etc.), the N-channel type is used. On the contrary, the source terminal potential is a high potential. When operating in a state close to the side power supply (Vdd or the like), it is desirable to use a P-channel type. This is because the absolute value of the voltage between the gate and the source can be increased, and the transistor can easily function as a switch. Note that both N-channel and P-channel switches may be used as CMOS switches. When a CMOS switch is used, the voltage output through the switch (that is, the input voltage to the switch) is appropriately operated even when the situation changes, such as when the output voltage is high or low. I can do it.

  Further, the plurality of semiconductor elements 96 provided over the substrate are not limited to transistors, and various types of elements can be formed depending on the function of the semiconductor device to be manufactured. For example, in the case of forming a semiconductor device (for example, an RFID, an IC tag, or the like) that transmits and receives information without contact, elements such as a capacitor, a resistor, an inductor, and a diode can be formed over a substrate. In the case of forming a semiconductor device having a function of storing data (also referred to as a memory or a memory device), a transistor and a memory element can be formed over the substrate. Here, the memory element has various shapes and functions in accordance with required characteristics of the semiconductor device. For example, a memory element having a shape in which a layer containing an organic substance is sandwiched between two conductive layers or a transistor type memory element having a floating gate can be formed.

  Next, a fourth insulating layer 97 is formed over the plurality of semiconductor elements 96 (see FIG. 4B). The fourth insulating layer 97 is formed using an arbitrary film formation method such as a vapor deposition method, a sputtering method, an SOG (spin on glass) method, a droplet discharge method (for example, an ink jet method), an oxide of silicon, Silicon nitride, polyimide, acrylic, siloxane, oxazole resin, or the like is used as a material. Siloxane has, for example, a skeleton structure formed of a bond of silicon and oxygen, and has an organic group containing at least hydrogen (eg, an alkyl group or aromatic hydrocarbon), a fluoro group, or an organic group containing at least hydrogen as a substituent. A fluoro group is used. The oxazole resin is, for example, photosensitive polybenzoxazole. Oxazole resin has a low relative dielectric constant (about 2.9) compared to the relative dielectric constant (about 3.2 to 3.4) of polyimide, etc., so that the generation of parasitic capacitance is suppressed and high speed operation is performed. Can do.

  In this embodiment mode, an example in which two insulating layers are formed as the fourth insulating layer 97 over the plurality of semiconductor elements 96 is described; however, the present invention is not limited to this structure. In other words, the number of insulating layers provided on the plurality of semiconductor elements 96 is not limited. In the case where the insulating layer is formed as a single layer, the manufacturing process is simplified. On the other hand, when the insulating layer is formed as a stacked layer, the stress applied to the semiconductor element can be relaxed as compared with the case where the insulating layer is formed as a single layer.

  Next, contact holes 104 to 109 are formed in the fourth insulating layer 97 (see FIG. 4C). A method for forming contact holes 104 to 109 is not particularly limited. For example, the contact holes 104 to 109 can be formed by providing a mask formed of a resist or the like over the fourth insulating layer 97 and then etching the fourth insulating layer 97.

  Further, by etching the fourth insulating layer 97, the opening 110 is formed so that a part of the second insulating layer 103 is exposed. The opening 110 can be formed simultaneously with the contact holes 104 to 109 or can be formed separately.

  In the case where the opening 110 is formed simultaneously with the contact holes 104 to 109, a part of the second insulating layer 103 is exposed by etching the fourth insulating layer 97 simultaneously with the formation of the contact holes 104 to 109. Thus, the opening 110 is formed.

  In the case where the opening 110 is formed separately from the contact holes 104 to 109, a part of the second insulating layer 103 is exposed by etching the fourth insulating layer 97 after the contact holes 104 to 109 are formed. Thus, the opening 110 is formed. In the case where the opening 110 is formed separately from the contact holes 104 to 109, the fourth insulating layer 97 and the second conductive layer are formed over the contact holes 104 to 109 in the process described later, By etching the insulating layer 97 and the second insulating layer 103, the opening 110 can be formed so that part of the separation layer 102 is exposed.

  In this embodiment, an example in which the opening 110 is formed simultaneously with the contact holes 104 to 109 is shown.

  The method for forming the opening 110 is not particularly limited. For example, similarly to the formation of the contact holes 104 to 109, a mask formed of a resist or the like is provided on the fourth insulating layer 97, and then the fourth insulating layer 97 is etched to form the opening 110. be able to. There is no particular limitation on the etching method for forming the opening 110, and a wet etching method, a dry etching method, or a combination of both may be used.

  Note that when the opening portion 110 is formed by applying a general etching method, the side surface of the opening portion is formed at an angle of about 70 ° to 80 ° with respect to the substrate. By setting appropriately, the side surface of the opening 110 is preferably at an angle of 10 ° to 60 ° with respect to the substrate. More preferably, it forms so that it may become an angle of 30 degrees-50 degrees. With this angle, it is easy to form a second conductive layer to be formed later on the side surface of the opening 110. However, the implementation of the present invention is not limited to this structure.

  Subsequently, second conductive layers 111 to 116 are formed over the fourth insulating layer 97, the contact holes 104 to 109, and the opening 110 (see FIG. 4D). The second conductive layers 111 to 115 are connected to the source (also referred to as a source region or a source electrode) or the drain (also referred to as a drain region or a drain electrode) of each of the plurality of semiconductor elements 96. The part and the second conductive layer 116 are formed on the side surface of the opening 110.

  The second conductive layers 111 to 116 are selected from titanium, tungsten, chromium, aluminum, tantalum, nickel, zirconium, hafnium, vanadium, iridium, niobium, lead, platinum, molybdenum, cobalt, rhodium, or the like by sputtering or the like. These elements, or alloy materials containing these elements as main components, or compound materials such as oxides or nitrides containing these elements as main components, are formed in a single layer or a stacked layer. Examples of the laminated structure of the second conductive layers 111 to 116 include, for example, a three-layer structure of titanium, aluminum, and titanium, a five-layer structure of titanium, titanium nitride, aluminum, titanium, and titanium nitride, titanium, titanium nitride, There are five-layer structures of aluminum, titanium, and titanium nitride to which silicon is added. By forming the second conductive layers 111 to 116 by stacking, the contact resistance with the source or the drain can be reduced. Further, the stress applied to the second conductive layers 111 to 116 can be relaxed.

  Here, as an explanation of the opening 110, a top view corresponding to AB in FIG. 4D is shown in FIG. In the opening 110, the second conductive layer 160 is formed over the fourth insulating layer 97 and the second insulating layer 103. Note that the second conductive layer 160 corresponds to the second conductive layers 115 and 116 in FIG. 4D viewed from above. The bottom surface of the opening 110 is not covered with the second conductive layer 160 and the fourth insulating layer 97, and the second insulating layer 103 is exposed. Here, there is one hole (a portion where the second insulating layer 103 is exposed) provided in the bottom surface of the opening. For example, as illustrated in FIG. 10B, the second conductive layer is formed on the bottom surface. A plurality of 160 may be formed, and the bottom surface of the opening 110 may have a mesh shape. In addition, the shape of the opening 110 and the hole on the bottom surface thereof is rectangular here, but it may be circular or polygonal. Here, the rectangular shape and the polygonal shape include a shape with rounded corners.

  Note that the size of the opening 110 may be formed in consideration of the size of conductive particles contained in a conductive material used in a later process, the time spent for the etching process when the opening 110 is provided, and the like. Good. In other words, the size of the opening 110 is selected in consideration of the size of the conductive particles contained in the conductive material used in the subsequent process and the time required for the process. do it. Specifically, it is preferably 1 μm or more. In consideration of a space for forming a semiconductor element, the opening 110 is desirably 50 μm or less.

  Through the above steps, the second insulating layer 103, the plurality of semiconductor elements 96, the fourth insulating layer 97, the second conductive layers 111 to 116, and the opening 110 are provided over the second substrate to the nth substrate. The second element formation layer to the nth element formation layer can be formed.

  Next, a fifth insulating layer 117 is selectively formed over the fourth insulating layer 97 and the second conductive layers 111 to 116 (see FIG. 5A). Since the fifth insulating layer 117 is not formed over the opening 110, part of the second conductive layers 115 and 116 is exposed. The fifth insulating layer 117 is also referred to as an adhesive layer because it functions to bond a layer including a semiconductor element. Further, since the fifth insulating layer 117 is used as an adhesive layer, the fifth insulating layer 117 can be formed after peeling in a later step and when bonded to another layer. In this embodiment, an example in which the fifth insulating layer 117 is formed before the peeling step is described.

  The fifth insulating layer 117 can be formed using various methods as described below. For example, it can be formed by preparing a photosensitive permanent resist with a slit coater, and exposing and developing. Alternatively, it can be formed by applying a dry film of a permanent resist and then exposing and developing. Alternatively, an insulating resin such as an epoxy resin, an acrylic resin, or a polyimide resin can be used to form a film with a thickness of 5 to 200 μm, preferably 15 to 35 μm, using a screen printing method, a droplet discharge method, or the like. Note that the film thickness of the fifth insulating layer 117 can be formed uniformly by using a screen printing method or a droplet discharge method. Preferably, a screen printing method is used. This is because the screen printing method can reduce the production time and the apparatus is inexpensive. Note that after the fifth insulating layer 117 is formed, heat treatment is performed as necessary.

  Next, the second insulating layer 103 exposed at the bottom surface of the opening 110 and a part of the peeling layer 102 under the second insulating layer 103 are removed with an etching agent, whereby the peeling layer removing region 118 from which the peeling layer is removed. (See FIG. 5A). Here, an example is shown in which the second insulating layer 103 and the separation layer 102 are removed by etching; however, the step of removing only the second insulation layer 103 and removing the separation layer 102 may not be performed. In the case where a subsequent peeling step is possible, the etching time for the peeling layer 102 is preferably reduced because time can be shortened.

  Further, as described above, when the opening 110 is formed after the second conductive layer is formed or after the fifth insulating layer 117 is formed, the second portion is formed when the opening 110 is formed. Since the insulating layer 103 can be removed by etching, the above-described etching process of the second insulating layer 103 can be omitted. In this case, when the opening 110 is formed, a part of the peeling layer 102 can be removed to form the peeling layer removal region 118.

  Next, the support substrate 130 is provided over the fifth insulating layer 117 (see FIG. 5B). The support substrate 130 is a substrate in which the sixth insulating layer 120 and the adhesive layer 119 are stacked. The adhesive layer 119 is a thermoplastic resin whose adhesive strength is reduced by heat treatment. For example, a material that softens by heating, a microcapsule that expands by heating, a material mixed with a foaming agent, a thermosetting resin, It is formed using a material imparted with thermal decomposability, a material whose interface strength is deteriorated due to intrusion of water, and a material in which the water absorbent resin expands. In this specification, the support substrate in which the sixth insulating layer 120 and the adhesive layer 119 are combined is also referred to as a heat-peeling support substrate.

  Moreover, instead of a heat-peeling type support substrate, a heat-peeling film made of a film whose adhesive strength is reduced by heat treatment, a UV (ultraviolet) -releasing film whose adhesive strength is reduced by UV (ultraviolet) irradiation, etc. May be used. The UV film is a film in which a sixth insulating layer 120 and an adhesive layer 119 whose adhesive strength is weakened by UV (ultraviolet) irradiation are laminated.

  Next, the second to nth element formation layers are separated from the substrate 100 using the support substrate 130 (see FIG. 5C). The n-th element formation layer 121 is peeled from the substrate 100 inside the peeling layer 102 or with the peeling layer 102 and the second insulating layer 103 as a boundary. In the configuration illustrated in FIG. 5, a case where separation is performed with the boundary between the separation layer 102 and the second insulating layer 103 is illustrated. As described above, by using the support substrate 130, the peeling process can be performed easily and in a short time.

  Next, heat treatment is performed to separate the n-th element formation layer 121 from the support substrate 130 (see FIG. 6A). As described above, since the support substrate 130 is a heat-peelable substrate, the adhesive force between the support substrate 130 and the fifth insulating layer 117 is reduced by heat treatment, so that the n-th element is formed from the support substrate 130. Layer 121 can be separated.

  Subsequently, the first element formation layer 122 having semiconductor elements and the second to nth element formation layers 121 are stacked to form a semiconductor integrated circuit having a plurality of semiconductor elements (FIG. 6 (B)). FIG. 6B illustrates a structure in which three layers of the first element formation layer 122 to the nth element formation layer 121 (n = 3) are stacked. However, the present invention is not limited to this structure, and the element formation layer may be two layers or three or more layers, and the practitioner may select according to the purpose of use. .

  In the above step, the first element formation layer 122 and the second element formation layer 121 may be stacked and bonded together, and then the second element formation layer 121 and the support substrate 130 may be separated. After that, the third to nth element formation layers 121 may be stacked. In this case, the step of attaching the element formation layer and the step of separating from the support substrate 130 are alternately repeated. As described above, the manufacturing order of the semiconductor integrated circuit described above may be changed in order of steps so that the manufacturing is easy.

  Here, in FIG. 6, the first element formation layer 122 including a semiconductor element has an opening, and as described in Embodiment Mode 1 with reference to FIG. An example is shown in which the element formation layers (here, the n-th element formation layer 121 (n = 3)) are provided so that the openings of the layers substantially coincide with each other. In this case, the fifth insulating layer 117 is selectively formed at a place other than the opening.

  As described above, in the semiconductor integrated circuit in which the layers having a plurality of semiconductor elements are stacked, the first element formation layer 122 which is the lowest layer is the second element formation layer to the nth layer which is the upper layer described above. A method similar to that for the element formation layer may be applied. Further, the first element formation layer 122 may be manufactured without providing the separation layer 102 and the opening 110.

  However, the first element formation layer 122, which is the lowermost layer, can be formed by providing the separation layer 102 and the opening 110 as in the case of the second to nth element formation layers. For example, the first element formation layer 122 is formed using a glass substrate or a semiconductor substrate, and then peeled off from the substrate and attached to a plastic substrate, a film, or the like, whereby the semiconductor integrated circuit is transferred from the manufacturing substrate to another substrate. It can be transferred. In this manner, by transferring the first element formation layer 122 from the manufacturing substrate to another substrate, a thin and soft semiconductor integrated circuit can be formed.

  In this embodiment mode, a method for manufacturing the first element formation layer 122 which is the lowest layer will be described with reference to FIGS. The first element formation layer 122 includes a plurality of semiconductor elements 96, a fourth insulating layer 97, and a plurality of semiconductor elements 96 on the substrate, like the second to nth element formation layers having the semiconductor elements described in FIG. Contact holes and openings are formed. Then, second conductive layers 111 to 114 and a second conductive layer 140 are formed over the contact hole and the opening (see FIG. 7A).

  Next, a fifth insulating layer 141 is selectively formed over the fourth insulating layer 97, the second conductive layers 111 to 114, and the second conductive layer 140 (see FIG. 7B). Like the fifth insulating layer 117, the fifth insulating layer 141 is not formed over the opening 143, so that a part of the second conductive layer 140 is exposed. The fifth insulating layer 141 also functions as an adhesive layer that bonds the stacked element formation layers together.

  In the case of forming the first element formation layer, a separation opening 78 is formed so that at least part of the separation layer 102 is exposed (see FIG. 7C). This step is preferably performed by laser beam irradiation because the processing time is short. The laser beam is applied from the surface of the fifth insulating layer 141 to the first insulating layer 101, the separation layer 102, the second insulating layer 103, the fourth insulating layer 97, and the fifth insulating layer 141. Is done. The second insulating layer 103, the fourth insulating layer 97, and the fifth insulating layer 141 are provided with an opening 78 for peeling. In the structure illustrated in FIG. 7C, the laser beam reaches the first insulating layer 101, and the first insulating layer 101, the separation layer 102, the second insulating layer 103, the fourth insulating layer 97, In addition, a case where a peeling opening 78 is formed in the fifth insulating layer 141 is shown. Note that the laser beam may reach the substrate 100.

  Ablation processing is used in the step of irradiating the laser beam. Ablation processing is processing using a phenomenon in which a molecular bond in a portion irradiated with a laser beam, that is, a portion that has absorbed the laser beam is photolyzed and cut and vaporized. In other words, the opening 78 for peeling is formed by irradiating a laser beam to cut off an intermolecular bond of molecules forming the insulating layer by photolysis and vaporize it.

The laser beam may be a solid-state laser having a wavelength of 150 to 380 nm which is an ultraviolet light region. Preferably, an Nd: YVO ₄ laser with a wavelength of 150 to 380 nm may be used. This is because the Nd: YVO ₄ laser having a wavelength of 150 to 380 nm is more easily absorbed by the insulating layer than other lasers on the higher wavelength side, and can be ablated. Moreover, it is because the workability is good without affecting the periphery of the processed part. Thus, the peeling process can be facilitated by providing the opening 78 for peeling.

  Note that the separation opening 78 shown in FIG. 7C is not necessarily provided, and the process may be omitted and the process may be moved to the process of FIG.

  Whether or not the opening 78 is formed, the supporting substrate 130 is provided over the fifth insulating layer 141 formed in FIG. 7B (see FIG. 7D). The support substrate 130 is a substrate in which the sixth insulating layer 120 and the adhesive layer 119 are stacked. In this embodiment, the heat-peeling support substrate described above is used.

  Next, the first element formation layer 122 is peeled from the substrate 100 using the support substrate 130. This separation step is omitted here because a method similar to the method for forming the second to nth element formation layers may be used. Then, after peeling from the substrate 100, the first element formation layer 122 may be attached to another substrate.

  After that, as described above, the nth element formation layer 121 (n = 2) is bonded to the first element formation layer 122, and the nth element formation layer 121 (n = 2) is bonded to the nth element formation layer 121 (n = 2). The element formation layer 121 (n = 3) is attached. The semiconductor integrated circuit of the present invention is manufactured by laminating and stacking n element forming layers of the first to nth element forming layers as required by the practitioner. In this embodiment, a semiconductor integrated circuit is manufactured by stacking three layers of the first element formation layer 122 to the n-th element formation layer 121 (n = 3) (see FIG. 6B).

  Subsequently, an opening provided in a semiconductor integrated circuit in which a first element formation layer 122 to an nth element formation layer (nth element formation layer 121 (n = 3) in the drawing) having semiconductor elements are stacked. 124 is filled with a conductive material. In this embodiment, the conductive paste 125 is dropped into the opening 124 (see FIG. 8A). As the conductive paste 125, as described above, a conductive particle having a diameter of several micrometers or less dissolved or dispersed in an organic resin is used. The conductive particles include at least one of Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Zr, and Ba. Grains, silver halide fine grains, etc., or carbon black can be used. As the organic resin, one or more selected from organic resins that function as a binder, a solvent, a dispersant, and a coating agent for metal particles can be used. Typically, an organic resin such as an epoxy resin or a silicone resin can be given.

  For example, in the case of using a conductive paste having fine particles mainly composed of silver (for example, particles having a particle diameter of 1 nm to 100 nm), the conductive layer is obtained by curing by baking in a temperature range of 150 to 300 ° C. Can do. Through these steps, a semiconductor integrated circuit in which layers having a plurality of stacked semiconductor elements are electrically connected to each other through the through wiring 126 can be manufactured (see FIG. 8B).

  In FIG. 8, as described in Embodiment Mode 1 with reference to FIG. 3, when the first to nth element formation layers are stacked and bonded, the openings of the respective layers are substantially aligned. In this example, the first to nth element formation layers are stacked, and then the conductive paste 125 is dropped to form the through wiring 126. However, when the first to nth element formation layers are stacked and bonded, the openings of the layers are not necessarily overlapped. For example, in Embodiment 1 described above, FIG. It is good also as a structure as shown in. An example of this case is shown in FIG.

  When the opening 124 is formed without overlapping, the second conductive layer is formed on a portion located immediately below the opening 124, for example, on the uppermost portion of the (a-1) th layer that is immediately below the opening of the ath layer. Layer 127 is formed (where a is 2 to n). In addition, the fifth insulating layer is not formed on the opening 124 of the a layer and the second conductive layer 127 of the a-1 layer, and the fifth insulating layer is selectively formed in other regions. (See FIG. 9A). Then, as shown in FIG. 9A, after the second element formation layer 121 is bonded to the first element formation layer 122, the conductive paste 125 is dropped to form the through wiring 126. Then, as illustrated in FIG. 9B, after the third element formation layer 121 is bonded to the second element formation layer 121, the conductive paste 125 is dropped to form the through wiring 126. Then, the semiconductor integrated circuit can be manufactured by alternately repeating the bonding of the element formation layer and the formation of the through wiring 126 by the dropping of the conductive paste 125 up to the nth layer.

  In addition, in the case where the conductive layer is obtained by baking the conductive paste 125, the first element formation layer 122 to the nth element formation are performed by repeatedly bonding the element formation layers and dropping the conductive paste 125. After all the layers 121 are stacked, baking may be performed. In this manner, a semiconductor integrated circuit in which the first element formation layer 122 to the nth element formation layer 121 including a plurality of stacked semiconductor elements are electrically connected by the through wiring 126 can be manufactured.

  By manufacturing a semiconductor integrated circuit using this embodiment mode, a step of forming a through hole and a step of polishing a back surface of a substrate for forming the through hole can be omitted. The time required for the process can be shortened. In addition, since no through hole is formed in the substrate or back surface polishing is not performed, the material of the substrate is not limited, and the substrate can be reused. Thereby, cost reduction of the semiconductor integrated circuit can be realized. Further, since the layer having a plurality of semiconductor elements is peeled off from the substrate and stacked, a small, thin, and flexible semiconductor integrated circuit can be manufactured.

(Embodiment 3)
In this embodiment mode, a method for manufacturing a semiconductor integrated circuit having a structure different from that in Embodiment Mode 2 will be described with reference to drawings. In this embodiment mode, a structure in which a conductive material is sandwiched between the element formation layers when the first to nth element formation layers are stacked is the embodiment mode. This is different from the configuration shown in FIG.

  FIG. 11 is a cross-sectional view of the first to nth element formation layers for forming a semiconductor integrated circuit. Here, the steps until the second conductive layers 111 to 116 are formed are the same as the steps up to FIG. 4D of Embodiment 2, and thus the description thereof is omitted here. A fifth insulating layer 150 is selectively formed so as to cover the fourth insulating layer 97 and the second conductive layers 111 to 116 (see FIG. 11A). The fifth insulating layer 150 is not formed over the opening 158 provided in the n-th element formation layer 153 having a semiconductor element.

  Here, a method of forming the opening 158 will be described. The opening 158 is formed by removing the fourth insulating layer 97 simultaneously with the formation of the contact hole. In addition, after the second conductive layers 111 to 116 are formed in the contact hole, the second insulating layer 103 and the separation layer 102 on the bottom surface of the opening can be removed. Alternatively, after the fifth insulating layer 150 is formed over the second conductive layers 111 to 116 and the fourth insulating layer 97, the second insulating layer 103 and the separation layer 102 on the bottom surface of the opening may be removed. .

  Subsequently, the conductive paste 125 is dropped into the opening 158 provided in the n-th element formation layer 153 (see FIG. 11B). As described in the above embodiment, the conductive paste 125 is obtained by dissolving or dispersing conductive particles having a particle size of several nanometers to several micrometers in an organic resin. Through wiring 126 is formed by a step of dropping conductive paste 125 (see FIG. 11C).

  Next, an opening 78 for peeling is formed so that at least part of the peeling layer 102 is exposed (see FIG. 12A). This step may be performed by laser beam irradiation as described in the above embodiment mode. The laser beam is irradiated from the surface of the fifth insulating layer 150, and the peeling opening 78 is formed so that at least a part of the peeling layer 102 is exposed. In the structure shown in the figure, the laser beam reaches the first insulating layer 101, and the first insulating layer 101, the peeling layer 102, the second insulating layer 103, the fourth insulating layer 97, and the fifth insulating layer. The case where 150 is divided is shown. Here, an example of forming the opening 78 for peeling so that a part of the peeling layer 102 is exposed is shown, but the opening 78 is formed when a later peeling process is possible without performing this process. There is no need to form.

  Next, the support substrate 130 is provided over the fifth insulating layer 150 (see FIG. 12B). As described in the above embodiment, the support substrate 130 is a substrate in which the sixth insulating layer 120 and the adhesive layer 119 are stacked, and is a heat-peelable substrate. Note that a heat release film or a UV (ultraviolet) release film may be used instead of the heat release type substrate.

  Next, the n-th element formation layer 153 is separated from the substrate 100 using the support substrate 130 (see FIG. 12C). The n-th element formation layer 153 is peeled off inside the peeling layer 102 or with the peeling layer 102 and the second insulating layer 103 as a boundary as described in the above embodiment mode. In the structure shown in the figure, a case where peeling is performed with the boundary between the peeling layer 102 and the second insulating layer 103 is shown. As described above, by using the support substrate 130, the peeling process can be performed easily and in a short time.

  Next, heat treatment is performed to separate the n-th element formation layer 153 from the support substrate 130 (see FIG. 13A). As described above, since the support substrate 130 is a heat-peelable substrate, the adhesive force between the support substrate 130 and the fifth insulating layer 150 is reduced by the heat treatment, and the plurality of semiconductor elements are separated from the support substrate 130. The n-th element formation layer 153 having is separated.

  Subsequently, the first element formation layer 154 and the second to nth element formation layers 153 are stacked with the conductive material 155 interposed therebetween, whereby a semiconductor integrated circuit including a plurality of semiconductor elements is formed. It is formed (see FIG. 13B). In this manner, the first element formation layer 154 and the nth element formation layer 153 stacked thereon are bonded together via the conductive material 155, whereby the upper and lower layers are electrically connected through the through wiring 126. can do. In the drawing, a structure in which three layers of a first element formation layer 154 to an nth element formation layer 153 (n = 3) are stacked is shown. However, the present invention is not limited to this structure, and the element formation layer may be two layers or three or more layers, and may be appropriately selected by the practitioner.

  Here, as the conductive material 155 for bonding the first element formation layer 154 and the n-th element formation layer 153 laminated thereon, for example, an adhesive or a conductive agent containing conductive particles 156 can be used. A conductive film can be used. In particular, it is desirable to use an anisotropic conductive material having anisotropic conductivity having conductivity only in a direction perpendicular to the layer (or substrate) and insulating in the parallel direction. Here, as the anisotropic conductive material, an anisotropic conductive paste (ACP: Anisotropic Conductive Paste) or an anisotropic conductive film (ACF: Anisotropic Conductive Film) is used. Can do. These materials have conductivity only in a specific direction (here, a direction perpendicular to the substrate). An anisotropic conductive paste is called a binder layer and has a structure in which particles having a conductive surface (hereinafter referred to as conductive particles) are dispersed in a layer whose main component is an adhesive. The anisotropic conductive film has a structure in which conductive particles are dispersed in a thermosetting or thermoplastic resin film. Note that the conductive particles are obtained by plating a spherical resin with nickel (Ni), gold (Au), or the like. Insulating particles made of silica or the like may be mixed in order to prevent an electrical short circuit between the conductive particles at unnecessary portions.

  As described above, the method for attaching the first element formation layer 154 and the n-th element formation layer 153 stacked thereon using the conductive material 155 is the same as the method for manufacturing the semiconductor integrated circuit described in Embodiment Mode 2. In comparison, the alignment accuracy may be low, and the manufacturing time can be shortened. This is because the through wiring 126 provided in the a-th layer and the through wiring 126 provided in the a-1th layer or the second conductive layer 157 are electrically connected through the conductive material 155. (Where a is 2 to n).

  In addition, the first element formation layer 154 which is the lowest layer among the plurality of element formation layers included in the semiconductor integrated circuit can be manufactured by applying the method described in the above embodiment mode. For example, the second element formation layer to the nth element formation layer 153 including a plurality of the semiconductor elements described above may be manufactured. Further, as shown in FIG. 7, an opening may be provided, and the second conductive layer may be formed on the bottom of the opening. In this example of FIG. 13B, a first element formation layer 154 manufactured by the method shown in FIG. 7 is shown. Furthermore, as shown in FIG. 9, the first element formation layer 154 may have a structure without an opening. The structure of the first element formation layer 154 can be arbitrarily selected depending on a manufacturing method.

  In addition, a semiconductor integrated circuit can be manufactured without peeling the first element formation layer 154 from the substrate 100. As described above, when the first element formation layer 154 is not peeled from the substrate 100, it is not necessary to provide the separation layer 102 and the support substrate 130 on the substrate 100 on which the first element formation layer 154 is formed. The second to nth element formation layers may be stacked after the first insulating layer 150 is formed.

  Alternatively, after the first element formation layer 154 is peeled from the substrate 100, the first element formation layer 154 can be attached to another substrate, and the second element formation layer to the nth element formation layer can be stacked thereover. At this time, as another substrate to which the first element formation layer 154 is attached, a thin and flexible plastic substrate (or a film-like substrate) is used so that the substrate is thin, light, and flexible. A semiconductor integrated circuit having the characteristics can be manufactured. In addition, as shown in FIG. 13B in this example, the first element formation layer 154 peeled from the substrate 100 can be used as it is without being attached to another substrate.

  In addition, when the method for manufacturing a semiconductor integrated circuit described in this embodiment is applied, the fifth insulating layer 150 is not provided over the first element formation layer 154 and the nth element formation layer 153 stacked thereover, Each layer can be stacked and bonded (see FIGS. 14A and 14B). In this case, after forming the second conductive layers 161 to 166, the opening 168 is filled with a conductive material to form the through wiring 126, and the first element formation layer 154 is formed using the conductive material 155. And the second to n-th element formation layers 153 are laminated and bonded together. By not providing the fifth insulating layer 150 in this manner, the material and process for forming the fifth insulating layer 150 can be reduced. However, the fifth insulating layer 150 has a role of reducing parasitic capacitance generated between the first element formation layer 154 and the n-th element formation layer 153 stacked thereon, and thus is not provided or provided as necessary. Can decide.

  In FIG. 13B, an opening provided in the first element formation layer 154 overlaps with an opening 158 provided in each of the second to nth element formation layers 153 stacked thereover. The through wiring 129 is formed there. However, the present invention is not limited to this example, and the first element formation layer 154 and the second to nth element formation layers 153 stacked thereover can have openings 158 at different locations (FIG. 14B). reference). This is the same as the method described with reference to FIG. 9 in the second embodiment, and when the opening 158 is not provided at the overlapping position, the portion located immediately below the opening 158, that is, the a-th layer. A second conductive layer 157 is formed at the uppermost part of the (a-1) th layer that comes directly below the opening 158 (where a is 2 to n). Then, the first element formation layer to the nth element formation layer are bonded to each other through the conductive material 155, so that the first element formation layer to the nth element formation layer are electrically connected to each other through the through wiring 129. A semiconductor integrated circuit connected to can be manufactured.

  In the present embodiment and the above embodiment, the first element formation layer to the nth element formation layer are each provided with one opening. However, the present invention is not limited to this example, and the first to nth element formation layers can each have a plurality of openings (see FIG. 14B). Also in this case, as in the above example, the opening or the second conductive layer is formed on the portion located immediately below the opening, for example, the uppermost part of the a-1 layer that is immediately below the opening of the a layer. ing. The first element formation layer to the nth element formation layer are electrically connected through the conductive material 155.

  Furthermore, in this embodiment and the above-described embodiment, an example in which the opening is filled with a conductive paste is illustrated. However, the conductive paste can be electrically connected to the upper and lower element forming layers by arbitrarily changing its viscosity and surface tension without filling. Therefore, the necessary amount of conductive paste may be dropped.

  By manufacturing a semiconductor integrated circuit using this embodiment mode, a process for forming a through hole and a process for polishing a back surface of a substrate can be eliminated, so that a manufacturing time can be shortened. Further, since the back surface of the substrate is not polished to form a through-hole penetrating the substrate, there is no restriction on the selection of the material of the substrate, and the substrate can be reused, so that cost reduction can be realized. . Further, since there is no substrate between the element formation layers, high integration is possible.

(Embodiment 4)
The semiconductor integrated circuit of the present invention has a plurality of semiconductor elements. Each of the plurality of semiconductor elements includes a semiconductor layer, an insulating layer serving as a gate insulating layer, and a conductive layer serving as a gate electrode. In this embodiment, an example of a method for manufacturing a semiconductor layer included in each of a plurality of semiconductor elements and an insulating layer to be a gate insulating layer will be described.

  As the semiconductor layer included in each semiconductor element, an amorphous semiconductor layer is formed by a sputtering method, an LPCVD method, a plasma CVD method, or the like. Next, laser crystallization, RTA (Rapid Thermal Anneal), thermal crystallization using a furnace annealing furnace, thermal crystallization using a metal element that promotes crystallization, heat using a metal element that promotes crystallization The amorphous semiconductor layer is crystallized by using a crystallization method combining a crystallization method and a laser crystallization method, and a crystallized semiconductor layer is formed. Then, the crystallized semiconductor layer is processed into a desired shape.

  Note that among the above manufacturing methods, a method in which a crystallization method with heat treatment and a crystallization method in which a continuous wave laser or a laser beam oscillated at a frequency of 10 MHz or higher is irradiated is preferably used. By irradiation with a continuous wave laser or a laser beam oscillated at a frequency of 10 MHz or higher, the surface of the crystallized semiconductor layer can be flattened. By planarizing the surface of the crystallized semiconductor layer, the gate insulating layer above the semiconductor layer can be thinned, and the breakdown voltage of the gate insulating layer can be improved.

  Of the above manufacturing methods, crystallization is preferably performed using a continuous wave laser or a laser beam oscillated at a frequency of 10 MHz or higher. A semiconductor layer that is crystallized by scanning in one direction while irradiating a continuous wave laser or a laser beam oscillating at a frequency of 10 MHz or more has a characteristic that crystals grow in the scanning direction of the laser beam. The semiconductor element is arranged so that the scanning direction is the channel length direction (the direction in which carriers flow when the channel formation region is formed), and the following method is adopted as the method for manufacturing the insulating layer to be the gate insulating layer By doing so, a semiconductor element with small variation in characteristics and high field effect mobility can be obtained.

An insulating layer as a gate insulating layer included in each of the plurality of semiconductor elements is preferably formed by oxidizing or nitriding the surface by performing plasma treatment on the semiconductor layer manufactured as described above. For example, it is formed by plasma treatment in which a rare gas (He, Ar, Kr, Xe, or the like) and a mixed gas (oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, or the like) are introduced. When excitation of plasma in this case is performed by introducing microwaves, plasma having an electron temperature of 1.5 eV or less and an electron density of 1 × 10 ¹¹ cm ⁻³ or more (hereinafter abbreviated as high-density plasma). Can be generated. More specifically, it is preferable that the electron density is 1 × 10 ¹¹ cm ⁻³ or more and 1 × 10 ¹³ cm ⁻³ or less and the plasma electron temperature is 0.5 eV or more and 1.5 eV or less. By oxidizing or nitriding the surface of the semiconductor layer with oxygen radicals (which may include OH radicals) or nitrogen radicals (which may also include NH radicals) generated by such high-density plasma, 5 to 10 nm. The insulating layer is formed on the surface of the semiconductor layer. This insulating layer having a thickness of 5 to 10 nm is preferably used as the gate insulating layer.

  Note that the reaction by the treatment using high-density plasma in this case is a solid-phase reaction, and thus the interface state density between the gate insulating layer and the semiconductor layer can be extremely low. Such a high-density plasma treatment directly oxidizes (or nitrides) a semiconductor layer (crystalline silicon or polycrystalline silicon), so that variation in thickness of the formed gate insulating layer can be extremely reduced. In addition, since it is not strongly oxidized even at the crystal grain boundary of crystalline silicon, a very preferable state is obtained. That is, by oxidizing or nitriding the surface of the semiconductor layer by the high-density plasma treatment shown here, the uniformity is good and the interface state density is low without causing abnormal oxidation reaction or nitridation reaction at the crystal grain boundary. A gate insulating layer can be formed.

  Note that only an insulating layer formed by high-density plasma treatment may be used as the gate insulating layer included in the semiconductor element, or plasma or thermal reaction is used in addition to the insulating layer formed by high-density plasma treatment. An insulating layer such as silicon oxide, silicon oxynitride, or silicon nitride may be stacked by a CVD method. In any case, a semiconductor element including an insulating layer formed by high-density plasma as part or all of the gate insulating layer can reduce variation in characteristics.

In some cases, a semiconductor layer, a gate insulating layer, and other insulating layers included in the semiconductor element are formed by plasma treatment. Such plasma treatment is preferably performed at an electron density of 1 × 10 ¹¹ cm ⁻³ or more and an electron temperature of plasma of 1.5 eV or less. More specifically, it is preferable that the electron density is 1 × 10 ¹¹ cm ⁻³ or more and 1 × 10 ¹³ cm ⁻³ or less and the plasma electron temperature is 0.5 eV or more and 1.5 eV or less.

When the electron density of plasma is high and the electron temperature in the vicinity of an object to be processed (for example, a semiconductor layer or a gate insulating layer) is low, damage to the object to be processed can be prevented. In addition, when the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or more, an oxide or nitride formed by oxidizing or nitriding an object to be processed using plasma treatment is a CVD method. Compared with a thin film formed by sputtering or the like, a dense film having excellent uniformity in film thickness and the like can be formed. In addition, since the electron temperature of plasma is as low as 1.5 eV or less, oxidation or nitridation treatment can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, the object to be processed can be sufficiently oxidized or nitrided to form an oxide or nitride even when plasma treatment is performed at a temperature 100 degrees or more lower than the strain point of the glass substrate.

(Embodiment 5)
A semiconductor device including the semiconductor integrated circuit described in any of the above embodiments is described with reference to FIGS.

  A semiconductor device 300 illustrated in FIG. 15A is provided by bonding a semiconductor integrated circuit 303 having any of the structures described in the above embodiments to a substrate 301 provided with a conductive film 302. . Here, a plurality of semiconductor integrated circuits 303 a to 303 d are provided over the substrate 301 so as to be electrically connected to the conductive film 302. Adhesion between the substrate 301 and the semiconductor integrated circuits 303 a to 303 d is performed by an adhesive resin 312, and electrical connection between the semiconductor integrated circuits 303 a to 303 d and the conductive film 302 is performed by conductive particles contained in the adhesive resin 312. 311 can be performed (see FIG. 15B). In addition, the electrical connection between the semiconductor integrated circuits 303a to 303d and the conductive film 302 is made by using a conductive adhesive such as silver paste, copper paste or carbon paste, an anisotropic such as ACP (Anisotropic Conductive Paste). Conductive adhesives, conductive films such as ACF (Anisotropic Conductive Film), solder bonding, or the like can also be used.

  Here, the semiconductor integrated circuit 303 included in the semiconductor device 300 is manufactured by applying the method described in the above embodiment. As shown in FIG. 15B, the electrical connection between the semiconductor integrated circuits 303a to 303d and the conductive film 302 is exposed on the back surface of the semiconductor integrated circuit 303 (the surface opposite to the surface on which the semiconductor element is provided). The conductive layer 214 and the conductive film 302 can be formed through the conductive particles 311.

  Further, the semiconductor integrated circuits 303a to 303d and the conductive film 302 are connected through a conductive layer exposed on the surface of the semiconductor integrated circuits 303a to 303d, or a through wiring 126 formed by dropping silver paste or the like. Also good. In this case, the semiconductor integrated circuits 303 a to 303 d can be attached to the substrate 301 by turning upside down so that the uppermost layer of the semiconductor integrated circuits 303 a to 303 d is in contact with the conductive film 302. It is also possible to connect the conductive film 302 and the semiconductor integrated circuits 303a to 303d using wire bonding.

  Although not shown here, an insulating film, an insulating film, or the like may be provided over the semiconductor integrated circuit 303 in order to protect the semiconductor integrated circuit 303.

  Each of the semiconductor integrated circuits 303a to 303d shown in the present embodiment includes a central processing unit (CPU), a memory, a network processing circuit, a disk processing circuit, an image processing circuit, an audio processing circuit, a power supply circuit, and a temperature sensor. , Function as one or more selected from humidity sensors, infrared sensors, and the like.

  As described above, the semiconductor integrated circuit included in the semiconductor device of the present invention can omit the process of forming a through hole and the process of polishing a substrate when manufacturing the semiconductor integrated circuit, so that the manufacturing time can be shortened. Further, since the substrate is not polished in order to provide a through-hole penetrating the substrate, there is no limitation on the selection of the material of the substrate, and the substrate can be reused, so that the cost can be reduced. Further, since the substrate is not provided between the layers having a plurality of semiconductor elements, the device can be highly integrated. By using such a semiconductor integrated circuit, a small and inexpensive semiconductor device can be provided.

(Embodiment 6)
In this embodiment mode, a semiconductor device (RFID (Radio Frequency Identification), ID tag, IC tag, IC chip, RF tag (Radio Frequency)) capable of transmitting and receiving data without contact, using the semiconductor integrated circuit of the present invention. An example of application to an ID film, an IC film, and an RF film is shown with reference to FIGS.

  A semiconductor device (RFID) according to the present invention is manufactured by separately forming a conductive film 219 functioning as an antenna and a semiconductor integrated circuit 303, and then connecting the conductive film 219 and the semiconductor integrated circuit 303 (FIG. 16). reference).

  The semiconductor integrated circuit 303 used here is formed by stacking a first element formation layer 154 to an nth element formation layer 153 (n = 3 in the drawing) as shown in the manufacturing example in Embodiment Mode 3 above. In addition, an electrical circuit of RFID (for example, a power supply circuit, a demodulation circuit, a logical operation circuit, etc.) is formed by being electrically connected by the through wiring 126. A conductive film 219 functioning as an antenna is formed over the substrate 221. As the substrate 221, a glass substrate, a thin and soft substrate such as plastic, a film, or the like can be used. Note that the ID film, the IC film, and the RF film have a thickness of 100 μm or less, preferably 50 μm or less, more preferably 20 μm or less (the thickness of the semiconductor layer in one integrated circuit is 200 nm or less, preferably 100 nm or less, more Preferably it is 70 nm or less. When the thickness of the film is in the above range, the film has flexibility and is not easily damaged by mechanical impact.

  In FIG. 16A, a conductive film 219 functioning as an antenna formed over a substrate 221 is electrically connected to the through wiring 126 and the semiconductor elements 205a to 205c included in the semiconductor integrated circuit 303, whereby a semiconductor device is manufactured. The

  As an example of a method for manufacturing the semiconductor device of the present invention, for example, the first element formation layer to the nth element formation layer are attached without peeling the first element formation layer 154 (lowermost layer) from the substrate 100. By connecting them together, the semiconductor integrated circuit 303 is manufactured over the substrate 100. Then, the conductive film 219 functioning as an antenna provided over the substrate 221 and the semiconductor integrated circuit 303 provided over the substrate 100 are attached so as to be electrically connected, whereby a semiconductor device can be manufactured.

  In addition, after bonding as described above, the substrate 100 is peeled from the semiconductor integrated circuit 303, whereby a flexible, thin semiconductor device capable of transmitting and receiving data without contact can be manufactured. Yes (FIG. 16).

  Further, after the substrate 100 is peeled off, the semiconductor integrated circuit 303 and the substrate 221 provided with the conductive film 219 functioning as an antenna can be attached to a thin and soft substrate, a film, or the like. In this manner, the semiconductor integrated circuit 303 and the conductive film 219 functioning as an antenna can be protected from contamination and impact by being attached to another substrate.

  The conductive film 219 functioning as an antenna provided over the substrate 221 is formed using a conductive material by a CVD method, a sputtering method, a printing method such as screen printing or gravure printing, a droplet discharge method, a dispenser method, or the like. As the conductive material, an element selected from aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), nickel (Ni), or these elements as a main component. An alloy material or a compound material is used to form a single layer structure or a laminated structure.

  In addition, the substrate 221 provided with the conductive film 219 functioning as an antenna and the semiconductor integrated circuit 303 are attached to each other with an adhesive resin 312 (see FIG. 16A). As the adhesive resin 312 used here, the anisotropic conductive material described in the above embodiment is preferably used. In the case where the anisotropic conductive material is used as the adhesive resin 312, electrical connection between the through wiring 126 and the semiconductor elements 205 a to 205 c included in the semiconductor integrated circuit 303 and the conductive film 219 functioning as an antenna is performed using an adhesive resin. This can be done through the conductive particles 311 included in 312.

  In addition, electrical connection between the through wiring 126 and the semiconductor elements 205a to 205c included in the semiconductor integrated circuit 303 and the conductive film 219 functioning as an antenna is made by conductive bonding such as silver paste, copper paste, or carbon paste. It can also be performed using an agent, solder bonding, or the like.

  In the case where the conductive film 219 functioning as an antenna is formed separately from the semiconductor integrated circuit 303 and then electrically connected thereto, the lower surface of the first element formation layer 154, that is, the first element formation layer. Can be electrically connected to the conductive layer 214 provided on the second insulating layer 103 side (see FIG. 16B).

  In this manner, the conductive layer 214 provided on the lower surface of the semiconductor integrated circuit 303 (that is, the second insulating layer 103 side of the first element formation layer having a semiconductor element), and the conductive film 219 functioning as an antenna. Are electrically connected to the upper surface of the semiconductor integrated circuit (that is, on the fifth insulating layer 150 side of the n-th element formation layer (uppermost layer)) Different semiconductor elements having different special functions can be provided.

  Here, an example in which a memory element is formed on the upper surface of the semiconductor integrated circuit is shown (see FIG. 16B). Specifically, a third conductive layer 380 and a seventh insulating layer 381 are provided over an nth element formation layer (n = 3 in the drawing) having semiconductor elements stacked to form a semiconductor integrated circuit, An example in which a memory element 230 formed with a stacked structure of a fourth conductive layer 231, a memory layer 232, and a fifth conductive layer 233 is provided over the seventh insulating layer 381 is shown. Here, the third conductive layer 380 is provided over the fifth insulating layer 150 provided in the n-th element formation layer 153. Then, the third conductive layer 380 is formed so as to be connected to the second conductive layer provided in the n-th element formation layer, whereby the memory element 230 and the semiconductor element included in the semiconductor integrated circuit 303 are formed. The structure which electrically connects is shown.

  As the memory layer 232, a material whose property or state is changed by an electric action, an optical action, a thermal action, or the like can be used. For example, a material whose property and state change due to melting due to Joule heat, dielectric breakdown, etc., and whose electrical properties (for example, resistance and capacitance) between the fourth conductive layer 231 and the fifth conductive layer 233 change is used. Use to form. For example, a material in which the fourth conductive layer 231 and the fifth conductive layer 233 are short-circuited by passing a current through the memory layer 232 can be used. In order to change the electrical characteristics in this way, the thickness of the memory layer 232 is 5 nm to 100 nm, preferably 10 nm to 60 nm.

As a material for forming the memory layer 232, for example, an organic compound can be used. The organic compound can be formed by a relatively easy film formation method such as a droplet discharge method, a spin coating method, or an evaporation method. Examples of the organic compound forming the memory layer 232 include 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD) and 4,4′-bis. [N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD) or 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: TDATA), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) and 4,4′-bis (N- (4 A compound of an aromatic amine type (that is, having a bond between a benzene ring and nitrogen) such as-(N, N-di-m-tolylamino) phenyl) -N-phenylamino) biphenyl (abbreviation: DNTPD), polyvinylcarbazole ( Abbreviation: P K) and phthalocyanine _{(abbreviation:} H 2 Pc), copper phthalocyanine (abbreviation: CuPc), or vanadyl phthalocyanine (abbreviation: VOPc), and can be used phthalocyanine compounds such as. These materials are substances having a high hole transporting property.

As other organic compounds, for example, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [h ] -Quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), etc., a material comprising a metal complex having a quinoline skeleton or a benzoquinoline skeleton And bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) ₂ ) Materials such as metal complexes with oxazole and thiazole ligands such as Can do. These materials are substances having a high electron transporting property.

  In addition to the above metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3- Bis [5- (p-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl -5- (4-biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl)- A compound such as 1,2,4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), or the like can be used.

In addition, the memory layer 232 may have a single layer structure of an organic compound or a stacked structure. In the case of a laminated structure, a laminated structure can be selected from the above materials. Alternatively, the organic compound and an organic compound used as a light-emitting material may be stacked. The organic compound used as the light-emitting material includes 4-dicyanomethylene-2-methyl-6- [2- (1,1,7,7-tetramethyljulolidyl-9-yl) ethenyl] -4H-pyran ( Abbreviation: DCJT), 4-dicyanomethylene-2-t-butyl-6- [2- (1,1,7,7-tetramethyljulolidyl-9-yl) ethenyl] -4H-pyran, periflanthene, 2 , 5-dicyano-1,4-bis [2- (10-methoxy-1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] benzene, N, N′-dimethylquinacridone (abbreviation: DMQd ), Coumarin 6, coumarin 545T, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), 9,9′-bianthryl, 9,10-diphenylanthracene (abbreviation: DPA) and 9, 10-bis (2-naphthyl) anthracene (abbreviation: DNA), 2,5,8,11-tetra-t-butylperylene (abbreviation: TBP), and the like.

Alternatively, the memory layer 232 may be formed using a material in which the light-emitting material is dispersed in a base material. As a base material to be dispersed with a light emitting material, anthracene derivatives such as 9,10-di (2-naphthyl) -2-tert-butylanthracene (abbreviation: t-BuDNA), 4,4′-bis (N-carbazolyl) biphenyl Carbazole derivatives such as (abbreviation: CBP), bis [2- (2-hydroxyphenyl) pyridinato] zinc (abbreviation: Znpp ₂ ), bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: ZnBOX) ) And the like can be used. In addition, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), 9,10-bis (2-naphthyl) anthracene (abbreviation: DNA), bis (2-methyl-8-quinolinolato) -4-phenylphenolato- Aluminum (abbreviation: BAlq) or the like can be used.

  Such an organic compound has a glass transition temperature (Tg) of 50 ° C. to 300 ° C., preferably 80 ° C. to 120 ° C., in order to change its properties by a thermal action or the like.

  Alternatively, a material in which a metal oxide is mixed in the above organic compound may be used. Note that the material in which the metal oxide is mixed includes a state where the organic compound or the organic compound used as the light-emitting material and the metal oxide are mixed or stacked. Specifically, it includes a state formed by a co-evaporation method using a plurality of evaporation sources. Such a material can be called an organic-inorganic composite material.

  For example, in the case where a metal oxide is mixed with the organic compound having a high hole transport property shown above, the metal oxide includes vanadium oxide, molybdenum oxide, niobium oxide, rhenium oxide, tungsten oxide, Ruthenium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, and tantalum oxide are preferably used. In addition, in the case where a metal oxide is mixed with the organic compound having a high electron transport property described above, lithium oxide, calcium oxide, sodium oxide, potassium oxide, or magnesium oxide is used as the metal oxide. It is preferable to use a product.

  For the memory layer 232 forming the memory element, a material whose properties are changed by an electric action, an optical action, or a thermal action may be used. For example, a conjugated polymer doped with a compound that generates acid by absorbing light (a photoacid generator) can be used for the memory layer 232. As the conjugated polymer, polyacetylenes, polyphenylene vinylenes, polythiophenes, polyanilines, polyphenylene ethynylenes, and the like can be used. As the photoacid generator, arylsulfonium salts, aryliodonium salts, o-nitrobenzyl tosylate, arylsulfonic acid p-nitrobenzyl esters, sulfonylacetophenones, Fe-allene complex PF6 salts and the like can be used.

  Note that although an example in which an organic compound is used as a material for forming the memory layer 232 is described here, the present invention is not limited to this example. For example, a material that reversibly changes between a crystalline state and an amorphous state by an electrical action, an optical action, a chemical action, a thermal action, or the like, or a first crystalline state and a second crystalline state Phase change materials, such as materials that reversibly change between, can be used. It is also possible to use a material that changes irreversibly only from an amorphous state to a crystalline state.

Materials that reversibly change between a crystalline state and an amorphous state include germanium (Ge), tellurium (Te), antimony (Sb), sulfur (S), tellurium oxide (TeOx), Sn (tin), A material having a plurality of materials selected from gold (Au), gallium (Ga), selenium (Se), indium (In), thallium (Tl), Co (cobalt), and silver (Ag), for example, Ge-Te _{-Sb-S, Te-TeO 2} -Ge-Sn, Te-Ge-Sn-Au, Ge-Te-Sn, Sn-Se-Te, Sb-Se-Te, Sb-Se, Ga-Se-Te, Ga-Se-Te-Ge, In-Se, In-Se-Tl-Co, Ge-Sb-Te, In-Se-Te, and Ag-In-Sb-Te-based materials can be given. The materials that reversibly change between the first crystal state and the second crystal state are silver (Ag), zinc (Zn), copper (Cu), aluminum (Al), nickel (Ni), A material having a plurality of materials selected from indium (In), antimony (Sb), selenium (Se), and tellurium (Te). For example, Ag—Zn, Cu—Al—Ni, In—Sb, In—Sb— Se and In-Sb-Te are mentioned. In this material, the phase change takes place between two different crystalline states. The material that changes only from the amorphous state to the crystalline state is selected from tellurium (Te), tellurium oxide (TeOx), palladium (Pd), antimony (Sb), selenium (Se), and bismuth (Bi). For example, Te—TeO ₂ , Te—TeO ₂ —Pd, and Sb ₂ Se ₃ / Bi ₂ Te ₃ can be given. In the description of the above materials, Sb ₂ Se ₃ / Bi ₂ Te ₃ means that a layer containing Sb ₂ Se ₃ and a layer containing Bi ₂ Te ₃ are stacked.

  Further, the fourth conductive layer 231 and the fifth conductive layer 233 which form the memory element can be formed by a CVD method, a sputtering method, a screen printing method, a droplet discharge method, a dispenser method, or the like. The materials for forming the fourth conductive layer 231 and the fifth conductive layer 233 include aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni ), Platinum (Pt), copper (Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), or an alloy containing a plurality of such elements A single layer structure or a laminated structure made of can be used. In addition, single layers such as ITO film (indium tin oxide film), silicon-containing indium tin oxide film, zinc oxide (ZnO) film, titanium nitride film, chromium film, tungsten film, Zn film, Pt film, etc. In addition to the film, a stack of a titanium nitride film and a film containing aluminum as a main component, a three-layer structure of a titanium nitride film, a film containing aluminum as a main component, and a titanium nitride film can be used. Note that when the fourth conductive layer 231 or the fifth conductive layer 233 has a stacked structure, resistance as a wiring can be reduced.

  In the semiconductor device according to the present invention, a memory element can be formed on the upper surface of the semiconductor integrated circuit 303 as in the above example, and a sensor element or the like can be formed in the same manner. As described above, in the case of manufacturing a memory element or a sensor element on the upper surface of the semiconductor integrated circuit 303, the semiconductor integrated circuit 303 is attached to the substrate 221 provided with the conductive film 219 functioning as an antenna, and then the nth element. A memory element, a sensor element, or the like can be manufactured over the fifth insulating layer 215 provided in the formation layer.

(Embodiment 7)
In this embodiment mode, a method for manufacturing a semiconductor integrated circuit different from that in the above embodiment mode and a semiconductor device including the semiconductor integrated circuit will be described with reference to FIGS. Specifically, a case will be described in which each of the element formation layers for configuring the semiconductor integrated circuit has semiconductor elements having different functions or different configurations.

  The semiconductor integrated circuit of the present invention includes a semiconductor element having another function in addition to the layer having the semiconductor element functioning as the thin film transistor described in the above embodiment (for example, a diode, a field effect transistor, a resistance element, a capacitor element) , A memory element, a sensor element, and the like) can be stacked.

  In this manner, examples of manufacturing a semiconductor integrated circuit having various kinds of semiconductor elements will be described with reference to FIGS. First, as illustrated in FIG. 17A, a separation layer 702 is formed over a first substrate 701, and a semiconductor such as a diode, a field effect transistor, a resistance element, a capacitor, a memory element, or the like is formed over the separation layer 702. A first element formation layer 703 including a semiconductor element manufactured using a process is formed. The semiconductor element formed in the first element formation layer 703 is a semiconductor element manufactured using the semiconductor process described above as an example. Here, the semiconductor element formed in the first element formation layer 703 is used. Is referred to as an element group A.

  Similarly, the separation layer 702 and the second element formation layer 705 having the element group B to the nth element formation layer 707 having the element group X are formed over the second substrate 704 to the nth substrate 706. . Further, the second element formation layer 705 to the nth element formation layer 707 each have an opening 708 for forming a through wiring. Here, like the element group A, the element groups B to X include semiconductor elements manufactured using the semiconductor process. In addition, the element group A to the element group X may include one type of semiconductor element or a plurality of types of semiconductor elements.

  Next, as illustrated in FIG. 17B, the first element formation layer 703 to the nth element formation layer 707 are separated from the first substrate 701 to the nth substrate 706. As a peeling method, the method described in the above embodiment mode may be applied.

  Next, the first element formation layer 703 is attached to another substrate 712. Then, the second element formation layer 705 is bonded onto the first element formation layer 703, and a conductive paste is dropped to connect the first element formation layer 703 and the second element formation layer 705. A wiring 710 is formed. Similarly, the third element formation layer 709 to the nth element formation layer 707 are bonded to form a through wiring 710, whereby a semiconductor integrated circuit 711 is formed as shown in FIG. Can do.

  An example of manufacturing a semiconductor integrated circuit by stacking layers having different types of element groups as described above will be described with reference to FIGS. In this example, a first element formation layer having a thin film transistor as the element group A and a second element formation layer having the memory element described in Embodiment Mode 6 with reference to FIG. To do.

  First, as illustrated in FIG. 18A, a separation layer 702 is formed over a first substrate 701, and a first element formation layer 703 including an element group A (thin film transistor) is formed over the separation layer 702. Similarly, as illustrated in FIG. 18B, a separation layer 702 is formed over the second substrate 704, and a second element formation layer 705 including the element group B (memory element) is formed over the separation layer 702. To do. Here, the first element formation layer 703 including the element group A can be manufactured by applying the method described in the above embodiment mode.

  In the second element formation layer 705 including the element group B, first, the second insulating layer 713 is formed over the separation layer 702. Next, a conductive layer is formed over the second insulating layer and processed, whereby the third conductive layer 714 is formed. Next, a third insulating layer 715 is formed by forming an insulating layer over the third conductive layer and processing it. Next, the memory layer 716 is formed over the third insulating layer. Then, a fourth conductive layer 717 having conductivity is formed over the memory layer 716. Thus, the second element formation layer 705 including the memory element 719 formed with a stacked structure of the third conductive layer 714, the memory layer 716, and the fourth conductive layer 717 is manufactured. In addition, the second element formation layer can have an opening for connection with the first element formation layer.

  The third conductive layer 714 and the fourth conductive layer 717 are formed using a film formed of an element of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), or silicon (Si) or these elements. The used alloy film can be used. The third conductive layer 714 can be formed by a sputtering method, a CVD method, or the like, and a resist mask formed by a photolithography method and processed by an etching method. The fourth conductive layer 717 can be formed in a manner similar to that of the third conductive layer 714. However, the fourth conductive layer 717 can be formed in any shape using a metal mask.

  For the memory layer 716, the organic compound described in Embodiment 6 can be used. The second insulating layer 713 and the third insulating layer 715 are formed using a silicon oxide, a silicon nitride, a silicon oxide containing nitrogen, an oxygen, or the like by a vapor deposition method (CVD method), a sputtering method, or the like. A silicon nitride containing silicon is formed. In addition, the third insulating layer 715 is formed using an arbitrary film formation method such as a vapor deposition method, a sputtering method, an SOG (spin on glass) method, a droplet discharge method (for example, an ink jet method), or the like. It can also be formed using a material, silicon nitride, polyimide, acrylic, siloxane, oxazole resin, or the like.

  By peeling the first element formation layer 703 and the second element formation layer 705 formed in this manner and attaching them, a semiconductor integrated circuit can be formed as shown in FIG. The method described in the above embodiment can be applied to the separation, bonding, and formation of the through wiring of each element formation layer. Note that FIG. 18C illustrates an example in which the second element formation layer 705 is bonded so that the upper surface of the second element formation layer 705 faces the upper surface of the first element formation layer 703 and an anisotropic conductive material 718 is used for adhesion. Yes.

  In this manner, the uppermost layer of the first element formation layer 703 and the second element formation layer 705 is formed of a conductive layer, and these layers are bonded so as to face each other through the anisotropic conductive material 718. The first element formation layer 703 and the second element formation layer 705 can be electrically connected without forming the through wiring. This method can be applied when a semiconductor integrated circuit to be manufactured is formed by stacking two element formation layers.

  In the above example, the first element formation layer 703 and the second element formation layer 705 are separated from the first substrate 701 and the second substrate 704 to form a semiconductor integrated circuit. Either one of the element formation layer 703 and the second element formation layer 705 can be peeled off and bonded to the other element formation layer. At this time, the first element formation layer 703 having a thin film transistor can be peeled off and attached to the second element formation layer 705. In this case, an opening is formed also in the first element formation layer. May be.

  On the other hand, the second element formation layer 705 from which the memory element 719 is manufactured can be peeled off and attached to the first element formation layer 703. If the third conductive layer 714 and the fourth conductive layer 717 included in the memory element 719 are formed using a soft metal such as aluminum and the memory layer 716 is formed using an organic compound, the third conductive layer 714 includes the memory element 719. The second element formation layer 705 is very flexible. Therefore, peeling the second element formation layer 705 including the memory element 719 causes less damage at the time of peeling, so that a highly reliable semiconductor integrated circuit can be formed.

  Further, it is also possible to form both a thin film transistor and a memory element in the first element formation layer 703 and the second element formation layer 705 and to superimpose these layers to manufacture a semiconductor integrated circuit.

  Further, in the structure of the memory element shown in FIGS. 18B and 18C, a piezoelectric element can be formed by changing the material for forming the memory layer 716 to a material having piezoelectricity. . Since the piezoelectric element generates a voltage between the third conductive layer 714 and the fourth conductive layer 717 in accordance with a pressure applied from the outside, the piezoelectric element can be used as a pressure sensor or the like.

Examples of the piezoelectric material for forming the piezoelectric layer include quartz (SiO ₂ ), barium titanate (BaTiO), lead titanate (PbTiO ₃ ), and lead zirconate titanate (Pb (Zr, Ti) O). ₃ ), lead lanthanum zirconate titanate ((Pb, La) (Zr, Ti) O ₃ ), lithium niobate (LiNbO ₃ ), lead metaniobate (PbNb ₂ O ₆ ), polyvinylidene fluoride (PVDF), oxidation Zinc (ZnO), aluminum nitride (Al _x N _y ), and tantalum oxide (Ta ₂ O ₅ ) can be used. A piezoelectric material is an insulator having no crystal center. When stress is applied to the crystal, positive and negative charges are generated on the surface of the crystal and polarization occurs. This is called the positive piezoelectric effect. Conversely, when a voltage is applied to the crystal, distortion occurs. This is called the reverse piezoelectric effect. Therefore, when an alternating current is applied, the piezoelectric material vibrates due to the inverse piezoelectric effect.

  In this manner, by using the process of the above example, a semiconductor integrated circuit including a thin film transistor and a piezoelectric element can be formed by changing the memory layer to a piezoelectric layer and attaching it to the first element formation layer 703.

  When forming a semiconductor integrated circuit having a sensor element for detecting information from the outside, such as a piezoelectric element, the layer having the sensor element is used as an uppermost layer (nth element forming layer) forming the semiconductor integrated circuit. It is preferable to form. This is because information from the outside can be detected with high sensitivity by arranging the sensor element on the uppermost layer (outermost surface) of the semiconductor integrated circuit. In addition to the pressure sensor using a piezoelectric element, the sensor element has various configurations such as a temperature sensor using a thermoelectric element, an infrared sensor, an acceleration sensor using a structure having a movable part, and a pressure sensor. Sensors can be made.

  In addition, as an example of manufacturing a layer including a semiconductor element that functions as a memory element, a floating gate (floating gate) is used in addition to a memory element in which a memory layer is provided between two conductive layers as in the above example. Or a destructive memory element having the same shape as a thin film transistor can be manufactured. Here, an example of a semiconductor integrated circuit including a nonvolatile memory having a floating gate is described with reference to FIG.

  In this example, the first element formation layer 721 is formed by using the semiconductor substrate as the first substrate and manufacturing the memory element 720 having the floating gate on the first substrate. The memory element 720 included in the first element formation layer 721 includes a floating gate which is a charge holding region. Normally, a thin film transistor or a field effect transistor has a gate electrode formed on a gate insulating film, but the memory element 720 has a floating gate formed on a gate insulating film (also referred to as a tunnel oxide film). Further, a gate electrode is formed with an insulating film interposed therebetween. The storage element 720 having a floating gate (floating gate) realizes 1-bit storage using two states in which charges are stored or not stored in the floating gate.

  When writing to the memory element 720, one of the two high-concentration impurity regions (here, a source electrode) is used as a ground voltage, and the other of the gate electrode and the high-concentration impurity region (here, a drain electrode and a drain electrode). High voltage. Then, electrons flow from the source electrode to the drain electrode, but when a sufficiently high voltage is applied, electrons flowing through the channel portion become thermoelectrons (hot electrons), and part of the electrons pass through the tunnel oxide film. Accumulated in the floating gate. Thereafter, even if the electrons are sufficiently accumulated in the floating gate and then the gate is closed, the electrons in the floating gate are blocked and held by the tunnel oxide film. In this state, the threshold voltage of the transistor is raised by electrons stored in the floating gate, and the switch remains closed even when the transistor is operated at a low voltage. This state is a state in which information is stored in the storage element 720. Conversely, when erasing information, if the gate electrode is set to the ground voltage and the source electrode is kept at a high potential, electrons are gradually emitted from the floating gate, and the information is erased.

  Next, a glass substrate is used as the second substrate, and a separation element, a semiconductor element 722 functioning as a thin film transistor, and a second element formation layer 723 having an opening are formed over the second substrate. This second element formation layer can be manufactured by applying the method described in the above embodiment mode. Then, the second element formation layer 723 is peeled from the second substrate, and the upper surface of the second element formation layer 723 is formed on the first element formation layer 721 formed on the first substrate. A semiconductor integrated circuit including a memory element and a semiconductor element functioning as a transistor illustrated in FIG. 19A can be formed by bonding so as to face the upper surface of the element formation layer 721.

  Note that FIG. 19A illustrates an example in which an anisotropic conductive material 724 is used for bonding. In this manner, the uppermost layer of the first element formation layer and the second element formation layer is formed of a conductive layer, and the layers are bonded so as to face each other through an anisotropic conductive material. Without being formed, the first element formation layer 721 and the second element formation layer 723 can be electrically connected.

  Note that the embodiment mode of the present invention is not limited thereto, and an opening is provided in the second element formation layer 723, and a through wiring is formed in the opening to connect to the first element formation layer 721, so that memory A semiconductor integrated circuit including an element and a semiconductor element functioning as a transistor may be formed. Further, an opening may be formed in the first element formation layer 721.

  The semiconductor element 722 and the nonvolatile memory element 720 are similar in shape, but have different manufacturing processes. Therefore, the semiconductor element 722 and the nonvolatile memory element 720 are manufactured by using the present invention and bonding them after manufacturing them in different element formation layers. Thus, a highly reliable product can be manufactured.

  Further, as in the above example, the first element formation layer 721 uses a semiconductor substrate to form a bipolar transistor, a PN junction diode, a field effect transistor (FET), or the like, and the second element formation layer 723 to the second element formation layer 721. A semiconductor element that can be formed over a glass substrate, such as a thin film transistor, can be formed and bonded to the element formation layer of n. For example, in the case of a semiconductor integrated circuit having a sensor element, a bipolar transistor is often effective for amplifying the output from the sensor element. Therefore, a CMOS circuit and a bipolar transistor are combined by attaching an element formation layer. Alternatively, a BiCMOS circuit may be manufactured.

  Such an example is shown in FIG. The first element formation layer 725 includes a semiconductor element 726 functioning as a bipolar transistor on a semiconductor substrate, and the second element formation layer 727 and the third element formation layer 728 include a semiconductor element 729 functioning as a thin film transistor. And the fourth element formation layer 730 includes a sensor element 731 having a movable portion.

  In this example, the first element formation layer 725 is formed by using a semiconductor substrate as the first substrate and manufacturing a bipolar transistor over the first substrate. The bipolar transistor is a junction of a P-type semiconductor and an N-type semiconductor, and has three terminals of an emitter, a base, and a collector. There are an NPN type in which both ends of the P type are sandwiched between N types, and a PNP type in which both ends of the N type are sandwiched between P types, and the current between the collector and the emitter is controlled by the current flowing between the base and the emitter. Here, normal operation can be performed by increasing the impurity concentration of the semiconductor on the emitter side.

  Next, a separation layer, a semiconductor element 729 functioning as a thin film transistor, and a second element formation layer 727 or a third element formation layer 728 having an opening are formed over the second substrate or the third substrate. . The second element formation layer 727 and the third element formation layer 728 can be manufactured by applying the method described in the above embodiment mode.

  Next, a structure that functions as the sensor element 731 having a separation layer and a movable portion is formed over the fourth substrate. First, a peeling layer and an insulating layer are sequentially formed over a substrate, and a conductive layer 732 functioning as a fixed electrode is formed thereover. Next, a sacrificial layer is formed over the conductive layer 732, and a structural layer 733 is formed over the sacrificial layer. The conductive layer 732, the sacrificial layer, and the structural layer 733 can be formed using a known material and a deposition method. The structural layer 733 can be formed by stacking a plurality of kinds of layers such as a conductive layer and an insulating layer. In addition, since the sacrificial layer is finally removed, it is preferable to use a material having an etching selectivity with respect to the material constituting the other layer.

Next, the second element formation layer 727 to the fourth element formation layer 730 are peeled from the second substrate to the fourth substrate, and over the first element formation layer 725 formed over the first substrate. Bonding is performed to form a through wiring. Then, in order to form a movable portion of the manufactured structure in the fourth element formation layer 730, the sacrificial layer is etched to remove the sacrificial layer, thereby functioning as a bipolar transistor shown in FIG. A semiconductor integrated circuit including a semiconductor element 726 and a structure functioning as the sensor element 731 can be formed.

  In the semiconductor integrated circuit of the present invention, semiconductor elements manufactured through different steps can be separately manufactured and bonded. For example, a layer having a P-channel transistor and a layer having an N-channel transistor can be formed in different layers and bonded to each other.

  In this manner, a semiconductor integrated circuit can be manufactured by freely combining the various element formation layers described above. Further, for example, a semiconductor device such as an RFID described in the above embodiment can be manufactured using the semiconductor integrated circuit described in this embodiment. In the case of manufacturing a semiconductor device functioning as an RFID, an antenna formed separately may be attached to a semiconductor integrated circuit manufactured according to the example of this embodiment. In the process of manufacturing the semiconductor integrated circuit, the first element formation layer to the (n−1) th element formation layer and the nth layer having an antenna are formed, and the first element formation layer to the nth element are formed. A semiconductor device functioning as an RFID can be manufactured by stacking the formation layers.

(Embodiment 8)
In this embodiment mode, usage modes of a semiconductor device functioning as an IC card will be described with reference to FIGS.

  A semiconductor device 300 illustrated in FIG. 20 is provided by bonding the semiconductor integrated circuit 323 manufactured in the above embodiment mode to a substrate 321. A conductive film 322 functioning as an antenna is formed over the substrate 321, and the semiconductor element included in the semiconductor integrated circuit 323 is electrically connected to the conductive film 322 functioning as an antenna provided over the substrate 321 (see FIG. 20 (A)).

  Here, the semiconductor integrated circuit 323 used for forming the semiconductor device 300 is formed using the method described in the above embodiment mode, and includes a first element formation layer to an nth element formation layer. (N = 3 in the figure) are laminated and bonded together, and each layer is electrically connected through the through wiring. In the semiconductor integrated circuit 323, an electric circuit (for example, a power supply circuit, a demodulation circuit, a logical operation circuit, a memory circuit, or the like) for forming a semiconductor device is formed.

  The electrical connection between the semiconductor element included in the semiconductor integrated circuit 323 and the conductive film 322 functioning as an antenna is the upper surface on the side where the semiconductor element is provided, that is, the n-th element formation layer 153 including the semiconductor element ( This is performed by connecting the second conductive layer 140 or the through wiring 126 and the conductive film 322, which is the uppermost layer forming the semiconductor integrated circuit and is located on the upper surface of the third element formation layer in the figure (see FIG. (See FIG. 20C). Here, an example is shown in which the through wiring 126 electrically connected to the semiconductor element 335 and the conductive film 322 functioning as an antenna are connected using a conductive resin. As the resin, the anisotropic conductive material described in the above embodiment is used, so that the semiconductor integrated circuit and the conductive film functioning as an antenna can be electrically connected through the conductive particles 311 included in the adhesive resin 312. (See FIG. 20C).

  In addition, the semiconductor device can be protected by connecting a semiconductor integrated circuit to a substrate over which a conductive film functioning as an antenna is formed, and then bonding a film serving as a protective layer over the substrate.

  Further, by using a flexible substrate such as plastic as the substrate 321, a semiconductor device functioning as an IC card can be curved, so that an IC card with added value can be provided (FIG. 20). (See (B)).

(Embodiment 9)
In this embodiment mode, operation of a semiconductor device capable of exchanging data without contact will be described below with reference to FIGS.

  The semiconductor device 80 has a function of communicating data without contact, and controls the high frequency circuit 81, the power supply circuit 82, the reset circuit 83, the clock generation circuit 84, the data demodulation circuit 85, the data modulation circuit 86, and other circuits. A control circuit 87, a memory circuit 88, and an antenna 89 are provided (FIG. 21).

  The high frequency circuit 81 is a circuit that receives a signal from the antenna 89 and outputs the signal received from the data modulation circuit 86 from the antenna 89. The power supply circuit 82 is a circuit that generates a power supply potential from a reception signal input from the antenna 89. The reset circuit 83 is a circuit that generates a reset signal, and the clock generation circuit 84 is a circuit that generates various clock signals based on the received signal input from the antenna 89. The data demodulation circuit 85 is a circuit that demodulates the received signal and outputs it to the control circuit 87, and the data modulation circuit 86 is a circuit that modulates the signal received from the control circuit 87.

  Further, as the control circuit 87, for example, a code extraction circuit 71, a code determination circuit 72, a CRC determination circuit 73, and an output unit circuit 74 are provided. The code extraction circuit 71 is a circuit that extracts each of a plurality of codes included in an instruction sent to the control circuit 87. The code determination circuit 72 is a circuit that compares the extracted code with a code corresponding to a reference to determine the content of the instruction. The CRC circuit detects the presence or absence of a transmission error or the like based on the determined code. Circuit.

  Further, the memory circuit 88 is not limited to one, and a plurality of memory circuits 88 may be provided. An SRAM, a flash memory, a ROM, an FeRAM, or the like, or an organic compound layer using a memory element portion can be used.

  Next, an example of the operation of the semiconductor device capable of data communication without contact according to the present invention will be described. First, a radio signal is received by the antenna 89. The wireless signal is sent to the power supply circuit 82 via the high frequency circuit 81, and a high power supply potential (hereinafter referred to as VDD) and a low power supply potential (hereinafter referred to as VSS) are generated. Then, VDD is supplied to each circuit included in the semiconductor device 80. Note that in a plurality of circuits included in the semiconductor device 80, VSS is common and VSS can be GND.

  The signal sent to the data demodulation circuit 85 via the high frequency circuit 81 is demodulated (hereinafter, demodulated signal). Further, the signal and the demodulated signal that have passed through the reset circuit 83 and the clock generation circuit 84 via the high frequency circuit 81 are sent to the control circuit 87. The signal sent to the control circuit 87 is analyzed by the code extraction circuit 71, the code determination circuit 72, the CRC determination circuit 73, and the like. Then, information on the semiconductor device stored in the memory circuit 88 is output in accordance with the analyzed signal. The output information of the semiconductor device is encoded through the output unit circuit 74. Further, the encoded information of the semiconductor device 80 passes through the data modulation circuit 86 and is transmitted as a radio signal by the antenna 89.

  As described above, by transmitting a signal from the reader / writer to the semiconductor device 80 and receiving the signal transmitted from the semiconductor device 80 by the reader / writer, the data of the semiconductor device can be read.

  The semiconductor device 80 may be of a type in which the power supply voltage is supplied to each circuit by electromagnetic waves without mounting a power supply device (for example, a battery or a battery). The power supply voltage may be supplied.

  By using the structure described in any of the above embodiments, a semiconductor device that can be bent can be manufactured; thus, the semiconductor device can be attached to an object having a curved surface.

  Next, an example of a usage mode of a semiconductor device having flexibility and capable of exchanging data without contact will be described. A reader / writer 3230 is provided on a side surface of the portable terminal 3220 including the display portion 3210 illustrated in FIG. Further, a semiconductor device 3200 of the present invention is provided on a side surface of the article 3240. When the reader / writer 3230 is held over the semiconductor device 3200 included in the product 3240, the display unit 3210 displays information about the product, such as a description of the product, such as the raw material and origin of the product, the inspection result for each production process, and the history of the distribution process. Is done.

  Further, as shown in FIG. 22B, when the product 3240 is conveyed by a belt conveyor, the product 3240 is used by using the reader / writer 3230 and the semiconductor device 3200 of the present invention provided in the product 3240. Can be inspected.

  In this manner, by using a semiconductor device in a system for managing articles, information can be easily acquired, and high functionality and high added value are realized. In addition, as described in the above embodiment, even when the semiconductor device of the present invention is attached to an object having a curved surface, the semiconductor element included in the semiconductor device is prevented from being damaged, and a highly reliable semiconductor An apparatus can be provided.

  As a signal transmission method in the semiconductor device capable of exchanging contactless data as described above, an electromagnetic coupling method, an electromagnetic induction method, a microwave method, or the like can be used. The transmission method may be appropriately selected by the practitioner in consideration of the intended use, and an optimal antenna may be provided according to the transmission method.

  For example, when an electromagnetic coupling method or an electromagnetic induction method (for example, 13.56 MHz band) is applied as a signal transmission method in a semiconductor device, the conductive film functioning as an antenna is used because electromagnetic induction due to a change in magnetic field density is used. Are formed in a ring shape (for example, a loop antenna) or a spiral shape (for example, a spiral antenna).

  As a signal transmission method in the semiconductor device, a microwave method (for example, a UHF band (860 to 960 MHz band), a 2.45 GHz band, or the like) can be used. In that case, a shape such as a length of a conductive layer functioning as an antenna may be appropriately set in consideration of a wavelength of an electromagnetic wave used for signal transmission. For example, a conductive film functioning as an antenna may be linear (for example, A dipole antenna), a flat shape (for example, a patch antenna), a ribbon shape, or the like. Further, the shape of the conductive film functioning as an antenna is not limited to a linear shape, and may be provided in a curved shape, a meandering shape, or a combination thereof in consideration of the wavelength of electromagnetic waves.

  The conductive film functioning as an antenna is formed using a conductive material by a CVD method, a sputtering method, a printing method such as screen printing or gravure printing, a droplet discharge method, a dispenser method, a plating method, or the like. Conductive materials are aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), platinum (Pt) nickel (Ni), palladium (Pd), tantalum (Ta), molybdenum An element selected from (Mo) or an alloy material or a compound material containing these elements as a main component is formed in a single layer structure or a laminated structure.

  For example, when a conductive film that functions as an antenna is formed using a screen printing method, a conductive paste in which conductive particles having a particle size of several tens of μm or less are dissolved or dispersed in an organic resin is selectively printed. Can be provided. As conductive particles, silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo) and titanium (Ti) Any one or more metal particles such as silver halide fine particles or carbon black can be used. In addition, as the organic resin contained in the conductive paste, one or more selected from organic resins functioning as a binder of metal particles, a solvent, a dispersant, and a coating material can be used. Typically, an organic resin such as an epoxy resin or a silicone resin can be given. In forming the conductive film, it is preferable to fire after printing the conductive paste. For example, when fine particles mainly composed of silver (for example, particles having a particle diameter of 1 nm to 100 nm) are used as a conductive paste material, the conductive film is cured by baking at a temperature range of 150 to 300 ° C. Can be obtained. Further, fine particles mainly composed of solder or lead-free solder may be used. In this case, it is preferable to use fine particles having a particle diameter of 20 μm or less. Solder and lead-free solder have the advantage of low cost.

  In addition to the materials described above, ceramics, ferrites, etc. may be applied to the antenna, and other materials (metamaterials) that have a negative dielectric constant and magnetic permeability in the microwave band may be applied to the antenna. Is also possible.

  In addition, when an electromagnetic coupling method or an electromagnetic induction method is applied and a semiconductor device including an antenna is provided in contact with a metal film, a magnetic device having a magnetic permeability between the semiconductor device and the metal film. It is preferable to provide a material. When a semiconductor device including an antenna is provided in contact with a metal film, an eddy current flows through the metal film as the magnetic field changes, and the change in the magnetic field is weakened by the demagnetizing field generated by the eddy current. descend. Therefore, by providing a material having magnetic permeability between the semiconductor device and the metal film, it is possible to suppress metal eddy current and suppress a decrease in communication distance. As the magnetic material, a metal thin film or ferrite having high magnetic permeability and low high-frequency loss can be used.

  In the case of providing an antenna, a semiconductor element such as a transistor and a conductive film functioning as an antenna may be provided over the same substrate, or after the semiconductor element and the conductive film functioning as an antenna are provided over different substrates. Alternatively, they may be provided by bonding so as to be electrically connected.

  Note that sealing treatment can be performed on the above-described semiconductor device. For example, as illustrated in FIG. 23, a semiconductor integrated circuit or a semiconductor device can be sealed using a first sheet material 337 (also referred to as a film or a substrate) and a second sheet material 338. In FIG. 23, the sealed semiconductor device is the semiconductor device described in Embodiment Mode 6 with reference to FIG. The semiconductor device is attached so that a semiconductor integrated circuit and a conductive film 219 functioning as an antenna formed over the substrate 221 are electrically connected.

  By such sealing, impurity elements, moisture, and the like mixed into the semiconductor element from the outside can be suppressed. As the first sheet material 337 and the second sheet material 338 used for sealing, a film made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, paper made of a fibrous material, a base film (polyester) , Polyamide, inorganic vapor-deposited film, paper, etc.) and an adhesive synthetic resin film (acrylic synthetic resin, epoxy synthetic resin, etc.) can be used.

  Moreover, a film melt | dissolves the adhesive layer provided in the outermost surface, or the layer (not adhesive layer) provided in the outermost layer by heat processing, and adhere | attaches it by pressurization. Further, an adhesive layer may be provided on the surfaces of the first sheet material 337 and the second sheet material 338, or the adhesive layer may not be provided. The adhesive layer corresponds to a layer containing an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, or a resin additive. In addition, it is preferable to perform silica coating on the sheet material to be sealed in order to prevent moisture and the like from entering the inside after sealing. For example, a sheet material obtained by laminating an adhesive layer, a film such as polyester, and silica coating is used. be able to.

  Moreover, when performing the heat processing of a film, it is preferable to use the thing with the same thermal expansion coefficient of a 1st sheet material and a 2nd sheet material. This is for preventing the semiconductor device from being deformed and applying an abnormal stress to the semiconductor element by making the shrinkage rate of the sheet material after the heat treatment the same.

  Further, as the first sheet material 337 or the second sheet material 338, a film provided with an antistatic measure for preventing static electricity (hereinafter referred to as an antistatic film) can be used. Examples of the antistatic film include a film in which an antistatic material is dispersed in a resin, a film on which an antistatic material is attached, and the like. The film provided with an antistatic material may be a film provided with an antistatic material on one side, or a film provided with an antistatic material on both sides. Furthermore, a film provided with an antistatic material on one side may be attached to the layer so that the surface provided with the antistatic material is on the inside of the film, or on the outside of the film. It may be pasted. Note that the antistatic material may be provided on the entire surface or a part of the film. As the antistatic material here, surfactants such as metals, oxides of indium and tin, amphoteric surfactants, cationic surfactants and nonionic surfactants can be used. In addition, as the antistatic material, a resin material containing a crosslinkable copolymer polymer having a carboxyl group and a quaternary ammonium base in the side chain can be used. These materials can be attached to a film, kneaded, or coated on the surface to form an antistatic film. By sealing with an antistatic film, it is possible to prevent the semiconductor element from being adversely affected by external static electricity or the like when handled as a product.

  In the sealing process, either one of the first sheet material 337 and the second sheet material 338 may be used to selectively seal one of the surfaces. In addition, sealing may be performed by using a glass substrate instead of the first sheet material 337 or the second sheet material 338. In this case, the glass substrate functions as a protective film, and the semiconductor element is externally provided. Intrusion of moisture and impurity elements can be suppressed.

(Embodiment 10)
The semiconductor device of the present invention can be used in various articles and various systems as shown in FIG. 24 by utilizing the function of transmitting and receiving data without contact.

  Articles include, for example, keys (see FIG. 24A), banknotes, coins, securities, bearer bonds, certificate documents (driver's license, resident's card, etc.), books, containers (pets, etc.) 24 (B)), accessories (such as bags and glasses, see FIG. 24 (C)), packaging containers (wrapping paper, bottles, etc., see FIG. 24 (D)), recording media (discs, video tapes, etc.) Vehicles (bicycles, etc.), foods, clothing, daily necessities, electronic devices (liquid crystal display devices, EL display devices, television devices, portable terminals, etc.).

  The semiconductor device 1120 of the present invention can be fixed to an article by being attached to or embedded in the surface of an article having various shapes as described above.

  The system using the semiconductor device of the present invention is a physical distribution / inventory management system, an authentication system, a distribution system, a production history system, a book management system, or the like. By using the semiconductor device 1120 of the present invention, it is possible to achieve high functionality, multiple functionality, and high added value of the system.

  For example, a semiconductor device 1120 of the present invention is provided inside an identification card, and a reader / writer 1121 is provided at the entrance of a building or the like (see FIG. 24E). The reader / writer 1121 reads an authentication number in an identification card owned by each person, and supplies information about the read authentication number to the computer 1122. Based on the information supplied from the reader / writer 1121, the computer 1122 determines whether to allow entry or exit. As described above, by using the semiconductor device of the present invention, an entrance / exit management system with improved convenience can be provided. Note that in this specification, the reader / writer includes not only a device having a reader function and a writer function, but also a communication device having a reader function or a writer function.

  Note that the structure of this embodiment can be used in combination with the structure of any of the other embodiments.

(Embodiment 11)
In this embodiment mode, a structure of the semiconductor device of the present invention which is different from that in the above embodiment mode will be described with reference to FIGS. Specifically, a semiconductor device having display means will be described.

  First, the case where a light emitting element is provided in the pixel portion as a display means will be described with reference to FIG. 25A is a top view showing an example of a semiconductor device having the display means of the present invention, and FIG. 25B is between the chain lines ab and cd in FIG. 25A. Sectional drawing cut | disconnected by is shown.

  As shown in FIG. 25A, the semiconductor device including the display means described in this embodiment includes a scan line driver circuit 502, a signal line driver circuit 503, a pixel portion 504, and the like provided over a substrate 501. ing. Further, a counter substrate 506 is provided so as to sandwich the pixel portion 504 with the substrate 501, and the substrate 501 and the counter substrate 506 are bonded to each other with a sealant 505. In the scan line driver circuit 502, the signal line driver circuit 503, and the pixel portion 504, a semiconductor element having any one of the structures described in the above embodiments is provided over the substrate 501.

  The scan line driver circuit 502 and the signal line driver circuit 503 receive a video signal, a clock signal, a start signal, a reset signal, and the like from a flexible printed circuit (FPC) serving as an external input terminal. Although only the flexible printed wiring board 507 is shown in the figure, a printed wiring board may be attached to the flexible printed wiring board 507.

  Here, as the signal line driver circuit 503 or the scan line driver circuit 502, a semiconductor integrated circuit in which element formation layers are stacked can be used as described in the above embodiment mode. By providing a semiconductor integrated circuit manufactured by stacking element formation layers in this manner, the area occupied by the signal line driver circuit 503 or the scan line driver circuit 502 can be reduced, so that the area of the pixel portion 504 is increased. It becomes possible to form.

  FIG. 25B is a schematic view of a cross section between chain lines ab and cd in FIG. 25A. Here, a signal line driver circuit 503 provided over a substrate 501 and a pixel The structure of the part 504 is shown. In the signal line driver circuit 503, a semiconductor integrated circuit 510 including a CMOS circuit in which an n-type semiconductor element 511a and a p-type semiconductor element 511b each having one of the structures described in the above embodiments is combined is formed. Yes. The semiconductor integrated circuit 510 is manufactured by applying any one of the methods described in the above embodiments and stacking a first element formation layer to an nth element formation layer (a second element formation layer in the drawing). . Then, a through wiring 126 is formed by dropping conductive paste into openings provided in the first element formation layer to the nth element formation layer, and the first element formation layer to the nth element formation layer are formed. A plurality of n-type semiconductor elements 511a or p-type semiconductor elements 511b provided are electrically connected to form a scan line driver circuit 502, a signal line driver circuit 503, and the like.

  The driver circuits such as the scan line driver circuit 502 and the signal line driver circuit 503 may be formed of a CMOS circuit, a PMOS circuit, or an NMOS circuit, and the semiconductor integrated circuit of the present invention described in the above embodiment mode is applied. It is also possible. In this embodiment mode, a driver integrated type in which driving circuits such as a scanning line driving circuit 502 and a signal line driving circuit 503 are formed over a substrate 501 is shown; however, this is not necessarily required, and it is not necessarily provided on the substrate 501 and externally. A drive circuit can also be formed.

  The pixel portion 504 is formed with a plurality of pixels including a light-emitting element 516 and a semiconductor element 511c for driving the light-emitting element 516. The configuration of the semiconductor element 511c is not particularly limited. Here, the first electrode 513 is provided so as to be connected to the conductive layer 512 connected to the source region or the drain region of the semiconductor element 511c, and is insulated so as to cover an end portion of the first electrode 513. A layer 509 is formed. The insulating layer 509 functions as a partition wall in the plurality of pixels. A light-emitting layer 514 is formed over the first electrode 513, and a second electrode 515 is formed over the light-emitting layer 514. A light-emitting element 516 is provided with a stacked structure of the first electrode 513, the light-emitting layer 514, and the second electrode 515.

  Here, the insulating layer 509 is formed using a positive photosensitive acrylic resin film. Further, in order to improve the coverage of the insulating layer 509, the insulating layer 509 is provided so that a curved surface having a curvature is formed at the upper end portion or the lower end portion thereof. For example, when positive photosensitive acrylic is used as a material for the insulating layer 509, it is preferable that only the upper end portion of the insulating layer 509 has a curved surface with a curvature radius (0.2 μm to 3 μm). As the insulating layer 509, either a negative type that becomes insoluble in an etchant by photosensitive light or a positive type that becomes soluble in an etchant by light can be used. In addition, the insulating layer 509 can be provided with a single layer or a stacked structure including an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, or benzocyclobutene, or a siloxane material such as a siloxane resin.

  Further, as shown in the above embodiment mode, the insulating layer 509 is subjected to plasma treatment, and the insulating layer 509 is oxidized or nitrided, whereby the surface of the insulating layer 509 is modified to obtain a dense film. Is possible. By modifying the surface of the insulating layer 509, the strength of the insulating layer 509 is improved, and it is possible to reduce physical damage such as generation of cracks during the formation of openings and the like and film loss during etching. . Furthermore, by modifying the surface of the insulating layer 509, interface characteristics such as adhesion to the light-emitting layer 514 provided over the insulating layer 509 are improved.

  One of the first electrode 513 and the second electrode 515 is used as an anode, and the other is used as a cathode.

  When used as the anode, it is desirable to use a material having a large work function. For example, an indium tin oxide film, an indium tin oxide film containing silicon, a transparent conductive film formed by a sputtering method using a target in which indium oxide is mixed with 2 to 20 wt% zinc oxide (ZnO), zinc oxide ( In addition to a single layer film such as a ZnO) film, a titanium nitride film, a chromium film, a tungsten film, a Zn film, or a Pt film, a stack of a titanium nitride film and a film containing aluminum as a main component, a titanium nitride film and aluminum as a main component A three-layer structure of a film and a titanium nitride film can be used. Note that when the anode has a laminated structure, the resistance as a wiring is low and good ohmic contact can be obtained.

In addition, when used as a cathode, it is preferable to use a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof, MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride). Note that when the electrode used as the cathode is light-transmitting, a thin metal film and a transparent conductive film (indium tin oxide film, indium tin oxide film containing silicon, indium oxide) are used as the electrode. It is preferable to use a laminate of a transparent conductive film, a zinc oxide (ZnO) film, or the like formed by sputtering using a target in which 2 to 20 wt% zinc oxide (ZnO) is mixed.

  Here, light-transmitting indium tin oxide is used with the first electrode 513 as an anode, and light is extracted from the substrate 501 side. Note that a light-transmitting material may be used for the second electrode 515 to extract light from the counter substrate 506 side, or the first electrode 513 and the second electrode 515 may have a light-transmitting material. It is also possible to provide a structure for extracting light to both sides of the substrate 501 and the counter substrate 506 (double-sided emission).

  The light-emitting layer 514 is formed of a single layer or a stacked structure using a low molecular compound, a high molecular compound (including oligomers and dendrimers), or the like by an evaporation method using an evaporation mask, an inkjet method, a spin coating method, or the like. Can do.

  Here, the light-emitting element 516 is provided in the space 508 surrounded by the substrate 501, the counter substrate 506, and the sealant 505 by attaching the counter substrate 506 to the substrate 501 with the sealant 505. . Note that the gap 508 includes not only an inert gas (such as nitrogen or argon) but also a structure filled with a sealant 505.

  Note that an epoxy-based resin is preferably used for the sealant 505. The sealant 505 is desirably made of a material that does not transmit moisture and oxygen as much as possible. In addition to a glass substrate and a quartz substrate, a plastic substrate made of FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), polyester film, polyester, acrylic, or the like can be used as a material used for the counter substrate 506.

  Note that the semiconductor device having the display means of the present invention is not limited to the structure using the light emitting element in the pixel portion as described above, and includes a semiconductor device using liquid crystal in the pixel portion. A semiconductor device in the case where liquid crystal is used for the pixel portion is shown in FIG.

  Here, the semiconductor device illustrated in FIG. 26 has a top surface structure similar to that illustrated in FIG. 25A and is a cross-sectional view taken along chain lines ab and cd in FIG. ing. As in the above example, the semiconductor device illustrated in FIG. 26 includes a scan line driver circuit 502, a signal line driver circuit 503, a pixel portion 504, and the like provided over a substrate 501. Further, a counter substrate 506 is provided so as to sandwich the pixel portion 504 with the substrate 501, and the substrate 501 and the counter substrate 506 are bonded to each other with a sealant 505. The scanning line driver circuit 502 and the signal line driver circuit 503 receive a video signal, a clock signal, a start signal, a reset signal, and the like from the flexible printed wiring board 507 serving as an external input terminal.

  Here, as the signal line driver circuit 503 or the scan line driver circuit 502, a semiconductor integrated circuit in which an element formation layer is stacked is used as described in the above embodiment mode.

  In FIG. 26, the signal line driver circuit 503 includes a semiconductor integrated circuit 510 having a CMOS circuit in which an n-type semiconductor element 511a and a p-type semiconductor element 511b having any of the structures described in the above embodiments are combined. Is formed. The semiconductor integrated circuit 510 is manufactured by applying any one of the methods described in the above embodiments and stacking a first element formation layer to an nth element formation layer (a second element formation layer in the drawing). . Then, a through wiring 126 is formed by dropping conductive paste into openings provided in the first element formation layer to the nth element formation layer, and the first element formation layer to the nth element formation layer are formed. A plurality of n-type semiconductor elements 511a and p-type semiconductor elements 511b provided are electrically connected to form a scan line driver circuit 502, a signal line driver circuit 503, and the like.

  26, the pixel portion 504 of the semiconductor device includes an alignment film 521 provided so as to cover the conductive layer 512 and the first electrode 513, and an alignment film 523 provided on the counter substrate 506 side. A liquid crystal 522 is provided therebetween. A spacer 525 is provided in the liquid crystal 522 in order to control the distance (cell gap) between the first electrode 513 and the second electrode 524. In addition, the second electrode 524 is provided over the counter substrate 506, and the light transmittance is controlled by controlling the voltage applied to the liquid crystal provided between the first electrode 513 and the second electrode 524. The image can be displayed.

  In the semiconductor device described in this embodiment, the semiconductor element 511c in the pixel portion can be formed at the same time as the first element formation layer included in the semiconductor integrated circuit. Then, the scan line driver circuit 502, the signal line driver circuit 503, or the like can be formed by stacking the second to nth element formation layers only on the portion where the semiconductor integrated circuit 510 is formed. it can. As described above, as a mode of the semiconductor device including the display means described in this embodiment mode, the pixel portion can be provided with a light-emitting element or liquid crystal.

  In FIGS. 25 and 26, a driver integrated type in which a driving circuit such as a scanning line driving circuit or a signal line driving circuit is formed on the substrate is shown. However, the driver integrated type is not formed directly on the substrate, but on the substrate. A driver circuit can also be formed by bonding. An example of the display device in this case will be described with reference to FIG. FIG. 27A is a perspective view of a semiconductor device having a driver circuit outside, and FIG. 27B is a schematic diagram of a cross section taken along line AB in FIG. 27A.

  As shown in FIG. 27A, the semiconductor device of this example includes a pixel portion 504 provided over a substrate 501 and a scan line driver circuit, a signal line driver circuit, and the like formed by a semiconductor integrated circuit as in the above example. Have. A counter substrate 506 is provided so as to sandwich the pixel portion 504 with the substrate 501, and the substrate 501 and the counter substrate 506 are bonded to each other with a sealant 505.

  As shown in FIG. 27B, in the semiconductor device, a semiconductor integrated circuit 531a is attached to a substrate 501 and a semiconductor integrated circuit 531b is attached to a flexible printed wiring board 507 functioning as a connection film. Is provided. The pixel portion 504 and the semiconductor integrated circuit 531a are connected to each other through the first conductive layer 532 over the substrate 501. The semiconductor integrated circuit 531a and the semiconductor integrated circuit 531b are connected via a second conductive layer 533 on the substrate 501 and a third conductive layer 534 on the flexible printed wiring board 507.

  Such a connection between the semiconductor integrated circuit 531a and the first conductive layer 532 or between the semiconductor integrated circuit 531b and the third conductive layer 534 includes adhesion including the conductive particles 311 described in the above embodiment mode. An anisotropic conductive material composed of the conductive resin 312 can be used. In addition to the anisotropic conductive material, the above-mentioned connection includes a conductive adhesive such as silver paste, copper paste or carbon paste, a conductive adhesive such as ACP, a conductive film such as ACF, It can also be performed by soldering or the like.

  By using the semiconductor integrated circuit of the present invention, high integration of the semiconductor device can be realized, and the time required for the manufacturing process can be shortened.

(Embodiment 12)
An electronic device manufactured according to the present invention will be described with reference to FIG.

  A television 8001 illustrated in FIG. 28A includes a display portion 8002, a driver circuit, and the like. By applying the structure and the manufacturing method of the semiconductor device described in the above embodiment modes to the display portion 8002, a driver circuit, and the like, a television which is one of usage modes of the semiconductor device of the present invention can be manufactured.

  An information terminal device 8101 shown in FIG. 28B includes a display portion 8102, an electronic control circuit, an input / output interface, and the like. By applying the structure and the manufacturing method of the semiconductor device described in the above embodiment modes to the display portion 8102, an electronic control circuit, and the like, an information terminal device which is one of the usage modes of the semiconductor device of the present invention can be manufactured. it can.

  A video camera 8201 illustrated in FIG. 28C includes a display portion 8202, an image processing circuit, and the like. By applying the structure and manufacturing method of the semiconductor device described in the above embodiment modes to the display portion 8202, an image processing circuit, or the like, a video camera which is one of usage modes of the semiconductor device of the present invention can be manufactured. .

  A telephone 8301 illustrated in FIG. 28D includes a display portion 8302, a wireless communication circuit, and the like. By applying the structure and the manufacturing method of the semiconductor device described in any of the above embodiments to the display portion 8302, a wireless communication circuit, or the like, a telephone which is one of usage modes of the semiconductor device of the present invention can be manufactured.

  A portable television 8401 illustrated in FIG. 28E includes a display portion 8402, a driver circuit, a wireless communication circuit, and the like. By applying the structure and the manufacturing method of the semiconductor device described in the above embodiment to the display portion 8402, a driver circuit, a wireless communication circuit, or the like, a portable television which is one of the usage modes of the semiconductor device of the present invention is used. Can be produced. In addition, the present invention can be applied to a wide range of televisions, from small ones mounted on portable terminals such as cellular phones to medium-sized ones that can be carried and large ones (for example, 40 inches or more). Can be applied.

  Note that the electronic device according to the present invention is not limited to FIGS. 28A to 28E, and includes an electronic device including a plurality of semiconductor elements in a display portion, a driver circuit portion, or the like.

  As described above, the applicable range of the present invention is so wide that the present invention can be applied to methods for manufacturing electronic devices in various fields. Further, by using the semiconductor integrated circuit of the present invention, high integration of the semiconductor device can be realized, and the time required for the manufacturing process can be shortened. By using the semiconductor integrated circuit of the present invention for an electronic device, a high-performance electronic device can be provided at low cost.

(Embodiment 13)
In addition, the semiconductor integrated circuit of the present invention can be made flexible by being peeled from the manufactured substrate. A specific example of a semiconductor device including a flexible semiconductor integrated circuit will be described below with reference to FIGS.

  FIG. 29A shows a display 4101 which includes a support base 4102 and a display portion 4103. The display portion 4103 is formed using a flexible substrate, and a lightweight and thin display can be realized. In addition, the display portion 4103 can be curved, and the display can be attached along a curved wall that is detached from the support base 4102. The semiconductor integrated circuit or the semiconductor device described in any of the above embodiments is used for an integrated circuit such as the display portion 4103 and a peripheral driver circuit, so that flexibility which is one of usage modes of the semiconductor device of the present invention is provided. A display can be made. In this manner, a flexible display can be installed on a curved portion as well as a flat surface, and thus can be used for various applications.

  FIG. 29B illustrates a display 4201 that can be wound, which includes a display portion 4202. By using the semiconductor integrated circuit or the semiconductor device described in any of the above embodiments for an integrated circuit such as the display portion 4202 or a driver circuit, the semiconductor device of the present invention can be wound and thinned. Large display can be manufactured. Since the display 4201 that can be wound is formed using a flexible substrate, the display 4201 can be folded and wound together with the display portion 4202 and carried. Therefore, even when the rewound display 4201 is large, it can be folded or rolled up and carried in a bag.

  FIG. 29C illustrates a sheet-type computer 4401, which includes a display portion 4402, a keyboard 4403, a touch pad 4404, an external connection port 4405, a power plug 4406, and the like. By using the semiconductor integrated circuit or the semiconductor device described in the above embodiment for an integrated circuit such as the display portion 4402, a driver circuit, or an information processing circuit, the semiconductor device of the present invention is thin or A sheet-type computer can be manufactured. The display portion 4402 is formed using a flexible substrate, and a lightweight and thin computer can be realized. Further, by providing a storage space in the main body portion of the sheet type computer 4401, the display portion 4402 can be wound around and stored in the main body. Further, by providing the keyboard 4403 so as to be flexible, the keyboard 4403 can be wound and stored in the storage space of the sheet-type computer 4401 similarly to the display portion 4402, which is convenient to carry. Further, even when not in use, it can be stored without taking up space by folding.

  FIG. 29D illustrates a display device 4300 having a large display portion of 20 to 80 inches, which includes a keyboard 4302 which is an operation portion, a display portion 4301, a speaker 4303, and the like. The display portion 4301 is formed using a flexible substrate, and the display device 4300 can be folded and rolled up to be carried by removing the keyboard 4302. The keyboard 4302 and the display portion 4301 can be connected wirelessly. For example, the keyboard 4302 can be operated wirelessly while the display device 4300 is attached along a curved wall.

  In the example illustrated in FIG. 29D, the semiconductor integrated circuit or the semiconductor device described in the above embodiment is a wireless communication circuit that controls communication between the display portion 4301, a driver circuit for the display portion, and the display portion and the keyboard. It is used for integrated circuits. Thus, a thin large-sized display device which is one of the usage forms of the semiconductor device of the present invention can be manufactured.

  FIG. 29E illustrates an electronic book 4501, which includes a display portion 4502, operation keys 4503, and the like. A modem may be incorporated in the electronic book 4501. The display portion 4502 is formed using a flexible substrate and can be bent or wound. Therefore, the electronic book can be carried without taking up space. Further, the display portion 4502 can display moving images as well as still images such as characters.

  In the example illustrated in FIG. 29E, the semiconductor integrated circuit or the semiconductor device described in the above embodiment is used for an integrated circuit such as a display portion 4502, a driver circuit, or a control circuit. Thus, a thin electronic book which is one of the usage forms of the semiconductor device of the present invention can be manufactured.

  FIG. 29F illustrates an IC card 4601 which includes a display portion 4602, a connection terminal 4603, and the like. Since the display portion 4602 has a lightweight and thin sheet shape using a flexible substrate, the display portion 4602 can be attached to the surface of the card. In addition, when the IC card can receive data without contact, information acquired from the outside can be displayed on the display portion 4602.

  In the example illustrated in FIG. 29F, the semiconductor integrated circuit or the semiconductor device described in the above embodiment is used for an integrated circuit such as a display portion 4602 or a wireless communication circuit. Thus, a thin IC card, which is one of the usage forms of the semiconductor device of the present invention, can be manufactured.

  As described above, the application range of the present invention is extremely wide and can be used for electronic devices and information display means in various fields.

(Embodiment 14)
In this embodiment mode, as described in the above embodiment mode, a specific example in which a semiconductor integrated circuit is manufactured by applying a method of stacking element formation layers and connecting each layer with a through wiring will be described. Specifically, in this embodiment, an example in which a semiconductor integrated circuit is manufactured using an SRAM memory cell as a volatile memory as an example is shown.

  FIG. 30A shows a block diagram of the SRAM. The SRAM 820 controls a memory cell array 821 in which memory cells are arranged in a matrix, a row decoder 822 and a column decoder 823 that decode a specified address, a selector 824 that selects an address of the memory cell array from the output of the column decoder, and a data read / write control The R / W circuit 825 is provided.

  FIG. 30B illustrates one memory cell included in the memory cell array at a transistor level. An SRAM memory cell includes two selection transistors 801 and 802 (N-type transistors) for selecting a memory cell, and two inverters for storing information, that is, two sets of N-type transistors 804 and 806 and a P-type transistor 803. 805. Therefore, one memory cell of SRAM has six transistors of four N-type transistors and two P-type transistors.

  In the selection transistor 801, either one of the high concentration impurity regions (either the source electrode or the drain electrode) is connected to the bit line 808, and the selection transistor 802 includes either one of the high concentration impurity regions (the source electrode). , Or one of the drain electrodes) is connected to the bit b line 809. The gate electrodes of the two selection transistors 801 and 802 are connected to the word line 807.

  Further, in the selection transistor 801, the higher concentration impurity region which is not connected to the bit line 808 is an input portion of an inverter constituted by the P-type transistor 805 and the N-type transistor 806, and the P-type transistor 803 and the N-type transistor. It is connected to the output portion of the inverter constituted by the transistor 804. In the select transistor 802, the higher concentration impurity region not connected to the bit b line 809 is the output portion of the inverter constituted by the P-type transistor 805 and the N-type transistor 806, and the P-type transistors 803 and N Connected to the input portion of the inverter constituted by the type transistor 804.

  Next, a method for manufacturing the memory cell having the above structure by applying the present invention will be described with reference to FIGS. In the circuit diagram of the memory cell shown in FIG. 30B, only the N-type transistor is arranged at the lower stage and only the P-type transistor is arranged at the upper stage while maintaining the connection relationship, as shown in FIG. Can be rewritten.

  FIG. 31B shows an example in which the circuit shown in FIG. 31A is manufactured by applying the present invention. In the circuit diagram shown in FIG. 31A, a portion shown in the lower part is formed with the first element formation layer 810 having an N-type transistor, and a part shown in the upper part is a second part having a P-type transistor. An element formation layer 811 is used. An opening is formed in the second element formation layer 811. The first element formation layer 810 and the second element formation layer 811 are stacked and bonded, and a through wiring 813 is formed in the opening of the second element formation layer 811, whereby the first element formation layer 810 is formed. And the second element formation layer 811 can be electrically connected.

  In FIG. 31B, the high-concentration impurity regions 842 and 843 of the selection transistor 801 and the N-type transistor 804 are connected to the high-concentration impurity region 844 of the P-type transistor 803 through a through wiring. Similarly, high-concentration impurity regions 846 and 847 of select transistor 802 and N-type transistor 806 are connected to high-concentration impurity region 848 of P-type transistor 805 through a through wiring.

  Here, FIG. 31B shows only the connection relation of the high-concentration impurity regions constituting the source electrode or the drain electrode of each transistor, and does not show the connection relation of the gate electrode. The connection relationship shown in FIG. 31A can be obtained by routing the wiring formed by the second conductive layer or the third conductive layer.

  A semiconductor integrated circuit constituting such an SRAM can be manufactured by applying the method described in the above embodiment.

  In the memory cell, the N-type transistors 804 and 806 and the selection transistors 801 and 802 constituting the inverter have different connection relations and functions with other circuits. For example, the selection transistor is connected to the selector via the bit line 808 and the bit b line 809, and operates when reading or writing data stored in the memory cell. On the other hand, the N-type transistors 804 and 806 constituting the inverter are connected to the P-type transistors 803 and 805, the selection transistor, and the wiring for supplying the ground voltage, which also constitute the inverter, and function for storing and holding data. As described above, an example in which the structure of a layer forming a semiconductor integrated circuit is determined in accordance with the function of each transistor will be described with reference to FIGS.

  FIG. 32 is an equivalent circuit diagram of the semiconductor integrated circuit, and FIG. 33 is a cross-sectional view of the semiconductor integrated circuit having such a circuit configuration. The following description will be given with reference to these drawings.

  A selector to which a selection transistor is connected via a bit line 808 or a bit b line 809 is composed of N-type transistors 816 and 818 and P-type transistors 817 and 819 shown in FIGS. 32A and 33A. The first element formation layer 828 is formed to have P-type transistors 817 and 819 constituting the analog switch, and the second element formation layer 829 is made to have N-type transistors 816 and 818 constituting the analog switch. To do. Further, the bit line 808 and the bit b line 809 are formed in the first element formation layer 828. Connection between the N-type transistors 816 and 818 in the second element formation layer 829 and the bit line 808 and the bit b line 809 in the first element formation layer 828 can be performed by a through wiring 813.

  Further, as shown in FIGS. 32B and 33B, the first element formation layer 828 has selection transistors 801 and 802 (N-type transistors), and the second element formation layer 829 forms an inverter. The transistors 803 and 805 and the third element formation layer 830 can be formed to have N-type transistors 804 and 806 that constitute an inverter. The first element formation layer 828, the second element formation layer 829, and the third element formation layer 830 are connected by a through wiring 813.

  In this manner, a circuit area can be reduced by manufacturing a transistor which forms a circuit with a stacked structure. Further, by forming the bit line 808 and the bit b line 809 that connect the selector and the selection transistor by using only the first element formation layer 828, the wiring length can be shortened. Similarly, by forming the column decoder connected to the selection transistor in the first element formation layer 828, the length of the wiring connecting each circuit and the memory cell can be shortened. Thus, by shortening the length of the wiring, power consumption can be reduced and the operation speed can be improved.

  One of the high concentration impurity regions of the N-type transistor constituting the inverter is supplied with a ground voltage (also referred to as reference voltage, ground, 0 V, VSS), and one of the high concentration impurity regions of the P-type transistor constituting the inverter is A power supply voltage is supplied. Accordingly, a wiring for supplying a power supply voltage is formed in the second element formation layer, and a wiring for supplying a ground voltage is formed in the third element formation layer. These wirings are formed in different element formation layers. Preferably, by forming the element formation layer so that the wirings do not overlap each other when bonded, the parasitic capacitance generated between the wirings can be reduced and the operation speed can be improved.

  In this way, each element formation layer constituting the semiconductor integrated circuit can be formed in consideration of the operation of the circuit.

8A and 8B illustrate a method for manufacturing a semiconductor integrated circuit of the present invention. 8A and 8B illustrate a method for manufacturing a semiconductor integrated circuit of the present invention. 8A and 8B illustrate a method for manufacturing a semiconductor integrated circuit of the present invention. 8A and 8B illustrate a method for manufacturing a semiconductor integrated circuit of the present invention. 8A and 8B illustrate a method for manufacturing a semiconductor integrated circuit of the present invention. 8A and 8B illustrate a method for manufacturing a semiconductor integrated circuit of the present invention. 8A and 8B illustrate a method for manufacturing a semiconductor integrated circuit of the present invention. 8A and 8B illustrate a method for manufacturing a semiconductor integrated circuit of the present invention. 8A and 8B illustrate a method for manufacturing a semiconductor integrated circuit of the present invention. 8A and 8B illustrate a method for manufacturing a semiconductor integrated circuit of the present invention. 8A and 8B illustrate a method for manufacturing a semiconductor integrated circuit of the present invention. 8A and 8B illustrate a method for manufacturing a semiconductor integrated circuit of the present invention. 8A and 8B illustrate a method for manufacturing a semiconductor integrated circuit of the present invention. 8A and 8B illustrate a method for manufacturing a semiconductor integrated circuit of the present invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 8A and 8B illustrate a method for manufacturing a semiconductor integrated circuit of the present invention. 8A and 8B illustrate a method for manufacturing a semiconductor integrated circuit of the present invention. 8A and 8B illustrate a method for manufacturing a semiconductor integrated circuit of the present invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 4A and 4B each illustrate an example of usage of a semiconductor device of the invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 4A and 4B each illustrate an example of usage of a semiconductor device of the invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention. FIG. 10 illustrates a configuration example of a semiconductor integrated circuit of the present invention. FIG. 10 illustrates a configuration example of a semiconductor integrated circuit of the present invention. FIG. 10 illustrates a configuration example of a semiconductor integrated circuit of the present invention. FIG. 10 illustrates a configuration example of a semiconductor integrated circuit of the present invention.

Explanation of symbols

90 Semiconductor layer 91 Gate insulating layer 92 First conductive layer 93 Impurity region 94 Impurity region 95 Channel formation region 96 Semiconductor element 97 Fourth insulating layer 100 Substrate 101 First insulating layer 102 Release layer 103 Second insulating layer 104 Contact hole 105 Contact hole 106 Contact hole 107 Contact hole 108 Contact hole 109 Contact hole 110 Opening 111 Second conductive layer 112 Second conductive layer 113 Second conductive layer 114 Second conductive layer 115 Second conductive layer 116 Second conductive layer 117 Fifth insulating layer 118 Peeling layer removing region 119 Adhesive layer 120 Sixth insulating layer 121 nth element forming layer 122 first element forming layer 124 opening 125 conductive paste 126 through wiring 127 Second conductive layer 129 Through wiring 130 Support substrate 140 Second conductive layer 141 Fifth insulating layer 143 Opening portion 150 Fifth insulating layer 153 nth element forming layer 154 first element forming layer 155 conductive material 156 conductive particles 157 second conductive layer 158 opening Part 160 Second conductive layer 161 Second conductive layer 162 Second conductive layer 163 Second conductive layer 164 Second conductive layer 165 Second conductive layer 166 Second conductive layer 168 Opening 205a Semiconductor element 205b Semiconductor element 205c Semiconductor element 214 Conductive layer 215 Fifth insulating layer 219 Conductive film 221 Substrate 230 Memory element 231 Fourth conductive layer 232 Memory layer 233 Fifth conductive layer 300 Semiconductor device 301 Substrate 302 Conductive film 303 Semiconductor integrated circuit 303a Semiconductor integrated circuit 303b Semiconductor integrated circuit 303c Semiconductor integrated circuit 303d Semiconductor integrated circuit 311 Conductive particles 312 Adhesive resin 321 Substrate 322 Conductive film 323 Semiconductor integrated circuit 335 Semiconductor element 337 First sheet material 338 Second sheet material 380 Third conductive layer 381 Seventh insulating layer 601 First substrate 602 First element formation Layer 603 Second substrate 604 Release layer 605 Second element formation layer 606 Opening 607 Third substrate 608 Third element formation layer 609 nth substrate 610 nth element formation layer 611 Conductive paste 612 Through wiring 613 n−1th element formation layer 614 Semiconductor integrated circuit

Claims (19)

Forming a first element formation layer on the first substrate;
On the second substrate, a second element formation layer having a semiconductor element and an opening is formed via a release layer.
Separating the second element formation layer from the second substrate;
After laminating the separated second element formation layer on the first element formation layer,
A method for manufacturing a semiconductor integrated circuit, wherein the first element formation layer and the second element formation layer are electrically connected by forming a through wiring in the opening. Forming a first element formation layer on the first substrate;
A second element formation layer having a semiconductor element and the opening penetrating the second substrate and the peeling layer is formed on the second substrate via a peeling layer,
After laminating the second element formation layer on the first element formation layer,
By forming a through wiring in the opening, the first element formation layer and the second element formation layer are electrically connected,
A method for manufacturing a semiconductor integrated circuit, wherein the second element formation layer is separated from the second substrate. In claim 1 or claim 2,
The first element formation layer includes a semiconductor element including a conductive layer,
The method for manufacturing a semiconductor integrated circuit, wherein the conductive layer is exposed in the opening. In claim 1 or claim 2,
A method for manufacturing a semiconductor integrated circuit, wherein a conductive layer is formed on a side surface of the opening. In any one of Claims 1 thru | or 4,
A method for manufacturing a semiconductor integrated circuit, wherein the wiring is formed by dropping a conductive material into the opening. In any one of Claims 1 thru | or 5,
The method for manufacturing a semiconductor integrated circuit, wherein the semiconductor element includes a transistor. In any one of Claims 1 thru | or 6,
The release layer is tungsten, molybdenum, a mixture of tungsten and molybdenum, tungsten oxide, tungsten nitride, tungsten oxynitride, tungsten nitride oxide, molybdenum oxide, molybdenum nitride, molybdenum oxide Nitride, molybdenum nitride oxide, tungsten and molybdenum mixture oxide, tungsten and molybdenum mixture nitride, tungsten and molybdenum mixture oxynitride, tungsten and molybdenum mixture nitride oxide, titanium, tantalum , Niobium, nickel, cobalt, zirconium, zinc, ruthenium, rhodium, palladium, osmium, iridium,
Or a method for manufacturing a semiconductor integrated circuit, which includes silicon. Forming a first element formation layer on the first substrate;
A second element formation layer having a first semiconductor element and a first opening is formed on the second substrate via the first peeling layer,
Separating the second element formation layer from the second substrate, after bonding to the first element formation layer,
Electrically connecting the first element formation layer and the second element formation layer by forming a first through wiring in the first opening;
Forming a third element formation layer having a second semiconductor element and a second opening on the third substrate via the second peeling layer;
After separating the third element formation layer from the third substrate and pasting it on the second element formation layer,
A method for manufacturing a semiconductor integrated circuit, wherein the first through third element formation layers are electrically connected by forming a second through wiring in the second opening. In claim 8,
In the semiconductor integrated circuit, the first through wiring or the second through wiring is formed by dropping a conductive material into the first opening or the second opening. Manufacturing method. Forming a first element formation layer on the first substrate;
A second element formation layer having a first semiconductor element and a first opening is formed on the second substrate via the first peeling layer,
The second element formation layer is separated from the second substrate and bonded onto the first element formation layer,
Forming a third element formation layer having a second semiconductor element and a second opening on the third substrate via the second peeling layer;
The third element formation layer is separated from the third substrate, and is bonded onto the second element formation layer so that the first opening and the second opening substantially coincide with each other . After
A method for manufacturing a semiconductor integrated circuit, wherein the first to third element formation layers are electrically connected by forming through wirings in the first opening and the second opening. In claim 10,
A method for manufacturing a semiconductor integrated circuit, wherein the through wiring is formed by dropping a conductive material into the first opening and the second opening. In any one of Claims 8 thru | or 11,
The first element formation layer includes a semiconductor element including a conductive layer,
The method for manufacturing a semiconductor integrated circuit, wherein the conductive layer is exposed in the first opening. In any one of Claims 8 thru | or 11,
A method for manufacturing a semiconductor integrated circuit, wherein a conductive layer is formed on a side surface of the first opening or the second opening. In any one of Claims 8 to 13,
Each of the first semiconductor element and the second semiconductor element includes a transistor. A method for manufacturing a semiconductor integrated circuit, In any one of Claims 8 to 14,
The first release layer or the second release layer is formed of tungsten, molybdenum, a mixture of tungsten and molybdenum, tungsten oxide, tungsten nitride, tungsten oxynitride, tungsten nitride oxide, or molybdenum oxide. Molybdenum nitride, Molybdenum oxynitride, Molybdenum nitride oxide, Tungsten and molybdenum mixture oxide, Tungsten and molybdenum mixture nitride, Tungsten and molybdenum mixture oxynitride, Tungsten and molybdenum A mixture of oxynitride, titanium, tantalum,
A method for manufacturing a semiconductor integrated circuit, comprising niobium, nickel, cobalt, zirconium, zinc, ruthenium, rhodium, palladium, osmium, iridium, or silicon. In any one of Claims 1 to 15,
The first element formation layer is formed on a release layer formed on the first substrate,
A method for manufacturing a semiconductor integrated circuit, comprising: separating the first element formation layer from the first substrate; and bonding the second element formation layer. In any one of Claims 1 thru | or 16,
The method for manufacturing a semiconductor integrated circuit, wherein the first element formation layer has an opening. In claim 5, claim 9, or claim 11,
The method for manufacturing a semiconductor integrated circuit, wherein the conductive material is a material in which conductive particles are dissolved or dispersed in an organic resin. In claim 18,
The conductive particles are made of one or more metals of Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Zr, and Ba. A method of manufacturing a semiconductor integrated circuit, characterized in that the semiconductor integrated circuit is a grain, a silver halide fine grain, or carbon black.

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