JPH0661418A - Laminated semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a laminated semiconductor integrated circuit which has an excellent heat radiating property when the circuit is formed by piling up LSI chips upon another and can prevent the occurrence of the malfunction or insufficient operation of a circuit element caused by heat. CONSTITUTION:The circuit is a three-dimensional laminated LSI 100 formed by piling up a plurality of LSI chips 208 and 210 with a bonding agent 501 in between and the surfaces of the upper and lower chips 208 and 210 are coated with heat conductive substances 700 and 701.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated LSI, and more particularly to a laminated LSI in which semiconductor LSIs having circuit elements are laminated in multiple layers.

[0002]

2. Description of the Related Art In recent years, the degree of integration of semiconductor integrated circuits has increased fourfold over three years.
In M, the design rule is expected to be 1G integration degree of about 0.15 μm. However, these highly integrated circuits pose technical difficulties in all aspects of design, manufacturing, and inspection. For example, ROM, RAM, ALU, CPU, I
There is a one-chip microcomputer including an I / O controller, etc., but as the number of integrated elements on one chip increases, the time required for designing increases, the manufacturing yield decreases, and the inspection time increases, and at the same time, complete The inspection is difficult.

Therefore, research and development for three-dimensionally bonding and laminating chips and wafers, rather than planar miniaturization, are being actively pursued.

In recent years, most of semiconductor substrates used industrially have a thickness of about 500 μm to 600 μm, and a transistor manufactured by utilizing the surface thereof has a thickness of about several μm. Therefore, the semiconductor substrate to be laminated is thinned, and the thinned semiconductor substrate is laminated to reduce the size of the LSI.

FIGS. 4A to 4H are a schematic plan view and a schematic cross-sectional view showing the steps of LSI lamination generally performed. 4 (a ') and 4 (e') show a semiconductor substrate 202 and a semiconductor substrate 201 in which a transistor circuit is formed on a semiconductor substrate called a wafer through processing steps such as thermal oxidation and ion implantation. FIG. 4 is a schematic plan view, and FIGS. 4A and 4E are schematic cross-sectional views showing the semiconductor substrate 202 and the semiconductor substrate 201.

These semiconductor substrate 201 and semiconductor substrate 2
02 is then advanced to the laminating step. This lamination process is roughly divided into three processes.

The first step is a step of manufacturing a laminated LSI chip and is shown in FIGS. 4 (a) to 4 (e). First, a support substrate 205 for holding an LSI chip is bonded to the front surface side of a semiconductor substrate 202 on which an LSI is formed by using an adhesive such as resin (FIG. 4B). FIG. 5 shows an enlarged cross-sectional view of the semiconductor substrate 202 on which the support substrate 205 is mounted at this time. As shown in FIG. 5, a gate electrode 305 surrounded by a gate insulating film 307 is formed on the semiconductor substrate 202, and an insulating layer 302 is formed on the semiconductor substrate 202 where the gate electrode 305 is not formed.
An insulating film 303 is formed on the insulating layer 302.
An LSI wiring 301 is formed between the gate insulating film 307 and the insulating film 303, and a through hole 300 for connecting the upper and lower LSIs is formed at a predetermined portion of the insulating film 303 by chemical etching or reactive ion etching. It is formed by the method of. Furthermore, these through holes 30
0, the insulating film 303, the LSI wiring 301, and the gate insulating film 307, the insulating film 304 is formed by the CVD method or the like, the adhesive 306 is further applied to the surface of the wafer, and the supporting substrate 205 is bonded onto the semiconductor substrate 202. There is.

Next, the back surface of the semiconductor substrate 202 is polished to make the semiconductor substrate 202 sufficiently thin so that signals can be smoothly transferred between the upper and lower LSIs after lamination, and the semiconductor substrate 202a is thinned. Are formed (FIG. 4C). FIG. 6 shows an enlarged cross section of the internal structure of the thinned semiconductor substrate 202a at this time. As shown in FIG. 6, the thinned semiconductor substrate 2
02a is polished until the line AA 'shown in FIG. 5, that is, the through hole 300a penetrating the through hole 300 is formed, and the thinned semiconductor substrate 202a is formed.

Further, the thinned semiconductor substrate 202a and the supporting substrate 205 are connected to each other by the scribe line 204 described above.
Then, the fabrication of the stacked LSI chip 206 is completed (FIG. 4D).

Next, the second step is a step of adhering stacked LSI chips, which is shown in FIGS. 4 (f) and 4 (g).
First, the LSI chip portion formed on the surface of the semiconductor substrate 201 shown in FIG. 4E and FIG.
The layered LSI chip 206 on which the support substrate 205 manufactured in the above step is mounted is aligned and bonded with an adhesive or the like (FIG. 4F).

Next, the supporting substrate 205 of the stacked LSI chip 206 is removed by dissolving the adhesive 306 by a chemical means such as heat melting, and the upper LSI chip 208 is left on the semiconductor substrate 201 (FIG. 4 (g). )).

By repeating this second step as many times as necessary, the number of stacked LSIs can be selected, and FIG. 7 shows the semiconductor substrate 20 as shown in FIG.
It is an expanded sectional view which shows an internal structure at the time of laminating | stacking 2 pieces of 2, for example. A gate electrode 305 surrounded by a gate insulating film 307 is formed on the semiconductor substrate 201, an insulating layer 302 is formed on the semiconductor substrate 201 on which the gate electrode 305 is not formed, and an insulating film is formed on the insulating layer 302. Thirty
3 is formed, the insulating film 303 and the gate insulating film 30 are formed.
The LSI wiring 500 is formed between the wiring 7 and the wiring 7. The adhesive 501 is applied on the insulating film 303, the gate insulating film 307, and the LSI wiring 500, and the upper LSI chip 208 is formed.
Is installed. The upper LSI chip 208 also has the gate electrode 305 surrounded by the gate insulating film 307, and the insulating layer 302 is formed on the semiconductor substrate 201 on which the gate electrode 305 is not formed. An insulating film 303 is formed on the insulating film 3 and
03 and the gate insulating film 307, the LSI wiring 301 is formed. Through holes 300 are formed at predetermined locations in the upper LSI chip 208, and the adhesive 501 under the through holes 300 is removed through the through holes 300 by using a method such as chemical etching or reactive ion etching. And semiconductor substrate 201
The surface of the LSI wiring 500 is exposed. Upper LSI
An insulating film 304 is formed on the insulating film 303 of the chip 208, the LSI wiring 301, the gate insulating film 307, and the sidewall surface of the through hole 300.

FIG. 8 is a sectional view showing a state in which a through hole electrode 600 is formed in the through hole 300 for electrically connecting the LSI chip 208 and the LSI wiring 500 shown in FIG. The through-hole electrode 600 is formed by using a method such as plating or plating.

Finally, the third step is the LS after the lamination is completed.
This is a step of cutting I into chips, which is shown in FIG. In the second step, after laminating a desired number of LSI chips 208 on the semiconductor substrate 201, the laminated LSI chips 209 are cut along the scribe lines 203 shown in FIG. (H)). After this, the laminated L
The SI chip 209 becomes a product through an assembly process generally called a latter half process.

[0015]

However, in the above-mentioned laminated LSI, a plurality of upper LSI chips 2 are used.
Since the 08s are stacked, there is a problem that it is difficult to dissipate the generated heat as compared with the conventional two-dimensional LSI, and malfunction or malfunction occurs due to the heat generated by the circuit element.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a stacked semiconductor integrated circuit which has good heat dissipation and does not cause an erroneous operation or malfunction of the element due to heat.

[0017]

In order to achieve the above object, a laminated semiconductor integrated circuit according to the present invention is provided with a plurality of LSs.
Stacked LS in which I is three-dimensionalized by being stacked by adhesive means
I, the good thermal conductive material is formed on the surface of each LSI, and the good thermal conductive material has an uneven shape in the stacked semiconductor integrated circuit, The laminated semiconductor integrated circuit is characterized in that the good heat conductive material has a tunnel portion.

[0018]

According to the above-described laminated semiconductor integrated circuit, since the good thermal conductive material is formed on the surface of each laminated LSI, the heat generated in the LSI in the laminated LSI has the good thermal conductivity. Heat is dissipated through the substance, and the heat dissipation characteristics are improved.

Further, when the good thermal conductive material has an uneven shape, the area in contact with the outside air becomes large, and the heat dissipation characteristics are further improved.

When the good thermal conductive material has a tunnel portion, the area in contact with the outside air is further increased, and the heat dissipation characteristics are further improved.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a laminated semiconductor integrated circuit according to the present invention will be described below with reference to the drawings. It should be noted that components having the same functions as those of the conventional example are designated by the same reference numerals.

FIG. 1 is a schematic enlarged sectional view showing a laminated LSI according to an embodiment, which is a laminated LSI. In the figure, 210 indicates the lower LSI chip,
The lower LSI chip 210 is configured as follows. The gate electrode 305 surrounded by the gate insulating film 307 is formed on the semiconductor substrate 201.
The insulating layer 3 is formed on the semiconductor substrate 201 on which 05 is not formed.
02, the insulating film 303 is formed on the insulating layer 302, and the LSI wiring 500 is formed between the insulating film 303 and the gate insulating film 307. Further, a good heat conductive material 701 is formed on the insulating film 303 on which the LSI wiring 500 is not formed. Aluminum, chromium, gold, or the like is used as the material of the good heat conductive material 701. A metal vapor deposition method, a sputtering method, or the like is used as a method of forming the good thermal conductive material 701, and a plating method or the like may be further used when a composite film is formed. Further, the good heat conductive material 701 is formed so as not to adversely affect the electrical characteristics of the LSI (such as a short circuit), and efficiently dissipates the heat generated in the LSI chip 210.

Reference numeral 208 in the drawing denotes an upper LSI chip, and the upper LSI chip 208 is constructed as follows. A gate electrode 305 surrounded by a gate insulating film 307 is formed on the thinned semiconductor substrate 202a, and an insulating layer 302 is formed on the thinned semiconductor substrate 202a on which the gate electrode 305 is not formed. An insulating film 303 is formed on the insulating layer 302. The LSI wiring 3 is provided between the gate insulating film 307 and the insulating film 303.
No. 01 is formed, a through hole connecting the upper and lower LSIs is formed at a predetermined position of the insulating film 303 by a method such as chemical etching or reactive ion etching, and then a through hole 300a is formed by a polishing process. There is. The side wall insulating film 303, the LSI wiring 301, and the gate insulating film 3 of the through hole 300a penetrating therethrough.
An insulating film 304 for protecting the element is formed on the layer 07 by CVD or the like.
Are formed. Then, the upper LSI chip 208 is bonded onto the lower LSI chip 210 coated with the adhesive 501 to form the stacked LSI 100. A through hole electrode 600 is formed in the through hole 300a penetrating therethrough. A good heat conductive material 700 is formed on the entire surface of the upper LSI chip 208 except for the vicinity of the through hole electrode 600.
Are formed. This good thermal conductive material 700 has a lower L
The good thermal conductive material 701 of the SI chip 210 is formed using the same method and material.
0 and 701 are formed after the steps shown in FIGS. 4A ′ and 4E ′.

Stacked type LSI 10 constructed as described above
At 0, the heat generated from the good thermal conductive material 700 in the upper LSI chip 208 and the good thermal conductive material 701 in the lower LSI chip 210 is applied to the upper and lower LSI chips 208 and 210, respectively. It can radiate heat to the outside. Therefore, the heat dissipation characteristics are improved,
It is possible to prevent erroneous operation and malfunction of the element.

FIG. 2 is a schematic enlarged sectional view showing another embodiment of the laminated LSI according to the present invention. Reference numeral 208 in the drawing denotes an upper LSI chip, and the upper LSI chip 208
Has the same configuration as that of the above-described embodiment, and detailed description of this portion will be omitted here. Reference numeral 201 in the figure denotes a semiconductor substrate. A gate insulating film 307 surrounding a gate electrode 305 is formed on the semiconductor substrate 201, and an insulating layer 302 is formed on the semiconductor substrate 201 on which the gate insulating film 307 is not formed. Has been formed,
An insulating film 303 is formed on the insulating layer 302. The LSI wiring 5 is provided between the insulating film 303 and the gate insulating film 307.
00 is formed, and the good thermal conductive material 702 is formed on the insulating film 303 on which the LSI wiring 500 is not formed. The material of the good thermal conductive material 702 is similar to that in the above-described embodiment. Aluminum, chrome, gold, etc. are used. An adhesive agent 501 is applied to a portion of the lower LSI chip 210 where the upper LSI chip 208 is mounted,
The lower LSI chip 210 and the upper LSI chip 208 are bonded. Although the surface of the good thermal conductive material 702 where the upper LSI chip 208 is mounted is formed in a planar shape, a large number of good thermal conductive material 702 surfaces that are not covered with the upper LSI chip 208 and are exposed to the outside air. Convex portion 702
a is formed. A selective plating method or the like is used for forming the good heat conductive material 702, and the good heat conductive material 702 is formed in the same manner as in the above-described embodiment.
It is formed after the step shown in (e ′).

Stacked type LSI 101 configured as described above
In this case, since a large number of convex portions 702a are formed on the surface of the good thermal conductive material 702 that comes into contact with the outside air, the area in contact with the outside air can be increased. Therefore, the lower LSI
The heat dissipation characteristics of the heat generated in the chip 210 can be further improved, and malfunction or malfunction of the element due to the generated heat can be prevented.

FIG. 3 is a schematic enlarged sectional view showing still another embodiment of the laminated LSI according to the present invention. 20 in the figure
Reference numeral 8 denotes an upper LSI chip, and the upper LSI chip 208 has the same configuration as that of the above-described embodiment, and a detailed description of this portion will be omitted here. Reference numeral 201 in the drawing denotes a semiconductor substrate, and the gate insulating film 3 surrounding the gate electrode 305 on the semiconductor substrate 201.
07, the insulating layer 302 is formed on the lower semiconductor substrate 201 on which the gate insulating film 307 is not formed, and the insulating film 303 is formed on the insulating layer 302. The LSI wiring 500 is formed between the insulating film 303 and the gate insulating film 307.
The good thermal conductive material 7 is formed on the insulating film 303 on which the film is not formed.
No. 03 is formed, and as the material of the good thermal conductive material 703, aluminum, chromium, gold or the like is used as in the case of the above-mentioned embodiment. Adhesive 50 is applied to the lower LSI chip 210 where the upper LSI chip 208 is mounted.
1 is applied and the lower LSI chip 210 and the upper LSI chip 208 are adhered to each other to form the laminated LSI 102. Further, the surface of the good thermal conductive material 703 at the place where the upper LSI 208 is mounted is formed in a flat shape,
A large number of tunnel portions 703a are formed on the surface of the good thermal conductive material 703 which is not covered with the upper LSI chip 208 and is exposed to the outside air. The inside of the tunnel portion 703a is a cavity that contacts the outside air. Also, this good heat conductive material 7
A selective plating method is used to form 03, and the tunnel portion 703a is etched by using an etching solution.
Are formed.

The laminated LSI 102 thus configured
In this case, since a large number of tunnel portions 703a are formed on the surface of the good thermal conductive material 703 that comes into contact with the outside air, the area in contact with the outside air can be increased. Therefore, it is possible to further improve the heat dissipation characteristic of the heat generated in the lower LSI chip 210, and prevent malfunction or malfunction of the element due to the generated heat.

In the above embodiment, the case of application to a MOS-LSI has been shown, but the present invention is not limited to this and may be applied to a bipolar LSI, a compound semiconductor, or an individual semiconductor such as an LED. Moreover, in FIG.
Although I is laminated after being cut into chips, the present invention is not limited to this, and the wafer may be laminated as it is.

[0030]

As described above in detail, in the stacked semiconductor integrated circuit according to the present invention, since the good thermal conductive material is formed on the surface of each stacked LSI, each of the stacked LSIs The heat generated in the LSI is efficiently radiated through the good heat conductive material, and the heat radiation characteristics can be improved.

Further, in the case where the good heat conductive material has an uneven shape, the area in contact with the outside air becomes large, and it becomes possible to further improve the heat dissipation characteristics.

Further, when the good thermal conductive material has a tunnel portion, the area in contact with the outside air is further increased, so that the heat radiation characteristics can be further improved.

[Brief description of drawings]

FIG. 1 is an enlarged sectional view schematically showing an embodiment of a laminated LSI according to the present invention.

FIG. 2 is an enlarged sectional view schematically showing another embodiment of the laminated LSI according to the present invention.

FIG. 3 is an enlarged sectional view schematically showing still another embodiment of the laminated LSI according to the present invention.

4A to 4H are a plan view and a cross-sectional view showing a manufacturing process of a general laminated LSI.

FIG. 5 is an upper LSI on which a supporting substrate according to a conventional example is mounted.
It is an expanded sectional view showing.

FIG. 6 is an upper LSI on which a supporting substrate according to a conventional example is mounted.
FIG. 5 is an enlarged cross-sectional view showing the structure after backside polishing of FIG.

FIG. 7 is an enlarged cross-sectional view showing a stacked LSI in a conventional example.

FIG. 8 is an enlarged cross-sectional view showing a state after a through-hole electrode is formed on the stacked LSI in the conventional example.

[Explanation of symbols]

 100, 101, 102 Stacked LSI 208 Upper LSI chip 210 Lower LSI chip 501 Adhesive (adhesive means) 700, 701, 702, 703 Good thermal conductive material 702a Convex portion (uneven shape) 703a Tunnel portion

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideyuki Tsuji 22-22 Nagaike-cho, Abeno-ku, Osaka City, Osaka Prefecture

Claims (3)

[Claims] 1. A multi-layered LSI in which a plurality of semiconductor integrated circuits (hereinafter referred to as "LSIs") are laminated by an adhesive means to form a three-dimensional structure, and a good thermal conductive material is formed on the surface of each LSI. A laminated LSI characterized by the above. 2. The laminated LSI according to claim 1, wherein the good thermal conductive material has an uneven shape. 3. The laminated LS according to claim 1, wherein the good heat conductive material has a tunnel portion.
I.