JP2008124448A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an element structure in which defects are not easily generated, and to provide a semiconductor device having the same. <P>SOLUTION: An element has a structure in which a layer containing an organic compound is interposed between a pair of electrode layers of a first electrode layer and a second electrode layer. At least one of the pair of the electrode layers has a Young's modulus of ≤7.5×10<SP>10</SP>N/m<SP>2</SP>. A layer containing an organic compound is formed using an organic compound appropriate to usage of an element to be formed, and a memory element, a light-emitting element, a piezoelectric element, or an organic transistor element is formed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device having an element having a layer containing an organic compound.

  2. Description of the Related Art In recent years, attention has been focused on an individual recognition technique in which an ID (individual identification number) is given to an individual object to clarify information such as a history of the object and to be useful for production and management. Among them, development of semiconductor devices capable of transmitting and receiving data without contact is underway. Among such semiconductor devices, RFID (Radio Frequency Identification) (ID tag, IC tag, IC chip, RF (Radio Frequency) tag, wireless tag, electronic tag, also called wireless chip) and the like are especially used in companies and markets. It has begun to be introduced.

  Many of these semiconductor devices include a circuit using a semiconductor substrate such as silicon (Si) (hereinafter, also referred to as an IC (Intergrated Circuit) chip) and an antenna, and the IC chip is a memory circuit (hereinafter referred to as a memory). And a control circuit.

In the manufacturing process of such a semiconductor device, in order to reduce the manufacturing cost, a process of transferring an element, a peripheral circuit, or the like manufactured on a glass substrate to an inexpensive substrate such as a plastic substrate is performed (for example, a patent) Reference 1).
Japanese Patent Laid-Open No. 11-097357

  By transferring an element manufactured over a glass substrate onto a plastic substrate, an ultrathin semiconductor device that can be bent can be provided. However, in the process of transposing the element or the like, there is a problem that the element is destroyed due to the element not being peeled off from the substrate or the substrate or the element being bent during the process.

  For example, an element in which a layer containing an organic compound is provided between a pair of electrode layers can be applied to a variety of elements such as a memory element and a light-emitting element. If the material constituting the electrode layer of these elements is selected in consideration of the electrical characteristics such as work function and electrical resistance depending on the required element characteristics, etc., the range of selection of the material constituting the electrode layer is likely to be narrow, and the element May be destroyed when transposing. FIG. 21 illustrates an example in which an element is destroyed when a memory element having a layer containing an organic compound is transferred between a pair of electrode layers.

  FIG. 21A illustrates a structure in which the element 3020 is provided over the first substrate 3000 and the second substrate 3040 is provided over the element 3020.

  The first substrate 3000 is a substrate on which the element 3020 is formed, and is a substrate from which the element 3020 is peeled off. The element 3020 includes a layer 3024 containing an organic compound between the first electrode layer 3022 and the second electrode layer 3026. In the element 3020, the first electrode layer 3022 is in contact with the first substrate 3000, and the second electrode layer 3026 is in contact with the second substrate 3040. The second substrate 3040 is a substrate to which the element 3020 formed on the first substrate 3000 is transferred, that is, a substrate from which the element 3020 is peeled from the first substrate 3000. The second substrate 3040 is a flexible substrate.

  The element 3020 is transferred (peeled) from the first substrate 3000 to the second substrate 3040. The element 3020 receives a force in the direction of the first substrate 3000 or the second substrate 3040 when the element 3020 is transferred, and the element 3020 is bent by the received force. For example, in the case where the second substrate 3040 is a flexible substrate, the second substrate 3040 is bent by receiving a force during transfer. At this time, the element 3020 needs to be bent as the second substrate 3040 is bent. However, since the electrode layer constituting the element 3020 is made of a conductive material such as metal, it is generally hard and difficult to bend. Therefore, the element 3020 cannot cope with the bending of the second substrate 3040, and the element may be destroyed.

  In addition, after the element 3020 is transferred from the first substrate 3000 to the second substrate 3040, the third substrate (a flexible substrate) is bonded to the surface from which the first substrate 3000 is peeled off. The second substrate 3040 or the third substrate may be bent. Similarly, in this case, since the electrode layer constituting the element 3020 is made of a conductive material such as metal and is hard and not easily bent, the element may be destroyed.

  FIG. 21B shows an example in which the element breaks during the transposition process. For example, a state where peeling occurs at the interface between the second electrode layer 3026 and the layer 3024 containing an organic compound or a crack occurs in the second electrode layer 3026 is shown. Note that the defects illustrated in FIG. 21B are merely examples, and various elements may be destroyed. In addition, the destruction of the element includes a case where electrical characteristics, reliability, and the like are deteriorated even if the element is not damaged in appearance. In this manner, when an element is destroyed during the transposition process, a yield is reduced in manufacturing a semiconductor device having the element. In addition, if the element included in the completed semiconductor device cannot cope with a behavior such as bending, the reliability is adversely affected.

  In view of such problems, it is an object of the present invention to provide an element structure in which defects are less likely to occur and a semiconductor device having the element. It is another object of the present invention to provide a highly reliable semiconductor device and a manufacturing method thereof. Furthermore, another object of the present invention is to provide a technique capable of manufacturing a semiconductor device having elements with high yield.

  The present invention is characterized in that an element which is less likely to cause a defect and a semiconductor device including the element are manufactured. In particular, it is characterized in that an element capable of performing a transposition step satisfactorily and a semiconductor device including the element are manufactured. In this specification, transposition means that an element formed on the first substrate is transferred to the second substrate. During the transposition, the element is peeled from the first substrate. In addition, the fact that the transposition process can be performed satisfactorily means that the transposition process is performed without causing defects such as appearance damage and characteristic deterioration of the element. Hereinafter, the fact that the transposition process can be performed satisfactorily is also expressed as good transposition characteristics.

The element according to the present invention has an element structure having a layer containing an organic compound between a pair of electrode layers composed of a first electrode layer and a second electrode layer. Of the pair of electrode layers, at least one of the electrode layers has a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less. For the layer containing an organic compound, an organic compound corresponding to the application of the element to be manufactured is used.

After the element having the above structure is formed over the first substrate, the element is transferred to the second substrate, so that a semiconductor device having the element is manufactured. In the present invention, the element has an Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less on the side that is bonded to the second substrate without contacting the first substrate.

One embodiment of the present invention is a semiconductor device including a flexible substrate and a memory element over the flexible substrate. The memory element includes a layer containing an organic compound between the first electrode layer and the second electrode layer, and the second electrode layer has a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less. It is characterized by that.

One embodiment of the present invention is a semiconductor device including a flexible substrate and a light-emitting element over the flexible substrate. The light-emitting element includes a layer containing an organic compound between the first electrode layer and the second electrode layer, and the second electrode layer has a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less. It is characterized by that.

  In the above structure, the second electrode layer preferably has a thickness of 10 nm to 200 nm. The second electrode layer is made of indium (In), barium (Ba), lead (Pb), calcium (Ca), bismuth (Bi), magnesium (Mg), tin (Sn), or aluminum (Al). It is preferable that at least one of them is included.

  In addition to a memory element and a light-emitting element, an element having a layer containing an organic compound can be a piezoelectric element, an organic transistor element, a capacitor element, a resistance element, or a photoelectric conversion element.

Another embodiment of the present invention is to form a separation layer over a first substrate, a first electrode layer over the separation layer, a layer containing an organic compound over the first electrode layer, and a layer containing an organic compound. An element layer having a second electrode layer having a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less is formed thereon, and the element layer is fixed to the second substrate. The substrate is peeled off.

  In the above structure, the second electrode layer is preferably formed with a thickness of 10 nm to 200 nm.

  In addition, after peeling the first substrate from the element layer, a flexible third substrate can be fixed to the element layer.

  The second substrate is preferably a flexible substrate.

  As the second electrode layer, indium (In), barium (Ba), lead (Pb), calcium (Ca), bismuth (Bi), magnesium (Mg), tin (Sn), or aluminum (Al) It is preferable to form using a material containing at least one of them.

  The element layer is preferably formed with a memory element, a light emitting element, a piezoelectric element, an organic transistor element, a capacitor element, a resistance element, or a photoelectric conversion element. Further, a transistor may be formed in the element layer.

  According to the present invention, it is possible to provide an element that is strong in bending or the like and hardly causes defects. Therefore, a semiconductor device including the element can be manufactured with high yield.

  Further, according to the present invention, a semiconductor device provided over a flexible substrate can be provided. By applying the present invention, element defects can be prevented even when a semiconductor device is provided over a flexible substrate, so that the reliability of the semiconductor device can be improved.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals may be used in common in different drawings.

(Embodiment 1)
The present invention relates to an element structure such as a memory element, a light emitting element, a piezoelectric element, an organic transistor element, a capacitor element, a resistance element, or a photoelectric conversion element, and a semiconductor device including the element. The basic structure of an element applied to the present invention includes a layer containing an organic compound (also referred to as an organic compound layer) between a pair of electrode layers. In the element according to the present invention, the Young's modulus of at least one of the electrode layers is 7.5 × 10 ¹⁰ N / m ² or less. More preferably, the Young's modulus of aluminum is 7.06 × 10 ¹⁰ N / m ² or less. Note that the Young's modulus shown in this specification is the Young's modulus at room temperature.

A conductive material is used for the pair of electrode layers. Both of the pair of electrode layers may have a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less, or only one of them may have a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less. Therefore, one electrode layer may be selected in consideration of Young's modulus, and the other electrode layer may be selected in consideration of electric characteristics such as work function and electric resistance. For the layer containing an organic compound, an organic compound corresponding to the application of the element to be manufactured is used. Hereinafter, a specific element structure will be described.

  FIG. 1 shows an example of a memory element according to the present invention. A memory element 100 illustrated in FIG. 1A has a structure in which a first electrode layer 102, a layer 104 containing an organic compound, and a second electrode layer 106 are sequentially stacked.

  The first electrode layer 102 is formed using a conductive material. For example, gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), copper (Cu ), Palladium (Pd), carbon (C), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), or an alloy material or compound material containing the element can be used. . As the compound containing the element, a nitrogen compound, an oxygen compound, a carbon compound, a halogen compound, or the like can be used. For example, titanium nitride, tungsten nitride, molybdenum nitride, or the like can be used. In addition, alkali metals such as lithium (Li) and cesium (Cs), and alkaline earth metals such as magnesium (Mg), calcium (Ca) and strontium (Sr), rare earths such as europium (Er) and ytterbium (Yb) A metal and an alloy (MgAg, AlLi, etc.) containing any of these can be used. Further, a light-transmitting oxide conductive material such as indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), and zinc oxide to which gallium is added (GZO), indium tin oxide containing silicon oxide ( Hereinafter, a conductive material such as indium oxide containing 2 wt% to 20 wt% of zinc oxide (ZnO) can be used. The first electrode layer 102 can be used alone or in combination of two or more of these materials.

  Note that the thickness of the first electrode layer 102 is not particularly limited, but is preferably about 20 nm to 200 nm, and more preferably about 50 nm to 100 nm.

The second electrode layer 106 is formed using a conductive material so that the Young's modulus of the second electrode layer 106 in the completed memory element is 7.5 × 10 ¹⁰ N / m ² or less. For example, Young's modulus formed by using a 7.5 × ^{10 10} N / ^{m 2} or less of the metal element, or Young's modulus 7.5 × ^{10 10} N / ^{m 2} or less of an alloy material or a compound material. Note that in the case of using an alloy material or a compound material, it is preferable to include a metal element having a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less. The second electrode layer 106 is preferably formed using a material having a lower Young's modulus. The second electrode layer 106 is more easily deformed by reducing the Young's modulus.

  For example, the second electrode layer 106 includes indium (In), barium (Ba), lead (Pb), calcium (Ca), bismuth (Bi), magnesium (Mg), tin (Sn), aluminum (Al), and the like. Or an alloy material or compound material containing the metal element can be used. As an alloy material containing the element, an indium-tin (In-Sn) alloy, an aluminum-magnesium (Al-Mg) alloy, a magnesium-silver (Mg-Ag) alloy, or the like can be used. As the compound containing the element, a nitrogen compound, an oxygen compound, a carbon compound, a halogen compound, or the like can be used. The second electrode layer 106 can be used alone or in combination of two or more of these materials.

  Note that the thickness of the second electrode layer 106 is not particularly limited, but is preferably about 10 nm to 200 nm, and more preferably about 10 nm to 100 nm. The second electrode layer 106 is more easily deformed by being relatively thin with a thickness of about 10 nm to 100 nm.

  The first electrode layer 102 or the second electrode layer 106 is formed using the above-described material with a single-layer structure or a stacked structure by an evaporation method, a sputtering method, a printing method, or a droplet discharge method.

  The layer 104 including an organic compound is formed with a single-layer structure or a stacked structure using an organic compound whose conductivity changes or an organic compound whose shape changes by an optical action or an electrical action. The memory element having the layer 104 containing the organic compound can store two values corresponding to the “initial state” and the “state after change” before and after the change in conductivity or before and after the change in shape. As the layer 104 containing such an organic compound, an organic compound having a hole-transport property, an organic compound having an electron-transport property, or a polymer organic compound can be used.

As an organic compound having a hole-transport property, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: NPB), 4,4′-bis [N- ( 3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD), 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: TDATA), 4 , 4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA), 4,4′-bis (N- (4- (N, N-di-m-tolylamino) phenyl) -N-phenylamino) biphenyl (abbreviation: DNTPD) and other aromatic amine-based compounds (that is, having a benzene ring-nitrogen bond) can be used. In addition, phthalocyanine compounds such as phthalocyanine (abbreviation: H ₂ Pc), copper phthalocyanine (abbreviation: CuPc), and vanadyl phthalocyanine (abbreviation: VOPc) can also be used. The compounds described here mainly have a hole mobility of 10 ⁻⁶ cm ² / Vs or higher.

As an organic compound having an electron transporting property, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo) [H] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), and other metal complexes having a quinoline skeleton or a benzoquinoline skeleton Can be used. In addition, bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) ₂ ) ) And other metal complexes having a thiazole ligand can be used. Besides metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (p -Tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- (4- Biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2,4- Triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), or the like can be used. The compounds described here mainly have an electron mobility of 10 ⁻⁶ cm ² / Vs or higher.

  The layer 104 containing an organic compound is formed with a single layer structure or a stacked structure by an evaporation method, a sputtering method, a droplet discharge method, or a spin coating method. In the case where the layer 104 including an organic compound is formed using a plurality of materials, the layers can be formed by forming each material at the same time. For example, co-evaporation method by resistance heating evaporation, co-evaporation method by electron beam evaporation, co-evaporation method by resistance heating evaporation and electron beam evaporation, film formation by resistance heating evaporation and sputtering, film formation by electron beam evaporation and sputtering, etc. It can be formed by combining the same type and different types of methods.

  Note that the thickness of the layer 104 containing an organic compound is set such that conductivity or shape can be changed by an optical action or an electrical action. The thickness of the layer 104 containing a specific organic compound is preferably about 5 nm to 100 nm. More preferably, the thickness is about 10 nm to 60 nm, 5 nm to 20 nm, or 5 nm to 10 nm.

The present invention is characterized in that the Young's modulus of at least one of the pair of electrode layers (in this embodiment, the second electrode layer 106) is 7.5 × 10 ¹⁰ N / m ² or less. It is said. The Young's modulus is a kind of elastic modulus, and the Young's modulus (E) is represented by the following mathematical formula (1).

  In the above formula (1), when the same stress (T) works, the smaller the Young's modulus, the larger the strain (ε) of the substance. That is, the smaller the Young's modulus, the easier the material is deformed.

In this embodiment mode, the second electrode layer 106 has a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less, compared with metals such as silver (Ag), zinc (Zn), and copper (Cu). Young's modulus is small. Therefore, the second electrode layer 106 is easily deformed and is easily deformed along with a behavior such as bending. In other words, the second electrode layer 106 is easily tuned to a behavior such as bending. Therefore, a defect (destruction of the element) due to a behavior such as bending can be prevented, and the reliability of the memory element is improved.

  In addition, it is preferable to reduce the thickness of the second electrode layer 106 because the second electrode layer 106 can be easily tuned by a behavior such as bending. Therefore, it is preferable that the second electrode layer 106 has a thickness that can function as an electrode layer and is thinner. Specifically, 10 nm to 200 nm, preferably 10 nm to 100 nm is desirable.

  Note that the structure of the memory element according to the present invention is not particularly limited. For example, as in the memory element 110 illustrated in FIG. 1B, a structure in which the layer 108 is provided between the first electrode layer 102 and the layer 104 containing an organic compound may be employed. The layer 108 can be formed as a semiconductor layer, an insulating layer, or a metal oxide layer using a semiconductor material, an insulating material, a metal oxide material, or the like. The layer 108 may be formed of a plurality of layers by combining the above materials. Further, a semiconductor layer, an insulating layer, or a metal oxide layer may be provided between the second electrode layer 106 and the layer 104 containing an organic compound. The thickness of the layer 108 has two values corresponding to an “initial state” and a “post-change state” before and after the change in conductivity of the layer 104 including the organic compound or before and after the change in shape of the layer 104 including the organic compound. The film thickness is set so as not to prevent memory.

  By providing the layer 108 as shown in FIG. 1B, the thickness between the first electrode layer 102 and the second electrode layer 106 can be increased, and an initial failure due to a short circuit between the electrodes can be prevented. can do. In addition, variation in characteristics such as a writing voltage of the memory element can be reduced.

  Next, FIGS. 2 and 3 show examples of the light emitting element, the piezoelectric element, and the organic transistor element according to the present invention.

  A light-emitting element 220 illustrated in FIG. 2 includes a first electrode layer 226, an electron injection layer 236, an electron transport layer 234, a light-emitting layer 224, a hole transport layer 232, a hole injection layer 230, a second The electrode layers 222 are sequentially stacked. Layers provided between the first electrode layer 226 and the second electrode layer 222 (electron injection layer 236, electron transport layer 234, light-emitting layer 224, hole transport layer 232, hole injection layer 230) are organic compounds. It is a layer formed using.

  One of the first electrode layer 226 and the second electrode layer 222 serves as an anode, and the other serves as a cathode. Note that the anode refers to an electrode layer that injects holes into the light emitting layer, and the cathode refers to an electrode layer that injects electrons into the light emitting layer. In this embodiment mode, the first electrode layer 226 is a cathode and the second electrode layer 222 is an anode.

  The first electrode layer 226 is formed using a conductive material. For example, elements belonging to Group 1 or Group 2 of the periodic table, alkali metals such as lithium (Li) and cesium (Cs), alkaline earth metals such as magnesium (Mg), calcium (Ca), and strontium (Sr), Alternatively, an alloy material containing these elements (Mg—Ag, Al—Li), a rare earth metal such as europium (Eu), ytterbium (Yb), or an alloy material containing these elements can be used. Other elements such as gold (Au), platinum (Pt), silver (Ag), copper (Cu), aluminum (Al), or alloy materials or compound materials containing such elements, indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), translucent oxide conductive material such as zinc oxide added with gallium (GZO), indium tin oxide containing silicon oxide (ITSO), 2 wt% to 20 wt% zinc oxide An oxide conductive material such as indium oxide containing (ZnO) can be used. The first electrode layer 226 can be used alone or in combination of two or more of these materials.

  Note that there is no particular limitation on the thickness of the first electrode layer 226, but it is preferably about 100 nm to 1000 nm, and more preferably about 200 nm to 500 nm.

The second electrode layer 222 is formed using a conductive material such that the Young's modulus of the second electrode layer 222 is 7.5 × 10 ¹⁰ N / m ² or less. For example, an element having a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less, an alloy material, or a compound material is used. In addition, when using an alloy material or a compound material, it is preferable to include an element having a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less. The second electrode layer 222 is preferably formed using a material having a lower Young's modulus. For example, the second electrode layer 222 includes indium (In), barium (Ba), lead (Pb), calcium (Ca), bismuth (Bi), magnesium (Mg), tin (Sn), aluminum (Al), and the like. Or an alloy material or compound material containing the metal element can be used. As an alloy material containing the metal element, an indium-tin (In-Sn) alloy, an aluminum-magnesium (Al-Mg) alloy, a magnesium-silver (Mg-Ag) alloy, or the like can be used. As the compound containing the metal element, a nitrogen compound, an oxygen compound, a carbon compound, a halogen compound, or the like can be used. For example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), indium oxide containing 2 wt% to 20 wt% zinc oxide (ZnO), or the like can be used. The second electrode layer 222 can be used alone or in combination of two or more of these materials.

  Note that the thickness of the second electrode layer 222 is not particularly limited, but is preferably about 10 nm to 200 nm, and more preferably about 10 nm to 100 nm.

  The first electrode layer 226 or the second electrode layer 222 is formed with a single-layer structure or a stacked structure by an evaporation method, a sputtering method, a printing method, or a droplet discharge method.

  Note that in order to extract the emitted light to the outside, one or both of the first electrode layer 226 and the second electrode layer 222 may be formed using a light-transmitting oxide conductive material such as indium tin oxide, or Silver, aluminum, or the like is preferably formed to have a thickness of several nanometers to several tens of nanometers so that visible light can be transmitted.

The electron injection layer 236 is a layer having a function of assisting injection of electrons from the first electrode layer 226 to the electron transport layer 234. The electron injection layer 236 has an electron affinity higher than that of a material used to form the electron transport layer 234 among materials that can be used to form the electron transport layer 234 such as BPhen, BCP, p-EtTAZ, TAZ, and BzOs. It can be formed by selecting and using a substance having a relatively large value. By forming the electron injection layer 236 in this manner, the difference in electron affinity between the first electrode layer 226 and the electron transport layer 234 is alleviated and electrons are easily injected. The electron injection layer 236 is formed of an alkali metal such as Li or Cs, an oxide of an alkali metal such as lithium oxide, potassium oxide, or sodium oxide, or an alkaline earth metal such as calcium oxide or magnesium oxide. Oxides, fluorides of alkali metals such as lithium fluoride and cesium fluoride, fluorides of alkaline earth metals such as calcium fluoride, or inorganic substances such as alkaline earth metals such as Mg and Ca Good. Further, the electron injection layer 236 may include an organic compound such as BPhen, BCP, p-EtTAZ, TAZ, and BzOs, an alkali metal fluoride such as LiF, or an alkaline earth metal such as CaF _2. It may be composed of an inorganic compound such as fluoride. As described above, the electron injection layer 236 is provided as a 1 nm to 2 nm thin film using an inorganic compound such as an alkali metal fluoride such as LiF or an alkaline earth metal fluoride such as CaF ₂ . When the energy band is bent or a tunnel current flows through the electron injection layer 236, injection of electrons from the first electrode layer 226 to the electron transport layer 234 is facilitated. Note that the present invention is not particularly limited, and the electron injection layer 236 is not necessarily provided.

The electron transport layer 234 is a layer having a function of transporting electrons injected from the first electrode layer 226 to the light emitting layer 224. Thus, by providing the electron transport layer 234, the distance between the first electrode layer 226 and the light-emitting layer 224 can be increased. As a result, light emission can be prevented from disappearing due to the metal contained in the first electrode layer 226 and the like. The electron transport layer 234 is preferably formed using an electron transporting substance, and particularly preferably formed using a substance having an electron mobility of 1 × 10 ⁻⁶ cm ² / Vs or higher. Note that the electron transporting substance has higher electron mobility than holes, and the ratio of the electron mobility to the hole mobility (= electron mobility / hole mobility) is preferably from 100. Also refers to a large substance. Specific examples of a substance that can be used for forming the electron-transport layer 234 include tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq _3). ), Bis (10-hydroxybenzo [h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), bis [2- In addition to metal complexes such as (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) ₂ ) 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (approximately) Name: PBD), 1,3-bis [5- (p-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4- tert-butylphenyl) -4-phenyl-5- (4-biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2,4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), 4,4-bis (5-methylbenzoxa) Sol-2-yl) stilbene (abbreviation: BzOs) or the like can be used. In addition, the electron transport layer 234 may have a single layer structure or a combination of two or more of these materials. Note that the present invention is not particularly limited, and the electron transport layer 234 is not necessarily provided.

  The light emitting layer 224 is a layer having a light emitting function, and includes a light emitting material made of an organic compound. Moreover, the inorganic compound may be included. The organic compound contained in the light-emitting layer 224 is not particularly limited as long as it is a light-emitting organic compound, and various low-molecular organic compounds and high-molecular organic compounds can be used. As the light-emitting organic compound, either a fluorescent light-emitting material or a phosphorescent light-emitting material can be used. The light-emitting layer 224 may be a layer including only a light-emitting organic compound, or may have a structure in which a light-emitting organic compound is dispersed in a host material having an energy gap larger than that of the organic compound. Note that in the case where the light-emitting layer 224 is a layer in which a plurality of compounds are mixed, such as a layer including a light-emitting material formed using an organic compound and a host material, the light-emitting layer 224 can be formed using a co-evaporation method. Here, co-evaporation refers to a vapor deposition method in which raw materials are vaporized from a plurality of vapor deposition sources provided in one processing chamber, the vaporized raw materials are mixed in a gas phase state, and deposited on an object to be processed.

The hole transport layer 232 is a layer having a function of transporting holes injected from the second electrode layer 222 side to the light emitting layer 224. In this manner, by providing the hole transport layer 232, the distance between the second electrode layer 222 and the light-emitting layer 224 can be increased. As a result, light emission can be prevented from disappearing due to the metal contained in the second electrode layer 222 and the like. The hole transporting layer 232 is preferably formed using a hole transporting substance, and particularly preferably formed using a substance having a hole mobility of 1 × 10 ⁻⁶ cm ² / Vs or higher. Note that the hole-transporting substance has higher hole mobility than electrons, and the ratio of the hole mobility to the electron mobility (= hole mobility / electron mobility) is preferably 100. Larger than the substance. Specific examples of a substance that can be used for forming the hole-transport layer 232 include 4,4′-bis [N- (1-naphthyl) -N-phenylamino] biphenyl (abbreviation: NPB), 4, 4′-bis [N- (3-methylphenyl) -N-phenylamino] biphenyl (abbreviation: TPD), 4,4 ′, 4 ″ -tris (N, N-diphenylamino) triphenylamine (abbreviation: TDATA), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenylamino] triphenylamine (abbreviation: MTDATA), 4,4′-bis {N- [4- ( N, N-di-m-tolylamino) phenyl] -N-phenylamino} biphenyl (abbreviation: DNTPD), 1,3,5-tris [N, N-di (m-tolyl) amino] benzene (abbreviation: m -MTDAB), 4,4 ', 4''- Squirrel (N- carbazolyl) triphenylamine (abbreviation: TCTA), phthalocyanine _{(abbreviation:} H 2 Pc), copper phthalocyanine (abbreviation: CuPc), or vanadyl phthalocyanine (abbreviation: VOPc), 4,4'-bis [N- ( 4-biphenylyl) -N-phenylamino] biphenyl (abbreviation: BBPB) and the like. Note that the hole-transport layer 232 may have a single-layer structure or a stacked structure in which two or more of these materials are combined. Note that the present invention is not particularly limited, and the hole-transport layer 232 is not necessarily provided.

The hole injection layer 230 is a layer having a function of assisting injection of holes from the second electrode layer 222 to the hole transport layer 232. By providing the hole injection layer 230, the difference in ionization potential between the second electrode layer 222 and the hole transport layer 232 is reduced, and holes are easily injected. The hole injection layer 230 has a lower ionization potential than the material forming the hole transport layer 232 and has a higher ionization potential than the material forming the second electrode layer 222, or the hole transport layer. It is preferable to use a substance whose energy band bends when it is provided as a thin film having a thickness of 1 nm to 2 nm between 232 and the second electrode layer 222. Specific examples of a substance that can be used to form the hole-injecting layer 230 include phthalocyanine-based compounds such as phthalocyanine (abbreviation: H ₂ Pc) and copper phthalocyanine (CuPC), or poly (ethylenedioxythiophene) / Examples thereof include a polymer such as a poly (styrenesulfonic acid) aqueous solution (PEDOT / PSS). That is, the hole injection layer 230 is formed by selecting a substance from among the hole transporting materials so that the ionization potential in the hole injection layer 230 is relatively smaller than the ionization potential in the hole transport layer 232. can do. Note that the present invention is not particularly limited, and the hole injection layer 230 is not necessarily provided.

  Note that a hole generation layer may be provided instead of the hole injection layer 230, or an electron generation layer may be provided instead of the electron injection layer 236.

  Here, the hole generation layer is a layer that generates holes. The hole generating layer can be formed by mixing at least one substance selected from the hole transporting substances and a substance that exhibits an electron accepting property with respect to the hole transporting substance. Here, as the hole transporting substance, a substance similar to the substance that can be used for forming the hole transporting layer 232 can be used. As the substance exhibiting electron accepting properties, it is preferable to use a metal oxide such as molybdenum oxide, vanadium oxide, ruthenium oxide, or rhenium oxide.

  The electron generating layer is a layer that generates electrons. The electron generating layer can be formed by mixing at least one substance selected from electron transporting substances and a substance exhibiting an electron donating property with respect to the electron transporting substance. Here, as the electron transporting substance, a substance similar to the substance that can be used to form the electron transporting layer 234 can be used. Moreover, as the substance exhibiting electron donating property, a substance selected from alkali metals and alkaline earth metals, specifically, lithium (Li), calcium (Ca), sodium (Na), potassium (K), Magnesium (Mg) or the like can be used.

  The electron injection layer 236, the electron transport layer 234, the light emitting layer 224, the hole transport layer 232, and the hole injection layer 230 may be formed by an evaporation method, a droplet discharge method, or a coating method, respectively. The first electrode layer 226 or the second electrode layer 222 may be formed by a sputtering method, an evaporation method, or the like.

  In this embodiment mode, the light-emitting element 220 only needs to include at least the light-emitting layer 224 between the pair of electrode layers (the first electrode layer 226 and the second electrode layer 222), and has other functions ( The electron injection layer 236, the electron transport layer 234, the hole transport layer 232, the hole injection layer 230, and the like may be provided as appropriate.

  Alternatively, the first electrode layer 226 may be an anode and the second electrode layer 222 may be a cathode. In that case, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer are sequentially stacked from the first electrode layer 226 side.

The second electrode layer 222 included in the light-emitting element 220 has a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less, compared with metals such as silver (Ag), zinc (Zn), and copper (Cu). Young's modulus is small. Therefore, the second electrode layer 222 can be relatively easily deformed and can be easily tuned to the behavior of the element such as bending. Therefore, a defect due to a behavior such as bending can be prevented, and the reliability of the light emitting element is improved.

  A piezoelectric element 300 illustrated in FIG. 3A has a structure in which a first electrode layer 306, a piezoelectric layer 304, and a second electrode layer 302 are sequentially stacked.

  The first electrode layer 306 is formed using a conductive material. For example, gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), copper (Cu ), Palladium (Pd), carbon (C), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), or an alloy material or compound material containing the element can be used. . In addition, light-transmitting oxide conductive materials such as indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), and zinc oxide to which gallium is added (GZO), and indium tin oxide containing silicon oxide ( (ITSO) A conductive material such as indium oxide containing 2 wt% to 20 wt% of zinc oxide (ZnO) can also be used. The first electrode layer 306 can be used alone or in combination of two or more of these materials.

The second electrode layer 302 is formed using a conductive material such that the Young's modulus of the second electrode layer 302 is 7.5 × 10 ¹⁰ N / m ² or less. For example, an element having a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less, an alloy material, or a compound material is used. In addition, when using an alloy material or a compound material, it is preferable to include an element having a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less. For the second electrode layer 302, a material having a lower Young's modulus is preferably used.

  For example, the second electrode layer 302 includes indium (In), barium (Ba), lead (Pb), calcium (Ca), bismuth (Bi), magnesium (Mg), tin (Sn), aluminum (Al), and the like. Or an alloy material or compound material containing the metal element can be used. As an alloy material containing the metal element, an indium-tin (In-Sn) alloy, an aluminum-magnesium (Al-Mg) alloy, a magnesium-silver (Mg-Ag) alloy, or the like can be used. As the compound containing the element, a nitrogen compound, an oxygen compound, a carbon compound, a halogen compound, or the like can be used. The second electrode layer 302 can be used alone or in combination of two or more of these materials.

  Note that the thickness of the second electrode layer 302 is not particularly limited, but is preferably about 10 nm to 200 nm, and more preferably about 10 nm to 100 nm.

  The first electrode layer 306 or the second electrode layer 302 is formed using the above-described material with a single-layer structure or a stacked structure by an evaporation method, a sputtering method, a printing method, or a droplet discharge method.

  The piezoelectric layer 304 uses an organic piezoelectric material. For example, a high molecular weight organic compound such as polyvinylidene fluoride or a copolymer thereof can be used. The piezoelectric layer 304 may be formed by a sputtering method or a vapor deposition method.

The second electrode layer 302 constituting the piezoelectric element 300 has a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less, and the Young's modulus is smaller than that of a metal element such as Ag, Zn, or Cu. Therefore, the second electrode layer 302 can be relatively easily deformed, and can be easily tuned to a behavior such as bending of the element. Therefore, a defect due to a behavior such as bending can be prevented, and the reliability of the piezoelectric element is improved.

  An organic transistor element 320 illustrated in FIG. 3B has a structure in which a gate electrode layer 326, a gate insulating layer 330, an organic semiconductor layer 324, and an electrode layer 322 functioning as a source electrode or a drain electrode are stacked. Have. First, the gate electrode layer 326 is formed over the substrate 328. A gate insulating layer 330 is formed over the gate electrode layer 326, and an organic semiconductor layer 324 is formed over the gate electrode layer 326 with the gate insulating layer 330 interposed therebetween. An electrode layer 322 functioning as a source electrode or a drain electrode is formed in contact with the organic semiconductor layer 324.

  As the substrate 328, a glass substrate, a quartz substrate, a semiconductor substrate, a metal substrate, a stainless steel substrate, or the like is used.

  The gate electrode layer 326 is formed using a conductive material. For example, platinum (Pt), gold (Au), aluminum (Al), chromium (Cr), nickel (Ni), cobalt (Co), copper (Cu), titanium (Ti), magnesium (Mg), calcium (Ca ), An element such as barium (Ba), or an alloy material or compound material containing the element, a conductive layer is formed by a vapor deposition method or a sputtering method, and the conductive layer can be selectively etched. . The gate electrode layer 326 can be formed by various printing methods (screen (stencil printing), offset (lithographic printing), method of forming a desired pattern such as relief printing or gravure printing (intaglio printing)), nanoimprinting, and droplet discharge method. Alternatively, a dispenser method, a selective coating method, or the like may be used. When such a method is used, a conductive layer can be selectively formed at a desired place.

  The gate insulating layer 330 is formed using an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide, or an organic insulating material such as polyimide. The gate insulating layer 330 may have a single-layer structure, or a combination of two or more of these materials may have a stacked structure. Note that the gate insulating layer 330 may be formed by a CVD method, a sputtering method, a droplet discharge method, a coating method, or the like.

  The organic semiconductor layer 324 has a carrier transporting property (hole transporting property or electron transporting property) and is formed using an organic compound whose carrier density (hole density or electron density) is changed by an electric field effect. For example, a low molecular organic compound such as pentacene or naphthacene, or a high molecular organic compound such as poly (ethylenedioxythiophene) (PEDOT) or polyphenylene vinylene (PPV) can be used. The organic semiconductor layer 324 may be formed by a vapor deposition method, a coating method, a droplet discharge method, or the like. In addition, when using a low molecular weight organic compound, forming by a vapor deposition method is preferable.

The electrode layer 322 is formed using a conductive material in which the Young's modulus of the electrode layer 322 is 7.5 × 10 ¹⁰ N / m ² or less. For example, an element having a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less, an alloy material, or a compound material is used. In addition, when using an alloy material or a compound material, it is preferable to include an element having a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less. For the electrode layer 322, a material having a lower Young's modulus is preferably used.

  For example, the electrode layer 322 includes metal elements such as indium (In), barium (Ba), lead (Pb), calcium (Ca), bismuth (Bi), magnesium (Mg), tin (Sn), and aluminum (Al). Alternatively, an alloy material or a compound material containing the metal element can be used. As an alloy material containing the metal element, an indium-tin (In-Sn) alloy, an aluminum-magnesium (Al-Mg) alloy, a magnesium-silver (Mg-Ag) alloy, or the like can be used. As the compound containing the element, a nitrogen compound, an oxygen compound, a carbon compound, a halogen compound, or the like can be used. The electrode layer 322 can be used alone or in combination of two or more of these materials. The electrode layer 322 can be formed by using the above-described materials by forming a conductive layer by a sputtering method or an evaporation method and selectively etching the conductive layer. The electrode layer 322 may be formed by various printing methods (screen (stencil) printing, offset (lithographic printing) printing, a method of forming a desired pattern such as relief printing or gravure printing (intaglio printing)), nanoimprinting method, droplet discharge method, You may form using the dispenser method, the selective application method, etc. When such a method is used, an electrode layer can be selectively formed at a desired location. The electrode layer 322 functions as a source electrode or a drain electrode.

The electrode layer 322 constituting the organic transistor element 320 has a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less, and the Young's modulus is small as compared with metal elements such as Ag, Zn, and Cu. Therefore, the electrode layer 322 is relatively easy to deform and easily tuned to the behavior of the element such as bending. Therefore, defects due to bending or the like can be prevented, and the reliability of the element is improved.

  As described above, the present invention can be applied to various elements having a layer containing an organic compound. By applying the present invention, it is possible to provide an element in which defects are less likely to occur. In addition, according to the characteristics required by the element to be applied, even when selecting a material constituting the electrode layer in consideration of electrical characteristics such as work function and electrical resistance, by applying the present invention and considering the Young's modulus, It is possible to provide an element in which defects are less likely to occur. Therefore, since the defect of an element can be prevented, the reliability of the element can be improved. Further, it becomes possible to improve the yield in the manufacture of the element.

(Embodiment 2)
In this embodiment, an example of a method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS. Note that in the semiconductor device described in this embodiment, an element including a layer containing an organic compound is provided over a flexible substrate.

  As shown in FIG. 11A, a separation layer 702 is formed over the first substrate 700, and an insulating layer 704 is formed over the separation layer 702. Next, a semiconductor element is formed over the insulating layer 704. Here, a transistor 706, a transistor 708, and a transistor 710 are formed as semiconductor elements. Next, a first electrode layer 718 connected to the transistor 706, a first electrode layer 719 connected to the transistor 708, and a first electrode layer 720 connected to the transistor 710 are formed, and the first electrode layers 718 and 719 are formed. , 720, and a partition wall layer 721 that covers the end portion of the 720 is formed. A layer 722 including an organic compound is formed over the first electrode layers 718, 719, and 720 and the partition layer 721, and a second electrode layer 724 is formed over the layer 722 including the organic compound to include an organic compound. Thus, an element 726, an element 728, and an element 730 are obtained. An insulating layer 734 that functions as a protective layer is formed over the second electrode layer 724. Here, a stacked body from the insulating layer 704 to the second electrode layer 724 stacked as an upper layer is referred to as an element formation layer 738.

  As the first substrate 700, a substrate having heat resistance such as a glass substrate, a quartz substrate, a semiconductor substrate, a metal substrate, or a stainless steel substrate that can withstand the processing temperature in this manufacturing process is used.

  The release layer 702 includes tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium (Zr), zinc (Zn), It is formed using a metal element such as ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), or an alloy material or a compound material containing the metal element. The peeling layer 702 can also be formed using a material containing silicon (Si). In the case where the separation layer 702 is formed using silicon, any of an amorphous structure, a microcrystalline structure, and a polycrystalline structure may be used. The release layer 702 is formed using a single layer structure or a stacked layer structure using these materials by a sputtering method, a CVD method, a coating method, a printing method, or the like. Note that the coating method includes a spin coating method and a droplet discharge method.

  In the case where the separation layer 702 is formed with a single-layer structure, a tungsten layer, a molybdenum layer, a layer containing a mixture of tungsten and molybdenum, a layer containing tungsten oxide or oxynitride, or a layer containing molybdenum oxide or oxynitride Alternatively, a layer containing an oxide or oxynitride of a mixture of tungsten and molybdenum is preferably formed. Note that the mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum.

  In the case where the separation layer 702 is formed to have a stacked structure, it is preferable that a metal layer be formed as a first layer and a layer containing a metal oxide or metal nitride be formed as a second layer. For example, a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum is formed as a first layer, and a tungsten oxide or oxynitride layer, a molybdenum oxide or oxynitride layer, or tungsten as a second layer It is preferable to form an oxide or oxynitride of a mixture of molybdenum and molybdenum. Note that the peeling layer 702 is a first layer and a second layer in order from the first substrate 700 side.

  In the case where the separation layer 702 has a stacked structure including a metal layer and a layer containing a metal oxide, the metal oxide layer can be formed by forming a metal layer and oxidizing the metal layer. For the oxidation treatment, thermal oxidation treatment, oxygen plasma treatment, treatment using a solution having strong oxidizing power such as ozone water, or the like may be performed. In addition, a metal layer is formed as a separation layer, and an insulating layer made of an oxide is formed over the metal layer, so that a layer containing the metal oxide at the interface between the metal layer and the insulating layer (metal oxide layer) ) Can also be formed. For example, in the case where the separation layer 702 has a stacked structure of a tungsten layer and a layer containing tungsten oxide, the tungsten layer is formed, and the tungsten layer is oxidized to form a layer containing tungsten oxide. it can. Further, by forming an insulating layer formed using an oxide over the tungsten layer, a layer containing tungsten oxide can be formed at the interface between the tungsten layer and the insulating layer. Similarly, by forming an insulating layer containing nitride over the tungsten layer, a layer containing nitride of tungsten can be formed at the interface between the tungsten layer and the insulating layer.

The tungsten oxide used for the separation layer 702 can be represented by WO _x . x is in the range of 2 to 3, WO ₂ when x is ₂ , W ₂ O ₅ when x is 2.5, W ₄ O ₁₁ when x is 2.75, and x is 3. In this case, it becomes WO ₃ .

  Note that although the separation layer 702 is formed in contact with the first substrate 700 in this embodiment mode, the present invention is not particularly limited. For example, an insulating layer may be formed in contact with the first substrate 700, and the peeling layer 702 may be formed in contact with the insulating layer.

The insulating layer 704 includes silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon oxynitride (SiO _x N _y ) (x>y> 0), and silicon nitride oxide (SiN _x O _y ) (x>y> 0) or the like using an inorganic insulating material. The insulating layer 704 is formed using these materials with a single-layer structure or a stacked structure by a sputtering method, a CVD method, a coating method, a printing method, or the like.

  Various transistors can be used as the transistor 706, the transistor 708, and the transistor 710. For example, as the transistors 706, 708, and 710, TFTs 1380, 1390, 1480, and 1490 as illustrated in FIGS. Hereinafter, a specific method for manufacturing a transistor will be described with reference to FIGS.

  A TFT 1380 illustrated in FIG. 10A is an example of a top-gate thin film transistor. A thin film transistor is also referred to as a TFT. An insulating layer 1301 is provided over the substrate with a separation layer interposed therebetween, and a TFT 1380 is provided over the insulating layer 1301.

  In the TFT 1380, a semiconductor layer 1302 is formed over an insulating layer 1301, and a gate electrode layer 1304 is formed over the semiconductor layer 1302 with a gate insulating layer 1303 interposed therebetween. In addition, an insulating layer 1308 which is also referred to as a sidewall is formed on a side surface of the gate electrode layer 1304. An insulating layer 1351 and an insulating layer 1352 that function as interlayer insulating layers are formed over the semiconductor layer 1302 and the gate electrode layer 1304, and an electrode layer 1312 that is connected to the semiconductor layer 1302 through the insulating layers 1351 and 1352 is formed. . The electrode layer 1312 functions as a source electrode or a drain electrode.

  The semiconductor layer 1302 is formed using a semiconductor material. For example, a silicon-based material such as silicon or silicon germanium, germanium, or the like is used. The semiconductor layer 1302 is formed using a semiconductor material by a CVD method or a sputtering method, and the semiconductor layer is selectively etched to form the island-shaped semiconductor layer 1302.

  The semiconductor layer 1302 may be formed using either an amorphous semiconductor or a crystalline semiconductor. In this embodiment, the semiconductor layer 1302 is a layer formed using a semiconductor having a crystal structure. As a layer formed of a semiconductor having a crystal structure, a crystalline semiconductor obtained by crystallizing an amorphous or microcrystalline semiconductor by laser beam irradiation, a crystalline semiconductor crystallized by heat treatment, or a heat treatment It is preferable to apply a crystalline semiconductor which is crystallized by combining irradiation with a laser beam. In the heat treatment, a crystallization method using a metal element such as nickel which has an action of promoting crystallization of a semiconductor can be applied.

  In the case of forming a crystallized semiconductor layer by applying heat treatment, an oxide layer of the separation layer is formed at the interface between the separation layer and the insulating layer formed in the lower layer of the semiconductor layer by heat treatment at the time of crystallization. Can be formed. For example, in FIG. 11A, when a metal layer is formed as the separation layer 702, the separation layer 702 and the insulating layer are formed by heat treatment when the semiconductor layer included in the transistors 706, 708, and 710 provided in the upper layer is crystallized. At the interface 704, the surface of the metal layer that is the release layer 702 can be oxidized to form a metal oxide layer. In this manner, by forming an oxide layer (metal oxide layer) of the separation layer at the interface between the separation layer 702 and the insulating layer 704, the separation layer and the insulating layer can be easily separated in a subsequent separation step. can do.

When crystallization is performed by irradiation with a laser beam, a continuous wave laser beam or an ultrashort pulse having a repetition frequency of 10 MHz or more and a pulse width of 1 nanosecond or less, preferably 1 picosecond to 100 picoseconds. By irradiating with an oscillating laser beam, crystallization can be performed while the molten region in which the crystalline semiconductor is melted is continuously moved in the irradiation direction of the laser beam. By such a crystallization method, a crystalline semiconductor having a large particle diameter and a crystal grain boundary extending in one direction can be obtained. By adjusting the carrier drift direction to the direction in which the crystal grain boundary extends, the field-effect mobility in the transistor can be increased. For example, field effect mobility of 400 cm ² / V · sec or more can be realized.

  Further, when crystallization is performed using a crystallization process at a heat resistant temperature (about 600 ° C.) or lower of the glass substrate, a large area glass substrate can be used. Therefore, a large amount of semiconductor devices can be manufactured per substrate, and the cost can be reduced.

  Note that the semiconductor layer 1302 can also be formed by performing a crystallization step by heating at or above a heat resistant temperature of the glass substrate. Typically, a quartz substrate is used as the insulating substrate, and an amorphous or microcrystalline semiconductor is heated at 700 ° C. or higher to form the semiconductor layer 1302. As a result, a semiconductor with high crystallinity can be formed. Therefore, a thin film transistor that has favorable characteristics such as response speed and mobility and can operate at high speed can be provided.

  In the semiconductor layer 1302, an impurity region functioning as at least a channel formation region and a source or drain region is formed. Further, a low-concentration impurity region functioning as an LDD region (Lightly Doped Drain) may be formed between the channel formation region and the impurity region functioning as a source region or a drain region. The impurity region can be formed by adding an element imparting conductivity to the semiconductor layer. As an element imparting conductivity, an element imparting p-type conductivity or an element imparting n-type conductivity may be added. As an element imparting n-type, phosphorus (P), arsenic (As), or the like can be used. As an element imparting p-type, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, a channel formation region 1313, a high concentration impurity region 1311 which functions as a source region or a drain region, and a low concentration impurity region 1310 (also referred to as an LDD region) are formed in the semiconductor layer 1302. The low concentration impurity region 1310 is formed between the channel formation region 1313 and the high concentration impurity region 1311. An element imparting conductivity at a higher concentration than the low concentration impurity region 1310 is added to the high concentration impurity region 1311. Further, the channel formation region 1313 overlaps with the gate electrode layer 1304 with the gate insulating layer 1303 interposed therebetween, and the low concentration impurity region 1310 overlaps with the insulating layer 1308 with the gate insulating layer 1303 interposed therebetween. Note that the present invention is not particularly limited, and the low concentration impurity region may be formed so as to overlap with the gate electrode layer, or the low concentration impurity region may not be formed.

The gate insulating layer 1303 is formed using an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. The gate insulating layer 1303 is formed using these materials with a single-layer structure or a stacked-layer structure by a CVD method or a sputtering method. Alternatively, the gate insulating layer 1303 may be formed using an insulating solution by a droplet discharge method, a coating method, a sol-gel method, or the like. Typical examples of the insulating solution include a solution in which fine particles of inorganic oxide are dispersed, polyimide, polyamide, polyester, acrylic, PSG (phosphorus glass), BPSG (boron phosphorus glass), and silicate-based SOG (Spin on Glass). ), SiO ₂ having a Si—CH ₂ bond represented by alkoxysilicate SOG, polysilazane SOG, and polymethylsiloxane can be used as appropriate.

  The gate electrode layer 1304 is formed using an element such as tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), or aluminum (Al), or a conductive material such as an alloy material or a compound material containing the element. Form. Alternatively, a polycrystalline semiconductor to which an element imparting conductivity is added can be used. The gate electrode layer 1304 can be formed by using these materials to form a single layer structure or a stacked layer conductive layer by a CVD method, a sputtering method, an evaporation method, or the like, and selectively etching the conductive layer. . The gate electrode layer 1304 is formed by various printing methods (screen (stencil) printing, offset (lithographic) printing, a method of forming a desired pattern such as relief printing or gravure printing (intaglio printing)), nanoimprinting, and droplet discharge method. Alternatively, a dispenser method, a selective coating method, or the like may be used. When such a method is used, a conductive layer to be the gate electrode layer 1304 can be selectively formed at a desired place, and an etching step is not necessary.

  For example, in the case where the gate electrode layer 1304 is formed to have a stacked structure, a metal nitride layer can be formed as the first layer and a metal element layer as the second layer. The gate electrode layer 1304 is a first layer and a second layer from the gate insulating layer 1303 side. In the case where the gate electrode layer 1304 has such a stacked structure, the end portion of the first layer may protrude outward from the end portion of the second layer. In addition, a barrier metal can be formed by using a metal nitride layer as the first layer, and the metal element constituting the second layer can diffuse into the gate insulating layer 1303 and the semiconductor layer 1302 below it. Can be prevented.

  The insulating layer 1308 is formed using an insulating material containing silicon such as silicon oxide. For example, the insulating layer 1308 is formed by forming a gate electrode layer 1304, forming an insulating layer using silicon oxide by a CVD method, and etching the insulating layer by a RIE (Reactive Ion Etching) method. Can be formed. The insulating layer 1308 is formed on the side surface of the gate electrode layer 1304. The insulating layer 1308 is also referred to as a sidewall. Note that the insulating layer 1308 is not necessarily provided. Note that in this embodiment, when the insulating layer 1308 is formed by etching, the underlying gate insulating layer 1303 is also etched. Of course, only the insulating layer 1308 may be etched.

  The insulating layers 1351 and 1352 are formed using an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide, or an organic insulating material such as acrylic or polyimide. The insulating layers 1351 and 1352 are formed using these materials with a single-layer structure or a stacked structure by a sputtering method, a CVD method, a coating method, or the like. For example, the insulating layers 1351 and 1352 can be formed using a coating method such as spin coating or a roll coater. In that case, an insulating layer containing silicon oxide can be formed by heat treatment after applying a liquid insulating material. Specifically, an insulating layer containing silicon oxide can be formed by applying a material containing a siloxane bond and then performing heat treatment at 200 ° C. to 400 ° C. As the insulating layers 1351 and 1352, by forming an insulating layer formed by a coating method or an insulating layer flattened by reflow, disconnection of a wiring formed thereon can be prevented. It can also be used effectively when forming multilayer wiring. Note that although the example in which the interlayer insulating layer has a two-layer structure of insulating layers 1351 and 1352 is described in FIG. 10A, the present invention is not particularly limited, and a single-layer structure or a stacked structure of three or more layers may be used. .

  The electrode layer 1312 includes aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt), copper (Cu), gold (Au), It can be formed using an element such as silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or a conductive material such as an alloy material or a compound material containing the element. . For example, as an alloy material containing aluminum, an alloy material containing aluminum and nickel, or an alloy material containing one or both of carbon and silicon in addition to aluminum and nickel can be used. Note that the electrode layer 1312 employs a stacked structure of a barrier layer, an aluminum silicon (Al—Si) layer, and a barrier layer, and a stacked structure of a barrier layer, an aluminum silicon (Al—Si) layer, a titanium nitride layer, and a barrier layer. Is preferred. Here, the barrier layer corresponds to a layer made of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum silicon are optimal materials for forming the electrode layer 1312 because they have low resistance and are inexpensive. Further, by providing barrier layers in the upper layer and the lower layer, it is possible to prevent the occurrence of hillocks in aluminum or aluminum silicon. Furthermore, even if a thin natural oxide layer is formed on the crystalline semiconductor layer by forming a barrier layer made of titanium which is a highly reducing element, the natural oxide layer is reduced, and the crystalline semiconductor layer It makes it possible to make good contact. The electrode layer 1312 can be formed using these materials by forming a conductive layer having a single-layer structure or a stacked structure by a sputtering method, a CVD method, or the like, and selectively etching the conductive layer. . The electrode layer 1312 may be formed by various printing methods (screen (stencil) printing, offset (lithographic printing) printing, a method of forming a desired pattern such as relief printing or gravure printing (intaglio printing)), nanoimprinting method, droplet discharge method, You may form using the dispenser method, the selective application method, etc. When such a method is used, a conductive layer to be the electrode layer 1312 can be selectively formed at a desired place.

  Note that the insulating layers 1351 and 1352 in FIG. 10A correspond to the insulating layers 712 and 714 in FIG. The insulating layer 1301 corresponds to the insulating layer 704.

  A TFT 1390 illustrated in FIG. 10B is an example of a bottom-gate thin film transistor. An insulating layer 1361 is provided over the substrate with a separation layer interposed therebetween, and a TFT 1390 is provided over the insulating layer 1361.

  In the TFT 1390, a gate electrode layer 1364 is formed over the insulating layer 1361, and a semiconductor layer 1362 is formed over the gate electrode layer 1364 with the gate insulating layer 1363 interposed therebetween. A channel protective layer 1369 is formed over the semiconductor layer 1362. Over the semiconductor layer 1362 and the channel protective layer 1369, an insulating layer 1391 and an insulating layer 1392 functioning as an interlayer insulating layer are formed, and an electrode layer 1372 connected to the semiconductor layer 1362 through the insulating layers 1391 and 1392 is formed. The The electrode layer 1372 functions as a source electrode or a drain electrode.

  The gate electrode layer 1364, the gate insulating layer 1363, the semiconductor layer 1362, and the electrode layer 1372 are formed using a similar material and manufacturing method in accordance with the above description of FIG. The insulating layers 1361, 1391, and 1392 may be formed using similar materials and manufacturing methods in accordance with the insulating layers 1301, 1351, and 1352 in FIG.

  The channel protective layer 1369 is formed using an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide, or an organic insulating material such as acrylic or polyimide. The channel protective layer 1369 is formed by using these materials by forming an insulating layer by a CVD method or a sputtering method and selectively etching the insulating layer. Alternatively, an insulating layer functioning as a channel protective layer can be selectively formed using a solution having an insulating property by a droplet discharge method, a coating method, a sol-gel method, or the like.

  A TFT 1480 illustrated in FIG. 10C is an example of a staggered organic semiconductor transistor. An insulating layer 1401 is provided over the substrate with a separation layer interposed therebetween, and a TFT 1480 is provided over the insulating layer 1401.

  In the TFT 1480, a gate electrode layer 1402 is formed over an insulating layer 1401, and an organic semiconductor layer 1404 is formed over the gate electrode layer 1402 with a gate insulating layer 1403 interposed therebetween. An electrode layer 1412 connected to the organic semiconductor layer 1404 is formed over the organic semiconductor layer 1404 and the gate insulating layer 1403. The electrode layer 1412 functions as a source electrode or a drain electrode.

  The gate electrode layer 1402 can be formed using a material and a manufacturing method similar to those of the gate electrode layer 1304. Alternatively, the gate electrode layer 1402 can be formed by drying and baking using a droplet discharge method. Alternatively, the gate electrode layer 1402 can be formed by printing a paste containing conductive fine particles over the insulating layer 1401 by a printing method, drying, and baking. As typical examples of the conductive fine particles, fine particles mainly composed of gold, copper, an alloy of gold and silver, an alloy of gold and copper, an alloy of silver and copper, or an alloy of gold, silver and copper may be used. Alternatively, fine particles mainly composed of an oxide conductive material such as indium tin oxide (ITO) may be used.

  The gate insulating layer 1403 can be formed using a material and a manufacturing method similar to those of the gate insulating layer 1303.

  The organic semiconductor layer 1404 has a carrier transporting property (hole transporting property or electron transporting property) and is formed using an organic compound whose carrier density (hole density or electron density) is changed by an electric field effect. For example, a low molecular organic compound such as pentacene or naphthacene, or a high molecular organic compound such as poly (ethylenedioxythiophene) (PEDOT) or polyphenylene vinylene (PPV) can be used. The organic semiconductor layer 1404 may be formed using these materials by an evaporation method, a coating method, a droplet discharge method, or the like. In addition, when using a low molecular weight organic compound, forming by a vapor deposition method is preferable.

  The electrode layer 1412 can be formed using a material and a manufacturing method similar to those of the electrode layer 1312.

  A TFT 1490 illustrated in FIG. 10D is an example of a coplanar organic semiconductor transistor. An insulating layer 1461 is provided over the substrate with a separation layer interposed therebetween, and a TFT 1490 is provided over the insulating layer 1461.

  In the TFT 1490, a gate electrode layer 1462 is formed over the insulating layer 1461, and a gate insulating layer 1463 is formed over the gate electrode layer 1462. An electrode layer 1472 is formed over the gate insulating layer 1463, and an organic semiconductor layer 1464 is formed over the electrode layer 1472 and the gate insulating layer 1463. The organic semiconductor layer 1464 is formed so as to cover part of the electrode layer 1472 and is connected to the electrode layer 1472. Further, the organic semiconductor layer 1464 is opposed to the gate electrode layer 1462 with the gate insulating layer 1463 interposed therebetween. The electrode layer 1472 functions as a source electrode or a drain electrode.

  The gate electrode layer 1462, the gate insulating layer 1463, the electrode layer 1472, and the organic semiconductor layer 1464 are formed using a similar material and manufacturing method in accordance with the above description of FIG.

  The TFTs 1380, 1390, 1480, and 1490 formed as described above can be applied to the transistors 706, 708, and 710 illustrated in FIG.

  The first electrode layers 718, 719, and 720 shown in FIG. 11A are made of gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), and molybdenum. (Mo), iron (Fe), cobalt (Co), copper (Cu), palladium (Pd), carbon (C), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), etc. It is formed using an element or a conductive material such as an alloy material or a compound material containing the element. In addition, alkali metals such as lithium (Li) and cesium (Cs), and alkaline earth metals such as magnesium (Mg), calcium (Ca) and strontium (Sr), rare earths such as europium (Er) and ytterbium (Yb) A conductive material such as a metal and an alloy (MgAg, AlLi, or the like) containing any of these can be used. Further, a light-transmitting oxide conductive material such as indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), and zinc oxide to which gallium is added (GZO), indium tin oxide containing silicon oxide ( (ITSO) A conductive material such as indium oxide containing 2 wt% to 20 wt% of zinc oxide (ZnO) can also be used. The first electrode layers 718, 719, and 720 are formed using these materials by forming a single layer structure or a stacked layer conductive layer by a sputtering method, a CVD method, an evaporation method, or the like, and selectively etching the conductive layer. It can be formed by processing. The first electrode layers 718, 719, and 720 can be formed by various printing methods (screen (stencil) printing, offset (flat plate) printing, a method of forming a desired pattern such as relief printing or gravure (intaglio printing)), and nanoimprinting. It may be formed using a method, a droplet discharge method, a dispenser method, a selective coating method, or the like. When such a method is used, a conductive layer to be the first electrode layers 718, 719, and 720 can be selectively formed at a desired place, and an etching step is not necessary.

  The first electrode layers 718, 719, and 720 and the transistors 706, 708, and 710 are connected to each other through an insulating layer 716. The insulating layer 716 functions as an interlayer insulating layer and is formed using an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide, or an organic insulating material such as acrylic or polyimide. The insulating layer 716 may be formed using a single layer structure or a stacked layer structure using these materials by a sputtering method, a CVD method, a coating method, or the like. Note that as the insulating layer 716, a planarized insulating layer is preferably formed in order to prevent disconnection of the first electrode layers 718, 719, and 720 formed as an upper layer.

  The partition layer 721 is formed using an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide, or an organic insulating material such as acrylic or polyimide. The partition layer 721 can be formed by selectively etching an insulating layer which is formed over the entire surface using these insulating materials by a CVD method, a sputtering method, a coating method, or the like. Alternatively, an insulating layer functioning selectively as a partition layer can be formed by a droplet discharge method, a printing method, or the like. In addition, after forming an insulating layer on the entire surface using a photosensitive material, the insulating layer can be processed into a desired shape by exposure and development. Note that the shape of the partition wall layer 721 is preferably a shape in which the radius of curvature of the end portion changes continuously. By forming the partition layer 721 in such a shape, the coverage of a layer formed as an upper layer can be improved.

  The layer 722 containing an organic compound is formed using an organic compound whose conductivity changes or an organic compound whose shape changes by an optical action or an electrical action. Specifically, the layer 722 containing an organic compound can be formed using an organic compound having a hole-transport property, an organic compound having an electron-transport property, or a polymer organic compound. The layer 722 containing an organic compound is formed using these materials with a single-layer structure or a stacked-layer structure by a sputtering method, an evaporation method, a printing method, or a droplet discharge method.

The second electrode layer 724 is formed using a conductive material having a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less. For example, an element having a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less, an alloy material, or a compound material is used. In addition, when forming using an alloy material or a compound material, it is preferable to contain an element with a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less. The second electrode layer 724 preferably has a smaller Young's modulus. Specifically, metal elements such as indium (In), barium (Ba), lead (Pb), calcium (Ca), bismuth (Bi), magnesium (Mg), tin (Sn), and aluminum (Al), or What is necessary is just to form using the alloy material or compound material containing the said metal element. The second electrode layer 724 is formed using a single layer structure or a stacked layer structure using these materials by a sputtering method, an evaporation method, a printing method, a droplet discharge method, or the like. The thickness of the second electrode layer 724 is not particularly limited, but is preferably about 10 nm to 200 nm, and more preferably about 10 nm to 100 nm.

  Through the above steps, the element 726, the element 728, and the element 730 can be obtained. In this embodiment mode, the elements 726, 728, and 730 function as memory elements. Note that in the case where the elements 726, 728, and 730 function as memory elements, the materials and manufacturing methods similar to those of the memory element 100 or the memory element 110 described in Embodiment Mode 1 may be used. Detailed description is omitted in the form. Therefore, although an example in which the first electrode layer and the layer containing an organic compound are formed in contact with each other is described in this embodiment mode, an insulating layer or a semiconductor layer is provided between the first electrode layer and the layer containing an organic compound. Etc. may be provided. Similarly, an insulating layer, a semiconductor layer, or the like may be provided between the second electrode layer and the layer containing an organic compound.

  In addition, the present invention is not particularly limited, and elements 726, 728, and 730 that function as light-emitting elements can be formed by appropriately selecting a material included in the layer 722 containing an organic compound.

  In the case where the elements 726, 728, and 730 function as light-emitting elements, a layer having a light-emitting function is formed as the layer 722 containing an organic compound. For example, as the layer 722 containing an organic compound, a light-emitting layer containing a light-emitting material made of an organic compound is formed. The light emitting layer may contain an inorganic compound. The organic compound contained in the light emitting layer is not particularly limited as long as it is a light emitting organic compound, and various low molecular organic compounds and high molecular organic compounds can be used. As the light-emitting organic compound, either a fluorescent material or a phosphorescent material may be used. The light emitting layer may be a layer made of only a light emitting organic compound, or may have a structure in which a light emitting organic compound is dispersed in a host material having an energy gap larger than that of the organic compound. In addition, the layer 722 containing an organic compound may include at least a light-emitting layer, and a hole transport layer, a hole injection layer, an electron transport layer, an electron injection layer, or the like may be provided as appropriate. Note that in the case where the elements 726, 728, and 730 function as light-emitting elements, the light-emitting layer, the hole-transport layer, the hole-injection layer, the electron-transport layer, and the electron-injection layer of the light-emitting element 220 described in Embodiment Mode 1 are used. Detailed description is omitted in this embodiment because it is only necessary to use similar materials and manufacturing methods.

  In the present invention, the layer 722 containing an organic compound is formed using an organic piezoelectric material, whereby the elements 726, 728, and 730 can function as piezoelectric elements. For example, as the layer 722 containing an organic compound, a layer containing an organic piezoelectric material such as a high molecular weight organic compound such as polyvinylidene fluoride or a copolymer thereof can be formed. Note that in the case where the elements 726, 728, and 730 are made to function as piezoelectric elements, the elements 726, 728, and 730 may be formed using a material and a manufacturing method similar to those of the piezoelectric element 300 described in Embodiment Mode 1; The explanation is omitted.

  A stacked body from the transistor formed so far to the second electrode layer 724 is referred to as an element formation layer 738.

  Next, as illustrated in FIG. 11B, an insulating layer 734 is formed over the second electrode layer 724, and a second substrate 736 is attached to the surface of the insulating layer 734.

  The insulating layer 734 is made of acrylic resin, polyimide resin, melamine resin, polyester resin, polycarbonate resin, phenol resin, epoxy resin, polyacetal, polyether, polyurethane, polyamide (nylon), furan resin, diallyl phthalate resin, or other organic resin, silica An inorganic siloxane polymer containing a Si-O-Si bond among compounds composed of silicon, oxygen, and hydrogen formed from a siloxane polymer-based material typified by glass, or an alkylsiloxane polymer, an alkylsilsesquioxane polymer, Using hydrogenated silsesquioxane polymer, organosiloxane polymer in which hydrogen bonded to silicon represented by hydrogenated alkylsilsesquioxane polymer is substituted by organic groups such as methyl and phenyl It is made. The insulating layer 734 can be formed by applying these materials by a coating method, followed by drying and heating. It is preferable to form the insulating layer 734 using a coating method because an insulating layer with less surface unevenness can be formed. The insulating layer 734 can also be formed by forming an insulating layer such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide by a CVD method, a sputtering method, or the like, and then polishing the surface by a CMP method. The insulating layer 734 also functions as a protective layer in a subsequent peeling step.

  Note that although the second substrate 736 is attached to the surface of the insulating layer 734 in this embodiment, the present invention is not particularly limited, and the insulating layer 734 is not necessarily provided. That is, the second substrate 736 may be directly attached to the second electrode layer 724.

  As the second substrate 736, a flexible substrate is preferably used. In this specification, a flexible substrate means a substrate that can be bent (flexible). The second substrate 736 is preferably a thin and light substrate. Specifically, the second substrate 736 includes PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PES (polyethersulfone), polypropylene, polypropylene sulfide, polycarbonate, polyetherimide, polyphenylene sulfide, polyphenylene oxide, and polysulfone. A substrate made of polyphthalamide or the like can be used. Also, paper made of a fibrous material, a laminated film of a base film (polyester, polyamide, inorganic vapor deposition film, paper, etc.) and an adhesive organic resin film (acrylic organic resin, epoxy organic resin, etc.) are used. You can also Note that in the case where the above-described substrate is used as the second substrate 736, an adhesive layer is provided between the insulating layer 734 and the second substrate 736, and the insulating layer 734 and the second substrate 736 are attached to each other. Is preferred.

  Alternatively, the second substrate 736 can be a film (including polypropylene, polyester, vinyl, polyvinyl fluoride, or vinyl chloride) having an adhesive layer that is bonded to an object by thermocompression bonding. These films are bonded to the object by melting the adhesive layer provided on the outermost surface of the film or the layer provided on the outermost layer (a layer that is not an adhesive layer) by heat treatment and adhering it by pressure. Is possible. In the case of using such a film, it is not necessary to separately provide an adhesive layer between the insulating layer 734 and the second substrate 736.

  Here, the object to be processed indicates a stacked body from the insulating layer 734 to the first substrate 700 stacked below, and the surface to be processed is a surface that does not contact the second electrode layer 724 of the insulating layer 734.

  In this embodiment, first, an epoxy resin composition is applied by a coating method, and then dried and fired to form an insulating layer 734 made of an epoxy resin. Next, a film having an adhesive layer is used as the second substrate 736, and the film which is the second substrate 736 is thermocompression bonded to the surface of the insulating layer 734, so that the insulating layer 734 and the second substrate 736 are attached to each other.

  Next, as illustrated in FIG. 12A, the separation between the separation layer 702 and the insulating layer 704 is separated. In this manner, the element formation layer 738 including transistors and elements is separated from the first substrate 700 and transferred to the second substrate 736.

As a method for peeling the element formation layer 738 from the first substrate 700, (1) a stacked structure of a layer containing a metal layer and a metal oxide (or metal nitride) as a separation layer between the substrate and the element formation layer And (2) a metal layer and a metal as a separation layer between the substrate and the element formation layer, wherein the element formation layer is weakened by crystallization and the element formation layer is physically separated from the substrate. A layered structure including a layer including an oxide (or metal nitride) is provided, the layer including the metal oxide is weakened by crystallization, and a part of the peeling layer is formed of a solution, NF ₃ , BrF ₃ , ClF ₃ or the like. A method of physically peeling the element formation layer from the substrate after etching with a halogenated gas, (3) forming a separation layer using amorphous silicon containing hydrogen between the substrate and the element formation layer, The release layer is irradiated with a laser beam to generate hydrogen gas (4) A release layer is formed using amorphous silicon between the substrate and the element formation layer, and the release layer is removed by etching with a solution or halogen fluoride gas. (5) The substrate on which the element formation layer is formed (the first substrate 700 in this embodiment) is mechanically shaved, or a solution or a halogen fluoride gas such as NF ₃ , BrF ₃ , or ClF _{3 is used.} A method of removing by etching and the like can be selected as appropriate. For the above-described peeling methods (1) and (2), a peeling layer and an insulating layer are formed between the substrate and the element formation layer, and a metal oxide (or metal nitridation) is formed between the peeling layer and the insulating layer. And a layer containing the metal oxide may be weakened by crystallization. In this embodiment, the separation layer 702 and the insulating layer 704 are formed between the first substrate 700 and the element formation layer 738, and a metal oxide layer is provided at the interface between the separation layer 702 and the insulation layer 704. The element formation layer 738 is physically separated from the first substrate 700 by weakening the oxide layer by crystallization.

  Next, as shown in FIG. 12B, a third substrate 740 is attached to the surface of the insulating layer 704. As the third substrate 740, a flexible substrate is preferably used. Specifically, a substrate similar to the second substrate 736 is used and attached to the insulating layer 704 in the same manner. In this embodiment, a film is used as the third substrate 740, and the film which is the third substrate 740 is thermocompression bonded to the exposed surface of the insulating layer 704, so that the insulating layer 704, the third substrate 740, Paste together. Through the above steps, an element having a layer containing an organic compound can be transferred over a flexible substrate using a peeling step.

  In the element transfer process, the element is inevitably bent in a process of peeling the element from a substrate (supporting substrate such as a glass substrate) or a process of attaching a substrate (a flexible substrate) to the element. When the Young's modulus is large, it is difficult for the electrode layer constituting the element to be deformed in synchronization with the bending of the element. In addition, the flexible substrate and the element are bonded to each other with relatively good adhesion using a method such as thermocompression bonding. Therefore, if the Young's modulus of the electrode layer bonded to the flexible substrate is large on the side not in contact with the support substrate, the electrode layer cannot be tuned to the behavior of the substrate or element such as bending. The element will be destroyed.

In the present invention, the second electrode layer that is not in contact with the supporting substrate and is bonded to the flexible substrate has a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less. By applying the present invention, the Young's modulus of the electrode layer adhered with good adhesion to the flexible substrate is formed so as to be relatively small, 7.5 × 10 ¹⁰ N / m ² or less, It becomes easy to tune the element to the behavior of the substrate. As a result, it is possible to prevent the occurrence of element defects and the destruction of elements in the transposition process. Therefore, it is possible to manufacture a semiconductor device with high yield and high reliability.

(Embodiment 3)
In this embodiment, an example of a semiconductor device including a memory element according to the present invention will be described with reference to FIGS. Here, an example in which the structure of the semiconductor device is a passive matrix type will be described.

  4A shows an example of a semiconductor device according to the present invention, which includes a memory cell array 10, a bit line driver circuit 32, a word line driver circuit 40, and an interface 30 provided over a substrate 20. FIG. Yes.

  The memory cell array 10 includes a plurality of bit lines Bx (1 ≦ x ≦ m) extending in the x direction and a plurality of word lines Wy (1 ≦ y ≦ n) extending in the y direction orthogonal to the x direction. It is configured. A memory cell 12 having a memory element 14 is provided at a portion where the bit line Bx and the word line Wy intersect. The memory cells 12 are provided in a matrix in the memory cell array 10.

  The bit line drive circuit 32 includes a column decoder 34, a read / write circuit 36, and a selector 38. The bit line driving circuit 32 is connected to the bit line Bx and the interface 30.

  The word line driving circuit 40 includes a row decoder 42 and a level shifter 44. The word line driving circuit 40 is connected to the word line Wy and the interface 30.

  The interface 30 is a circuit that supplies a signal input from the outside to the bit line driving circuit 32 or the word line driving circuit 40 or supplies a signal output from the bit line driving circuit 32 to the outside.

  Note that the structure illustrated in FIG. 4A is merely an example, and may include other circuits such as a sense amplifier, an output circuit, and a buffer circuit. In addition, a writing circuit may be provided in the interface 30.

  Next, an example of a top view of the memory cell array 10 is illustrated in FIG. FIG. 5B illustrates an example of a cross-sectional view taken along line OP in FIG. In FIG. 5A, the structure other than the first electrode layer and the second electrode layer is partly omitted.

As shown in FIG. 5, the memory cell array 10 includes a first electrode layer 22 that forms the bit line Bx and a second electrode layer 28 that forms the word line Wy. Further, in the memory cell array 10, the intersection of the first electrode layer 22 and the second electrode layer 28 corresponds to the memory cell 12 in FIG. 4A, and the memory element 14 is formed. As the memory element 14, the memory element as shown in the first and second embodiments is formed. Specifically, the memory element 14 has a structure including a layer containing an organic compound between a pair of electrode layers including at least a first electrode layer and a second electrode layer, and at least one of the pair of electrode layers. The Young's modulus of the electrode layer (second electrode layer in this embodiment) is 7.5 × 10 ¹⁰ N / m ² or less. In this embodiment mode, the memory element 14 has a structure in which a layer 26 containing an organic compound is provided between the first electrode layer 22 and the second electrode layer 28 (FIG. 5B). reference). Note that the present invention is not particularly limited, and an insulating layer, a semiconductor layer, or a metal oxide is provided between the first electrode layer and the layer containing an organic compound, or between the second electrode layer and the layer containing an organic compound. A structure provided with a layer or the like may be employed.

  Another configuration example of the memory cell array 10 is shown in FIG. For example, as shown in FIG. 6A, a rectifying element may be provided on the side opposite to the layer 26 containing an organic compound with the first electrode layer 22 interposed therebetween. The element having a rectifying property is a Schottky diode, a diode having a PN junction, a diode having a PIN junction, a diode such as an avalanche diode, or a transistor in which a gate electrode layer and a drain electrode layer are connected. Of course, other configurations of diodes may be used. Here, the diode 50 including the third electrode layer 52 and the semiconductor layer 54 is provided in contact with the first electrode layer 22. Specifically, the semiconductor layer 54 is provided in contact with the first electrode layer 22, and the third electrode layer 52 is provided in contact with the semiconductor layer 54. That is, the semiconductor layer 54 is sandwiched between the first electrode layer 22 and the third electrode layer 52. Note that the element having a rectifying property may be provided on the side opposite to the layer 26 containing an organic compound with the second electrode layer 28 interposed therebetween. For example, a diode may be formed by sequentially stacking a semiconductor layer and a third electrode layer in contact with the second electrode layer 28. Thus, by providing an element having a rectifying property, the direction of current flow can be controlled in only one direction. Therefore, the error is reduced and the reading accuracy is improved. Note that an insulating layer 55 for insulating the diode is provided between adjacent memory elements.

  For example, a thin film transistor (TFT) may be provided on an insulating substrate and the memory element 14 may be provided thereon, or a semiconductor substrate such as Si or an SOI (Silicon On Insulator) substrate instead of the insulating substrate. May be used to form a field effect transistor (FET) on a substrate, and a memory element 14 may be provided thereon.

  Further, a memory element and a TFT or FET may be attached. In this case, the memory element and the TFT or FET can be manufactured in separate steps and then bonded together using a conductive film, an anisotropic conductive adhesive, or the like. Further, any configuration of TFT or FET may be used as long as it is known.

  A TFT may be provided over a flexible substrate, and the memory element 14 may be provided thereover. For example, as described in Embodiment Mode 2, after an element formation layer including a TFT and a memory element is formed over a support substrate having heat resistance that can withstand a processing temperature in a manufacturing process, the element formation layer is formed from the support substrate. And is transferred to another substrate (preferably a flexible substrate). Alternatively, after the element formation layer is formed over the support substrate, the element formation layer may be fixed to another substrate, and the element formation layer may be peeled off from the support substrate and transferred.

  In addition, when there is a concern about the influence of the electric field in the lateral direction between adjacent memory elements, the organic compound provided in each memory element is separated to separate the layer containing the organic compound provided in each memory element. An insulating layer functioning as a partition wall (hereinafter, also referred to as a partition layer) may be provided between the layers containing. Alternatively, a layer including an organic compound may be selectively provided for each memory cell.

  For example, as shown in FIG. 6B, when the layer 26 containing an organic compound is provided so as to cover the first electrode layer 22, a partition wall layer 56 may be provided between the adjacent first electrode layers 22. . With such a structure, it is possible to prevent the step of the layer 26 containing an organic compound caused by the step of the first electrode layer 22 and the influence of the electric field in the lateral direction between the memory cells. Note that in the cross section of the partition layer 56, the side surface of the partition layer 56 has an inclination angle of 10 degrees to less than 60 degrees, preferably 25 degrees to 45 degrees with respect to the surface of the first electrode layer 22. . Furthermore, it is preferable that it is curved. Thereafter, a layer 26 containing an organic compound and a second electrode layer 28 are formed so as to cover the first electrode layer 22 and the partition wall layer 56.

  In addition, as shown in FIG. 6C, an interlayer insulating layer 62 covering a part of the first electrode layer 22 provided on the substrate 20 and extending in the x direction, and a part of the interlayer insulating layer 62 A partition layer 64 may be provided to cover the surface. The interlayer insulating layer 62 has an opening at a portion where the memory element 14 is provided. The partition layer 64 is provided so as to extend in the y direction on a region where the opening of the interlayer insulating layer 62 is not formed. The partition wall layer 64 preferably has an inclination angle of 95 degrees or more and 135 degrees or less with respect to the surface of the interlayer insulating layer 62.

  The material of the partition wall layer 64 is not particularly limited. For example, the partition wall layer 64 can be formed by a photolithography method using a positive photosensitive resin in which an unexposed portion remains. In this case, it is possible to form the partition wall layer having a preferable inclination angle by adjusting the exposure amount or the development time so that the lower part of the pattern to be the partition wall layer is etched more. The partition layer 64 may be formed by forming an insulating layer using an inorganic insulating material, an organic insulating material, or the like, and selectively etching the insulating layer.

  The height of the partition wall layer 64 is set higher than the thickness of the layer 26 containing an organic compound and the second electrode layer 28. As a result, a memory element that is electrically independent and separated into a plurality of regions can be formed only by the step of depositing the layer containing the organic compound and the second electrode layer on the entire surface of the substrate 20. Specifically, a layer 26 containing a stripe-shaped organic compound extending in the y direction intersecting the first electrode layer 22 extending in the x direction and the second electrode layer 28 can be formed. Therefore, the number of processes can be reduced. Note that the organic compound-containing layer 25 and the second electrode layer 27 are also formed on the partition wall layer 64, and these are the organic compound-containing layer 26 and the second electrode layer 28 that constitute the memory element 14. It is divided.

  Note that the substrate 20 can be a flexible substrate, a glass substrate, a quartz substrate, a semiconductor substrate, a metal substrate, a stainless steel substrate, or the like. As the flexible substrate, a plastic substrate, paper made of a fibrous material, a film, or the like can be used.

In the memory element of this embodiment, when the second electrode layer has a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less, it can be easily tuned to a behavior such as bending. As a result, it becomes possible to prevent and reduce the occurrence of defects in the memory element. Therefore, a semiconductor device having a memory element can be manufactured with high yield. In addition, a highly reliable semiconductor device can be provided.

  Next, an example of data writing operation in a semiconductor device having the memory element of the present invention will be described. For example, when data is written to the memory cell 12 located in the xth column and the yth row among the plurality of memory cells 12 provided in the memory cell array 10 shown in FIG. 4A, the row decoder 42 and the column decoder 34 are written. The selector 38 selects the bit line Bx in the xth column and the word line Wy in the yth row, and selects the memory cell 12 located at the intersection of the bit line Bx and the word line Wy. Then, data is written into the selected memory cell 12 using a writing circuit.

  The memory cell 12 has a storage element 14. Since the electrical resistance of the memory element 14 changes before and after voltage application, data can be selectively written into the memory cell 12 by utilizing the change in the electrical resistance of the memory element 14.

  A specific operation when data is written to the semiconductor device of the present invention will be described below with reference to FIG. Note that writing is performed by changing the electrical characteristics such as the electrical resistance of the memory cell. The initial state (state in which no electrical action is applied) of the memory cell is data “0”, and the state in which the electrical characteristic is changed is “ 1 ”.

  When data “1” is written in the memory cell 12, first, the memory cell 12 is selected by the row decoder 42, the level shifter 44, the column decoder 34, and the selector 38 shown in FIG. For example, when the memory cell 12 located at the intersection of the bit line B3 and the word line W3 is selected, a predetermined voltage V2 is applied to the word line W3 connected to the memory cell 12 by the row decoder 42 and the level shifter 44. . Further, the bit line B 3 connected to the memory cell 12 is connected to the read / write circuit 36 by the column decoder 34 and the selector 38. Then, the write voltage V1 is output from the read / write circuit 36 to the bit line B3. Thus, the voltage Vw = V1−V2 is applied between the first electrode layer 22 and the second electrode layer 28 constituting the memory cell 12. By appropriately selecting the voltage Vw to be applied, the organic compound layer 26 provided between the first electrode layer 22 and the second electrode layer 28 of the memory element 14 is changed physically or electrically. The data “1” can be written. Specifically, in the read operation voltage, the electrical resistance between the first electrode layer 22 and the second electrode layer 28 in the data “1” state is significantly larger than that in the data “0” state. It is good to change so that it may become small. For example, it may be appropriately selected from the range of (V1, V2) = (0V, 5-15V), or (3-5V, -12--2V). The voltage Vw may be 5 to 15V, or -5 to -15V.

  Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. For example, unselected word lines and unselected bit lines may be set in a floating state. The first electrode layer 22 and the second electrode layer 28 constituting the memory cell need to have characteristics such as diode characteristics that can ensure selectivity.

  On the other hand, when data “0” is written in the memory cell 12, it is not necessary to apply an electrical action to the memory cell 12. In terms of circuit operation, for example, as in the case of writing “1”, the memory cell 12 is selected by the row decoder 42, the level shifter 44, the column decoder 34, and the selector 38, but from the read / write circuit 36 to the bit line B3. Is set to the same level as the potential of the selected word line W3 or the potential of the non-selected word line, and between the first electrode layer 22 and the second electrode layer 28 constituting the memory cell 12, the memory cell It is sufficient to apply a voltage (for example, −5 to 5 V) that does not change the electrical characteristics of 12.

  Next, a specific operation when reading data from the semiconductor device of the present invention will be described. In reading data, the electrical characteristics between the first electrode layer and the second electrode layer constituting the memory cell are different between the memory cell having data “0” and the memory cell having data “1”. Use it. For example, the effective electrical resistance between the first electrode layer and the second electrode layer constituting the memory cell having data “0” (hereinafter simply referred to as the electrical resistance of the memory cell) is R0 at the read voltage. A method of reading data by using the difference in electric resistance when the electric resistance of the memory cell having data “1” is R1 in the read voltage will be described. Note that R1 << R0. For the read / write circuit 36, for example, a circuit using a resistance element 72 and a differential amplifier 74 shown in FIG. The resistance element 72 has a resistance value Rr, and R1 <Rr <R0. Further, as shown in FIG. 4C, a transistor 76 may be used instead of the resistance element 72, and a clocked inverter 78 may be used instead of the differential amplifier. The clocked inverter 78 receives a signal φ or an inverted signal φ that is High when reading is performed and is Low when the reading is not performed. Of course, the circuit configuration is not limited to FIGS. 4B and 4C.

  When reading data from the memory cell 12, first, the memory cell 12 is selected by the row decoder 42, the level shifter 44, the column decoder 34, and the selector 38. Specifically, a predetermined voltage Vy is applied to the word line Wy connected to the memory cell 12 by the row decoder 42 and the level shifter 44. Further, the bit line Bx connected to the memory cell 12 is connected to the terminal P of the read / write circuit 36 by the column decoder 34 and the selector 38. As a result, the potential Vp of the terminal P becomes a value determined by resistance division by the resistance element 72 (resistance value Rr) and the memory cell 12 (resistance value R0 or R1). Therefore, when the memory cell 12 has data “0”, Vp0 = Vy + (V0−Vy) × R0 / (R0 + Rr). When the memory cell 12 has data “1”, Vp1 = Vy + (V0−Vy) × R1 / (R1 + Rr). As a result, in FIG. 4B, Vref is selected to be between Vp0 and Vp1, and in FIG. 4C, the change point of the clocked inverter is selected to be between Vp0 and Vp1. Thus, Lo / Hi (or Hi / Lo) is output as the output potential Vout according to the data “0” / “1”, and reading can be performed.

  For example, the differential amplifier 74 is operated at Vdd = 3V, and Vy = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9, if the memory cell data is “0”, Vp0 = 2.7 V and Vout is High, and if the memory cell data is “1”, Vp1 = 0.3V and Low is output as Vout. Thus, the memory cell can be read.

  According to the above method, the state of the electrical resistance of the memory element 14 is read as a voltage value using the difference in resistance value and resistance division. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. In addition, when the electrical characteristics of the memory cell have data “0” and “1” and diode characteristics with different threshold voltages, reading may be performed using the threshold voltage difference. It is also possible to adopt a method of reading the resistance value of the memory element by replacing it with the magnitude of the current, or a method of precharging the bit line.

  By applying the present invention, the occurrence of a memory element failure is prevented. Thus, yield can be improved in manufacturing a semiconductor device including the memory element. In addition, a highly reliable semiconductor device can be provided.

  Further, it is possible to provide a semiconductor device having a memory element that can write (additional) data other than during manufacturing and can prevent forgery due to data rewriting.

  Note that this embodiment can be freely combined with the first and second embodiments.

(Embodiment 4)
In this embodiment, an example of a semiconductor device including a memory element according to the present invention will be described with reference to FIGS. Here, an example in which the structure of the semiconductor device is an active matrix type will be described.

  FIG. 7A illustrates an example of a semiconductor device according to the present invention, which includes a memory cell array 610, a bit line driver circuit 632, a word line driver circuit 640, and an interface 630 provided over a substrate 620. Yes.

  The memory cell array 610 includes a plurality of bit lines Bx (1 ≦ x ≦ m) extending in the x direction and a plurality of word lines Wy (1 ≦ y ≦ n) extending in the y direction orthogonal to the x direction. It is configured. A memory cell 612 including a transistor 680 and a memory element 614 is provided at a portion where the bit line Bx and the word line Wy intersect. The memory cells 612 are provided in a matrix in the memory cell array 610.

  The bit line driver circuit 632 includes a column decoder 634, a read / write circuit 636, and a selector 638. The bit line driving circuit 632 is connected to the bit line Bx and the interface 630.

The word line driver circuit 640 includes a row decoder 642 and a level shifter 644. The word line driving circuit 640 is connected to the word line Wy and the interface 630.

  The interface 630 is a circuit that supplies a signal input from the outside to the bit line driving circuit 632 or the word line driving circuit 640 or supplies a signal output from the bit line driving circuit 632 to the outside.

  Note that the structure illustrated in FIG. 7A is just an example, and may include other circuits such as a sense amplifier, an output circuit, and a buffer circuit. Further, a writing circuit may be provided in the interface 630.

  Next, the memory cell 612 will be described in detail with reference to FIG. FIG. 8A illustrates an example of a top view of the memory cell array 610. FIG. 8B illustrates an example of a cross-sectional view taken along line AB in FIG. Note that in the top view of FIG. 8A, part of the structure other than the transistor and the first electrode layer is omitted.

The memory cell 612 includes a first electrode layer 622 connected to the bit line Bx (1 ≦ x ≦ m), a second electrode layer 628 connected to the word line Wy (1 ≦ y ≦ n), and a memory element 614 and a transistor 680. The memory element 614 has a structure as shown in Embodiment Mode 1. Specifically, the memory element 614 includes a layer containing an organic compound between a pair of electrode layers including at least a first electrode layer and a second electrode layer, and at least one of the pair of electrode layers ( In the present embodiment, the Young's modulus of the second electrode layer) is 7.5 × 10 ¹⁰ N / m ² or less. Further, the gate electrode layer of the transistor 680 is connected to the word line Wy, one of the source electrode and the drain electrode is connected to the bit line Bx, and the other is connected to one of two terminals of the memory element 614. The remaining one terminal of the memory element is connected to a common electrode (potential Vcom).

  For example, as illustrated in FIG. 8B, the memory element 614 can be formed over a substrate 620 provided with a transistor 680. As the memory element 614, a memory element as shown in Embodiment Mode 1 is formed. Specifically, the memory element 614 has a structure in which a first electrode layer 622, a layer 626 containing an organic compound, and a second electrode layer 628 are sequentially stacked. In addition, a partition layer 654 that covers an end portion of the first electrode layer 622 is provided between the adjacent first electrode layers 622. Further, in this embodiment, an insulating layer 656 that functions as a protective layer is provided over the memory element 614. Note that in the memory element 614, as illustrated in FIG. 1B in Embodiment 1, an insulating layer or a semiconductor layer is provided between the first electrode layer 622 and the layer 626 containing an organic compound. It is good also as a structure.

  The transistor 680 is provided over the substrate 620 with a base insulating layer 650 interposed therebetween. In addition, an electrode layer functioning as a source electrode or a drain electrode of the transistor 680 is connected to the first electrode layer 622 of the memory element 614.

  Various transistors can be used as the transistor 680 in this embodiment. For example, a TFT 1380, a TFT 1390, a TFT 1480, or a TFT 1490 as shown in FIGS. 10A to 10D can be used. Note that a specific structure, a manufacturing method, and the like of the transistor illustrated in FIGS. 10A to 10D are not described here because they are similar to those described in Embodiment Mode 2. In addition, the insulating layers 651 and 652 in FIG. 8B may be formed using a material and a manufacturing method similar to those of the insulating layers 1351 and 1352 in FIG. In this embodiment, an example in which the top-gate TFT 1380 illustrated in FIG.

  In the TFT 1380 used as the transistor 680, a semiconductor layer 1302 is formed, and a gate electrode layer 1304 is formed over the semiconductor layer 1302 with a gate insulating layer 1303 interposed therebetween. An insulating layer 1308 (side wall) is formed on the side surface of the gate electrode layer 1304. Over the semiconductor layer 1302, the gate electrode layer 1304, and the insulating layer 1308, insulating layers 1351 and 1352 functioning as interlayer insulating layers are formed, and an electrode layer 1312 connected to the semiconductor layer 1302 through the insulating layers 1351 and 1352 is formed. Has been. In the semiconductor layer 1302, a channel formation region, an impurity region that functions as a source region or a drain region, and a low-concentration impurity region that functions as an LDD region are formed.

  Note that the electrode layer 1312 in FIG. 10A functions as a source electrode or a drain electrode; however, in this embodiment, the electrode layer 1312 also functions as an electrode layer included in the memory element. That is, in FIG. 8B, the electrode layer functioning as the source electrode or the drain electrode of the transistor 680 and the first electrode layer 622 included in the memory element 614 are formed in the same layer. Note that an electrode layer functioning as a source electrode or a drain electrode of the transistor 680 can be provided so as to intersect with a wiring formed in the same layer as the gate electrode layer of the transistor 680, so that a multilayer wiring structure is formed. Can do. Furthermore, a multilayer wiring structure can be formed by stacking a plurality of insulating layers similar to the insulating layer 652 and forming a wiring thereon. The first electrode layer 622 includes a stacked structure of titanium (Ti) and aluminum (Al), a stacked structure of molybdenum (Mo) and aluminum (Al), a low resistance material such as aluminum (Al), and titanium (Ti). And a combination with a barrier metal using a refractory metal material such as molybdenum (Mo).

  In addition, the transistor 680 includes a multi-gate including a semiconductor layer including at least two or more channel formation regions connected in series and at least two or more gate electrode layers for applying a voltage to each channel formation region. A structure may be employed, or a dual gate structure in which a semiconductor layer is sandwiched between upper and lower gate electrode layers may be employed.

  Note that the thin film transistor and the organic semiconductor transistor illustrated in FIGS. 10A to 10D may have any structure as long as they can function as a switching element.

  Alternatively, a transistor may be formed using a single crystal substrate or an SOI substrate, and a memory element may be provided thereover. An SOI substrate is a bonding method in which two substrates, a substrate having an oxide film formed on the surface and a substrate having no oxide film formed on the surface, are bonded together, and the surface of one substrate is shaved, or oxygen ions are implanted into the Si substrate. Accordingly, an ion implantation method called SIMOX for forming an insulating layer inside may be used. For example, as illustrated in FIG. 8C, a field-effect transistor 662 is formed using a single crystal semiconductor substrate 660, and a memory element 614 is provided thereover. Here, the electrode layer 663 connected to the impurity region of the field effect transistor 662 and the first electrode layer 622 of the memory element 614 are connected, whereby the field effect transistor 662 and the memory element 614 are connected. . In addition, an insulating layer 672 is provided so as to cover the electrode layer 663 functioning as a source electrode or a drain electrode of the field-effect transistor 662, and the memory element 614 is provided over the insulating layer 672. Field effect transistor 662 is separated by field oxide film 661.

  A transistor formed using a single crystal semiconductor has favorable characteristics such as response speed and mobility, and thus can operate at high speed. In addition, since a transistor formed using a single crystal semiconductor has less variation in characteristics, a semiconductor device with high reliability can be provided.

  Note that in the case where the electrode layer functioning as the source electrode or the drain electrode of the transistor and the first electrode layer included in the memory element are formed in the same layer as illustrated in FIG. It is necessary to provide a storage element in the area. On the other hand, as illustrated in FIG. 8C, an insulating layer is formed over an electrode layer functioning as a source electrode or a drain electrode of the transistor, and a first electrode layer included in the memory element is formed over the insulating layer. With the structure in which the electrode layer of the transistor and the first electrode layer of the memory element are connected to each other through the insulating layer, the memory element can be freely arranged.

  8B and 8C illustrate an example in which the layer 626 containing an organic compound is provided over the entire surface of the substrate, it may be selectively provided only in each memory cell. In this case, the use efficiency of the material can be improved by ejecting and baking the organic compound using a droplet discharge method or the like and selectively providing the layer containing the organic compound.

  The specific structure, manufacturing method, and the like of the memory element 614 conform to those described in Embodiments 1 to 3. Specifically, the storage element 100, the storage element 110, the element 726 functioning as the storage element, the element 728, the element 730, and the storage element 14 described in any of Embodiments 1 to 3 can be used. That's fine.

  The partition layer 654 can be provided using a material and a formation method similar to those of the partition layer 56 and the partition layer 721 described in Embodiments 2 and 3.

In the memory element of this embodiment, when the second electrode layer has a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less, it can be easily tuned to a behavior such as bending. As a result, it becomes possible to prevent and reduce the occurrence of defects in the memory element. Therefore, a semiconductor device having a memory element can be manufactured with high yield. In addition, a highly reliable semiconductor device can be provided.

  Next, specific operation when data is written to the semiconductor device of the present invention will be described with reference to FIGS. Writing is performed by changing the electrical characteristics of the memory cell. The initial state of the memory cell (the state where no electrical action is applied) is data “0”, and the state where the electrical characteristic is changed is “1”. To do.

  Here, a case where data is written to the memory cell 612 in the third column and the third row will be described. When data “1” is written to the memory cell 612, first, the memory cell 612 is selected by the row decoder 642, the column decoder 634, and the selector 638. Specifically, the row decoder 642 applies a predetermined voltage V22 to the word line W3 connected to the memory cell 612. Further, the bit line B 3 connected to the memory cell 612 is connected to the read / write circuit 636 by the column decoder 634 and the selector 638. Then, the write voltage V21 is output from the read / write circuit 636 to the bit line B3.

  Thus, the transistor 680 included in the selected memory cell 612 is turned on, the bit line is electrically connected to the memory element 614, and a voltage of approximately Vw = Vcom−V21 is applied. Note that one electrode of the memory element 614 is connected to a common electrode of the potential Vcom. By appropriately selecting the potential Vw, the layer including the organic compound provided between the first electrode layer and the second electrode layer included in the memory element 614 is physically or electrically changed, and data “1”. Can be written. Specifically, at the read operation voltage, the electrical resistance between the first electrode layer and the second electrode layer in the data “1” state is significantly smaller than that in the data “0” state. It may be changed as described above, or it may be simply short-circuited. Note that the potential may be appropriately selected from the range of (V21, V22, Vcom) = (5V to 15V, 5V to 15V, 0V), or (−12V to 0V, −12V to 0V, 3V to 5V). The voltage Vw may be 5V to 15V, or -5V to -15V.

  Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. Specifically, a potential (for example, 0 V) for turning off the transistor of the memory cell to be connected is applied to the non-selected word line, and the non-selected bit line is in a floating state or approximately equal to Vcom. A potential may be applied.

  On the other hand, when data “0” is written to the memory cell 612, it is not necessary to apply an electrical action to the memory cell 612. In circuit operation, for example, as in the case of writing “1”, the memory cell 612 is selected by the row decoder 642, the column decoder 634, and the selector 638, but the output potential from the read / write circuit 636 to the bit line B3 is changed. The bit line B3 is set in a floating state or the same level as Vcom. As a result, a small voltage (for example, −5 V to 5 V) is applied to the memory element 614 or no voltage is applied, so that the electrical characteristics do not change and data “0” writing is realized.

  Next, an operation when data is read by electrical action will be described. Data is read using the fact that the electrical characteristics of the memory element 614 differ between the memory cell having data “0” and the memory cell having data “1”. For example, the electrical resistance of the memory element constituting the memory cell having data “0” is R0 at the read voltage, and the electrical resistance of the memory element constituting the memory cell having data “1” is R1 at the read voltage. A method of reading using the difference will be described. Note that R1 << R0. As the structure of the reading / writing circuit, for example, a reading / writing circuit 636 using a resistance element 673 and a differential amplifier 674 shown in FIG. 7B can be considered. The resistance element has a resistance value Rr, and R1 <Rr <R0. Note that as shown in FIG. 7C, a transistor 676 may be used instead of the resistance element 673, and a clocked inverter 678 may be used instead of the differential amplifier 674. Of course, the circuit configuration is not limited to FIGS. 7B and 7C.

  When reading data from the memory cell 612 in the x-th column and the y-th row, first, the memory cell 612 is selected by the row decoder 642, the column decoder 634, and the selector 638. Specifically, the row decoder 642 applies a predetermined voltage V24 to the word line Wy connected to the memory cell 612 to turn on the transistor 680. Further, the bit line Bx connected to the memory cell 612 is connected to the terminal P of the read / write circuit 636 by the column decoder 634 and the selector 638. As a result, the potential Vp of the terminal P becomes a value determined by resistance division of Vcom and V0 by the resistance element 673 (resistance value Rr) and the memory element 614 (resistance value R0 or R1). Therefore, when the memory cell 612 has data “0”, Vp0 = Vcom + (V0−Vcom) × R0 / (R0 + Rr). When the memory cell 612 has data “1”, Vp1 = Vcom + (V0−Vcom) × R1 / (R1 + Rr). As a result, by selecting Vref to be between Vp0 and Vp1 in FIG. 7B, the change point of the clocked inverter 678 is between Vp0 and Vp1 in FIG. 7C. By selecting the output potential Vout, Lo / Hi (or Hi / Lo) is output according to the data “0” / “1”, and reading can be performed.

  For example, the differential amplifier 674 is operated at Vdd = 3V, and Vcom = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9 and the on-resistance of the transistor 680 can be ignored, when the data in the memory cell is “0”, Vp0 = 2.7 V and Vout is output as High When the data of “1” is “1”, Vp1 = 0.3V and Vout is output as Low. Thus, the memory cell can be read.

  According to the above method, the voltage value is read by utilizing the difference in resistance value of the memory element 614 and the resistance division. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. In addition, when the electrical characteristics of the memory cell have data “0” and “1” and diode characteristics with different threshold voltages, reading may be performed using the threshold voltage difference.

  By applying the present invention, the occurrence of a memory element failure is prevented. Thus, yield can be improved in manufacturing a semiconductor device including the memory element. In addition, a highly reliable semiconductor device can be provided.

  Further, it is possible to provide a semiconductor device having a memory element that can write (additional) data other than during manufacturing and can prevent forgery due to data rewriting.

  Note that this embodiment mode can be implemented in combination with Embodiment Modes 1 and 2 as appropriate.

(Embodiment 5)
An example of a semiconductor device having a light emitting element according to the present invention will be described. Note that in this embodiment, an example of a display device having a display function is described with reference to FIGS.

  FIG. 9A illustrates an example of a top view of the display device. FIG. 9B illustrates an example of a cross-sectional view taken along the line QR in FIG.

  A display device 900 illustrated in FIG. 9 includes a pixel portion 902 and a driver circuit portion 904 provided over a substrate 901. A substrate 908 is provided above the substrate 901 with a sealant 910 interposed therebetween. A terminal portion 906 is provided on the substrate 901. A signal for controlling the operation of a plurality of elements included in the pixel portion 902 and a power supply potential are input from the outside through the terminal portion 906.

  As shown in FIG. 9B, the pixel portion 902 is provided with a driving transistor 924 and a capacitor 920 over a substrate 901. The pixel portion 902 may be provided with a switching transistor. The light emitting element 930 is provided above the driving transistor 924. Further, the light emitting element 930 and the driving transistor 924 are connected.

The light-emitting element 930 is a light-emitting element as described in Embodiment Mode 1 and the like. Specifically, the light-emitting element 930 has a structure including a layer containing an organic compound having a light-emitting function between a pair of electrode layers including a first electrode layer and a second electrode layer. The Young's modulus of at least one of the electrode layers (second electrode layer in this embodiment) is 7.5 × 10 ¹⁰ N / m ² or less. In this embodiment, the light-emitting element 930 has a structure in which a layer 934 containing an organic compound having a light-emitting function is provided between the first electrode layer 932 and the second electrode layer 936. Note that the light-emitting element 930 has a structure in which a hole transport layer, a hole injection layer, an electron transport layer, an electron injection layer, or the like is appropriately provided between the first electrode layer 932 and the second electrode layer 936. Also good.

  An end portion of the first electrode layer 932 of the light-emitting element 930 is covered with a partition wall layer 918. The partition layer 918 is formed using an inorganic insulating material such as silicon oxide or silicon nitride, or an organic insulating material such as acrylic or polyimide. A partition layer 918 can be separated from another light-emitting element provided adjacent to the partition layer 918. As for the shape of the partition layer 918, it is preferable that the curvature radius of the end portion is continuously changed. With such a shape, coverage with the layer 934 containing the organic compound and the second electrode layer 936 stacked on the upper layer can be improved.

  The driving transistor 924 and the capacitor 920 are provided over the substrate 901 with an insulating layer 903 interposed therebetween. An electrode layer functioning as a source electrode or a drain electrode of the driving transistor 924 is connected to the first electrode layer 932 of the light-emitting element 930 through the insulating layer 916.

  Various transistors can be used as the driving transistor 924. For example, the transistors illustrated in FIGS. 10A to 10D can be used. In this embodiment mode, a top-gate TFT is applied. An example of a top-gate TFT is illustrated in FIG. 10A; however, the structure of the TFT illustrated in FIG. 10A and the structure of the driving transistor 924 described in this embodiment include two gate electrode layers. A multi-layer structure (two channel formation regions connected in series to a semiconductor layer are formed, and two channel voltages are applied to each channel formation region). A structure having a gate electrode).

  In the driving transistor 924, a gate electrode layer is formed over a semiconductor layer with a gate insulating layer interposed therebetween. In the semiconductor layer, two channel formation regions and a source region or a drain region are formed. A high concentration impurity region is formed between adjacent channel formation regions. The concentration of the high concentration impurity region is approximately the same as that of the source region or the drain region. In addition, LDD regions are formed between the source or drain region and the channel formation region, and between the high-concentration impurity region and the channel formation region. The concentration of the LDD region is lower than that of the source region or the drain region.

  Two gate electrode layers of the driving transistor 924 are formed corresponding to two channel formation regions formed in the semiconductor layer. Here, the gate electrode layer has a two-layer structure, and the width of the gate electrode layer in the lower layer (side in contact with the gate insulating layer) (the direction in which carriers flow in the channel formation region (the direction connecting the source region and the drain region)) ) Is larger than the width of the upper gate electrode layer.

  An electrode layer functioning as a source electrode or a drain electrode of the driving transistor 924 is formed so as to be connected to a source region or a drain region formed in the semiconductor layer through the insulating layer 913 and the insulating layer 914.

  In the capacitor 920, an electrode layer is formed over a semiconductor layer with a gate insulating layer interposed therebetween. The semiconductor layer is the same layer as the semiconductor layer of the driving transistor 924, and includes an intrinsic region to which an impurity element is not added, a low concentration impurity region, and a high concentration impurity region. The concentration of the low-concentration impurity region is about the same as that of the LDD region of the driving transistor 924, and the concentration of the high-concentration impurity region is about the same as the source region or drain region of the driving transistor 924. The source region or the drain region of the driving transistor 924 also has a function of connecting the driving transistor 924 and the capacitor 920. The electrode layer of the capacitor 920 is the same layer as the gate electrode layer of the driving transistor 924.

  The insulating layers 913, 914, and 916 are formed using an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide, or an organic insulating material such as acrylic or polyimide. The insulating layers 913, 914, and 916 function as interlayer insulating layers. Here, with the insulating layers 913 and 914, a wiring formed in the same layer as the gate electrode layer of the driving transistor 924 and an electrode layer functioning as a source electrode or a drain electrode can be provided to intersect with each other. A multilayer wiring structure can be formed. Similarly, a multilayer wiring structure can be formed by forming the insulating layer 916 and forming the first electrode layer 932 thereon.

  In the driver circuit portion 904, a plurality of transistor groups 926 are provided over a substrate 901. The plurality of transistor groups 926 form a driver circuit that controls the operation of the pixel portion 902. The driver circuit portion 904 is provided with, for example, a shift register, a decoder, a buffer, a sampling circuit, a latch circuit, and the like.

  The plurality of transistor groups 926 includes a plurality of transistors. FIG. 9B illustrates two transistors as the plurality of transistor groups 926.

  Various transistors can be used as the transistors included in the plurality of transistor groups 926. For example, the transistor illustrated in FIGS. 10A to 10D can be used. Here, similarly to the driving transistor 924, a top-gate TFT is used.

  In each of the transistors included in the plurality of transistor groups 926, a gate electrode layer is formed over a semiconductor layer with a gate insulating layer interposed therebetween. In the semiconductor layer, a channel formation region and a source region or drain region are formed, and a concentration region of the LDD region is formed between the channel formation region and the source region or drain region. The concentration of the LDD region is lower than that of the source region or the drain region. The gate electrode layer has a two-layer structure, and is formed so that the width of the lower gate electrode layer is larger than that of the upper layer. An electrode layer functioning as a source electrode or a drain electrode of the transistor is formed so as to be connected to a source region or a drain region formed in the semiconductor layer through insulating layers 913 and 914.

  Note that two transistors illustrated as the plurality of transistor groups 926 in FIG. 9B may have different conductivity (p-type or n-type). A CMOS circuit can be formed by complementarily combining transistors having different conductivities.

  The substrate 901 and the substrate 908 are attached to each other with a sealant 910 so as to enclose the pixel portion 902 and the drive circuit portion 904.

  The sealant 910 is preferably a photocurable resin or a thermosetting resin. For example, a phenol resin or an epoxy resin can be used. A region 938 surrounded by the sealant 910 may be filled with a filler such as an epoxy resin, or may be sealed in a nitrogen atmosphere and filled with nitrogen. In addition, when a hygroscopic substance such as a desiccant is used as the filler, deterioration of the light-emitting element 930 and the like due to moisture can be prevented. Note that when light emitted from the light-emitting element 930 is extracted from the substrate 908 side, a light-transmitting filler is used.

  As the substrate 901 and the substrate 908, a glass substrate, a quartz substrate, a semiconductor substrate, a metal substrate, a stainless steel substrate, or the like can be used. As the substrate 908, a flexible substrate such as a plastic substrate can be used. In addition, as described in Embodiment Mode 2, after an element formation layer including a TFT and a light-emitting element is formed over a heat-resistant support substrate that can withstand the processing temperature in the manufacturing process, the element formation layer is formed from the support substrate. It is also possible to use a flexible substrate as the substrate 901 by peeling and transferring to a flexible substrate.

  In the terminal portion 906, a terminal electrode layer 950 is provided over a substrate 901 with an insulating layer interposed therebetween. The terminal electrode layer 950 is connected to the FPC 954 by an anisotropic conductive layer 952 and electrically connected to the outside.

  Note that in this embodiment, a structure in which the pixel portion 902 and the driver circuit portion 904 are provided over the same substrate as illustrated in FIG. 9A is described; however, the present invention is not particularly limited. For example, an IC chip may be mounted as a drive circuit unit by a COG method or a TAB method.

  Next, FIG. 20 shows an example of a circuit diagram of a pixel portion of the display device shown in FIG.

  In FIG. 20, the pixel portion includes a light-emitting element 2030, a transistor 2024, a transistor 2003, and a capacitor 2020. The light-emitting element 2030 corresponds to the light-emitting element 930 in FIG. 9B, the transistor 2024 corresponds to the driving transistor 924, and the capacitor 2020 corresponds to the capacitor 920. The transistor 2003 is a switching transistor having a switching function, and the transistor 2024 is a driving transistor.

  The gate of the transistor 2003 is connected to the gate wiring 2004. One of a source and a drain of the transistor 2003 is connected to the source wiring 2005, and the other of the source and the drain is connected to the gate of the transistor 2024 and one terminal of the capacitor 2020. One terminal of the capacitor 2020 is connected to the other of the source and the drain of the transistor 2003 and the gate of the transistor 2024, and the other terminal is connected to the current supply line 2006 and one of the source and the drain of the transistor 2024. One of a source and a drain of the transistor 2024 is connected to the current supply line 2006, and the other is connected to the light-emitting element 2030. The source wiring 2005 and the current supply line 2006 are provided so as to cross the gate wiring 2004.

  As described above, one of the source and the drain of the transistor 2024 is connected to the current supply line 2006, and current is supplied to the light-emitting element 2030 when the transistor 2024 is turned on.

  In the pixel portion of the display device of this embodiment mode, a plurality of light-emitting elements driven by a circuit as shown in FIG. 20 are arranged in a matrix. Note that the circuit for driving the light emitting element is not limited to the one shown in FIG. For example, a circuit having a configuration in which an erasing line for forcibly erasing an input signal and an erasing transistor used for an erasing operation may be provided.

  In the display device of this embodiment mode, a driving method for screen display is not particularly limited, and for example, a dot sequential driving method, a line sequential driving method, a surface sequential driving method, or the like may be used. When the line sequential driving method is used, a time division gray scale driving method or an area gray scale driving method may be selected as appropriate. The video signal input to the source wiring of the display device may be an analog signal or a digital signal, and a driver circuit or the like may be appropriately designed in accordance with the video signal.

  By applying the present invention, it is possible to prevent a light emitting element included in the display device from being defective. In addition, when selecting a material in consideration of the work function of the material constituting the electrode layer in order to improve the light emission efficiency of the light emitting element, the present invention is applied and the Young's modulus is taken into consideration, so that the light emitting element is defective. Can be prevented. Therefore, the reliability of the display device can be improved. In addition, yield can be improved in the manufacturing process of the display device.

  Note that this embodiment mode can be implemented in combination with Embodiment Modes 1 and 2 as appropriate.

(Embodiment 6)
In this embodiment, an example of a semiconductor device of the present invention and a manufacturing method thereof will be described with reference to FIGS.

  The semiconductor device described in this embodiment is characterized in that data can be read and written without contact. Data transmission formats are broadly divided into three types: electromagnetic coupling method in which a pair of coils are arranged facing each other to communicate by mutual induction, electromagnetic induction method to communicate by inductive electromagnetic field, and radio wave method to communicate using radio waves. However, any method may be used. There are two types of antennas used for data transmission. One is provided with a terminal portion provided on a substrate provided with a transistor and a memory element, and an antenna provided on another terminal is connected to the terminal portion. In another case, an antenna may be provided over a substrate over which a transistor and a memory element are provided.

  First, a structure example of a semiconductor device in the case where a terminal portion is provided over a substrate provided with a plurality of semiconductor elements and memory elements and an antenna provided over another terminal is connected to the terminal portion is shown in FIG. Will be described. Here, an antenna, a circuit connected to the antenna, and a part of a memory circuit are illustrated as part of a cross section of the semiconductor device.

  In the semiconductor device illustrated in FIG. 14A, a transistor layer 5250 including a transistor 5451 and a transistor 5452 is provided over a substrate 5300, and a memory element portion 5352 is provided above the transistor layer 5250. A conductive layer 5463 functioning as an antenna is provided over the substrate 5400. The substrate 5300 and the substrate 5400 are provided to face each other so that the transistor layer 5250 and the conductive layer 5463 are connected to each other.

  Although an example in which the memory element portion 5352 and the conductive layer 5463 are provided above the transistor layer 5250 is described here, the present invention is not particularly limited. For example, a conductive layer functioning as a memory element portion or an antenna may be provided below the element formation layer or in the same layer.

The memory element portion 5352 includes a memory element 5351a and a memory element 5351b. The memory element 5351a includes a first electrode layer 5361a formed over the insulating layer 5252, a layer 5362a containing an organic compound formed over the first electrode layer 5361a, and a layer 5362a containing the organic compound. A second electrode layer 5364a formed thereover. Similarly, the memory element 5351b includes a first electrode layer 5361b formed over the insulating layer 5252, a layer 5362b containing an organic compound formed over the first electrode layer 5361b, and a layer containing the organic compound. And a second electrode layer 5364b formed over 5362b. The memory element portion 5352 can be formed using a material or a manufacturing method similar to those of the memory element described in any of Embodiments 1 to 4. In this embodiment mode, the second electrode layers 5364a and 5364b have a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less.

  In addition, an insulating layer 5466 which functions as a protective layer is formed so as to cover the memory elements 5351a and 5351b. The insulating layer 5466 has a portion where the element formation layer and the conductive layer 5463 are connected to each other removed.

  The transistor 5452 forms part of a driver circuit that controls the operation of the memory element portion 5352. The drive circuit is provided with a decoder, a buffer, and the like. The transistor 5451 is connected to the conductive layer 5463 functioning as an antenna and forms part of a circuit connected to the antenna. Various transistors can be used as the transistors 5451 and 5452. For example, the transistor illustrated in FIGS. 10A to 10D can be used.

  A conductive layer 5463 functioning as an antenna is provided over the substrate 5400. As a material of the conductive layer 5463, gold (Au), platinum (Pt), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), aluminum (Al), manganese ( An element such as Mn) or titanium (Ti) or an alloy material containing the element can be used. The conductive layer 5463 can be formed by a variety of printing methods such as an evaporation method, a sputtering method, a screen printing method, or a gravure printing method, a droplet discharge method, or the like.

  A substrate 5300 provided with the transistor layer 5250 and the memory element portion 5352 is attached to a substrate 5400 provided with a conductive layer 5463 functioning as an antenna with an adhesive resin 5440. The transistor layer 5250 and the conductive layer 5463 are electrically connected through conductive fine particles 5444 contained in the resin 5440. Specifically, the terminal electrode layer 5360 connected to the transistor 5451 provided over the substrate 5300 and the conductive layer 5463 provided over the substrate 5400 are electrically connected by being in contact with the conductive fine particles 5444, respectively. . Note that a substrate provided with an element formation layer and a substrate provided with a conductive layer functioning as an antenna are attached to each other using a conductive adhesive such as silver paste, copper paste, or carbon paste or a method of solder bonding. You may combine them.

  Next, a structural example of a semiconductor device in the case where an antenna is provided over a substrate provided with a plurality of semiconductor elements and memory elements will be described with reference to FIG. Note that FIG. 14B will be described with respect to portions different from FIG.

  In the semiconductor device illustrated in FIG. 14B, a transistor layer 5250 including transistors 5451 and 5452 is provided over a substrate 5600, and a memory element portion 5355 and a conductive layer 5353 functioning as an antenna are provided above the transistor layer 5250. Yes. Further, a transistor 5453 and a transistor 5454 which function as a switching element of the memory element portion 5355 are provided in the same layer as the transistors 5451 and 5452. Note that the present invention is not particularly limited, and the memory element portion 5355 and the conductive layer 5353 functioning as an antenna may be provided below the transistor layer 5250 or in the same layer.

The memory element portion 5355 includes a memory element 5356a and a memory element 5356b. The memory element 5356a includes a first electrode layer 5371a formed over the insulating layer 5252, a layer 5372 containing an organic compound formed over the first electrode layer 5371a, and a layer 5372 containing the organic compound. A second electrode layer 5373 formed thereon. Similarly, the memory element 5356b includes a first electrode layer 5371b formed over the insulating layer 5252, a layer 5372 containing an organic compound formed over the first electrode layer 5371b, and a layer containing the organic compound. And a second electrode layer 5373 formed over 5372. The memory element portion 5355 can be formed using a material or a manufacturing method similar to those of the memory element described in any of Embodiments 1 to 4. In this embodiment mode, the second electrode layer 5373 has a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less. An end portion of the first electrode layer 5371a of the memory element 5356a and an end portion of the first electrode layer 5371b of the memory element 5356b are covered with a partition layer 5374. The partition layer 5374 can separate the adjacent memory elements 5356a and 5356b.

  Note that in the memory elements 5356a and 5356b, the layer 5372 containing an organic compound and the second electrode layer 5373 are used as a common layer. That is, a layer 5372 containing an organic compound and a second electrode layer 5373 are sequentially stacked over the first electrode layers 5371a and 5371b and the partition wall layer 5374 covering the end portions of the first electrode layers 5371a and 5371b. It has been.

  The memory element 5356a is connected to the transistor 5454, and the memory element 5356b is connected to the transistor 5453. For the transistors 5454 and 5453, a transistor similar to the transistor 5451 may be used.

  A conductive layer 5353 functioning as an antenna is provided over the terminal electrode layer 5360. The terminal electrode layer 5360 is provided above the transistor 5451, and the terminal electrode layer 5360 and the transistor 5451 are connected to each other through a wiring layer 5538. Specifically, the terminal electrode layer 5360 and an electrode layer functioning as a source electrode or a drain electrode of the transistor 5451 are connected to each other through a wiring layer 5538.

  The conductive layer 5353 functioning as an antenna includes gold (Au), platinum (Pt), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), aluminum (Al), and manganese. Using an element such as (Mn) or titanium (Ti) or an alloy material containing the element, or the like, by various printing methods such as a vapor deposition method, a sputtering method, a screen printing method or a gravure printing method, or a droplet discharge method. Can do. The terminal electrode layer 5360 can be formed using the same layer as the second electrode layer 5373. The wiring layer 5538 can be formed using the same layer as the first electrode layers 5371a and 5371b.

  An insulating layer 5366 functioning as a protective layer is formed so as to cover the memory elements 5356a and 5356b and the conductive layer 5353 functioning as an antenna.

  The substrate 5600 provided with the transistor layer 5250, the memory element portion 5355, and the conductive layer 5353 functioning as an antenna, and the substrate 5500 are attached to each other with an insulating layer 5540 interposed therebetween. Note that the substrate 5500 is preferably attached to the surface of the insulating layer 5540 with an adhesive layer.

  In FIGS. 14A and 14B, a sensor element may be provided in addition to the memory element. Examples of the sensor element include an element that detects temperature, humidity, illuminance, gas (gas), gravity, pressure, sound (vibration), acceleration, and other characteristics by physical or chemical means. Sensor elements are typically elements such as resistance elements, capacitive coupling elements, inductive coupling elements, photovoltaic elements, photoelectric conversion elements, thermoelectric elements, transistors, thermistors, diodes, capacitive elements, piezoelectric elements, etc. Formed with.

  Next, an example of a method for manufacturing the semiconductor device illustrated in FIG. 14B will be described with reference to FIGS.

  First, the peeling layer 5102 is formed over one surface of the substrate 5100 (see FIG. 15A). As the substrate 5100, a glass substrate, a quartz substrate, a metal substrate, a stainless steel substrate with an insulating layer formed on one surface, a heat-resistant plastic substrate that can withstand the processing temperature in this manufacturing process, or the like can be used. Although the separation layer 5102 is provided over the entire surface of the substrate 5100 here, it may be provided over part of the substrate 5100. Although the separation layer 5102 is formed so as to be in contact with the substrate 5100, an insulating layer in contact with the substrate 5100 may be formed as needed, and the separation layer 5102 may be formed so as to be in contact with the insulation layer.

  The separation layer 5102 is formed by a sputtering method, a CVD method, or the like using tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium ( From elements such as Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), lead (Pb), osmium (Os), iridium (Ir), silicon (Si), or alloy materials or compound materials containing such elements The layer to be formed is formed with a single layer structure or a laminated structure. In the case where a layer containing silicon is formed as the separation layer 5102, the crystal structure may be any of amorphous, microcrystalline, and polycrystalline.

  In the case where the separation layer 5102 has a single-layer structure, a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum is preferably formed. Alternatively, a layer containing tungsten oxide or oxynitride, a layer containing molybdenum oxide or oxynitride, or a layer containing an oxide or oxynitride of a mixture of tungsten and molybdenum is formed. Note that the mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum. The oxide of tungsten may be expressed as tungsten oxide.

  In the case where the separation layer 5102 has a stacked structure, it is preferable that a metal layer be formed as a first layer and a layer containing a metal oxide or metal nitride be formed as a second layer. For example, a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum is formed as the first layer. As the second layer, oxide, nitride, oxynitride, or nitride oxide of tungsten, molybdenum, or a mixture of tungsten and molybdenum is formed. Note that in the case where the separation layer 5102 has a stacked structure, the first layer and the second layer are sequentially formed from the side in contact with the substrate 5100.

  In the case where the separation layer 5102 has a stacked structure including a metal layer and a layer containing a metal oxide, the metal oxide layer can be formed by forming the metal layer and oxidizing the metal layer. For the oxidation treatment, thermal oxidation treatment, oxygen plasma treatment, treatment using a solution having strong oxidizing power such as ozone water, or the like may be performed. In addition, a metal layer is formed as a separation layer, and an insulating layer made of an oxide is formed over the metal layer, so that a layer containing the metal oxide at the interface between the metal layer and the insulating layer (metal oxide layer) ) Can also be formed. For example, in the case where a stacked layer structure including a layer containing tungsten and a layer containing tungsten oxide is formed as the separation layer 5102, a tungsten layer is formed, and a layer containing silicon oxide is formed thereover. A layer containing tungsten oxide is formed at the interface between the silicon oxide layer and the silicon oxide layer. The same applies to the case where a layer containing tungsten nitride, oxynitride, and nitride oxide is formed. After forming a layer containing tungsten, nitrogen and silicon such as silicon nitride and silicon nitride oxide are formed thereon. An insulating layer including the above may be formed. Note that after the metal layer is formed, an insulating layer formed using an oxide over the metal layer (for example, an insulating layer containing silicon nitride, silicon oxide, or other silicon) is used for the base insulating layer and a peeling process performed later. Functions as a protective layer.

The oxide of tungsten used for the peeling layer 5102 is represented by WOx, and x is in the range of 2 to 3. Specifically, when x is 2 (WO ₂ ), when x is 2.5 (W ₂ O ₅ ), when x is 2.75 (W ₄ O ₁₁ ), when x is 3 (WO ₃ ). In forming the tungsten oxide, the value of x mentioned above is not particularly limited, and may be determined based on the etching rate of the tungsten oxide. Note that it is preferable to determine the etching rate of a layer containing tungsten oxide (WOx, 0 <X <3) formed by a sputtering method in an oxygen atmosphere. Therefore, in order to shorten the manufacturing time, a layer containing a tungsten oxide is preferably formed as the separation layer 5102 by a sputtering method in an oxygen atmosphere. In this embodiment, a stacked-layer structure of a tungsten layer and a layer containing an oxide of tungsten is formed as the separation layer 5102. The layer containing tungsten oxide is formed by plasma treatment of the tungsten layer in an atmosphere containing oxygen and nitrogen.

  Next, an insulating layer 5104 is formed so as to cover the separation layer 5102. As the insulating layer 5104, an insulating layer containing silicon nitride, silicon oxide, or other silicon is formed with a single-layer structure or a stacked structure by a thin film formation method such as a sputtering method or a CVD method. The insulating layer 5104 functions as a blocking layer that prevents impurities from entering from the substrate 5100. Moreover, it functions also as a protective layer at the time of performing a peeling process later. In this embodiment, a silicon nitride layer is formed as the insulating layer 5104.

  Next, transistors 5451, 5452, 5453, and 5454 are formed (see FIG. 15B). As the transistors 5451, 5452, 5453, and 5454, transistors as illustrated in FIGS. 10A to 10D may be formed. The specific configuration, manufacturing method, and the like are omitted here in accordance with Embodiment Mode 2. In this embodiment mode, the top gate TFT 1380 shown in FIG. 10A is formed. Specifically, in FIG. 15B, a semiconductor layer is formed over the insulating layer 5104, and a gate electrode layer is formed over the semiconductor layer with the gate insulating layer interposed therebetween. An insulating layer functioning as a sidewall is formed on a side surface of the gate electrode layer, and an insulating layer covering the semiconductor layer, the gate electrode layer, and the sidewall is formed. Then, an electrode layer functioning as a source electrode or a drain electrode connected to the semiconductor layer through the insulating layer is formed.

  An element imparting conductivity is added to the transistors 5451, 5452, 5453, and 5454, and a channel formation region, an LDD region, and a source region or a drain region are formed in each semiconductor layer. An element imparting conductivity at a higher concentration than the LDD region is added to the source region or the drain region. Note that the LDD region is not necessarily provided. As an element imparting conductivity, an element imparting p-type conductivity or an element imparting n-type conductivity may be added. As an element imparting n-type, phosphorus (P), arsenic (As), or the like can be used. As an element imparting p-type, boron (B), aluminum (Al), gallium (Ga), or the like can be used.

  Here, a channel formation region 5106, an LDD region 5108, and a source region or a drain region 5110 are formed in the transistor 5451. The transistor 5452 includes two transistors to which elements imparting different conductivities are added. A channel formation region 5512, an LDD region 5114, a source or drain region 5116, and a channel formation region 5118 are included in each transistor. The LDD region 5120 and the source or drain region 5122 are formed. In the transistor 5452, different conductive elements are added to the LDD region 5114 and the source or drain region 5116 and the LDD region 5120 and the source or drain region 5122. The transistor 5453 forms a channel formation region 5124, an LDD region 5126, and a source region or a drain region 5128. The transistor 5454 forms a channel formation region 5130, an LDD region 5132, and a source or drain region 5134.

  Next, an insulating layer 5536 and an insulating layer 5252 are formed over the transistors 5451, 5452, 5453, and 5454 (see FIG. 16A). The insulating layers 5536 and 5252 are formed using an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide, or an organic insulating material such as acrylic or polyimide. When a coating method such as spin coating or roll coater is used, an insulating layer containing silicon oxide can be used by heat treatment after applying a liquid insulating layer material. For example, an insulating layer containing silicon oxide can be used by applying a material containing a siloxane bond and performing heat treatment at 200 ° C. to 400 ° C. As the insulating layers 5536 and 5252, by forming an insulating layer formed by a coating method or an insulating layer flattened by reflow, wirings formed over the layers (here, function as a first electrode layer and an antenna of a memory element) Disconnection of the conductive layer and the wiring layer connecting the transistor) can be prevented. Here, the interlayer insulating layer has a two-layer structure; however, there is no particular limitation, and a single-layer structure or a stacked structure of three or more layers can also be used. In addition, when the insulating layer 5536 in contact with the electrode layers of the transistors 5451, 5452, 5453, and 5454 is formed using an inorganic insulating material such as silicon oxide or silicon nitride, the transistor can function as a protective layer.

  Next, the insulating layers 5536 and 5252 are selectively etched to form contact holes that expose the electrode layers functioning as source and drain electrodes of the transistors 5451, 5453, and 5454. Then, a conductive layer is formed over the insulating layer 5252 so as to fill the contact holes. The conductive layer is formed by gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo) by a sputtering method, a printing method, a droplet discharge method, or the like. ), Iron (Fe), cobalt (Co), copper (Cu), palladium (Pd), carbon (C), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), and other metal elements Or an alloy material or a compound material containing the element. In addition, alkali metals such as lithium (Li) and cesium (Cs), and alkaline earth metals such as magnesium (Mg), calcium (Ca), and strontium (Sr), and alloy materials containing any of these (MgAg, Rare earth metals such as AlLi), europium (Er), ytterbium (Yb), and alloy materials containing these can be used. Further, indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc oxide added with gallium (GZO), indium tin oxide containing silicon oxide (ITSO), oxidation of 2 wt% to 20 wt% An oxide conductive material such as indium oxide containing zinc (ZnO) can also be used.

  A conductive layer formed using the above material is selectively etched to form a first electrode layer 5371a, a first electrode layer 5371b, and a wiring layer 5538 which form a memory element (FIG. 16). (See (A)). The first electrode layer 5371a is connected to the transistor 5454. The first electrode layer 5371b is connected to the transistor 5453. The wiring layer 5538 functions as a wiring for electrically connecting the transistor 5451 and a conductive layer functioning as an antenna to be formed later.

  Next, an insulating layer is formed to cover the first electrode layer 5371a, the first electrode layer 5371b, and the wiring layer 5538. The insulating layer is formed using an inorganic insulating material such as silicon oxide or silicon nitride, an organic insulating material such as acrylic, polyimide, or resist, or a material containing a siloxane bond. The insulating layer is formed by a sputtering method, a CVD method, a coating method, or the like depending on a material to be used.

  Next, the insulating layer is selectively etched to expose the first electrode layer 5371a and the first electrode layer 5371b. The remaining insulating layer is a partition layer 5374. A partition layer 5374 is formed so as to cover end portions of the first electrode layer 5371a and the first electrode layer 5371b (see FIG. 16A). In addition, for the insulating layer over the wiring layer 5538, a contact hole is formed so that a terminal electrode layer connected to the conductive layer functioning as an antenna can be formed, and part of the wiring layer 5538 is exposed. Note that in the case where a positive photosensitive resin in which an unexposed portion remains is used as the insulating layer, the process can be shortened because the insulating layer can be formed only by an exposure process and a development process.

  Next, a layer 5372 containing an organic compound is formed over the first electrode layer 5371a and the first electrode layer 5371b (see FIG. 16B). The layer 5372 containing an organic compound is formed by an evaporation method, an electron beam evaporation method, a sputtering method, or a CVD method using an organic compound whose conductivity changes by an optical action or an electric action, or an organic compound whose shape changes. A single layer structure or a laminated structure is used. The memory element having the layer 5372 containing the organic compound can store two values corresponding to the “initial state” and the “state after change” before and after the change in conductivity or shape. As the layer 5372 containing such an organic compound, specifically, organic resins such as polyimides, polyacrylic acid esters, and polymethacrylic acid esters, organic compounds having a hole transporting property, or organic compounds having an electron transporting property Can be used. Note that a material and a manufacturing method which can be specifically used as the layer 5372 containing an organic compound are according to the description of the memory element 100 in Embodiment 1.

Next, the second electrode layer 5373 is formed over the layer 5372 containing an organic compound (see FIG. 16B). The second electrode layer 5373 is a metal element, alloy material, or compound having a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less so that the Young's modulus is 7.5 × 10 ¹⁰ N / m ² or less. Using a material, the film is formed by an evaporation method, a sputtering method, a printing method, or a droplet discharge method. In the case of using an alloy material or a compound material, it is preferable to include a metal element having a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less. For example, the second electrode layer 5373 includes indium (In), barium (Ba), lead (Pb), calcium (Ca), bismuth (Bi), magnesium (Mg), tin (Sn), aluminum (Al), and the like. Or an alloy material or compound material containing the metal element can be used. The thickness of the second electrode layer 5373 is not particularly limited, but is preferably about 10 nm to 200 nm, and more preferably about 10 nm to 100 nm. Specifically, materials and the like that can be used for the second electrode layer 5373 are according to the description of the memory element 100 in Embodiment 1.

  In addition, when the second electrode layer 5373 is formed, the terminal electrode layer 5360 is also formed. The terminal electrode layer 5360 serves to connect the conductive layer functioning as an antenna formed in an upper layer and the transistor 5451. The terminal electrode layer 5360 is the same layer as the second electrode layer 5373 and is formed so as to fill a contact hole formed so that the wiring layer 5538 is exposed.

  Note that here, the first electrode layers 5371a and 5371b, and the partition wall layer 5374 covering end portions of the first electrode layers 5371a and 5371b, a layer 5372 containing an organic compound as a common layer, and a second electrode layer Although 5373 is stacked, it is not particularly limited. For example, a separated layer containing an organic compound and a second electrode layer may be selectively provided over the first electrode layer 5371a and the first electrode layer 5371b.

  Next, a conductive layer 5353 functioning as an antenna is formed in contact with the terminal electrode layer 5360 (see FIG. 16B). The conductive layer 5353 is formed using a conductive material by various printing methods such as an evaporation method, a sputtering method, screen printing, or gravure printing, or a droplet discharge method. Specifically, the conductive layer 5353 includes gold (Au), platinum (Pt), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), aluminum (Al), A single-layer structure or a stacked-layer structure is formed using a metal element such as manganese (Mn) or titanium (Ti) or an alloy material or a compound material containing the metal element.

  Next, an insulating layer 5366 functioning as a protective layer is formed over the second electrode layer 5373, the partition wall layer 5374, the terminal electrode layer 5360, and the conductive layer 5353 (see FIG. 16B). The insulating layer 5366 is formed by a sputtering method, a CVD method, or the like using an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. Note that the insulating layer 5366 may be formed as necessary and may not be provided. Up to this point, a stacked body up to the second electrode layer 5373 stacked above the insulating layer 5104 is referred to as an element formation layer 5541.

  Next, the insulating layer 5540 is formed over the second electrode layer 5373 with the insulating layer 5366 interposed therebetween, and the substrate 5500 is attached to the surface of the insulating layer 5540 (see FIG. 17A). The insulating layer 5540 is an acrylic resin, polyimide resin, melamine resin, polyester resin, polycarbonate resin, phenol resin, epoxy resin, polyacetal, polyether, polyurethane, polyamide (nylon), furan resin, diallyl phthalate resin, or other organic resin, silica An inorganic siloxane polymer containing a Si-O-Si bond among compounds composed of silicon, oxygen, and hydrogen formed from a siloxane polymer-based material typified by glass, or an alkylsiloxane polymer, an alkylsilsesquioxane polymer, Using hydrogenated silsesquioxane polymer, organic siloxane polymer in which hydrogen bonded to silicon represented by hydrogenated alkylsilsesquioxane polymer is substituted by organic groups such as methyl and phenyl These materials can be formed by dry heating applied by a coating method. The insulating layer 5540 is preferably formed by a coating method because surface unevenness can be reduced. The insulating layer 5540 may be formed by forming an insulating layer such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide by a CVD method, a sputtering method, or the like, and then polishing the surface by a CMP method. The insulating layer 5540 also functions as a protective layer in a subsequent peeling step.

  Although the substrate 5500 is bonded to the surface of the insulating layer 5540 here, there is no particular limitation, and the substrate 5500 may be directly bonded to the second electrode layer.

  The substrate 5500 is preferably a flexible substrate, and more preferably a thin and light substrate. Specifically, the substrate 5500 is made of PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PES (polyethersulfone), polypropylene, polypropylene sulfide, polycarbonate, polyetherimide, polyphenylene sulfide, polyphenylene oxide, polysulfone, polyphthal. A plastic substrate such as amide can be used. Also, paper made of a fibrous material, a laminated film of a base film (polyester, polyamide, inorganic vapor deposition film, paper, etc.) and an adhesive organic resin film (acrylic organic resin, epoxy organic resin, etc.) are used. You can also In addition, a film having an adhesive layer (made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, or the like) that can be bonded to the object to be processed by thermocompression bonding can be used. These films are bonded to the object by melting the adhesive layer provided on the outermost surface of the film or the layer provided on the outermost layer (a layer that is not an adhesive layer) by heat treatment and adhering it by pressure. Is possible. Note that here, the object to be processed refers to a stacked body from the insulating layer 5540 to the substrate 5100 that is stacked below, and the surface to be processed is a surface that does not contact the second electrode layer 5373 of the insulating layer 5540.

  Note that in the case of using a non-adhesive plastic substrate or the like as the substrate 5500, an adhesive layer is provided between the insulating layer 5540 and the substrate 5500, and the insulating layer 5540 and the substrate 5500 are attached to each other. In the case where an adhesive substrate (film) is used as the substrate 5500, it is not necessary to separately provide an adhesive layer between the insulating layer 5540 and the substrate 5500.

  In this embodiment mode, an epoxy resin composition is applied by a coating method, and dried and fired to form an insulating layer 5540 made of an epoxy resin. A film having an adhesive layer is used as the substrate 5500, and a film which is the substrate 5500 is thermocompression bonded to the surface of the insulating layer 5540 so that the insulating layer 5540 and the substrate 5500 are bonded to each other.

  Next, the element formation layer 5541 is separated from the substrate 5100 by separation between the separation layer 5102 and the insulating layer 5104 and transferred to the substrate 5500 (see FIG. 17B).

As an example of a method for peeling the element formation layer 5541 from the substrate 5100, (1) a stacked structure of a layer including a metal layer and a metal oxide (or metal nitride) as a separation layer between the substrate and the element formation layer is used. A method in which the layer containing the metal oxide is weakened by crystallization and the element formation layer is physically separated from the substrate; (2) a metal layer and a metal oxide as a separation layer between the substrate and the element formation layer; A layer structure including an oxide (or metal nitride) is provided, the layer including the metal oxide is weakened by crystallization, and a part of the release layer is fluorinated with a solution, NF ₃ , BrF ₃ , ClF ₃ or the like. A method of physically peeling the element formation layer from the substrate after etching away with a halogen gas, and (3) forming a separation layer using amorphous silicon containing hydrogen between the substrate and the element formation layer. Irradiate the release layer with a laser beam to (4) A release layer is formed using amorphous silicon between the substrate and the element formation layer, and the release layer is removed by etching with a solution or a halogen fluoride gas. (5) The substrate on which the element formation layer is formed (the substrate 5100 in this embodiment) is mechanically shaved or removed by etching with a solution, halogen fluoride gas such as NF ₃ , BrF ₃ , or ClF ₃ The method of peeling off and the like can be selected as appropriate. For the above-described peeling methods (1) and (2), a peeling layer and an insulating layer are formed between the substrate and the element formation layer, and a metal oxide (or metal nitridation) is formed between the peeling layer and the insulating layer. And a layer containing the metal oxide may be weakened by crystallization. In this embodiment, a tungsten layer and a layer containing an oxide of tungsten are provided as the separation layer 5102. The layer containing the oxide of tungsten is weakened when the semiconductor layer of the transistor provided in the upper layer is crystallized. Therefore, here, after the substrate 5500 is fixed to the element formation layer 5541, the element formation layer 5541 is physically separated from the substrate 5100. Note that the substrate 5100 from which the element formation layer 5541 is peeled is preferably reused for cost reduction.

  Next, the substrate 5600 is attached to the surface where the substrate 5100 is peeled and the insulating layer 5104 is exposed (see FIG. 18). The substrate 5600 is preferably a flexible substrate. Specifically, a substrate similar to the substrate 5500 can be used. In this embodiment, a film having an adhesive layer is used as the substrate 5600, and the film which is the substrate 5600 is thermocompression bonded to the surface of the insulating layer 5104, so that the insulating layer 5104 and the substrate 5600 are attached to each other. Through the above steps, the element formation layer 5541 can be sandwiched between flexible substrates.

  Note that after the element formation layer 5541 is transferred to the substrate 5500, the substrate 5500 may be peeled off. For example, after the element formation layer 5541 is peeled from the substrate 5100 which is a supporting substrate and transferred to the substrate 5500, the substrate 5600 is attached to the element formation layer 5541, and the element formation layer 5541 is peeled from the substrate 5500 and transferred to the substrate 5600. It is also possible to do.

  Through the above steps, a semiconductor device including a memory element and an antenna can be manufactured. In addition, a flexible semiconductor device can be manufactured. By applying the present invention, it is possible to prevent the element from being defective during the transposition process. Therefore, a semiconductor device with high yield and high reliability can be provided.

  Next, examples in which the semiconductor device of the present invention capable of reading and writing data without contact as shown in FIGS. 14A and 14B is used for various purposes will be described with reference to FIGS.

  FIG. 13 shows an example in which the semiconductor device according to the present invention is applied as a wireless chip. For example, a wireless chip 9210 to which the semiconductor device according to the present invention is applied includes banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 13A), recording medium ( DVD software, videotape, etc., see FIG. 13B), packaging containers (wrapping paper, bottles, etc., see FIG. 13C), vehicles (bicycles, etc., see FIG. 13D), personal items (Such as bags and glasses), foods, plants, clothing, daily necessities, electronic products, etc., and goods such as luggage tags (see FIGS. 13E and 13F) are used. be able to. It can also be attached to or embedded in animals or the human body. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also simply referred to as televisions, television receivers, television receivers), mobile phones, and the like.

  The semiconductor device of the present invention (for example, the wireless chip 9210 in FIGS. 13A to 13F) is fixed to an article by being mounted on a printed board, attached to a surface, or embedded. For example, in the case of a book, it is embedded in paper, and in the case of a package made of an organic resin, it is fixed to each article by being embedded in the organic resin. Since the semiconductor device of the present invention realizes a small size, a thin shape, and a light weight, the design of the article itself is not impaired even after being fixed to the article. In addition, by providing the semiconductor device of the present invention in bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and if this authentication function is utilized, counterfeiting can be prevented. it can. In addition, by providing the semiconductor device of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved.

  Note that this embodiment can be implemented in combination with any of Embodiments 1 to 4 as appropriate.

(Embodiment 7)
In this embodiment, an example of an electronic device in which the semiconductor device of the present invention is mounted is described with reference to FIGS.

  The electronic device illustrated in this embodiment is a mobile phone, which includes a housing 2700, a housing 2706, a panel 2701, a housing 2702, a printed wiring board 2703, operation buttons 2704, and a battery 2705. The panel 2701 is detachably incorporated in the housing 2702, and the housing 2702 is fitted on the printed wiring board 2703. The shape and dimensions of the housing 2702 are changed as appropriate in accordance with the electronic device in which the panel 2701 is incorporated. A plurality of packaged semiconductor devices are mounted on the printed wiring board 2703, and the semiconductor device of the present invention can be applied as one of them. Specifically, the semiconductor device including the memory element described in the above embodiment is applied. The plurality of semiconductor devices mounted on the printed wiring board 2703 have any one function of a controller, a central processing unit (CPU), a memory, a power supply circuit, a sound processing circuit, a transmission / reception circuit, and the like.

  The panel 2701 is connected to the printed wiring board 2703 through the connection film 2708. The panel 2701, the housing 2702, and the printed wiring board 2703 are housed in the housings 2700 and 2706 together with the operation buttons 2704 and the battery 2705. A pixel region 2709 included in the panel 2701 is arranged so as to be visible from an opening window provided in the housing 2700.

  As described above, the semiconductor device of the present invention is characterized in that it is small, thin, and lightweight, and the limited space inside the housings 2700 and 2706 of the electronic device can be effectively used due to the above characteristics. .

  Further, since the present invention includes a semiconductor device having a memory element with a simple structure in which a layer containing an organic compound that changes when an external voltage is applied is sandwiched between a pair of electrode layers, the manufacturing cost of the semiconductor device can be reduced. It becomes possible to provide an inexpensive electronic device. Further, since the semiconductor device of the present invention can be easily integrated, an electronic device having a large-capacity memory circuit can be provided.

  In addition, a semiconductor device having a memory element according to the present invention writes data by applying voltage from the outside, is nonvolatile, and can additionally write data. With the above feature, forgery due to rewriting can be prevented, and new data can be added and written. Accordingly, it is possible to provide an electronic device that achieves high functionality and high added value.

  Note that the housings 2700 and 2706 are examples of the appearance of a mobile phone, and the electronic device according to this embodiment can be modified into various modes depending on functions and uses.

  This embodiment mode can be combined with any of Embodiment Modes 1 to 6 as appropriate.

  In this example, a memory element is manufactured using the present invention, and a result of performing a transposition process is shown.

On the glass substrate, on the titanium layer as the first electrode layer, on the polyimide layer having a thickness of 1.5 μm as the partition layer covering a part (end) of the first electrode layer, on the first electrode layer and the partition layer A sample was prepared by sequentially laminating a calcium fluoride layer (CaF ₂ ) having a thickness of 1 nm as an insulating layer, an NPB layer having a thickness of 10 nm as a layer containing an organic compound, and a second electrode layer. In this example, samples 1 to 14 were manufactured by changing the material and manufacturing method of the second electrode layer. In addition, Comparative Examples 1 to 3 using silver (Ag), zinc (Zn), and copper (Cu) as the second electrode layer were produced.

In this embodiment, after the partition layer using polyimide is formed so as to have an opening on the first electrode layer, oxygen (O 2 O) is used to remove the polyimide residue on the first electrode layer. ₂ ) Ashing was performed.

  Next, the second electrode layer formed from Sample 1 to Sample 14 will be described. Sample 1 is an indium layer (film thickness 200 nm), sample 2 is a calcium layer (film thickness 150 nm), sample 3 is a tin layer (film thickness 200 nm), sample 4 is an aluminum layer (film thickness 100 nm), and sample 5 is an indium tin alloy Layer (thickness 200 nm), sample 6 is a layer (thickness 200 nm) formed by vapor deposition of indium tin alloy and indium in the same boat, and sample 7 has a tin content of 10 wt% with respect to indium. A layer formed by co-evaporation of indium and tin (thickness: 200 nm), and Sample 8 was formed by co-evaporation of indium and tin so that the content of tin was 1 wt% with respect to indium (film) Sample 9 has a layer (thickness of 200 nm) and an aluminum layer (thickness of 20 nm) formed by co-evaporation of indium and tin so that the content of tin is 10 wt% with respect to indium. sample 10 is a layer (thickness 200 nm) formed by co-evaporation of indium tin alloy and chromium so that the ratio of indium tin alloy to chromium is 10: 1, and sample 11 is indium A layer (thickness 150 nm) formed by co-evaporation of indium and magnesium so that the magnesium content is 10 wt%, Sample 12 is a laminate of an indium layer (thickness 100 nm) and an aluminum layer (thickness 200 nm), Sample 13 Is a stack of an indium tin alloy placed in the same boat, a layer formed by vapor deposition of indium (film thickness 100 nm) and an aluminum layer (film thickness 100 nm). Sample 14 is made of indium tin alloy and indium placed in the same boat. A stack of layers formed by vapor deposition (film thickness 200 nm) and an aluminum layer (film thickness 10 nm) is used as the second electrode layer. Form was. Samples 1 to 4 and Sample 12 were formed by vapor deposition using the respective materials.

  Comparative Example 1 formed a silver layer (film thickness 200 nm), Comparative Example 2 formed a zinc layer (film thickness 200 nm), and Comparative Example 3 formed a copper layer (film thickness 200 nm) as a second electrode layer. Comparative Examples 1 to 3 were formed by vapor deposition using the respective materials.

  An epoxy resin was applied to the memory element of Sample 1 produced on a glass substrate by stencil printing and heated at 110 ° C. for 60 minutes in a nitrogen atmosphere to form an epoxy resin layer having a thickness of 100 μm to 200 μm. Thereafter, the memory element of Sample 1 was peeled from the glass substrate and transferred to the epoxy resin layer. Table 1 shows the transposed state of the memory element of Sample 1 transposed to the epoxy resin layer. Similarly to Sample 1, an epoxy resin was applied by stencil printing on the memory elements of Samples 2 to 14 and Comparative Examples 1 to 3 fabricated on a glass substrate, respectively, and heated at 110 ° C. for 60 minutes in a nitrogen atmosphere. Then, an epoxy resin layer having a thickness of 100 μm to 200 μm was formed. Thereafter, the memory elements of Samples 2 to 14 and Comparative Examples 1 to 3 were each peeled from the glass substrate and transferred to the epoxy resin layer. Table 1 shows the transposed state of the memory elements of Samples 2 to 14 and Comparative Examples 1 to 3 that were transposed to the epoxy resin layer. In Table 1, “-” represents an alloy, and for example, “In—Sn” represents an indium tin alloy. “+” Indicates that deposition was performed using a material placed in the same boat. For example, “(In−Sn) + In” indicates that an indium tin alloy and indium were deposited in the same boat. “:” Indicates co-evaporation, for example, “In: Sn” indicates that indium and tin are co-evaporated. “\” Indicates a laminated structure, and what is indicated on the right side is higher than what is indicated on the left side. For example, “In \ Al” indicates a laminated structure of indium and aluminum, and aluminum is the upper layer.

  Samples 1 to 14 produced using the present invention could be peeled off in good condition with no visual film peeling or peeling residue. On the other hand, in Comparative Examples 1 to 3, only the second electrode layer (silver layer, zinc layer, copper layer) was transferred to the epoxy resin layer, and the entire memory element could not be peeled from the glass substrate.

Here, FIG. 22 and Table 2 show the mechanical properties of the metal elements. In the bar graph shown in FIG. 22, the horizontal axis indicates the type of metal element, and the vertical axis indicates the Young's modulus (10 ¹⁰ N / m ² ). In addition, the Young's modulus of the metal element shown below was extracted from Iwanami Dictionary of Physical and Chemical Dictionary 5th edition.

  In FIG. 22, the metal elements are arranged in the order of In, Ba, Pb, Ca, Bi, Mg, Sn, Al, Ag, Zn, Cu, Mn, and Ni from the left side on the horizontal axis, and the Young's modulus increases toward the right side. You can see that is getting bigger. Table 2 shows specific numerical values of the Young's modulus of the metal elements shown in FIG.

  Further, in FIG. 22, the peeling shown in Table 1 is performed well, and the metal element that has been successfully transposed is circled. On the other hand, metal elements that have poor peeling characteristics and failed to be transposed are surrounded by a square.

  As is clear from FIG. 22 and Table 1, metal elements (including aluminum) on the left side of aluminum, that is, metal elements (including aluminum) having a Young's modulus smaller than that of aluminum are favorably peeled and transposed. Has been successful. On the other hand, metal elements (including silver) on the right side of silver, that is, metal elements having a higher Young's modulus than silver have poor peeling properties, and transposition has failed, which is outside the scope of the present invention. . Therefore, a metal element having a Young's modulus lower than that of silver was excellently peeled off.

  In the element transfer process, the element is inevitably bent in a process of peeling the element from a substrate (supporting substrate such as a glass substrate) or a process of attaching a substrate (a flexible substrate) to the element. In addition, the flexible substrate and the element can be bonded with relatively high adhesion using a method such as thermocompression bonding. That is, the second electrode layer which is not in contact with the supporting substrate and is bonded to the flexible substrate is bonded to the flexible substrate with good adhesion.

  As shown in the above mathematical formula (1), the substance (electrode layer) is more easily deformed as the Young's modulus is smaller, and is more difficult to deform as the Young's modulus is larger. Therefore, when the Young's modulus of the second electrode layer is larger than a certain value, the second electrode layer is hardly deformed and is adhered to the flexible substrate with good adhesion, so that the element is bent. It is considered that the device cannot be tuned and the element is destroyed.

In this example, it can be seen from the results shown in Table 1, FIG. 22 and the like that the Young's modulus between aluminum and silver has the criticality of device destruction in the transposition process. From Table 2, the Young's modulus of aluminum is 7.06 × 10 ¹⁰ N / m ² , and the Young's modulus of silver is 8.27 × 10 ¹⁰ N / m ² . In the present invention, when the Young's modulus of the second electrode layer is a Young's modulus equal to or less than the value between aluminum and silver, the element can be peeled in a good state, and a successful transposition can be expected. Therefore, when the Young's modulus of the second electrode layer is 7.5 × 10 ¹⁰ N / m ² , and the Young's modulus of the second electrode layer is preferably 7.5 × 10 ¹⁰ N / m ² or less, the transposition is performed. Can be performed satisfactorily.

  In this example, a result of manufacturing a semiconductor device having a memory element according to the present invention by performing a transposition process, and a result of evaluating characteristics of the semiconductor device having the memory element are shown. In this embodiment, an aluminum layer is formed as the second electrode layer. The manufacture of the semiconductor device according to this example will be described with reference to a schematic diagram shown in FIG.

  A separation layer 7002 was formed over the first substrate 7000 and an element layer 7004 was formed over the separation layer 7002. An insulating layer 7009 was formed over the element layer 7004, and a second substrate 7019 was attached to the surface of the insulating layer 7009 (see FIG. 23A).

  As the first substrate 7000, a glass substrate was used. As the separation layer 7002, a stacked structure of a metal layer and a metal oxide layer was formed, specifically, a stacked structure of a tungsten layer and a layer containing an oxide of tungsten. Note that here, after a tungsten layer was formed, an insulating layer was formed over the tungsten layer, whereby a layer containing an oxide of tungsten was formed at the interface between the insulating layer and the tungsten layer.

  In the element layer 7004, a semiconductor element 7006 and a memory element 7008 electrically connected to the semiconductor element 7006 were formed. In addition, a conductive layer functioning as an antenna was formed in the element layer 7004. Note that FIG. 23 illustrates a configuration other than the memory element 7008 in a simplified manner.

The memory element 7008 has a structure according to the present invention, specifically, a titanium layer as the first electrode layer 7010 and a calcium fluoride (CaF ₂ ) layer with a thickness of 1 nm as the insulating layer 7012 over the first electrode layer 7010. A 10-nm-thick 9- [4- (N-carbazolyl)] phenyl-10-phenylanthracene (abbreviation: CzPA) layer, a layer 7014 containing the organic compound, and a layer 7014 containing an organic compound over the insulating layer 7012 In addition, an aluminum layer having a thickness of 75 nm was sequentially stacked as the second electrode layer 7016. The first electrode layer 7010 and the second electrode layer 7016 were formed by a sputtering method. The insulating layer 7012 and the layer 7014 containing an organic compound were formed by an evaporation method.

  The insulating layer 7009 was formed using an organic resin, specifically, an epoxy resin. As the second substrate 7019, a flexible substrate was used. Specifically, a film having an adhesive layer was attached to the surface of the insulating layer 7009.

  Next, the element layer 7004 was peeled from the first substrate 7000, and the element layer 7004 was transferred to the second substrate 7019 (see FIG. 23B).

  Peeling occurred at the interface between the peeling layer 7002 and the element layer 7004 or in the peeling layer 7002, and the element layer 7004 was physically peeled from the first substrate 7000.

  Next, a third substrate 7020 was attached to the surface from which the first substrate 7000 was peeled and the element layer 7004 was exposed (see FIG. 23C). As the third substrate 7020, a flexible substrate was used.

  Thus, a semiconductor device having a memory element transferred to a flexible substrate was obtained.

  In this example, Sample A and Sample B in which 50 semiconductor devices were formed on one substrate were manufactured. The configurations of the sample A and the sample B are the same, and 50 semiconductor devices are formed on one substrate. Each semiconductor device is provided with a semiconductor element, a memory element, and an antenna. It is assumed that 64 memory elements are formed in 50 semiconductor devices formed in Sample A and Sample B, respectively. A schematic diagram of the upper surface is shown in FIG. 24, and individual semiconductor devices are indicated by dotted lines.

  When an appearance inspection was performed on the sample A with an optical microscope, the memory element was able to be transposed without destruction in 50 semiconductor devices, and the transposition success rate was 100%. Further, in the sample B, when an appearance inspection was performed using an optical microscope as in the case of the sample A, the memory elements were transferred without destruction in 47 semiconductor devices, and the transfer success rate was 94%. . Therefore, it was found that the transposition can be favorably performed by using an aluminum layer as the second electrode layer.

  Next, FIG. 25 shows a writing success rate when data is written to the memory elements formed in the sample A and the sample B without contact. Here, a result of performing writing to the storage element wirelessly using a reader / writer is shown.

  FIG. 25A shows the writing rate of sample A, and FIG. 25B shows the writing rate of sample B. FIG. 25A shows that data can be written to the memory element at a rate of 93% by a single write command from the reader / writer. Further, FIG. 25B shows that data can be written into the memory element by a single write command from the reader / writer at a rate of 97%. That is, it can be seen that the data can be written to the memory element at a rate of 95% or more on the average of the sample A and the sample B by a single write command from the reader / writer. 25A and 25B, it can be seen that data can be written to the memory element at a rate of 100% by a write command within 10 times from the reader / writer. Therefore, it was found that Sample A and Sample B have a good writing rate, and the memory element according to the present invention can write data well even after transposition.

  Next, a writing rate when data is written to a memory element in a non-contact manner after storing a semiconductor device obtained from the sample A or the sample B and judged to have been successfully transferred by appearance inspection under certain conditions is shown in FIG. 26. Here, a result of performing writing to the storage element wirelessly using a reader / writer is shown.

  Here, a fixed time (0 hour, 60 hours, 120 hours, 240 hours) under any of the conditions of high temperature (+ 80 ° C.), low temperature (−40 ° C.), room temperature, or thermal shock (−45 ° C. to + 85 ° C.) , 500 hours, or 1000 hours), after storing a predetermined number of storage elements, the storage elements were wirelessly written using a reader / writer. Here, eight memory elements each of the four semiconductor devices, that is, 32 memory elements, were stored under certain conditions and then written.

  In addition, the thermal shock preservation | save in a present Example shows storing repeatedly high temperature preservation | save and low temperature preservation | save. Here, storage for 30 minutes at + 85 ° C. and storage for 30 minutes at −45 ° C. were repeated.

  26A shows the writing rate of the memory element stored at high temperature (+ 85 ° C.), FIG. 26B shows the writing rate of the memory element stored at low temperature (−40 ° C.), and FIG. 26C shows the memory element stored at room temperature. FIG. 26D shows the writing rate of the memory element preserved by thermal shock.

  26 (A) and 26 (C), no more than 3 times after storage at high temperature (+ 85 ° C) or room temperature for 0, 60, 120, 240, 500, or 1000 hours It can be seen that data can be written by the write command.

  In addition, from FIG. 26 (B) and FIG. 26 (D), even after storing for 0 hours, 60 hours, 120 hours, 240 hours, or 500 hours under a condition of applying a low temperature (−40 ° C.) or thermal shock, It can be seen that data can be written by a write command within three times.

  The results shown in FIGS. 26A to 26D are shown in Table 3 below. In Table 3, the case where data can be written by a write command within 100 times is indicated by a circle (◯).

  From the results of FIG. 26 and Table 3, the memory elements of Sample A and Sample B have a good writing rate, and the memory elements according to the present invention write data even after being stored under certain conditions after transposition. Was found to be good.

  In addition, when data is written in a non-contact manner to a memory element of a semiconductor device obtained from the sample A or the sample B and judged to have been successfully transferred by appearance inspection, the memory element of the semiconductor device is stored under certain conditions. Table 4 below shows the results of evaluating the presence or absence of data fluctuation.

  Here, data was written to the memory element wirelessly using a reader / writer. In addition, the storage condition after the data is written is a high temperature (+ 80 ° C.), a low temperature (−40 ° C.), a thermal shock (−45 ° C. to + 85 ° C.), or a room temperature for a certain time (60 hours). 120 hours, 240 hours, 500 hours, or 1000 hours), a predetermined number of storage elements were stored.

  In Table 4, the denominator indicates the number of semiconductor devices evaluated, and the numerator indicates the number of semiconductor devices whose data fluctuates after storage under a certain condition. Evaluation is performed on 64 memory elements included in each semiconductor device, and the number of memory elements whose data has changed after storage under a certain condition is shown in parentheses. In the parentheses, the denominator indicates the number of evaluated storage elements, and the numerator indicates the number of storage elements whose data has changed after storage under a certain condition. The number of memory elements as denominators in parentheses is obtained by multiplying the number of evaluated semiconductor devices by 64.

  From the results shown in Table 4, the probability that data variation was observed among the evaluated storage elements was 0.1% or less, and the storage element according to the present invention was able to store data under certain conditions after data writing. The probability of fluctuation was found to be very low.

The figure which shows the example of the element structure of this invention. The figure which shows the example of the element structure of this invention. The figure which shows the example of the element structure of this invention. FIG. 11 illustrates an example of a semiconductor device of the invention. 4A and 4B are a top view and a cross-sectional view illustrating an example of a semiconductor device of the invention. FIG. 14 is a cross-sectional view illustrating an example of a semiconductor device of the invention. FIG. 11 illustrates an example of a semiconductor device of the invention. 4A and 4B are a top view and a cross-sectional view illustrating an example of a semiconductor device of the invention. FIG. 11 illustrates an example of a display device of the present invention. FIG. 11 illustrates an example of a semiconductor device of the invention. 4A and 4B illustrate an example of a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate an example of a method for manufacturing a semiconductor device of the present invention. FIG. 11 illustrates an example of a semiconductor device of the invention. FIG. 11 illustrates an example of a semiconductor device of the invention. 4A and 4B illustrate an example of a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate an example of a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate an example of a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate an example of a method for manufacturing a semiconductor device of the present invention. FIG. 11 illustrates an example of a semiconductor device of the invention. FIG. 13 illustrates an example of an equivalent circuit of a pixel portion in a display device of the present invention. FIG. 9 is a diagram illustrating an example of a conventional semiconductor device. The figure which shows the mechanical property of a metal element. 4A and 4B illustrate an example of a method for manufacturing a semiconductor device of the present invention. FIG. 4 is a schematic view of the top surface of the semiconductor device of the present invention. The figure which showed the evaluation result of the semiconductor device of this invention. The figure which showed the evaluation result of the semiconductor device of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Memory element 102 1st electrode layer 104 Layer 106 containing an organic compound 2nd electrode layer 108 Layer 110 Memory element

Claims (10)

A flexible substrate;
A memory element on the flexible substrate;
Have
The memory element has a layer containing an organic compound between the first electrode layer and the second electrode layer,
The second electrode layer has a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less. A flexible substrate;
A light emitting element on the flexible substrate;
Have
The light-emitting element has a layer containing an organic compound between the first electrode layer and the second electrode layer,
The second electrode layer has a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less. In claim 1 or claim 2,
The semiconductor device, wherein the second electrode layer has a thickness of 10 nm to 200 nm. In any one of Claim 1 thru | or 3,
The second electrode layer is made of indium (In), barium (Ba), lead (Pb), calcium (Ca), bismuth (Bi), magnesium (Mg), tin (Sn), or aluminum (Al). A semiconductor device including at least one. Forming a release layer on the first substrate;
A first electrode layer on the release layer;
A layer containing an organic compound on the first electrode layer;
Forming an element layer having a second electrode layer having a Young's modulus of 7.5 × 10 ¹⁰ N / m ² or less on the layer containing the organic compound;
A method for manufacturing a semiconductor device, comprising: fixing the element layer to a second substrate; and then peeling the first substrate from the element layer. In claim 5,
The method for manufacturing a semiconductor device, wherein the second electrode layer included in the element layer has a thickness of 10 nm to 200 nm. In claim 5 or claim 6,
A method for manufacturing a semiconductor device, comprising: peeling a first substrate from the element layer; and fixing a flexible third substrate to the element layer. In any one of Claims 5 thru | or 7,
A method for manufacturing a semiconductor device, wherein a flexible substrate is used as the second substrate. In any one of Claims 5 thru | or 8,
The second electrode layer is made of indium (In), barium (Ba), lead (Pb), calcium (Ca), bismuth (Bi), magnesium (Mg), tin (Sn), or aluminum (Al). A method for manufacturing a semiconductor device, characterized by forming using a material including at least one of them. In any one of Claims 5 thru | or 9,
A method for manufacturing a semiconductor device, wherein a memory element, a light-emitting element, a piezoelectric element, or an organic transistor element is formed in the element layer.

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