JP2007059785A - Semiconductor manufacturing equipment, semiconductor manufacturing method, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing equipment which can easily form a desired circuit by printing treatment in a wafer state after wafer testing; a and also to provide semiconductor manufacturing method and a semiconductor device. <P>SOLUTION: A drawing pattern printer of a semiconductor manufacturing equipment includes a printing head which injects a conductive solvent, an insulating solvent, and an interface treatment liquid, respectively. The printing head is constructed so as to be able to print the desired circuit drawing pattern for the wafer based on the information of the drawing pattern from the wafer tester, the information for the wafer from a memory, and coordinate information from a chip coordinate recognition portion. In the semiconductor manufacturing method, the desired circuit is formed by printing treatment using the semiconductor manufacturing equipment to manufacture a semiconductor device, and a pad electrode, etc. are formed to enable a trimming treatment by circuit drawing pattern printing in the semiconductor device. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor manufacturing apparatus for manufacturing a semiconductor device such as a semiconductor integrated circuit, a semiconductor manufacturing method using the semiconductor manufacturing apparatus, and a semiconductor device manufactured by the semiconductor manufacturing method.

  Semiconductor integrated circuits (hereinafter abbreviated as ICs) are variously formed by forming active elements such as CMOS and bipolar transistors on the wafer and passive elements such as resistors and capacitors, and further providing metal wiring for connecting them. The function is formed and the wafer manufacturing process is completed. After completion of the wafer manufacturing process, an inspection for quality confirmation as an IC product, a so-called wafer test is performed in a wafer state before dicing. In this wafer test, an IC that satisfies a preset characteristic standard value is selected, and an IC that does not satisfy the characteristic standard value is rejected and discarded. The characteristic standard value is set with a certain allowable range in consideration of the purpose of use of the IC.

  However, in recent years, with the goal of improving the sensitivity of detection signals in sensor ICs, wafer tests have been performed with the tolerance range of characteristic standard values being narrowed as much as possible to improve conversion efficiency in power conversion ICs. Inspections are being conducted to obtain ICs. However, when a wafer test is performed with the tolerance range of the characteristic standard value narrowed, defective products that are rejected (discharged) increase in the IC manufactured by the conventional semiconductor manufacturing method, resulting in an increase in manufacturing cost. It was.

Therefore, it will become an even more important and necessary technology in the future to create products that fall within the allowable range of the characteristic specification value by adjusting (trimming) the characteristic value of the IC that did not satisfy the characteristic specification value after the wafer test. ing. Various “trimming techniques” have been proposed. Typical “trimming technologies” include “laser trimming” in which a part of wiring is cut with a laser beam, “Zener Zapping” in which a Zener diode is forcibly avalanche broken to form a filament, and memory There are techniques such as “digital trimming” for adjusting circuit characteristics by writing digital data to an element, and “wiring formation trimming” for newly forming electric circuit wiring.
Japanese Patent Laid-Open No. 5-291589 JP 2004-273679 A

  As described above, various techniques have been proposed as "trimming techniques" after wafer testing. However, an expensive device is required for the trimming process, and elements and trimming circuits that may become unnecessary are added to the wafer. Since it must be formed in advance, there is a problem in that the manufacturing cost is increased.

  In “wiring formation trimming”, a special drawing pattern corresponding to the test result is formed on the thin film after the wafer test, and the thin film is attached to the corresponding position of the wafer to form the trimming wiring. (For example, refer to Patent Document 1). However, with this trimming technique, it is very difficult to perform wiring with high accuracy, and high quality ICs cannot be manufactured with a high yield.

  Furthermore, in “wiring formation trimming”, openings that expose electrode terminal groups are formed in advance on the wafer, and metal electrodes are applied to the corresponding openings at the time of trimming to connect desired electrode terminals to each other. And the trimming technique which apply | coats sealing resin on it is proposed (for example, refer patent document 2). However, in the conventional “wiring formation trimming” as described above, a metal paste is applied to a certain wide area on a desired electrode terminal group to form a metal paste layer and electrically connect. Adjustment was difficult. In addition, in order to prevent peeling of the metal paste layer formed on the electrode terminal, a sealing resin layer must be formed on the upper part of the metal paste layer, which is not easy to manufacture. The manufacturing process was complicated.

  An object of the present invention is to provide a semiconductor manufacturing apparatus and a semiconductor manufacturing method capable of easily forming a desired circuit on a semiconductor device by a printing process, and a semiconductor with high trimming accuracy and easy trimming. It is an object to provide a manufacturing apparatus, a semiconductor manufacturing method, and a semiconductor device obtained by the semiconductor manufacturing method.

In order to solve the above-described problems, a semiconductor manufacturing apparatus according to the present invention detects characteristics of each chip in a wafer to be inspected, and generates a drawing pattern for trimming for each chip based on the detected data. Wafer test department to determine,
Based on the storage unit for storing information on the wafer to be inspected, the drawing pattern information from the wafer test unit and the information on the wafer from the storage unit, a desired drawing pattern for each chip of the wafer A drawing pattern printing section formed by a printing operation;
The drawing pattern printing section includes at least a print head for injecting each of a conductive solvent, an insulating solvent, and an interface treatment liquid;
A chip coordinate recognition unit that acquires coordinate information of each chip by image recognition on the wafer,
A control unit for controlling a drawing operation of the print head on the wafer based on information on the drawing pattern from the wafer test unit, information on the wafer from the storage unit, and coordinate information from the chip coordinate recognition unit; It is configured. Since the semiconductor manufacturing apparatus configured in this manner forms a drawing pattern corresponding to the inspection result by a printing operation after the wafer test, it is possible to form the drawing pattern with high accuracy and a high-quality semiconductor device. Can be manufactured with a high yield.

The semiconductor manufacturing method according to the present invention detects the characteristics of each chip in a wafer to be inspected, and determines a drawing pattern for trimming for each chip based on the detected data,
Based on the determined drawing pattern information, the step of injecting the interface treatment liquid into the drawing pattern forming region on the chip surface of the wafer, and the drawing pattern forming region from which the interface processing solution was injected And a step of injecting a conductive solvent or an insulating solvent based on the drawing pattern. Since the semiconductor manufacturing method having such a process can form a drawing pattern with high accuracy on the chip surface of a wafer by a printing operation, a high-quality semiconductor device can be manufactured with a high yield.

In addition, a semiconductor manufacturing method according to another aspect of the present invention includes a step of forming a groove having a predetermined depth in a drawing pattern forming region of a wafer,
A process of inspecting the necessity of trimming the wafer,
A step of drawing a drawing pattern by injecting a conductive solvent into the groove of the wafer that needs trimming in the wafer;
Degassing and low-temperature annealing after drawing the drawing pattern,
After film formation after deaeration and low-temperature annealing, a step of flattening the film-forming surface and a step of high-temperature annealing after flattening are provided. The semiconductor manufacturing method having such steps can form a drawing pattern with high accuracy without causing a crack in a groove formed in a drawing pattern forming region of a wafer.

  In the semiconductor device according to the present invention manufactured by the semiconductor manufacturing apparatus and the semiconductor manufacturing method according to the present invention, a groove portion having a predetermined depth is formed in a pattern formation region for trimming on each chip in the wafer, Conductive wiring is formed inside the groove portion so that the side wall of the groove portion has an inclination angle of 5 ° or more and the opening side is widened. In the semiconductor manufacturing apparatus configured in this way, after a wafer test, a drawing pattern is easily formed by a printing operation in accordance with the test result. Therefore, the semiconductor device becomes a semiconductor device that can be easily trimmed, and a high-quality semiconductor device. .

  According to another aspect of the semiconductor device of the present invention, in the wafer state, at least two trimming pad electrodes exposed from the passivation film are formed on each chip surface, and the trimming is performed based on a result of a trimming necessity inspection. A drawing pattern is formed on the pad electrode by a printing process. The semiconductor manufacturing apparatus configured as described above is a structure in which a drawing pattern is formed by a printing operation in accordance with a test result after a wafer test. Become.

  A semiconductor device according to still another aspect of the present invention is an IGBT chip having a plurality of cells and provided with routing wiring in which routing pad electrodes are formed at positions corresponding to the cells. Includes a first pad electrode connected to the first electrode and a second pad electrode connected to the second electrode, and the first electrode A drawing pattern is formed by a printing process between the lead pad electrode or the second electrode. Since the semiconductor manufacturing apparatus configured as described above can be trimmed by a printing operation in accordance with a test result, the IGBT becomes an easy-to-trim process and becomes a high-quality semiconductor device.

  A semiconductor device according to still another aspect of the present invention is a nonvolatile memory, and is formed by a printing process so that a grounded electrostatic shield film body covers a memory region, and covers the electrostatic shield film body. Molded. Even if the semiconductor manufacturing apparatus configured as described above is formed on the same chip as the high breakdown voltage element, it is possible to prevent a problem that mold polarization occurs.

  Furthermore, a semiconductor device according to still another aspect of the present invention is a power integrated circuit device in which a power semiconductor device and a logic circuit are integrated on one chip, and is formed inside a high potential island isolation region. Conductive wiring, which is a level shift wiring that electrically connects the logic circuit and the high voltage switching element, is formed on the passivation film by printing a drawing pattern. In the semiconductor manufacturing apparatus configured as described above, since the level shift wiring is formed by the printing operation of the drawing pattern, it can be easily manufactured.

ADVANTAGE OF THE INVENTION According to this invention, the semiconductor manufacturing apparatus and semiconductor manufacturing method which can form a desired circuit easily with respect to the semiconductor device after a wafer test can be provided. Further, it is possible to provide a semiconductor manufacturing apparatus, a semiconductor manufacturing method, and a semiconductor device capable of easily performing the “trimming technique” after the wafer test.
Furthermore, according to the present invention, a highly reliable semiconductor device can be provided at low cost.

  In addition, according to the present invention, in forming the conductive wiring and the insulating film, the conductive characteristics and the insulating characteristics are stabilized, and the adhesion between the solvent and the wafer is improved to eliminate problems such as peeling. In addition to improving the controllability of the wiring shape and film forming shape, it is possible to improve the insulation from nearby elements and circuit wiring without increasing the chip area.

  Furthermore, according to the present invention, since a desired wiring can be formed on the IC chip after the wafer test with a highly versatile technique without restriction on the IC chip structure, a high-quality IC chip with little variation can be obtained, Since defective chips can be remedied, the yield rate is dramatically improved, and the manufacturing cost can be greatly reduced.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of a semiconductor manufacturing apparatus, a semiconductor manufacturing method, and a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

Embodiment 1
FIG. 1 is a block diagram showing a configuration of a circuit drawing system in the semiconductor manufacturing apparatus according to the first embodiment of the present invention. The circuit drawing system in the semiconductor manufacturing apparatus shown in FIG. 1 is an apparatus for printing a drawing pattern that forms a desired circuit on a wafer after a wafer test. The semiconductor device manufactured by the semiconductor manufacturing apparatus of the first embodiment is a semiconductor integrated circuit (hereinafter abbreviated as IC).

  The circuit drawing system in the semiconductor manufacturing apparatus of the first embodiment mainly measures the characteristic value of each IC chip in the wafer state, the position data of the IC chip to be trimmed, the trimming amount (drawing pattern) in the corresponding IC chip, etc. Wafer test unit 100 that determines the trimming data of the wafer, a drawing pattern printing unit 110 that prints a desired circuit on the wafer 1 based on the trimming data determined by the wafer test unit 100, and basic information of the IC chip on the wafer 1 And the like.

  The wafer test unit 100 performs a normal wafer test and detects data relating to each IC chip on the wafer. The data related to the IC chip includes, for example, coordinate data indicating the position of each IC chip and initial characteristic value data obtained from each IC chip. Each of these detected data is associated with the wafer test unit. Recorded at 100. Further, the wafer test unit 100 reads the basic information of the IC chip stored in the database unit 120, and compares this basic information with the detected initial characteristic value data related to each IC chip. The comparison result is stored in association with the coordinate data of each IC chip. At that time, the necessity of trimming of each IC chip and the drawing pattern for the IC chip that requires trimming are determined. In the initial characteristic value data detected for each IC chip, an IC chip that deviates greatly from the standard and cannot be adjusted by the trimming process is placed on the surface of the IC chip so that it can be identified as a defective product in a later manufacturing process. An NG mark is imprinted.

  The database unit 120 stores basic information of each IC chip in the target wafer in advance. As the basic information, various drawing patterns for trimming corresponding to the detected initial characteristic values, the wafer The reference image information for recognizing the IC chip pattern in FIG. 1 and the print position information in the IC chip corresponding to each drawing pattern are input and stored in the database unit 120 in advance.

  The drawing pattern printing unit 110 performs a drawing pattern printing process on an IC chip that requires trimming based on the trimming data transmitted from the wafer test unit 100. Trimming data transmitted from the wafer test unit 100 to the drawing pattern printing unit 110 includes coordinate data of an IC chip that requires trimming and drawing pattern data that indicates a necessary trimming amount of the IC chip.

The drawing pattern printing unit 110 includes a print head 111 that prints a drawing pattern for trimming on an IC chip on a wafer, a chip coordinate recognition unit 112 that captures an image of the IC chip surface on the wafer, and a print head based on various information. 111 has a control unit 113 that prints a drawing pattern on the surface of the IC chip of the corresponding wafer.
The chip coordinate recognition unit 112 specifies the position of each IC chip by capturing an image of the surface of the IC chip on the wafer. The image recognition processing used in the chip coordinate recognition unit 112 captures a wafer by image processing using a CCD, analyzes the captured pattern, and recognizes the position of each IC chip.

  The control unit 113 includes trimming data for each IC chip transmitted from the wafer test unit 100, image data related to the wafer transmitted from the chip coordinate recognition unit 112, and IC chip pattern related to the wafer transmitted from the database unit 120. Acquire data and wiring data. The control unit 113 sends data of a desired drawing pattern for trimming for each corresponding IC chip on the wafer to the print head 111 and controls the drive of the print head 111. That is, the control unit 113 specifies a printing place on the wafer based on the image data based on the imaging pattern, and provides the print data to the print head 111. The print head 111 uses an ink jet method capable of forming a designated drawing pattern by non-contact electronic printing.

Hereinafter, the drawing pattern printing unit 110 used in the semiconductor manufacturing apparatus and the semiconductor manufacturing method of the present invention will be described in detail.
FIG. 2 is a diagram illustrating a state in which a drawing pattern is formed on the wafer 1 using the print head 111 of the drawing pattern printing unit 110 in the semiconductor manufacturing apparatus according to the first embodiment. In FIG. 2, the shape of each part is shown in an enlarged manner for ease of explanation, and the shape is different from the actual one. In the following description, a wafer portion having an IC chip that requires trimming as a result of the wafer test is referred to as a base wafer 1.

  As shown in FIG. 2, three nozzles 111 </ b> A, 111 </ b> B, and 111 </ b> C are arranged in the print head 111 in substantially the same direction. That is, the three nozzles 111A, 111B, and 111C in the first embodiment are arranged so that the injection directions are substantially parallel, and the nozzles 111A, 111B, and 111C are integrally formed. Therefore, when the print head 111 scans the underlying wafer 1 that should be trimmed as a result of the wafer test, the third nozzle 111C scans first, and the second nozzle 111B follows the trajectory. The first nozzle 111A is arranged to scan and finally trace the same trajectory. When the print head 111 performs the above scanning operation, the conductive solvent 114 is ejected from the first nozzle 111A, the insulating solvent 115 is ejected from the second nozzle 111B, and the third nozzle 111C A pretreatment liquid 116 that is an interface treatment liquid is injected.

  As shown in FIG. 2, the print head 111 configured as described above is disposed on the base wafer 1, and the print head 111 scans the base wafer 1 on the basis of a control command from the control unit 113 and performs a desired operation. A wiring pattern which is a drawing pattern is drawn on the base wafer 1. In this drawing operation, first, the pretreatment liquid 116 is ejected from the third nozzle 111C onto the predetermined base wafer 1. As the pretreatment liquid 116, a surfactant having high affinity for silicon such as a silane coupling agent is used, and the surface of the base wafer 1 and conductive wiring by the conductive solvent 114 injected from the first nozzle 111 </ b> A are used. Improved adhesion. As described above, after the surfactant having high silicon affinity, which is the pretreatment liquid 116, is injected from the third nozzle 111C, the conductive solvent 114 is injected from the first nozzle 111A immediately after that along the locus. Thus, a desired wiring pattern is reliably drawn on the surface of the underlying wafer 1.

  Further, as shown in FIG. 3, in the print head 111 according to the first embodiment, drawing with an insulating film is possible using the insulating solvent 115 emitted from the second nozzle 111B. The print head 111 is disposed on the base wafer 1. The print head 111 scans the base wafer 1 based on a control command from the control unit 113, and a pattern with a desired insulating film is drawn on the base wafer 1. . In this drawing operation, first, the pretreatment liquid 116 is ejected from the third nozzle 111C onto the predetermined base wafer 1. The pretreatment liquid 116, which is a surfactant having high affinity for silicon, improves the adhesion between the surface of the underlying wafer 1 and the insulating film by the insulating solvent 115 ejected from the second nozzle 111B. In this way, after the surfactant having high silicon affinity, which is the pretreatment liquid 116, is injected from the third nozzle 111C, the insulating solvent 115 is injected from the second nozzle 111B immediately after that along the locus. Then, a desired insulating pattern is drawn on the surface of the underlying wafer 1.

  In the semiconductor manufacturing apparatus of the first embodiment, since the conductive solvent 114 or the insulating solvent 115 is injected onto the upper surface immediately after the pretreatment liquid 116 is discharged, the pretreatment liquid 116 is evaporated. It is possible to suppress a change in the interfacial property during film formation on the base wafer 1 and to perform desired drawing.

The drawing size of the print head 111 in the semiconductor manufacturing apparatus of the first embodiment is about 600 dpi, and a line having a desired thickness of about 43 μm or more is formed. According to the print head 111, it is possible to reliably draw a desired pattern on the passivation film on the IC chip. Therefore, in the semiconductor manufacturing apparatus of the first embodiment, a wiring pattern or an insulating pattern, which is a desired drawing pattern, can be reliably formed on the corresponding IC chip surface, and high-precision trimming can be performed.
As the conductive solvent 114 injected from the first nozzle 111A, a conductive polymer is used. By using the conductive polymer in this way, it is possible to reliably form (print) the precise drawing pattern in the first embodiment.
In the semiconductor manufacturing apparatus of the first embodiment configured as described above, it is not necessary to form a special trimming structure in each IC chip on the wafer, and the manufacturing cost of the semiconductor device can be greatly reduced. A highly versatile semiconductor manufacturing apparatus can be provided.

  In general inkjet printing technology, the adhesion between the film body of the printed pattern and the substrate may not be sufficient, and the adhesion is affected by stress due to the uneven surface shape of the substrate surface or the increase in the film thickness of the printed pattern. It may induce defects or peeling. In addition, in the ink jet system, there is no process for correcting pattern mismatch due to scattering or the like at the time of ejection, so that it is impossible to correct when adhesion failure or peeling occurs. Therefore, when a printing pattern is formed by a general ink jet method, the uneven shape of the base or the difference in familiarity between the film forming material and the base appears as a mismatch of the printing pattern as it is. Furthermore, in a general ink jet printing technique, a film forming solvent is simply ejected and applied to the base surface, and thus the film forming shape of the print pattern is not controlled.

  In the circuit drawing system in the semiconductor manufacturing apparatus according to the first embodiment of the present invention, the characteristic value of each IC chip in the wafer state is measured, the trimming data in each corresponding IC chip is determined, and the IC is based on the trimming data. A desired drawing pattern is printed on the chip surface 1. In order to form such a drawing pattern, in the semiconductor manufacturing apparatus according to the first embodiment, the thickness of a desired line along the drawing pattern in which the pretreatment liquid 116 is designated by the print head 111 having a special configuration. Immediately thereafter, the conductive solvent 114 or the insulating solvent 115 is reliably injected onto the line of the pretreatment liquid 116 along the locus of the drawing pattern formed by the pretreatment liquid 116.

Therefore, in the circuit drawing system in the semiconductor manufacturing apparatus of the first embodiment, the pretreatment liquid 116 is injected onto the wafer substrate 1 before the drawing pattern is formed with the conductive solvent 114 or the insulating solvent 115. The uneven shape on the surface of the substrate 1 is covered with the pretreatment liquid 116 to be a flat surface, and the adhesion between the film substrate of the drawing pattern by the conductive solvent 114 or the insulating solvent 115 and the wafer substrate 1 is always good. It has become a thing. Therefore, since the drawing pattern is in intimate contact with the surface of the wafer substrate 1, even if the film thickness of the drawing pattern is increased, there is no inferior adhesion or peeling, resulting in a highly reliable circuit drawing system. .
In the circuit drawing system in the semiconductor manufacturing apparatus of the first embodiment, three nozzles are provided in parallel, and a solvent or the like having a desired linear shape is sequentially ejected from each nozzle along the same locus. Based on the trimming data after the wafer test, the corresponding IC chip can be trimmed with high accuracy, and the yield of the wafer can be greatly improved.

  As described above, in the circuit drawing system in the semiconductor manufacturing apparatus according to the first embodiment of the present invention, the print head 111 has been described as having the three nozzles 111A, 111B, and 111C. One nozzle 111A and third nozzle 111C may be formed integrally. In the circuit drawing system configured as described above, the print head 111 scans the base wafer 1 and the pretreatment liquid 116 is ejected from the third nozzle 111C corresponding to the information of the drawing pattern. The conductive solvent 114 is injected along the locus to form the conductive wiring 3. At this time, since the surfactant having high affinity for silicon such as a silane coupling agent is used for the pretreatment liquid 116, the adhesion between the conductive wiring 3 and the underlying wafer 1 is improved. Further, since the conductive solvent 114 is injected immediately after the pretreatment liquid 116 is injected, it is possible to suppress a change in the interface property between the underlying wafer 1 and the film formation due to evaporation of the pretreatment liquid 116 or the like. it can.

  Similarly, in the circuit drawing system in the semiconductor manufacturing apparatus of the first embodiment, at least the second nozzle 111B and the third nozzle 111C are integrally formed in the print head 111 arranged on the base wafer 1. Also good. In the circuit drawing system configured as described above, the print head 111 scans the base wafer 1 and the pretreatment liquid 116 is ejected from the third nozzle 111C at a timing corresponding to the drawing pattern information. The insulating solvent 115 is injected along the locus to form the insulating wiring 4. At this time, since the pretreatment liquid 116 uses a surfactant having high affinity for silicon such as a silane coupling agent, the adhesion between the insulating film 4 and the underlying wafer 1 is improved. Further, the insulating solvent 115 can reduce the increase in stress accompanying the increase in film thickness by using, for example, a silicon ladder polymer, and can prevent problems such as cracks. In addition, since the insulating solvent 115 is injected immediately after the pretreatment liquid 116 is injected, it is possible to suppress a change in interfacial properties between the base and film formation due to evaporation of the pretreatment liquid 116 or the like. it can.

<< Embodiment 2 >>
The semiconductor manufacturing apparatus according to the second embodiment of the present invention will be described below. The semiconductor manufacturing apparatus of the second embodiment is different in the configuration of the drawing pattern printing unit 110 of the circuit drawing system in the semiconductor manufacturing apparatus of the first embodiment. In particular, the configuration of the print head 111 in the drawing pattern printing unit 110 is different. Therefore, 211 is attached to the reference numeral of the print head in the semiconductor manufacturing apparatus of the second embodiment, and the other components having the same functions and configurations as those of the first embodiment are given the same reference numerals. The description of Embodiment 1 is applied to the description.

The circuit drawing system in the semiconductor manufacturing apparatus according to the second embodiment includes the wafer test unit 100, the drawing pattern printing unit 110, and the database unit 120, similarly to the circuit drawing system in the first embodiment. Has been. However, as shown in FIG. 4, the configuration of the print head 211 of the drawing pattern printing unit 110 is different.
FIG. 4 shows that a convex portion 1P having a convex shape is formed on the underlying wafer 1 as a drawing pattern forming region for forming the conductive wiring 3 or the insulating film 4 using the circuit drawing system in the semiconductor manufacturing apparatus of the second embodiment. It is explanatory drawing which shows drawing operation in the case of being performed. FIG. 5 shows a case where a concave recess 1H is formed on the underlying wafer 1 as a pattern-forming pattern forming region for forming the conductive wiring 3 or the insulating film 4 using the circuit drawing system in the second embodiment. It is explanatory drawing which shows drawing operation | movement.

  As shown in FIGS. 4 and 5, the print head 211 in the semiconductor manufacturing apparatus according to the second embodiment detects the distance to the surface (printing surface) of the wafer substrate 1 in addition to the three nozzles 211A, 211B, and 211C. A first sensor 212 is provided. The first sensor 212 is an ultrasonic sensor, and detects the distance from the substantial nozzle tip of the print head 211 to the print surface of the wafer substrate. The first sensor 212 may use a distance detection element using laser light instead of an ultrasonic sensor. As with the first embodiment, the three nozzles 211A, 211B, and 211C in the print head 211 are provided so that their ejection directions are substantially parallel, and are integrally formed with the first sensor 212. ing. Therefore, when the print head 211 scans the underlying wafer 1 that should be trimmed as a result of the wafer test, the first sensor 212 first detects the distance to the printing surface of the underlying wafer 1 and then The third nozzle 211C scans, the second nozzle 211B scans along the trajectory, and finally the first nozzle 211A scans along the same trajectory. When the print head 211 performs a scanning operation, the conductive solvent 114 is ejected from the first nozzle 211A, the insulating solvent 115 is ejected from the second nozzle 211B, and the pretreatment liquid is ejected from the third nozzle 211C. 116 is configured to be injected.

  As shown in FIGS. 4 and 5, the print head 211 configured as described above is arranged on the designated base wafer 1, and the print head 211 is controlled by the control unit (see the control unit 113 in FIG. 1). A desired drawing pattern is drawn on the underlying wafer 1 by scanning the underlying wafer 1 based on the command. In this drawing operation, first, the first sensor 212 detects the distance to the printing surface of the underlying wafer 1 and is controlled to be a predetermined distance. Then, based on the information of the designated drawing pattern, the print head 211 ejects the pretreatment liquid 116 from the third nozzle 211C to the drawing pattern forming region on the predetermined underlying wafer 1, and the surface of the underlying wafer 1 and the first surface. The adhesiveness with the conductive wiring by the conductive solvent 114 injected from the nozzle 211A is improved. As described above, after the surfactant having high silicon affinity, which is the pretreatment liquid 116, is injected from the third nozzle 211C, the conductive solvent 114 is injected from the first nozzle 211A immediately after that along the locus. Thus, a desired drawing pattern to be the conductive wiring 3 is reliably drawn in the drawing pattern forming region of the base wafer 1.

  4 and 5, the case where the conductive solvent 114 is injected from the first nozzle 211A and the drawing pattern of the conductive wiring 3 is formed on the base wafer 1 has been described. It is also possible to form the insulating film 4 by injecting the insulating solvent 115 after injecting the liquid 116. Also in this drawing operation, similarly, the first sensor 212 first detects the distance to the printing surface of the base wafer 1 and is controlled so as to be a predetermined distance, whereby a desired drawing pattern to be the insulating coating 4 is formed. Is reliably drawn in the drawing pattern forming region of the underlying wafer 1.

  In the circuit drawing system in the semiconductor manufacturing apparatus according to the second embodiment of the present invention, the print head 111 has been described with the configuration in which the three nozzles 111A, 111B, and 111C and the first sensor 212 are integrally formed. A first sensor 212 is integrated with at least the first nozzle 211 </ b> A and the third nozzle 211 </ b> C in the print head 211 disposed in the drawing pattern formation region of the convex portion 1 </ b> P or the concave portion 1 </ b> H where a drawing pattern is to be formed. It may be configured. In the circuit drawing system configured as described above, the first sensor 212 has a function of measuring the distance between the print head 211 and the printing surface of the underlying wafer 1 using ultrasonic waves or laser light. The distance information measured by the first sensor 212 is ford-backed by the control unit (see the control unit 113 in FIG. 1), and the distance between the base wafer 1 and the printing surface is kept constant. Therefore, stable injection control can be performed.

In the circuit drawing system in the semiconductor manufacturing apparatus of the second embodiment, the pretreatment liquid 116 is ejected from the third nozzle 211C based on the drawing pattern information, and the pretreatment liquid film 2 is formed in the drawing pattern formation region. Then, the conductive solvent 114 or the insulating solvent 115 is injected onto the pretreatment liquid film 2 to form the desired conductive wiring 3 or the insulating film 4. At this time, since the pretreatment liquid 116 uses a surfactant having high affinity for silicon such as a silane coupling agent, the adhesion of the conductive wiring 3 or the insulating film 4 to the base wafer 1 is improved. .
Further, since the conductive solvent 114 or the insulating solvent 115 is injected immediately after the pretreatment liquid 116 is injected, the interface property between the printed surface of the underlying wafer 1 and the film formation due to the evaporation of the pretreatment liquid 116 or the like. Can be suppressed.

  In the circuit drawing system in the semiconductor manufacturing apparatus according to the second embodiment, the print sensor 211 may be integrally formed with the first sensor 212 together with at least the second nozzle 211B and the third nozzle 211C. In the case of such a configuration, the first sensor 212 measures the distance between the print head 211 and the printing surface of the underlying wafer 1, and sends the distance information to the control unit (see the control unit 113 in FIG. 1). Ford back is performed, and the distance between the underlying wafer 1 and the printing surface is kept constant. Then, based on the designated drawing pattern information, the pretreatment liquid 116 is ejected from the third nozzle 211C to form a pretreatment liquid film, and the insulating solvent 115 is ejected on the pretreatment liquid film. Insulating wiring 4 is formed.

  As described above, the print head 211 in the semiconductor manufacturing apparatus according to the second embodiment includes the first nozzle in addition to the configuration in which the three nozzles 111A, 111B, and 111C and the first sensor 212 are integrally formed. The configuration of 211A, the third nozzle 211C and the first sensor 212, the configuration of the second nozzle 211B, the third nozzle 211C and the first sensor 212 may be used, and an appropriate configuration is selected according to the purpose of use. .

<< Embodiment 3 >>
The semiconductor manufacturing apparatus according to the third embodiment of the present invention will be described below. The semiconductor manufacturing apparatus of the third embodiment is different in the configuration of the drawing pattern printing unit 110 of the circuit drawing system in the semiconductor manufacturing apparatus of the first embodiment. In particular, the configuration of the print head 111 in the drawing pattern printing unit 110 is different. Therefore, the reference numeral 311 is attached to the description of the print head in the semiconductor manufacturing apparatus of the third embodiment, and the other components having the same functions and configurations as those of the first embodiment are denoted by the same reference numerals. The description of Embodiment 1 is applied to the description.

The circuit drawing system in the semiconductor manufacturing apparatus according to the third embodiment includes a wafer test unit 100, a drawing pattern printing unit 110, and a database unit 120, similarly to the circuit drawing system in the first embodiment described above. Has been. However, as shown in FIG. 6, the configuration of the print head 311 of the drawing pattern printing unit 110 is different.
FIG. 6 shows that a convex portion 1P having a convex shape is formed on the underlying wafer 1 as a drawing pattern forming region on which the conductive wiring 3 or the insulating film 4 is printed using the circuit drawing system in the semiconductor manufacturing apparatus of the third embodiment. It is explanatory drawing which shows drawing operation in the case of being performed. FIG. 7 shows a case where a concave portion 1H having a concave shape is formed on the underlying wafer 1 as a drawing pattern forming region for printing the conductive wiring 3 or the insulating film 4 using the circuit drawing system in the third embodiment. It is explanatory drawing which shows drawing operation | movement.

  As shown in FIGS. 6 and 7, the print head 311 in the semiconductor manufacturing apparatus according to the third embodiment detects the distances between the three nozzles 311A, 311B, 311C and the surface (printing surface) of the wafer substrate 1 first. In addition to the sensor 312, a second sensor 313 is provided. The second sensor 313 is an ultrasonic sensor, and determines the distance from the substantial nozzle tip of the print head 311 to the surface of the injected solvent, that is, the distance to the surface of the conductive wiring 3 or the insulating film 4. To detect. The second sensor 313 may use a distance detection element using laser light instead of an ultrasonic sensor. As with the first embodiment, the three nozzles 311A, 311B, and 311C in the print head 311 are provided so that their ejection directions are substantially parallel to each other, and are combined with the first sensor 312 and the second sensor 313. Are integrally formed. Therefore, when the print head 311 scans the underlying wafer 1 that should be trimmed as a result of the wafer test, the first sensor 312 first detects the distance to the printing surface of the underlying wafer 1 and the locus thereof. The third nozzle 311C, the second nozzle 311B, and the first nozzle 311A scan sequentially, and finally the second sensor 313 is arranged to measure the distance to the film formation surface. Yes. In the scanning operation of the print head 311, the conductive solvent 114 is ejected from the first nozzle 311A, the insulating solvent 115 is ejected from the second nozzle 311B, and the pretreatment liquid 116 is ejected from the third nozzle 311C. Is configured to be injected.

  As shown in FIGS. 6 and 7, the print head 311 configured as described above is arranged on the designated base wafer 1, and the print head 311 is controlled by the control unit (see the control unit 113 in FIG. 1). A desired pattern is drawn on the underlying wafer 1 by scanning the underlying wafer 1 based on the command. In this drawing operation, first, the first sensor 312 measures the distance (A) to the printing surface of the underlying wafer 1, and the print head 311 is controlled to be in a predetermined position. Then, the pretreatment liquid 116 is ejected from the third nozzle 311C to the drawing pattern formation region on the underlying wafer 1, and the conductive wiring by the conductive solvent 114 ejected from the surface of the underlying wafer 1 and the first nozzle 311A. 3 is improved. As described above, after the surfactant having high silicon affinity, which is the pretreatment liquid 116, is injected from the third nozzle 311C, the conductive solvent 114 is injected from the first nozzle 311A immediately after that along the locus. Thus, a desired drawing pattern to be the conductive wiring 3 is reliably drawn in the drawing pattern forming region of the base wafer 1.

  Further, in the circuit drawing system according to Embodiment 3, the distance (B) from the tip of the print head 311 to the substantial surface of the conductive wiring 3 is measured by the second sensor 313, and the measurement information is stored in the control unit. Has been transmitted. In the control unit, the film thickness of the conductive wiring 3 is detected based on the difference between the measured distance (A) and the distance (B), and is controlled to have a desired film thickness. In this control, the injection amount of the conductive solvent 114 from the first nozzle 311A is controlled.

  In FIGS. 6 and 7, the case where the conductive solvent 114 is injected from the first nozzle 311A and the drawing pattern of the conductive wiring 3 is formed on the base wafer 1 has been described. It is also possible to form the insulating film 4 by injecting the insulating solvent 115 after injecting the liquid 116. Similarly in this drawing operation, first, the first sensor 312 first detects the distance to the printing surface of the base wafer 1, and the print head 311 is controlled to be a predetermined distance, and the second sensor 313 is also controlled. Thus, the distance (B) from the tip of the print head 311 to the substantial surface of the conductive wiring 3 is measured, and the insulating coating 4 is reliably drawn in the drawing pattern formation region of the underlying wafer 1 with a desired drawing pattern. The

  As described above, in the circuit drawing system in the semiconductor manufacturing apparatus according to the third embodiment of the present invention, the print head 211 that scans the convex portion 1P or the concave portion 1H, which is the pattern formation region on the underlying wafer 1, The first sensor 312 and the second sensor 313 are integrally configured together with at least the three nozzles of the first nozzle 311A, the second nozzle 311B, and the third nozzle 311C. The first sensor 312 has a function of measuring the distance between the print head 311 and the drawing pattern forming region of the underlying wafer 1 by using ultrasonic waves, laser light, or the like. The measured distance information (A) is ford-backed by the control unit and controlled so as to keep the distance between the print head 311 and the underlying wafer 1 constant, regardless of the shape of the drawing pattern formation region in the underlying wafer 1. Stable injection control can be performed.

  The circuit drawing system in the semiconductor manufacturing apparatus of the third embodiment according to the third embodiment is configured such that after the pretreatment liquid 116 is ejected from the third nozzle 311C to the drawing pattern forming area based on the drawing pattern information, The conductive solvent 114 or the insulating solvent 115 is injected to form the conductive wiring 3 or the insulating film 4 on the designated base wafer 1. At this time, since the pretreatment liquid 116 uses a surfactant having high affinity for silicon such as a silane coupling agent, the adhesion between the conductive wiring 3 or the insulating film 4 and the underlying wafer 1 is improved. Yes.

In the circuit drawing system according to the third embodiment, since the conductive solvent 114 or the insulating solvent 115 is injected thereon immediately after the pretreatment liquid 116 is injected, the evaporation of the pretreatment liquid is performed. It is possible to suppress a change in the interface property between the base wafer 1 and the film formation due to the above.
Furthermore, in the circuit drawing system in the semiconductor manufacturing apparatus according to the third embodiment, the surface of the print head 311 and the conductive wiring 3 or the surface of the insulating film 4 by the second sensor 313 irradiating ultrasonic waves or laser light. Therefore, the film thickness can be reliably monitored by performing Ford back together with the information measured by the first sensor 312.

<< Embodiment 4 >>
The semiconductor manufacturing apparatus according to the fourth embodiment of the present invention will be described below. The semiconductor manufacturing apparatus of the fourth embodiment is a specific example of the conductive solvent used in the circuit drawing system of the semiconductor manufacturing apparatus of the first to third embodiments. In the following description, the configuration of the semiconductor manufacturing apparatus of the first embodiment shown in FIG. 2 will be described. However, the conductive solvent used in the fourth embodiment is the same in any of the above-described embodiments. Applicable.

Hereinafter, the conductive solvent used in the circuit drawing system of the semiconductor manufacturing apparatus according to the fourth embodiment will be described.
A conductive viscous varnish is used as the conductive solvent 114 used in the semiconductor manufacturing apparatus of the fourth embodiment. FIG. 8 is a molecular structure diagram showing a composition example of a conductive viscous varnish. In this composition example, the carbon nanotubes 7 which are conductive materials are uniformly dispersed in the silicon ladder polymer 5 which is a film forming base material. Thus, by using the conductive viscous varnish shown in FIG. 8 as the conductive solvent 114, the flatness and the low stress property are secured, and the silane coupling agent 6 is used for the interface so that the thick film can be formed. Strengthen the bond.
The carbon nanotubes 7 used in Embodiment 4 are preferably purified in advance to a high purity, that is, an annealing step at a temperature of about 500 to 600 ° C. is performed in the atmosphere after generation by chemical vapor deposition (CVD). In addition, it is preferable to remove impurities such as amorphous carbon by a centrifugal separator after being immersed in a mixed solution of concentrated sulfuric acid and concentrated nitric acid.

As shown in FIG. 8, the general structure of the silicon ladder polymer 5 has a characteristic that Si—O bond is a main chain and various functional groups can be set on the side chain. For example, R1 and R2 are an aryl group, a hydrogen atom, an aliphatic alkyl group, or a functional group having an unsaturated bond, and may be the same or different. R3, R4, R5 and R6 are an aryl group, a hydrogen atom, an aliphatic alkyl group, a trialkylsilyl group or a functional group having an unsaturated bond, and may be the same or different. The weight average molecular weight is 1000 or more.
In the silane coupling agent 6, the main chain 6 </ b> A has a siloxane bond, and one side chain 6 </ b> B has an amino group that is an affinity group for carbon nanotubes. A functional group having an affinity function with the silicon ladder polymer 5 such as a hydroxyl group, a carboxyl group, a carbonyl group, an ester group, or a polymer composed of this functional group is formed on the other side chain 6C. ing.

  By mixing the silane coupling agent 6 and the purified carbon nanotube 7, the adsorption action of both functions and the aggregation of the carbon nanotubes is suppressed. In addition, since the affinity between the silicon ladder polymer 5 and the silane coupling agent 6 is high, the carbon nanotubes 7 uniformly dispersed in the silane coupling agent 6 are not re-aggregated. Spreads in. Further, the viscosity of the silicon ladder polymer 5 is adjusted to an optimum viscosity determined by a combination of the inner diameters, injection pressures, and the like of the nozzles 111A, 111B, and 111C of the print head 111 (see FIG. 2). The conductive viscous varnish used as the conductive solvent 114 in the semiconductor manufacturing apparatus of the fourth embodiment can be optimized while maintaining the uniform dispersion form of the carbon nanotubes 7 by adjusting the mixture with the organic solvent.

  In the semiconductor manufacturing apparatus of the fourth embodiment, when the conductive solvent 114 uses a conductive viscous varnish as the viscous solvent, the silicon ladder polymer solution dissolved in the organic solvent is added to, for example, carbon black, carbon nanotube, silver, copper A film-forming material in which a conductive material such as a filler selected from metals such as nickel and palladium, or a metal oxide thereof, and a silane coupling agent as a surface treatment agent for the conductive material is added and dispersed as necessary. Used

Next, the wiring drawing operation by the circuit drawing system in the semiconductor manufacturing apparatus of the fourth embodiment will be described using the conductive viscous varnish as the conductive solvent 114. FIG.
FIG. 9 is a flowchart showing a circuit drawing operation by the circuit drawing system in the semiconductor manufacturing apparatus of the fourth embodiment. The flowchart showing the circuit drawing operation shows a process in which the conductive solvent 114 is injected in accordance with a designated drawing pattern to form a conductive wiring.
In the semiconductor manufacturing apparatus according to the fourth embodiment, a drawing pattern forming region in which conductive wiring is formed is shown in FIGS. FIG. 10 is a cross-sectional view showing the groove portion 8 formed in the drawing pattern formation region of the underlying wafer 1, and FIG. 11 shows the groove portion 8 formed in the convex portion 1 </ b> P formed in the drawing pattern formation region of the underlying wafer 1. FIG. As shown in FIG. 10 or FIG. 11, in the semiconductor device manufactured in the semiconductor manufacturing apparatus of the fourth embodiment, a groove portion 8 having a predetermined depth is formed in advance in the pattern forming region.

After performing a wafer test on the wafer to be inspected (step A), an IC chip to be trimmed is determined (step B). Next, the IC chip is mounted on the circuit drawing system in the semiconductor manufacturing apparatus of the fourth embodiment, and based on the drawing pattern information, the conductive viscous varnish having the silicon ladder polymer 5 as a film forming base material is used as the conductive solvent 114. To the corresponding groove 8 (step C). Immediately after the injection, degassing is performed to eliminate bubbles and the like that are secondarily generated in the sidewall portion of the groove 8 in the injected solvent (step D).
Next, the organic solvent is evaporated by exposure to low temperature annealing, for example, at 100 ° C. for 15 minutes (step E). Then, the surface of the conductive wiring 3 is flattened by CMP (Chemical-Mechanical Polishing) (step F).
Finally, it is hardened by high-temperature annealing, for example, by placing it in a nitrogen atmosphere at 300 ° C. for 60 minutes (Step G).
In the drawn pattern formed as described above, almost no contraction stress is generated in the silicon ladder polymer 5 which is a film forming base material, and therefore cracks may occur even when a thick film filled in the groove 8 is formed. Therefore, the highly reliable conductive wiring 3 can be formed.

In the circuit drawing system in the semiconductor manufacturing apparatus of the fourth embodiment, cracks are prevented from occurring even in the case of the conductive wiring 3 formed as a thick film in the groove 8 in the drawing pattern as described above. In consideration of the expansion coefficient of the conductive material added to the conductive solvent 114, the side wall of the groove 8 formed in the base wafer 1 is formed so as to be inclined so as to open more upward.
As shown in FIG. 10, the groove 8 is inclined so that the side wall surfaces 8A on both sides thereof are more open upward. The inventor confirmed that the inclination angle of the wall surface 8A is preferably in the range of 5 degrees to 10 degrees. When the inclination angle is less than 5 degrees, the relaxation region due to the expansion of the conductive material added to the conductive solvent 114 is insufficient, and the drawing pattern by the grooves 8 formed in the underlying wafer 1 is as much as possible. Since it is preferable to be fine, an inclination angle of 10 degrees or less that is sufficient as a relaxation region is preferable.

As shown in FIG. 10, a conductive solvent 114 is injection-filled (step C), degassed (step D), low-temperature annealed (step E), polished and flattened into the groove 8 having the inclined side wall surface 8A. The desired drawing pattern is formed by performing the conversion (step F) and the high temperature annealing (step G). Since the side wall surface 8A of the groove 8 shown in FIG. 10 has an inclination angle of 5 degrees or more in advance, damage such as cracks does not occur in the drawing pattern.
In the conductive solvent 114, the silicon ladder polymer itself hardly undergoes shrinkage stress due to high-temperature annealing, so there is little concern that cracks will occur in the groove portion 8, but the expansion rate of the conductive material added to impart conductivity is low. Need to be considered. Therefore, an inclined side wall surface 8A is formed in the groove 8 shown in FIG. 10, and a space for relaxing stress due to expansion of the conductive material is secured.
In the groove portion 8 shown in FIG. 10, the stress relaxation space due to the expansion of the conductive material is defined by defining the inclination angle of the side wall surface 8A. A configuration in which only a region close to the front surface side of the wall surface 8A is an inclined surface, or a configuration in which the side wall surface is curved and bowed is possible.

In the semiconductor device, in the case of a specification in which a high voltage and large current is passed through the conductive wiring 3 of the drawing pattern, it is necessary to improve the insulation performance or to secure an insulation distance with respect to the elements in the vicinity of the drawing pattern and other wiring portions. There is. Therefore, the circuit drawing system in the semiconductor manufacturing apparatus of the fourth embodiment has a configuration in which the ridge-shaped convex portion 1P is formed on the surface of the base wafer 1, and the top region 1B of the convex portion 1P is used as a drawing pattern. Used.
FIG. 11 is a cross-sectional view showing the convex portion 1 </ b> P formed on the base wafer 1. As shown in FIG. 11, a groove 8 is formed in the top region 1B, which is the tip surface of the convex portion 1P. The side wall surfaces 8A on both sides of the groove 8 are inclined so as to open more upward. The inclination angle of the wall surface 8A is preferably in the range of 5 degrees or more and 10 degrees or less, similarly to the groove portion 8 shown in FIG. As described above, by forming the groove portion 8 in the top region 1B of the convex portion 1P formed on the base wafer 1 to form a drawing pattern, an insulation distance can be increased with respect to elements in the vicinity of the drawing pattern and other wiring portions. It is possible to ensure with certainty. In addition, by using the top region 1B of the convex portion 1P as a drawing pattern in this way, it is possible to achieve a configuration that satisfies the desired specifications without increasing the IC chip area.

As shown in FIG. 11, the groove 8 is formed in the top region 1B of the convex portion 1P formed on the base wafer 1, and the side wall surface 8A of the groove 8 is formed with a predetermined inclination angle. Yes. In the structure shown in FIG. 11, the conductive solvent 114 is injected and filled into the groove 8 formed in the convex portion 1P (process C), degassed (process D), low-temperature annealing (process E), polished and flattened. (Step F) and high-temperature annealing (Step G) are performed, whereby a desired drawing pattern is formed in the top region 1B of the convex portion 1P. Therefore, as shown in FIG. 11, by forming a drawing pattern on the convex portion 1P, which is a drawing pattern forming region on the base wafer 1, the insulation distance between the drawing pattern and nearby elements and other wiring portions can be reduced. Since such a configuration can be ensured, such a configuration is particularly effective when the energization conditions of the conductive wiring require a high voltage and a large current.
The convex portion 1P formed on the base wafer 1 may be formed integrally with the base wafer 1, but the convex portion 1P may be separately formed on the base wafer 1.

In the circuit drawing system in the semiconductor manufacturing apparatus of the fourth embodiment, in order to form the conductive wiring 3 and the insulating film 4 with high accuracy, the width of the groove 8 which is a film formation region or the top region in the convex portion 1P. It is preferable that the diameter of the injection region of the conductive solvent 114 and the insulating solvent 115 injected from the nozzle is set to 30% or less with respect to the width of 1B. By setting the injection region of the viscous solvent in this way, the conductive wiring 3 and the insulating film 4 can be formed with high accuracy in the predetermined region of the groove 8 or the convex portion 1P.
The above numerical values are based on the results of the inventor performing various experiments on the setting of the viscosity and injection pressure of the solvent at the time of injection of the viscous solvent and taking into account the spread and scattering of the solvent after injection. . In the range where the film thickness is about several μm to 10 μm, it is particularly necessary to consider when the minimum line width of the drawing pattern is 30 μm or more. However, when the conductive wiring 3 and the insulating film 4 are thin and have a fine width, for example, when the film thickness is about 2 μm or less and the minimum width is 5 μm or less, the injection region of the conductive solvent 114 and the insulating solvent 115 is used. This can be dealt with by restricting the diameter of the film to 30 to 50% of the width of the film formation region.

<< Embodiment 5 >>
The semiconductor manufacturing apparatus according to the fifth embodiment of the present invention will be described below. The semiconductor manufacturing apparatus of the fifth embodiment is a specific example of manufacturing a semiconductor device using the circuit drawing system of the semiconductor manufacturing apparatus of the first to third embodiments described above. In the following description, the configuration of the semiconductor manufacturing apparatus according to the first embodiment shown in FIG. 2 will be described. However, the semiconductor manufacturing apparatus according to the second and third embodiments may be used. Good. In addition, the conductive solvent and the insulating solvent used in the above-described fourth embodiment can be applied to any of the embodiments according to the present invention.
The semiconductor manufacturing apparatus according to the fifth embodiment trims the semiconductor device after the wafer test using the drawing pattern printing unit 110 of the circuit drawing system in the semiconductor manufacturing apparatus according to the first embodiment.

  The resistance value trimming used in the circuit drawing system according to the fifth embodiment will be briefly described. FIG. 12 is a circuit diagram showing the principle of resistance value trimming by the R-2R circuit system having a ladder-type register network. In FIG. 12, in the D / A converter of the semiconductor device shown in FIG. 12A, all of the trimming regions S1 to S5 corresponding to the switches are on, and the output voltage Vout is 31/32 of the reference voltage Vref. On the other hand, the semiconductor device shown in FIG. 12B is the same DA converter as in FIG. 12A, and the second trimming wiring S2 and the fourth trimming wiring S4 in the trimming regions S1 to S5 corresponding to the switches are turned off. The other trimming wires S1, S3, S5 are in the on state. As a result, the output voltage Vout is 21/32 of the reference voltage Vref. As shown in FIG. 12, in order to set the output voltage Vout to a desired value, a desired trimming wiring in the trimming regions S1 to S5 corresponding to the switches is subjected to on / off control (connection / disconnection control). Trimming can be performed by adjusting the resistance value.

FIGS. 13 to 15 are views showing a state where wiring drawing for trimming is performed on a wafer-like IC chip after a wafer test in the circuit drawing system of the fifth embodiment, and the print head 111 performs trimming. FIG. 6 is a diagram showing a state in which a conductive wiring 3 is formed by injecting a pretreatment liquid 116 and a conductive solvent 114 between two designated pad electrodes 9A and 9B in the pad electrode 9 for use. FIG. 14 is a cross-sectional view taken along the line AA ′ in FIG. 13 and shows the ejection state of the print head 111. FIG. 15 is a cross-sectional view showing a state in which the conductive wiring 3 is formed between the pad electrodes 9A and 9B.
14 and 15, pad electrodes 9A and 9B for trimming are formed on the upper surface of the underlying wafer 1, and a passivation film 10 is formed so that the upper surfaces of the pad electrodes 9A and 9B are exposed. Trimming processing is performed on the base wafer 1 after the wafer test formed in this way using the drawing pattern printing unit 110 of the circuit drawing system in the semiconductor manufacturing apparatus of the first embodiment.

  The pretreatment liquid 116 and the conductive solvent 114 are ejected from the print head 111 of the drawing pattern printing unit 110 to the pad electrodes 9A and 9B for trimming of the underlying wafer 1 to form the conductive wiring 3 that forms a desired drawing pattern. It is formed between pad electrodes 9A and 9B. As a result, the pad electrodes 9A and 9B are electrically connected (on state), and the designated trimming process is performed.

In the wiring drawing operation of the drawing pattern, the trimming process is performed based on the trimming data indicating the result of the wafer test, and the semiconductor device has a characteristic value within a desired range. In this wiring drawing operation, the conductive solvent 114 is injected between the electrode pads designated based on the trimming data to form a wiring. The printed state at this time is 600 dpi (dot per inch), about A resolution of 43 μm or more can be obtained. Therefore, wiring can be drawn also on the passivation film on the IC chip.
Therefore, by using the circuit drawing system of the fifth embodiment, an inexpensive and highly versatile drawing pattern can be formed in the structure of a wafer-like IC chip without forming a special trimming structure. This makes it possible to perform trimming with high reliability.

<< Embodiment 6 >>
The semiconductor device according to the sixth embodiment of the present invention will be described below. The semiconductor device of the sixth embodiment is a semiconductor device manufactured by the semiconductor manufacturing device of the first to third embodiments described above, and the trimming data after the wafer test is performed using the drawing pattern printing unit 110 of the circuit drawing system. The semiconductor device to be trimmed based on the above.

  FIG. 16 is a plan view of the semiconductor device showing a pair of pad electrodes 9 and 9 to be subjected to the trimming process of the semiconductor device, and shows a state before the trimming process. 17A is a cross-sectional view taken along line B-B ′ in FIG. 16, and FIG. 17B is a cross-sectional view taken along line C-C ′ in FIG. 16. FIG. 18A is a cross-sectional view taken along line B-B ′ of FIG. 16 in a state after trimming the semiconductor device shown in FIG. FIG. 18B is a cross-sectional view taken along line C-C ′ of the semiconductor device shown in FIG. 16 after the trimming process.

  As shown in FIGS. 16 and 17, in the semiconductor device of the sixth embodiment, an interlayer oxide film 11 is formed on a semiconductor substrate 12, and a trimming aluminum electrode (pad electrode) 9 is provided thereon. Yes. The surface of the semiconductor device according to the sixth embodiment is covered with a passivation film 10 except for the pair of pad electrodes 9 and 9 and the interlayer oxide film 11 exposed between them which are wired during the trimming process. A pair of pad electrodes 9, 9 and a concave region 13 are provided therebetween.

  Trimming processing is performed on the semiconductor device configured as described above by using the circuit drawing system of the semiconductor manufacturing apparatus according to the first to third embodiments described above. As shown in FIGS. 18A and 18B, based on the trimming data, the conductive solvent is injected into the pair of pad electrodes 9 and 9 and the recessed region 13 therebetween, and the pair of pad electrodes 9 is obtained. , 9 is formed between the conductive lines 3, and the trimming process is completed.

  In the manufacturing of semiconductor devices, when trimming is performed, a pretreatment liquid or a conductive solvent is ejected from the print head onto the surface of the IC chip. Therefore, during the period until these solvents volatilize and solidify. There is a risk that blurring (liquid dripping) occurs and disconnection occurs in the wiring portion on the surface of the IC chip. In order to prevent such a problem, in the semiconductor device of the sixth embodiment, as shown in FIG. 16, the passivation film 10 is patterned leaving a region to be trimmed as a drawing pattern, By forming the recessed area 13, it is possible to reliably perform wiring drawing for the trimming process by injecting a necessary solvent into the recessed area 13.

  Further, as shown in FIG. 19, the recessed area for patterning the passivation film 10 may be extended from the trimming aluminum electrode (pad electrode) 9 to an outer area having a predetermined distance. 20A is a cross-sectional view taken along line B-B ′ in the semiconductor device shown in FIG. 19. FIG. 20B is a cross-sectional view taken along line B-B ′ in the state after trimming the semiconductor device shown in FIG. 19. As shown in FIG. 20B, the recessed region 13 for trimming is formed so as to surround the pad electrode 9, so that more reliable trimming can be performed.

<< Embodiment 7 >>
The semiconductor device according to the seventh embodiment of the present invention will be described below. The semiconductor device according to the seventh embodiment is a semiconductor device manufactured by the semiconductor manufacturing apparatus according to the first to third embodiments described above, and the drawing pattern printing unit 110 of the circuit drawing system is used for trimming data after the wafer test. This is a semiconductor device that has been trimmed.
In order to improve the adjustment accuracy of the characteristic value in each semiconductor device by the trimming process, the number of types of drawing patterns for the trimming process may be increased. However, when a plurality of drawing patterns are simply arranged side by side, as described in the above-described sixth embodiment, the solvent may bleed (sag) and flow into the adjacent drawing pattern and interfere with it. . In the trimming process, the generation of further defective products is absolutely a matter to be avoided. In order to prevent the occurrence of such a defective product, there is a method in which the drawing pattern interval for the trimming process is sufficiently wide and the margin is widened in consideration of liquid dripping. However, in such a method, the arrangement area of the drawing pattern on the IC chip increases, which leads to a loss (increase in cost) of the IC chip area due to an increase in the invalid area. In order to prevent this, a dripping prevention groove 14 is further formed outside the recessed area 13 so as to surround the recessed area (drawing pattern forming area) 13 formed by the passivation film 10 as shown in FIG.

FIG. 21 is a plan view of the semiconductor device according to the seventh embodiment. FIG. 22A is a cross-sectional view taken along line EE ′ in FIG. FIG. 22B shows a state in which a solvent is injected to the pad electrodes 9 and 9 which are a desired drawing pattern in the semiconductor device of FIG. 21, and E when the solvent is injected into the semiconductor device in FIG. It is sectional drawing by -E 'line.
As shown in FIG. 22, even when the injected solvent exceeds the recess region (drawing pattern forming region) 13, it is surely stopped in the liquid dripping prevention groove 14 and is prevented from interfering with a neighboring drawing pattern. .
In the semiconductor device shown in FIG. 21, an example in which the single liquid dripping prevention groove 14 is formed so as to surround the recessed area 13 is shown, but it is effective to form such liquid dripping prevention grooves in multiple layers. It is. The liquid dripping prevention groove formed in this way prevents bleeding (liquid dripping) due to a solvent to an unnecessary region, and it is possible to form a drawing pattern area for trimming processing as small as possible.

<< Embodiment 8 >>
The semiconductor device according to the eighth embodiment of the present invention will be described below. Similar to the semiconductor device of the seventh embodiment, the semiconductor device of the eighth embodiment is a semiconductor device manufactured by the semiconductor manufacturing device of the first to third embodiments described above, and the drawing pattern printing unit 110 of the circuit drawing system. Is a semiconductor device that is trimmed based on trimming data after the wafer test.
In the semiconductor device of the eighth embodiment, in order to prevent liquid dripping, unlike the liquid dripping prevention groove in the semiconductor device of the seventh embodiment, a liquid dripping prevention protrusion 15 is formed.

FIG. 23 is a plan view of the semiconductor device according to the eighth embodiment. FIG. 24A is a cross-sectional view taken along line FF ′ in FIG. FIG. 24B shows a state in which a solvent is injected to the pad electrodes 9 and 9 so as to obtain a desired drawing pattern in the semiconductor device of FIG. 23. When the solvent is injected into the semiconductor device in FIG. It is sectional drawing by the FF 'line.
As shown in FIG. 23, the dripping prevention protrusion 15 is formed so as to surround the recessed area (drawing pattern forming area) 13, and is formed by arranging an aluminum wiring and patterning the passivation film 10 thereon. Has been. Therefore, in the semiconductor device of the eighth embodiment, the passivation film 10 is formed around the recessed area 13, and the liquid dripping prevention protrusion 15 is formed as an outer ring protrusion that surrounds the recessed area 13 in the passivation film 10. Has been. For this reason, as shown in FIGS. 24A and 24B, a concave-convex shape is formed around the concave region 13, and dripping from the concave region 13 which is a drawing pattern forming region is completely prevented. Is done.

Embodiment 9
The semiconductor device according to the ninth embodiment of the present invention will be described below. The semiconductor device of the ninth embodiment is a semiconductor device manufactured by the semiconductor manufacturing apparatus of the first to third embodiments described above, similarly to the semiconductor devices of the seventh and eighth embodiments. A mechanism for preventing liquid dripping in a wiring drawing operation different from that of a semiconductor device is disclosed.
FIG. 25 is a plan view of the semiconductor device according to the ninth embodiment. FIG. 26 is a cross-sectional view showing a state before a trimming process for a drawing pattern in the semiconductor device of the ninth embodiment, and FIG. 27 is a cross-sectional view showing a state after the trimming process. 26A is a cross-sectional view taken along line GG ′ in FIG. 25, and FIG. 26B is a cross-sectional view taken along line HH ′. 27A is a cross-sectional view taken along line GG ′ after trimming in the semiconductor device of FIG. 25, and FIG. 27B is a cross-sectional view taken along line HH ′ after trimming of the semiconductor device shown in FIG. FIG.

  As shown in FIGS. 25 to 27, a groove 16 is formed in the interlayer insulating film 11 inside the recessed region 13 formed by the passivation film 10. The groove 16 is formed by piercing the interlayer insulating film 11 so as to connect positions where a pair of pad electrodes 9, 9 to be connected in the trimming process is formed. The groove 16 is formed by recessing the interlayer insulating film 11 by a contact etching process or the like in the manufacturing process of the semiconductor device, and the surface of the interlayer insulating film 11 is greatly formed to form a pad electrode 9 in a subsequent process. , 9 are stepped. By forming in this way, dripping of the injected conductive solvent 114 is prevented in the trimming process, and a desired conductive wiring 3 can be formed in a predetermined region.

<< Embodiment 10 >>
The semiconductor device according to the tenth embodiment of the present invention will be described below. The semiconductor device of the tenth embodiment is a semiconductor device manufactured by the semiconductor manufacturing apparatus of the first to third embodiments described above, and the test result after the wafer test is performed using the drawing pattern printing unit 110 of the circuit drawing system. Is a semiconductor device that is trimmed based on the trimming data corresponding to. The semiconductor device of the tenth embodiment is an IGBT (insulated gate bipolar transistor).

  FIG. 28 is a plan view of an IGBT chip that is the semiconductor device of the tenth embodiment. As shown in FIG. 28, the IGBT chip has a gate electrode pad 17, an emitter electrode pad 18, and an aluminum wiring 19 for routing the gate electrode. In this IGBT chip, reference numeral 22 denotes a high breakdown voltage isolation region. FIG. 29 is an equivalent circuit of the IGBT chip shown in FIG. When viewed microscopically, the IGBT chip which is the semiconductor device of the tenth embodiment is an aggregate of a plurality of minute IGBT cells as shown in the equivalent circuit of FIG. The IGBT chip according to the tenth embodiment includes six IGBT cells 20A, 20B, 20C, 20D, 20E, and 20F.

  In general, an IGBT having a large chip area has a structure in which a manufacturing defect is likely to occur due to a short circuit between a gate and an emitter due to a defect in a gate oxide film. Such a gate defect occurs in a part of the IGBT cells in the IGBT chip. However, if a gate defect occurs even at one location, the entire IGBT chip becomes a defective product and is discarded. Therefore, by cutting the gate wiring of only the IGBT cell in which the gate defect has occurred and short-circuiting between the gate and the emitter, that is, by performing the trimming process on the corresponding IGBT cell, the entire IGBT chip is made non-defective. It becomes possible.

  Therefore, in the IGBT chip which is the semiconductor device of the tenth embodiment, a trimming pad is provided on each IGBT cell 20A, 20B, 20C, 20D, 20E, and 20F so that trimming can be performed after each IGBT cell inspection by the wafer test. Electrodes 21A, 21B, 21C, 21D, 21E, and 21F are provided. In the IGBT cell inspection, a measuring needle is brought into contact with the pad electrodes 21A, 21B, 21C, 21D, 21E, and 21F of each IGBT cell to inspect the good / bad state of the gate.

In the IGBT chip shown in FIG. 28, it is detected that one of the IGBT cells 20E has a gate defect in the inspection and is trimmed. FIG. 29 shows an equivalent circuit of the IGBT chip shown in FIG. 28, in which the gate and emitter of the IGBT cell 20E are short-circuited. In the IGBT chip, the pad electrodes 21A, 21B, 21C, 21D, and 21F are connected to the gate electrodes via the gate electrode routing aluminum wirings 19 and the gate pad electrodes 17 for the non-defective IGBT cells. Trimming pads 23A, 23B, 23C, 23D, 23E, and 23F are formed on the aluminum wiring 19 at positions corresponding to the pad electrodes 21A, 21B, 21C, 21D, 21E, and 21F. Therefore, in the trimming process, the pad electrodes 21A, 21B, 21C, 21D, and 21F are connected to the trimming pads 23A, 23B, 23C, 23D, and 23F of the corresponding aluminum wiring 19. On the other hand, a trimming process for connecting the pad electrode 21E to the emitter electrode pad 18 is performed on the defective IGBT cell 20E in which a gate defect is detected. The emitter electrode pad 18 is common to all IGBT cells.
By performing the trimming process as described above, only defective IGBT cells are in an unused state, and the entire IGBT chip is in a non-defective state.

FIG. 30 is a graph showing effects in the IGBT which is the semiconductor device according to the tenth embodiment of the present invention. In the graph shown in FIG. 30, the broken line indicates the relationship between the chip area and the yield rate in the conventional semiconductor device, and the solid line indicates the relationship between the chip area and the yield rate in the IGBT which is the semiconductor device according to the tenth embodiment. ing.
As described above, the yield rate of IGBTs decreases as the chip area increases. In the IGBT of the tenth embodiment, it is necessary to form a pad electrode and a trimming pad, and therefore there is an invalid area on the chip surface. For this reason, the apparent non-defective rate is essentially reduced. This is because the number of chips that can be manufactured in one wafer is, for example, 500, but when the number of chips is reduced to 450 due to an increase in the ineffective area, the apparent non-defective rate is 90%.

However, in the semiconductor device according to the tenth embodiment of the present invention, even a defective IGBT chip can be relieved as a non-defective product, so that the reduction of the non-defective product rate with respect to the chip area is greatly improved. However, when an IGBT cell becomes defective due to reasons other than a gate failure, or when a plurality of IGBT cells become defective in one IGBT chip, such IGBT may not be relieved. For this reason, as shown by a solid line in FIG. 30, not all defective IGBTs are relieved in the semiconductor device of the tenth embodiment according to the present invention, but it is slightly lowered. However, a dramatic effect is shown when the chip area is large to some extent as compared with the conventional semiconductor device indicated by the broken line.
As shown in FIG. 30, when the chip area is small, the non-defective product rate is higher in the case of the conventional semiconductor device, but this includes the apparent non-defective product rate as described above. The rate is almost unchanged. However, when the chip area is increased to some extent, the effect of the semiconductor device according to the tenth embodiment of the present invention is greatly increased.

<< Embodiment 11 >>
The semiconductor device according to the eleventh embodiment of the present invention will be described below. The semiconductor device of the eleventh embodiment is a semiconductor device manufactured by the semiconductor manufacturing apparatus of the first to third embodiments described above, and the electrostatic pattern is printed using the drawing pattern printing unit 110 of the circuit drawing system. It is a semiconductor device formed by. The semiconductor device of the eleventh embodiment is an EPROM (Erasable Programmable Read Only Memory) of a nonvolatile memory.

  FIG. 31 is a cross-sectional view showing a general non-volatile memory EPROM. In FIG. 31, an N-channel EPROM includes a P-type semiconductor substrate 24, an N-type diffusion region 25 that forms the source / drain of the EPROM, a gate oxide film 26, a floating gate 27, a control gate 28, an interlayer oxide film 29, and a passivation film. 30 and a field oxide film 31. In this FPROM, the floating gate 27 and the control gate 28 have a self-aligned structure.

A general RPROM performs a write / erase operation to confirm its operation during a wafer test. In this wafer test, to erase data, it is necessary to excite electrons in the floating gate 27 by irradiating light such as ultraviolet rays. Therefore, in the conventional RPROM, the interlayer oxide film 29 and the passivation film 30 are required to have high light transmittance. The silicon oxide film (SiO ₂ ) used as the interlayer oxide film 29 has no problem since it has essentially high light transmittance. Further, the silicon nitride film (SiN) used as the passivation film 30 that is a protective film has been formed under a special condition to form a light-transmitting film body. The physical properties of the silicon nitride film at this time included many N—H bonds, and the refractive index had to be 1.95 or less.
When the conventional EPROM configured as described above is formed on the same chip as the high breakdown voltage element, the following problems occur. FIG. 32 is a cross-sectional view showing a state in which a conventional EPROM is formed on the same chip as the high breakdown voltage element and packaged with a mold resin 32.

  When the conventional EPROM configured as shown in FIG. 32 is formed on the same chip as the high voltage element, the electric lines of force from the high voltage element reach the EPROM in the low potential region. Polarization occurs in the mold resin 32. Due to this polarization, a positive charge is induced on the EPROM side of the mold resin 32. As a result, the mold resin 32 is in a state where a positive potential is applied as a gate. At this time, the P-type semiconductor substrate 24 under the field oxide film 31 between the source and drain of the EPROM is inverted by the influence of the positive charge of the mold resin 32 to form an N-type MOS channel. As a result, as shown in FIG. 32, a leak current is generated between the source and the drain, causing a problem that data is garbled.

In the conventional EPROM configured as described above, as a countermeasure against a problem caused by polarization (mold polarization) in the mold resin, there is one using a semi-insulating silicon nitride film 33 as a part of the passivation film 30. However, when the semi-insulating silicon nitride film 33 is used as described above, the refractive index of the silicon nitride film is 2.1 or more, and the light transmittance is extremely poor, so that light reaches the EPROM. In addition, the silicon nitride film has been patterned so as not to be formed on the EPROM (see FIG. 32).
Therefore, in the EPROM which is the semiconductor device according to the eleventh embodiment of the present invention, an electrostatic shield is formed by a printing operation after the wafer test using the semiconductor manufacturing apparatus described in the first to third embodiments. Yes.

FIG. 33 is a sectional view showing the structure of the EPROM according to the eleventh embodiment of the present invention. As shown in FIG. 33, since there is no need to erase data by light irradiation after the wafer test, the wiring drawing technique according to the present invention provides an electrostatic shield in an area on the EPROM where the semi-insulating silicon nitride film 33 is not covered. 34 is printed. The electrostatic shield 34 is a conductive wiring formed by injecting a conductive solvent. The electrostatic shield 34 functions as a shield film that prevents mold polarization when packaged with a mold resin by being connected to a GND terminal or the like.
Since the semiconductor device according to the eleventh embodiment configured as described above can prevent the problem that mold polarization occurs, it is possible to form the high breakdown voltage element and the EPROM on the same chip.

<< Embodiment 12 >>
The semiconductor device according to the twelfth embodiment of the present invention is a power integrated circuit device (HVIC: High Voltage IC) in which a power semiconductor device and a logic circuit are integrated on one chip, and this power integrated circuit device ( In the manufacturing of the HVIC, the level shift wiring described later is formed by the print head using the semiconductor manufacturing apparatus described in the first to third embodiments.

  FIG. 34 is a plan view showing a conventional power integrated circuit device (HVIC: High Voltage IC) in which a power semiconductor device and a logic circuit are integrated on one chip. This power integrated circuit device (hereinafter abbreviated as HVIC) is used for drive control of various devices such as motors, lighting devices, and video devices. 35 to 37 are cross-sectional views of the HVIC shown in FIG. 34, FIG. 35 is a cross-sectional view taken along line AA ′ in FIG. 34, and FIG. 36 is a cross-sectional view taken along line BB ′ in FIG. FIG. 37 is a sectional view taken along the line CC ′ of FIG.

  34 includes a high-voltage N-channel MOSFET 35, a first logic circuit 36 connected to the gate electrode thereof, and a second logic circuit 37 on the high potential side connected to the drain electrode of the MOSFET 35. The HVIC shown in FIG. And a high-potential island isolation region 38. The drain electrode of the MOSFET 35 and the second logic circuit 37 are connected by a high-level level shift wiring 39.

As shown in the HVIC cross-sectional views of FIGS. 35, 36, and 37, an N + buried diffusion region 41 and an N− epitaxial layer 42 are formed on the P− semiconductor substrate 40. As shown in FIG. 35, the P + isolation diffusion region 43 is formed so as to reach the buried diffusion region 41. 35, 36, and 37, reference numeral 44 is a deep N + diffusion region, reference numeral 45 is a P diffusion region, reference symbol 46 is a P + diffusion region, reference symbol 47 is an N + diffusion region, and reference symbol 48 is a gate also used as a field plate. Reference numeral 49 is an aluminum electrode also used as a GND side field plate, reference numeral 50 is an oxide film, reference numeral 51 is a level shift aluminum electrode used as a level shift wiring, and reference numeral 52 is a field oxide film (LOCOS film). is there. Reference numeral 53 denotes a passivation film which is a protective film.
The HVIC configured as described above has a RESURF (Reduced Surface Field) structure isolation structure in which the N + buried diffusion region 41 and the N− epitaxial layer 42 are separated and surrounded by the P + isolation diffusion region 43.

In the conventional HVIC, since the high-potential level shift aluminum electrode 51 crosses the P + isolation diffusion region 43 and the P diffusion region 45 which are the substrate potential, the extension of the depletion layer is hindered and the breakdown voltage decreases. There is. In order to deal with this problem, in the conventional structure shown in FIG. 35, a field plate is formed on the PN junction by the gate electrode 48, etc., and the depletion layer is stretched. In addition, a MFFP (Multiple Floating Field Plate) structure that stabilizes the surface electric field by capacitive coupling has been used.
However, in the above-described conventional configuration, the thickness of the oxide film 50 formed between the level shift aluminum electrode 51 serving as the high potential level shift wiring and the aluminum electrode 49 serving as the GND side field plate is 1. It was 0 μm or more. However, such a configuration has a problem that the manufacturing process becomes complicated and the cost increases. Further, when the interlayer oxide film 50 is thick, a demerit that a fine processing technique cannot be applied has occurred.

In a power integrated circuit device (HVIC) which is a semiconductor device according to the twelfth embodiment of the present invention, the semiconductor manufacturing apparatus described in the first to third embodiments described above is used to solve the above-described problems and to provide level shift wiring. It is used to draw wiring.
FIG. 38 is a sectional view showing a structure in which level shift wiring 54 is formed in the HVIC according to the twelfth embodiment of the present invention. In FIG. 38, the film body having the same function as that shown in FIGS.

As shown in FIG. 38, in the HVIC of the twelfth embodiment, the level shift wiring 54, which is a conductive wiring, is formed on the passivation film 53 using the circuit drawing system of the semiconductor manufacturing apparatus described in the first to third embodiments. Is formed. Therefore, it is not necessary to provide the level shift aluminum electrode 51 as shown in FIG. 35, and the thickness of the interlayer oxide film 50 on the surface side of the aluminum electrode 49 which is the GND side field plate needs to be 1.0 μm or more. Disappear. As a result, a fine processing technique can be applied in the manufacture of HVIC.
Further, in the HVIC of the twelfth embodiment, the patterning for forming the passivation film 53 only requires an opening for a pad electrode of several tens of μm or more, and therefore the passivation film 53 is more than 1.0 μm. A thick film can be formed. Further, since a semi-insulating Sin film can be applied to the passivation film 53, the influence on the electric field distribution on the Si surface can be further mitigated by the electrostatic shielding effect.

  In the semiconductor device of the present invention, there are cases where there are more wiring formation portions than the insulating region depending on the IC chip surface. In this case, printing is performed on the surface of the IC chip using a highly insulating material such as polyimide as a printing solvent at a location where no wiring is formed. After that, by applying a conductive solvent to the entire wafer surface, an insulating film is reliably formed in the insulating region of the IC chip surface, and the insulating region in the IC chip surface is reliably insulated, and a highly reliable semiconductor device It becomes.

  FIG. 39 is a plan view showing an example in which a plurality of trimming pad electrodes are formed in a semiconductor device. In the semiconductor device shown in FIG. 39, cutting between pad electrodes designated for trimming processing and connection of other pad electrodes are performed. In the trimming process of the semiconductor device shown in FIG. 39, the film body is formed using a circuit drawing system so that the pad electrodes 9A and 9B in the region surrounded by the broken line T are cut and the other pad electrodes 9 are connected. It is formed.

  FIG. 40 is a plan view showing a state in which an insulating film body 4 is formed by injecting an insulating solvent between two pad electrodes 9A and 9B in the semiconductor device shown in FIG. 41 is a plan view showing a state in which the conductive film body 3 is formed by applying a conductive solvent to the entire surface of the semiconductor device shown in FIG.

42A is a cross-sectional view taken along line AA ′ in FIG. 40, FIG. 42B is a cross-sectional view taken along line BB ′ in FIG. 40, and FIG. It is sectional drawing by the -C 'line, (a) is sectional drawing by the AA' line of FIG. 40, and (d) is sectional drawing by the DD 'line of FIG. 42, the same reference numerals are given to the film bodies having the same functions as those shown in FIGS.
In the semiconductor device of the present invention, the surface may be protected with an insulating material such as polyimide after conductive wiring is formed by a circuit drawing system.
It is also possible to print chip information, for example, various information such as specifications, quality, and chip position in the wafer by the circuit drawing system used in the semiconductor manufacturing apparatus of the present invention.

  The present invention is useful in the field of semiconductor manufacturing because a desired conductive wiring or insulating film can be easily formed on a semiconductor device.

It is a block diagram which shows the structure of the circuit drawing system in the semiconductor manufacturing apparatus of Embodiment 1 which concerns on this invention. 6 is an explanatory diagram illustrating a drawing operation of a print head of the circuit drawing system according to Embodiment 1. FIG. 6 is an explanatory diagram illustrating a drawing operation of a print head of the circuit drawing system according to Embodiment 1. FIG. In the semiconductor manufacturing apparatus of Embodiment 2 which concerns on this invention, it is explanatory drawing which shows drawing operation | movement of the print head of a circuit drawing system in case the base wafer 1 has a convex shape. In the semiconductor manufacturing apparatus of Embodiment 2 which concerns on this invention, it is explanatory drawing which shows drawing operation | movement of the print head of a circuit drawing system in case the base wafer 1 has a concave shape. In the semiconductor manufacturing apparatus of Embodiment 3 which concerns on this invention, it is explanatory drawing which shows drawing operation | movement of the print head of a circuit drawing system in case the base wafer 1 has a convex shape. In the semiconductor manufacturing apparatus of Embodiment 3 which concerns on this invention, it is explanatory drawing which shows drawing operation | movement of the print head of a circuit drawing system in case the base wafer 1 has a concave shape. It is the molecular structure figure which showed the example of a composition of the electroconductive viscosity varnish as the electroconductive solvent 114 used in the semiconductor manufacturing apparatus of Embodiment 4 which concerns on this invention. 10 is a flowchart illustrating a wiring drawing operation by the circuit drawing system according to the fourth embodiment. FIG. 6 is a cross-sectional view showing a groove 8 formed in a base wafer 1 in the circuit drawing system according to the fourth embodiment. 6 is a cross-sectional view showing a convex portion 1A formed on a base wafer 1 in the circuit drawing system of Embodiment 4. FIG. In the semiconductor manufacturing apparatus of Embodiment 5 which concerns on this invention, it is a circuit diagram which shows the principle of the resistance value trimming by the R-2R circuit system which has a ladder type register network. In the circuit drawing system of Embodiment 5, it is a figure which shows the place which is performing the wiring drawing for trimming with respect to the wafer-like IC chip after a wafer test. It is sectional drawing which shows the injection | emission state of the print head 111 in the cross section by the A-A 'line in FIG. In the circuit drawing system of Embodiment 5, it is sectional drawing which shows the state in which the conductive wiring 3 was formed between the pad electrodes 9A and 9B for trimming. In the semiconductor manufacturing apparatus of Embodiment 6 which concerns on this invention, it is a top view of a semiconductor device which shows 1 set of pad electrodes 9 and 9 used as the object of the trimming process of a semiconductor device. (A) is sectional drawing by the B-B 'line of FIG. 16, (b) is sectional drawing by the C-C' line of FIG. (A) is sectional drawing by the B-B 'line in the state after the trimming process of the semiconductor device shown in FIG. FIG. 5B is a cross-sectional view taken along line C-C ′. FIG. 28 is a plan view of a semiconductor device showing another example in the semiconductor manufacturing apparatus of the sixth embodiment. 19A is a cross-sectional view taken along line B-B ′ of the semiconductor device of FIG. 19, and FIG. 19B is a cross-sectional view taken along line B-B ′ of the semiconductor device of FIG. 19 after the trimming process. It is a top view of the semiconductor device of Embodiment 7 which concerns on this invention. (A) is sectional drawing by the EE 'line in FIG. 21, (b) is a cross section which shows the state which apply | coated the solvent with respect to the pad electrodes 9 and 9 used as the desired drawing pattern in the semiconductor device of FIG. FIG. It is a top view of the semiconductor device of Embodiment 8 which concerns on this invention. It is sectional drawing by the FF 'line | wire in FIG. 23, (a) has shown the state before apply | coating a solvent to the semiconductor device of FIG. 23, (b) applied the solvent to the semiconductor device of FIG. Indicates the state. It is a top view of the semiconductor device of Embodiment 9 which concerns on this invention. FIG. 25 shows a state before a trimming process for a drawing pattern in the semiconductor device of the ninth embodiment, where (a) is a sectional view taken along line GG ′ in FIG. 25 and (b) is a sectional view taken along line HH ′. FIG. FIG. 25 shows a state after trimming processing of the semiconductor device of the ninth embodiment, where (a) is a cross-sectional view taken along line GG ′ in the semiconductor device of FIG. 25, and (b) is H in the semiconductor device of FIG. It is sectional drawing by a -H 'line. It is a top view of the chip | tip of IGBT which is a semiconductor device of Embodiment 10 which concerns on this invention. It is an equivalent circuit of the IGBT chip shown in FIG. 41 is a graph showing effects in the IGBT which is the semiconductor device of the tenth embodiment. It is sectional drawing which shows EPROM (Erasable Programmable Read Only Memory) of a general non-volatile memory. It is sectional drawing which shows the state by which EPROM was formed on the same chip | tip as a high voltage | pressure-resistant element, and was packaged with mold resin. It is sectional drawing which shows the structure of EPROM of Embodiment 11 which concerns on this invention. It is a top view which shows the conventional integrated circuit device for electric power. It is sectional drawing by the A-A 'line in FIG. It is sectional drawing by the B-B 'line | wire in FIG. It is sectional drawing by the C-C 'line | wire in FIG. It is sectional drawing which shows the structure of HVIC which is a semiconductor device of Embodiment 12 which concerns on this invention. It is a top view which shows the example in which the some pad electrode for trimming was formed in the semiconductor device of this invention. FIG. 40 is a plan view showing a state in which an insulating film is formed by injecting an insulating solvent between two pad electrodes 9A and 9B in the semiconductor device shown in FIG. 39. FIG. 41 is a plan view showing a state in which a conductive film 3 is formed by applying a conductive solvent to the entire surface to be a drawing pattern forming region of the semiconductor device shown in FIG. 40. 40A is a cross-sectional view taken along line AA ′ of FIG. 40, FIG. 40B is a cross-sectional view taken along line BB ′ of FIG. 40, and FIG. 40C is a cross-sectional view taken along line CC ′ of FIG. It is a figure, (a) is sectional drawing by the AA 'line of FIG. 40, and (d) is sectional drawing by the DD' line of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Ground wafer 2 Pretreatment liquid film 3 Conductive wiring 4 Insulating film 5 Silicon ladder polymer 6 Silane coupling agent 7 Carbon nanotube 8 Wafer ground groove part 9 Pad electrode 10 Passivation film 11 Interlayer oxide film 12 Semiconductor substrate 13 Recessed area 14 Liquid Anti-sagging groove 15 Anti-sagging protrusion 16 Groove hole 17 Gate electrode pad 18 Emitter electrode pad 19 Gate wiring aluminum wiring 20A, 20B, 20C, 20D, 20E, 20F IGBT cells 21A, 21B, 21C, 21D, 21E, 21F Pad electrode 22 High breakdown voltage isolation region 23A, 23B, 23C, 23D, 23E, 23F Trimming pad 24 P type semiconductor substrate 25 N type diffusion region 26 Gate oxide film 27 Floating gate 28 Control gate 29 Interlayer oxide film 30 Passivation 31 a field oxide film 32 mold resin portion 33 semi-insulating silicon nitride film 34 electrostatic shield layer 35 high-voltage N-channel MOSFET
36 First logic circuit 37 Second logic circuit 38 High potential island 39 Level shift wiring 100 Wafer test unit 110 Drawing pattern printing unit 111 Print head 112 Chip coordinate recognition unit 113 Control unit 114 Conductive solvent 115 Insulating solvent 116 Treatment liquid 120 database section

Claims (24)

A wafer test unit that detects the characteristics of each chip in the wafer to be inspected and determines a drawing pattern for trimming for each chip based on the detected data;
Based on the storage unit for storing information on the wafer to be inspected, the drawing pattern information from the wafer test unit and the information on the wafer from the storage unit, a desired drawing pattern for each chip of the wafer A drawing pattern printing section formed by a printing operation;
The drawing pattern printing unit
A print head for injecting at least each of a conductive solvent, an insulating solvent, and an interface treatment liquid;
A chip coordinate recognition unit that acquires coordinate information of each chip by image recognition on the wafer,
A control unit for controlling a drawing operation of the print head on the wafer based on information on the drawing pattern from the wafer test unit, information on the wafer from the storage unit, and coordinate information from the chip coordinate recognition unit; A semiconductor manufacturing apparatus having the structure. A print head for injecting a liquid from the opening having a single or a plurality of minute diameters to the pattern forming region;
A storage unit that stores information of a drawing pattern drawn by ejection from the print head;
A control unit that causes the print head to perform a drawing operation according to information on a drawing pattern stored in the storage unit,
The print head is
A first nozzle that injects a conductive solvent into the pattern forming region;
A second nozzle that injects an insulating solvent into the pattern forming region; and a pattern forming region before the conductive solvent is injected, or a pattern forming region before the insulating solvent is injected A semiconductor manufacturing apparatus having a third nozzle for injecting an interface treatment liquid.   The print head includes a first sensor that detects a distance from each nozzle tip to a drawing pattern formation region before the liquid is ejected, and the control unit is configured to control the print head based on distance information from the first sensor. The semiconductor manufacturing apparatus according to claim 1, which is configured to perform position control.   The print head includes a second sensor that detects a distance to the solvent surface on the drawing pattern formation region after the liquid is ejected from each nozzle tip, and is controlled based on distance information from the second sensor. The semiconductor manufacturing apparatus according to claim 1, wherein the unit is configured to perform film thickness control of the drawing pattern. Detecting the characteristics of each chip on the wafer to be inspected, and determining a drawing pattern for trimming on each chip based on the detected data;
Based on the determined drawing pattern information, the step of injecting the interface treatment liquid into the drawing pattern forming region on the chip surface of the wafer, and the drawing pattern forming region from which the interface processing solution was injected A step of injecting a conductive solvent or an insulating solvent based on the drawing pattern;
A semiconductor manufacturing method comprising:   A step of detecting a distance from a print head for injecting a conductive solvent or an insulating solvent to a drawing pattern forming region before the solvent is injected, and the position of the print head based on the detected pre-injection distance information The semiconductor manufacturing method according to claim 5, further comprising a step of performing control.   A step of detecting the distance from the print head that injects the conductive solvent or the insulating solvent to the solvent surface on the pattern formation area after the solvent is injected, and drawing based on the detected post-injection distance information The semiconductor manufacturing method of Claim 5 or 6 which has the process of controlling the film thickness of a pattern.   The semiconductor manufacturing method of Claim 5 using the film-forming material which added the electroconductive raw material to the silicon ladder polymer solution which the electroconductive solvent melt | dissolved in the organic solvent.   6. The semiconductor manufacturing method according to claim 5, wherein an injection region diameter at the time of injection of the conductive solvent or the insulating solvent is 30% or less with respect to a width of a line to be formed in the pattern forming region.   The semiconductor manufacturing method according to claim 9, wherein the conductive material includes at least one selected from carbon black, carbon nanotubes, silver, copper, nickel, palladium, and metal oxides of the above metals. The semiconductor manufacturing method according to claim 10, wherein the conductive material is a film forming material to which a silane coupling agent is added as a surface treatment agent. Forming a groove portion having a predetermined depth in a drawing pattern forming region of the wafer;
A process of inspecting the necessity of trimming the wafer,
A step of drawing a drawing pattern by injecting a conductive solvent into the groove of the wafer that needs trimming in the wafer;
Degassing and low-temperature annealing after drawing the drawing pattern,
A step of flattening the film-forming surface after degassing and low-temperature annealing, and a step of high-temperature annealing after flattening,
A semiconductor manufacturing method comprising:   The semiconductor manufacturing method according to claim 12, wherein an injection region diameter at the time of injection of the conductive solvent is 30% or less with respect to the width of the groove.   Grooves having a predetermined depth are formed in the pattern forming region for trimming on each chip in the wafer, and the side walls of the grooves are inclined so that the opening side becomes wider with an inclination angle of 5 ° or more, A semiconductor device in which conductive wiring is formed inside a groove.   The semiconductor device according to claim 14, wherein the groove portion formed in the drawing pattern forming region is formed in a convex region formed on the wafer surface.   In the wafer state, at least two trimming pad electrodes exposed from the passivation film are formed on each chip surface, and a drawing pattern is formed by a printing process on the trimming pad electrode based on the result of the necessity inspection of trimming. Semiconductor device.   The semiconductor device according to claim 16, wherein a passivation film is formed in a region other than a region connecting at least two trimming pad electrodes on which a drawing pattern is printed.   18. The semiconductor device according to claim 17, wherein a passivation film is formed in a region other than a region having a predetermined distance from at least two trimming pad electrodes on which a drawing pattern is printed.   19. The semiconductor device according to claim 17, wherein a groove is formed at a position surrounding at least two trimming pad electrodes on which a drawing pattern is printed.   19. The semiconductor device according to claim 17, wherein a protrusion is formed at a position surrounding at least two trimming pad electrodes on which a drawing pattern is printed.   19. The semiconductor device according to claim 17, wherein a groove is formed between at least two trimming pad electrodes on which the drawing pattern is printed.   The semiconductor device is an IGBT chip having a plurality of cells and provided with routing wiring in which routing pad electrodes are formed at positions corresponding to the cells, and each cell is connected to the first electrode. 1 pad electrode and a second pad electrode connected to the second electrode, and the first electrode and the routing pad electrode or the second electrode based on the inspection result of each cell A semiconductor device configured such that a drawing pattern is formed by a printing process.   A semiconductor device in which a semiconductor device is a non-volatile memory, a grounded electrostatic shield film body is formed by a printing process so as to cover a memory region, and is molded so as to cover the electrostatic shield film body. The semiconductor device is a power integrated circuit device in which a power semiconductor device and a logic circuit are integrated on a single chip,
A semiconductor device in which a conductive wiring which is a level shift wiring for electrically connecting a logic circuit formed in a high potential island isolation region and a high withstand voltage switching element is formed on a passivation film by a printing process of a drawing pattern.

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