JP2007258527A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of frequent generation of defective elements due to corrosion of a contact in a high temperature bias reliability test when a surface protection film of a chip is constituted of a low thermal-expansion polyimide resin alone in order to reduce a cost, since a first wiring metallic layer (high side part) of a high withstand voltage MOSFET and a contact part (low side part) between a second wiring metallic layer and a resistor are arranged closely in a high voltage level shift of an IC, for example. <P>SOLUTION: A third wiring metallic layer of the same potential (GND potential) as a low side is disposed between a high side and the low side. Consequently, even if corrosion is generated due to a high voltage applied, it is possible to shield corrosion from advancing in the third wiring metallic layer of a dummy pattern. In other words, even if a surface protection film is formed of only a low thermal-expansion polyimide resin of a low cost, it is possible to prevent corrosion from attaining a contact in a high temperature bias reliability test, thus avoiding generation of a defective element. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly, to a semiconductor device that improves an element defect in a high temperature and high humidity reverse bias reliability test.

A high-temperature bias test, which is one of reliability tests, is performed in a high-temperature electric furnace, and evaluation is performed by examining device operation by electrical measurement after a predetermined test time (for example, 1000 hours) has elapsed ( For example, see Patent Document 1).
JP-A-6-51017

The high-temperature, high-humidity reverse bias test for a high voltage IC needs to avoid stress from the package and improve reliability. For this reason, a low thermal expansion resin (for example, PIX (registered trademark): hereinafter, low thermal expansion polyimide resin) containing polyimide as a main component is employed as a surface protective film of a semiconductor substrate. The low thermal expansion type polyimide resin has a thermal expansion coefficient of about 3 × 10 ⁻⁵ ° C. ^{−1 to} 5 × 10 ⁻⁵ ° C. ⁻¹ . For example, the thermal expansion coefficient of a silicon semiconductor substrate (3 × 10 ⁻⁶ · ° C. ^{− Since the} difference in thermal expansion coefficient from ¹ ) is relatively small, it is widely used as a surface protective film material that suppresses warpage of the wafer.

  Since the low thermal expansion polyimide resin generally has high water absorption, there are cases where a two-layer structure of a nitride film and a low thermal expansion polyimide resin is used as a surface protective film. However, when a nitride film is used as the surface protective film, it is necessary to form it with a thickness of, for example, about 7000 mm, which is expensive. In addition, there is a variation in characteristics due to stress in the nitride film, and defects in the high temperature and high humidity reverse bias test increase. Therefore, a technique is known in which the film thickness of the low thermal expansion type polyimide resin is increased and the surface protective film is formed using only the low thermal expansion type polyimide resin.

  However, there is a limit to increasing the thickness of the low thermal expansion polyimide resin. That is, if the film thickness is too thick, there are disadvantages in that the etching time for creating the opening increases, the pad and metal overlap increase, and the size cannot be reduced, and the cost increases. In other words, the film thickness is limited to about 20000 mm, but when only the low thermal expansion polyimide resin is used as the surface protective film, the penetration of moisture cannot be completely prevented even if the above thickness is secured.

  For this reason, there is a problem in that defective elements that are likely to be corroded in a specific region due to application of a high potential and moisture during a high-temperature, high-humidity reverse bias reliability test and fail to operate normally occur frequently.

  The present invention has been made in view of the various circumstances described above. First, a transistor provided on a semiconductor substrate, a first wiring metal layer connected to the transistor, to which a high potential is applied, and the transistor are provided. A second wiring metal layer to which a low potential is applied; another conductor provided on the semiconductor substrate; a contact portion between the second wiring metal layer and the other conductor; and the contact portion And a third wiring metal layer disposed between the first wiring metal layers and connected to the second wiring metal layer, and a low thermal expansion resin layer mainly composed of polyimide covering the surface of the semiconductor substrate. To solve this problem.

  First, a third wiring metal connected to the second wiring metal layer between a first wiring metal layer that is at a high potential and a contact portion between the second wiring metal layer that is at a low potential and another conductor. Provide a layer. Application of a high electric field and corrosion due to moisture can be blocked by the third wiring metal layer and can be prevented from reaching the contact portion.

  Second, since corrosion at the contact portion can be prevented, only a low thermal expansion polyimide resin can be employed as the surface protective film, and a nitride film is not required, so that an increase in cost can be suppressed.

  Third, the third wiring metal layer is connected to the second wiring metal layer to which a low potential is applied. That is, since the third wiring metal layer can be provided by changing the pattern of the second wiring metal layer, it is possible to easily provide an element having high resistance to the high temperature bias reliability test.

  Specifically, 15 defective elements were generated in 30 pieces in the conventional high temperature bias reliability test for 168 hours (temperature 85 ° C., humidity 85%) due to corrosion of the contact portion. However, in this embodiment, the corrosion does not reach the contact portion, and no defective element was generated even in the test for 1000 hours (temperature 85 ° C., humidity 85%).

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.

  The semiconductor device of this embodiment includes a semiconductor substrate 1, a transistor 2, a first wiring metal layer 3, a second wiring metal layer 4, a third wiring metal layer 5, a contact portion 6, and other conductors. 7 and a low thermal expansion polyimide resin layer 8.

  FIG. 1 is a cross-sectional view showing an outline of the semiconductor element of this embodiment.

  The semiconductor substrate is, for example, a silicon semiconductor substrate 1, and an active element such as a transistor 2 is provided on the surface thereof. The transistor is, for example, a MOSFET 2 having a high breakdown voltage (about 100 V to 600 V). The first wiring metal layer 3 is connected to the MOSFET 2 and is a wiring or an electrode pad to which a high potential is applied. The second wiring metal layer 4 is a wiring or electrode pad that is connected to the MOSFET 2 and to which a low potential is applied. The other conductor 7 is a resistor, wiring, or other active element or passive element integrated on the same semiconductor substrate 1 as the MOSFET 2. The second wiring metal layer 4 and the other conductor 7 are electrically connected by the contact portion 6. The third wiring metal layer 5 is connected to the second wiring metal layer 4 and is disposed between the contact portion 6 and the first wiring metal layer 3. The first wiring metal layer 3, the second wiring metal layer 4, and the third wiring metal layer 4 on the surface of the semiconductor substrate 1 are formed of a low thermal expansion resin layer (low thermal expansion polyimide resin layer) 8 mainly composed of polyimide. Covered with a surface protective film

  Hereinafter, in the present embodiment, as an example of a semiconductor device, an integrated circuit (hereinafter referred to as a high voltage IC) in which a high voltage MOSFET 2 and a resistor are integrated on one silicon semiconductor substrate 1 will be described as an example.

  2 and 3 are enlarged views showing a part of the high voltage IC. FIG. 2A is a plan view in which a transistor and another conductor are superimposed on the first wiring metal layer 3, the second wiring metal layer 4, and the third wiring metal layer 5, and FIG. FIG. 3 is a plan pattern diagram of only one wiring metal layer 3, second wiring metal layer 4, and third wiring metal layer 5, and FIG. 3 is a cross-sectional view taken along the line aa in FIG.

  The high voltage IC is, for example, a high side driver having a high voltage level shift unit 10, and the figure is an enlarged view of the high voltage level shift unit 10.

  In the high voltage IC, desired elements are integrated inside the shielding polysilicon 30, and the high voltage level shift unit 10 is provided outside the high voltage MOSFET 2 and the like.

  Although not shown in detail, the MOSFET 2 forms a device region by providing a drain region and a source region by implanting and diffusing a p-type impurity and an n-type impurity in the semiconductor substrate 1, and a gate made of polysilicon or the like. An electrode is provided. The metal layer provided on the surface of the semiconductor substrate 1 is patterned into a desired shape, the drain electrode made of the first wiring metal layer 3 is brought into contact with the drain region, and the source electrode made of the second wiring metal layer 4 is brought into contact with the source region. Contact. In the case of the MOSFET 2, the first wiring metal layer 3 and the second wiring metal layer 2 are simultaneously formed by patterning the same wiring metal layer. However, the present embodiment is not limited to this. That is, the first wiring metal layer 3 and the second wiring metal layer 4 may be formed of different metal layers in different processes.

  For example, a high voltage of 300 V is applied to the first wiring metal layer (drain electrode) 3 of the MOSFET 2. On the other hand, the second wiring metal layer (source electrode) 4 of the MOSFET 2 is connected to another conductor (here, a resistor) 7 in the contact portion 6, and the other end of the resistor 7 becomes a ground (GND) potential. Although not shown, the resistor 7 intersects the first wiring metal layer 3 through an insulating film provided thereabove.

  That is, in the high voltage level shift part as shown in FIG. 2, the high side part H (first wiring metal layer 3) and the low side part L (contact part 6) are arranged close to each other at a distance of about 100 μm, for example. In the present embodiment, the third wiring metal layer 5 is disposed between the first wiring metal layer 3 that becomes the high side portion H and the contact portion 6 that becomes the low side portion L. The third wiring metal layer 5 is connected to the second wiring metal layer 4. Here, the same metal layer as the second wiring metal layer 4 is patterned as shown in FIG. 2B, and the third wiring metal layer 5 is provided.

  As shown in FIG. 3, in the contact portion 6, polysilicon is patterned into a desired shape through the insulating film 20 on the substrate 1 and a resistor 7 is arranged, and a contact hole CH is provided in the insulating film 20 covering the resistor 7. Then, the second wiring metal layer 4 and the resistor 7 are brought into contact.

  Further, as described above, the third wiring metal layer 5 is connected to the second wiring metal layer 4, that is, the third wiring metal layer 5 is equipotential with the low side portion L.

  In such a high voltage level shift part, a high voltage is applied between the high side part H and the low side part L in the high temperature bias reliability test. And when the surface protective film is not provided with a nitride film and only a low thermal expansion type resin layer is used, even if the film thickness is increased, moisture penetration is not complete, and high potential difference and corrosion due to moisture occur. .

  Conventionally, the corrosion frequently reaches the contact portion 6, resulting in frequent element failures, but in the present embodiment, this can be prevented by the third wiring metal layer 5.

  FIG. 4 illustrates failure modes in the high temperature bias reliability test. FIG. 4A is an equivalent circuit diagram of this embodiment. FIG. 4B is a plan view for explaining the state of corrosion in the conventional structure. In addition, the same component as this embodiment was shown with the same code | symbol.

  As shown in FIG. 4A, the drain of the MOSFET 2 is connected to a (CMOS) inverter circuit 32. The (CMOS) inverter circuit 32 is connected to the VH terminal of the power supply and the HFG terminal of the GND line.

  The drain is connected to the VH terminal which is the power line of the high side portion H via the level shift resistor 33, and the inverter circuit 32 is connected to the HFG terminal which is the GND line of the high side portion H. The source of the MOSFET 2 is connected to one end of the resistor 7 and the other end of the resistor 7 is grounded.

  In this circuit, when 300 V is applied between the HFG terminal and GND, 300 V is applied to the drain of the MOSFET 2. At this time, since the MOSFET 2 is in an off state, the source potential of the MOSFET 2 becomes the GND potential, and both ends of the resistor 7 become the GND potential.

  As shown in FIG. 4B, the first wiring metal layer 3 extends across the resistor 7 via an insulating film (not shown here) as shown in FIG. 3, for example, and is connected between the HFG terminal and GND. When 300 V is applied, a voltage of 300 V is applied between the first wiring metal layer 3 that is the drain electrode of the MOSFET 2 and both ends of the resistor 7 (see arrows in FIG. 4B)).

  Further, the surface protective film is only a low thermal expansion polyimide resin layer, and even if the film thickness is sufficiently thick, it is difficult to completely block moisture because of its high water absorption.

  Therefore, when a high temperature bias reliability test is performed in this state, moisture is concentrated between the high side portion H and the low side portion L (arrow in FIG. 4A) where a potential difference of 300 V is applied due to electric field concentration. As a result, the resistor 7 and the contact portion 6 'of the MOSFET 2 and the resistor 7 and the contact portion 6' of the GND line are corroded, and the resistor 7 is opened.

  Although one MOSFET 2 is shown here, the high voltage level shift unit 10 is provided with two MOSFETs 2 on the set side and the reset side. Since these have the same structure, if the contact portion 6 ′ of the set-side MOSFET 2 becomes abnormal, the high-side output HOUT continues to maintain “L”. On the other hand, if the contact portion 6 of the reset-side MOSFET 2 becomes abnormal, the high-side output HOUT is abnormally maintained at “H”.

  Therefore, in the present embodiment, as shown in FIG. 2, the third wiring metal layer 5 is disposed between the contact portion 6 that becomes the low side portion L and the first wiring metal layer 3 that becomes the high side portion H. The third wiring metal layer 5 is equipotential (GND potential) with the low side portion L. Thereby, even if it is a case where said corrosion generate | occur | produces by application of a high voltage, the progress of corrosion can be prevented by the 3rd wiring metal layer 5. FIG. The third wiring metal layer 5 is a so-called dummy pattern, and even if this portion is corroded, the element is not affected at all.

  Referring again to FIG. 2, in order to block the progress of corrosion by the third wiring metal layer 5, the length L2 of the third wiring metal layer 5 is the length of the contact portion 6 (width of the contact hole CH) L1. Make it longer. The third wiring metal layer 5 has a predetermined length in parallel with the first wiring metal layer 3 so that the distance between the first wiring metal layer 3 to which the high potential is applied and the third wiring metal layer 5 are equal. For example, it is desirable to arrange at 10 μm or more.

  Further, in the present embodiment, the separation distance L3 between the first wiring metal layer 3 and the third wiring metal layer 5 is 60 μm to 70 μm (preferably 68.5 μm), and the first wiring metal layer 3 and the contact portion. 6 is about 90 μm to 110 μm (preferably 103.5 μm).

  In the conventional case, after 168 hours (temperature 85 ° C., humidity 85%) with 300 V applied, the contact portion 6 ′ (FIG. 4B) turned black and corrosion was observed. Further, this corrosion was observed on 15 out of 30 chips.

  On the other hand, according to the present embodiment, after 1000 hours (temperature: 85 ° C., humidity: 85%) with 300 V applied, the third wiring metal layer 5 as the dummy pattern turned black and corrosion was observed, but the contact portion No corrosion was reached in 6. Also, no defects were found on all the chips tested.

  When the test time of the high temperature bias test is 168 hours (conventional) and the case of 1000 hours (this embodiment), for example, at the point x in FIG. 2, x ′ in the conventional case (FIG. 4B). Corrosion progressed from the point. However, in FIG. 2, the progress of the corrosion of the third wiring metal layer 5 is less than the vicinity of the point x, and it is found that the progress of the corrosion is suppressed by the third wiring metal layer 5 which is a dummy pattern.

That is, according to the present embodiment, the surface protective film can be constituted only by the low thermal expansion polyimide resin layer 8, and a semiconductor device that is low in cost and highly resistant to a high temperature bias reliability test can be provided.

It is the schematic for demonstrating this invention. It is a top view for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is (A) an equivalent circuit diagram and (B) top view for explaining the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Transistor 3 1st wiring metal layer 4 2nd wiring metal layer 5 3rd wiring metal layer 6 Contact part 7 Other conductors 8 Low thermal expansion type polyimide resin layer (surface protective film)
10 High voltage level shift part 20 Insulating film

Claims (4)

A transistor provided on a semiconductor substrate;
A first wiring metal layer connected to the transistor and to which a high potential is applied;
A second wiring metal layer connected to the transistor and to which a low potential is applied;
Another conductor provided on the semiconductor substrate;
A contact portion between the second wiring metal layer and the other conductor;
A third wiring metal layer disposed between the contact portion and the first wiring metal layer and connected to the second wiring metal layer;
A low thermal expansion resin layer mainly composed of polyimide covering the surface of the semiconductor substrate;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the third wiring metal layer is at a ground potential.   2. The semiconductor device according to claim 1, wherein each of the first wiring metal layer and the third wiring metal layer has a predetermined length and extends on the semiconductor substrate in parallel with each other. The semiconductor device according to claim 1, wherein a length of the third wiring metal layer is longer than a length of the contact portion.