CN103377954B - Gate pads and the forming method of source pad - Google Patents
Gate pads and the forming method of source pad Download PDFInfo
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- CN103377954B CN103377954B CN201210132712.XA CN201210132712A CN103377954B CN 103377954 B CN103377954 B CN 103377954B CN 201210132712 A CN201210132712 A CN 201210132712A CN 103377954 B CN103377954 B CN 103377954B
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Abstract
The present invention relates to the forming method of a kind of gate pads and source pad, form the step of the albronze layer of gate pads and source pad including physical vapor deposition on wafer, the deposition temperature of described depositing step maintains 250 ± 10 degrees Celsius.Between grid and source pad that the forming method of above-mentioned gate pads and source pad is formed, color distortion is bigger, therefore the identification requirement of bonding machine platform is met, rework rate can be reduced, and simple to operate, use original production equipment just can implement, without adding new equipment, the cost purchasing new equipment will not be increased.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to the formation of a kind of gate pads and source pad
Method.
Background technology
Double-diffusion metal-oxide-semiconductor field effect transistor (DMOSFET) product, in packaging technology, needs
Carry out being bonded (bonding) with gold thread by the pad (pad) on grid and source electrode.Generally, bonding
Board can be bonded automatically according to the pad of grid and source electrode difference in color, but sometimes can
Bonding machine platform is caused cannot the two to be made a distinction, such as Fig. 1 because difference is the least between gate pads and source pad
Shown in.In Fig. 1, the left side is the product that bonding machine platform is capable of identify that, the right is the impalpable product of bonding machine platform
Product.This series products on the right of Fig. 1 by the most manually connecting gold thread, thus can only cause production efficiency low
Under.
Summary of the invention
Based on this, it is necessary to the forming method for traditional gate pads and source pad can cause pad face
The different too small problem of aberration, it is provided that a kind of gate pads being obtained in that bigger color distortion and source pad
Forming method.
A kind of gate pads and the forming method of source pad, form grid including physical vapor deposition on wafer
The step of the albronze layer of pole pad and source pad, the deposition temperature of described depositing step maintains 250
± 10 degrees Celsius.
Wherein in an embodiment, described physical vapor deposition forms gate pads and source electrode weldering on wafer
The step of the albronze layer of dish, is specifically carried out in the second cavity, and also includes following after this step
Step: whether monitor the temperature in described second cavity more than the first temperature threshold, until described albronze
Layer deposit is complete；Once more than the first temperature threshold, interrupt the deposit of described albronze layer, and by described
Wafer removes described second cavity and lowers the temperature, and described second cavity is carried out cooling process simultaneously；Monitoring institute
State whether the temperature in the second cavity is less than the second temperature threshold, once less than the second temperature threshold, by described
Wafer is retracted described second cavity and is proceeded deposit.
Wherein in an embodiment, described first temperature threshold is 255 degrees Celsius.
Wherein in an embodiment, described physical vapor deposition forms gate pads and source electrode weldering on wafer
The step of the albronze layer of dish is included in and deposits the albronze layer of the first thickness in the second cavity and second
Cavity deposits two steps of the albronze layer of the second thickness, and also include between said two step by
Wafer removes described second cavity and lowers the temperature, and described second cavity is carried out cooling process simultaneously, until institute
State the step less than the second temperature threshold of the temperature in the second cavity.
Wherein in an embodiment, described first thickness is 22,000 angstroms and the second thickness is 22,000 angstroms.
Wherein in an embodiment, described second temperature threshold is 245 degrees Celsius.
Wherein in an embodiment, described physical vapor deposition forms gate pads and source electrode weldering on wafer
Before the step of the albronze layer of dish, it is additionally included in the first cavity by physical vapor deposition process in institute
State and on wafer, deposit titanium coating and the step of titanium nitride layer.
Wherein in an embodiment, described in the first cavity, deposit titanium by physical vapor deposition process
Before belonging to the step of layer and titanium nitride layer, it is additionally included in the step toasting described wafer in degassing cavity.
Wherein in an embodiment, baking temperature in the described step toasting described wafer in degassing cavity
It it is 150 ± 10 degrees Celsius.
Wherein in an embodiment, the step of described deposit titanium coating and titanium nitride layer is to enter at normal temperatures
Row deposit.
Color distortion between grid and source pad that the forming method of above-mentioned gate pads and source pad is formed
Relatively big, therefore meet the identification requirement of bonding machine platform, it is possible to reduce rework rate, and simple to operate, use former
Some production equipment just can be implemented, it is not necessary to adds new equipment, will not increase the cost purchasing new equipment.
Accompanying drawing explanation
Fig. 1 is that bonding machine platform is capable of identify that and impalpable grid and source pad photo；
Fig. 2 is to be 300 degrees Celsius and 250 degrees Celsius of lower grids and the photo of source pad respectively；
Fig. 3 is the deposition temperature data using a kind of Endura board to carry out when albronze layer deposits；
Fig. 4 is the flow chart of the forming method of gate pads and source pad in an embodiment；
Fig. 5 is titanium coating, titanium nitride layer and the structural representation of albronze layer；
Fig. 6 is the flow chart of the forming method of gate pads and source pad in another embodiment；
Fig. 7 is the deposition temperature data using the method for embodiment illustrated in fig. 6 to carry out when albronze layer deposits；
Fig. 8 is to use the comparative example and traditional 300 of temperature data shown in embodiment, Fig. 3 described in Fig. 6
Grid that degree Celsius technology is formed and the photo of source pad.
Detailed description of the invention
Understandable, below in conjunction with the accompanying drawings to this for enabling objects, features and advantages of the present invention to become apparent from
Bright detailed description of the invention is described in detail.
Gate pads is that (material is albronze to this metal level due to grid with the color distortion of source pad
Alloy) it is covered on a flatter surface, and this metal level (material is similarly albronze) of source electrode
It is covered on a rougher surface, therefore source pad in theory should be darker than gate pads.
But inventor finds according to research and experiment, if the metal level of above-mentioned source electrode temperature when deposit is higher,
Then the crystallite dimension (grain size) of metal level will be relatively big, even by the most coarse table below metal level
Surface curve all covers, and the layer on surface of metal causing source electrode is the least, finally with the layer on surface of metal difference of grid
Performance be exactly that source pad is the least with the color distortion of gate pads, cause be bonded (bonding) board without
Method identifies source pad and the gate pads of DMOS device automatically.
Therefore inventor speculates if reducing and efficiently controlling the metal level of the pad temperature in deposition process
Degree, it is possible to obtain the bigger grid of color distortion and source pad.Experimental result is as shown in Figure 2.Fig. 2
Respectively illustrate at 300 degrees Celsius and carry out under 250 degrees Celsius the metal of gate pads and source pad
The photo of two wafer (wafer) local of layer deposit, at a temperature of from figure, we can be respectively seen two kinds
It is positioned at the color distortion contrast of the chip (die) of crystal circle center and the chip of crystal round fringes, under 250 degrees Celsius
Color distortion between grid and source pad is significantly more than the color distortion under 300 degrees Celsius.This metal
The deposit of layer uses physical vapor deposition process, and what deposit was formed is albronze for metal level material.In reality
Physical vapor deposition can be formed the albronze layer of gate pads and source pad on wafer by border in producing
In technique, deposition temperature controls at 250 ± 10 degrees Celsius, preferably 250 degrees Celsius.
But in actual production, the temperature of deposit albronze layer is usually 270 and 300 degrees Celsius in the industry
Two kinds.To use the technique of 250 degrees Celsius, the conversion between the most various temperature process can be more complicated,
It is difficult to control to.As a example by a kind of Endura board, its purpose of design is for the ring at 300 degrees centigrade
Carry out the deposit of albronze thin film under border, if being therefore deposited under 250 degrees Celsius of technique, then along with
Being carried out continuously of depositing technics, temperature will be unstable, as shown in Figure 3.Specifically show temperature in figure 3
The trend that degree is gradually increasing.
For this problem, inventor proposes again the forming method of a kind of gate pads and source pad, and Fig. 4 is
In one embodiment, the flow chart of the forming method of gate pads and source pad, comprises the following steps:
S110, is placed in wafer in degassing cavity and toasts.
Notice that the DMOS front road technique of the wafer in this step completes, because using conventional process so
Place repeats no more.Baking temperature can be 150 ± 10 degrees Celsius, preferably 150 degrees Celsius.
S120, deposits titanium coating and nitridation by physical vapor deposition process in the first cavity on wafer
Titanium layer.
In the present embodiment, this step uses room temperature to be deposited.Use relatively low temperature (such as room temperature)
It is deposited in the step contributing to improving subsequent deposition albronze layer, the crystallite dimension of crystal so that it is become
Obtain less.Titanium nitride layer 20 is covered on titanium coating 10, as shown in Figure 5.It is pointed out that titanium
Structure under metal level 10 is omitted in Figure 5.In the present embodiment, the thickness of titanium coating is
The thickness of titanium nitride layer is
S130, deposits albronze layer by physical vapor deposition process in the second cavity.
Wherein albronze layer 30 is covered on titanium nitride layer 20, as shown in Figure 5.Deposition temperature can be
250 ± 10 degrees Celsius, preferably 250 degrees Celsius.
Whether S140, monitoring the temperature in the second cavity more than the first temperature threshold, if exceeding, performing step
S142, otherwise performs step S150.
If the first temperature threshold arranges too high, then the color distortion of grid and source pad is the most obvious；If
Arrange too low, need frequently to cool down, affect production efficiency.In the present embodiment, the first temperature threshold is set to
255 degrees Celsius.
S142, interrupts deposit and wafer removes the second cavity cooling, carrying out cold to the second cavity cavity simultaneously
But process, until the temperature in the second cavity is less than the second temperature threshold.
Wafer specifically can be moved to cooling cavities cooling.The cooling down of wafer and the second cavity can use
Natural cooling, it is also possible to the nitrogen being passed through chemical property inactive gas such as temperature relatively low carries out cold
But.When second cavity cavity carries out cooling process, it is still to continue to monitor the temperature in the second cavity, until
Temperature in second cavity is less than the second temperature threshold, then perform step S150.
If the second temperature threshold arranges too high, then need frequently to cool down, affect production efficiency；If arranging too low,
Then deposition temperature is more less than preferred temperature, may affect device performance.In the present embodiment, the second temperature
Degree threshold value is set to 245 degrees Celsius.
In the present embodiment, the target thickness of albronze layer deposit is 44,000 angstroms, i.e. 4400 nanometers.
S150, continues deposit until completing the deposit of albronze.Wafer is carried out after completing by step S150
Cooling, finally returns to film magazine.
In one embodiment, step S140 is measured the temperature in the second cavity more than the first temperature threshold after,
It not to be immediately terminated deposit, but again the second cavity is carried out cooling process after this wafer has deposited.
After the second cavity has cooled down (temperature in the i.e. second cavity be less than the second temperature threshold) again under a piece of
Wafer carries out the deposit of albronze layer.
Fig. 6 is the flow chart of the forming method of gate pads and source pad in another embodiment, itself and Fig. 4
Differring primarily in that of illustrated embodiment: closed by physical vapor deposition process deposit copper aluminum in the second cavity
The step of layer gold is to be undertaken in two steps.I.e. comprise the following steps: after step S210 and S220
S230, first deposits the albronze layer of a half thickness in the second cavity by physical vapor deposition process.
Such as the albronze layer that target thickness is 44,000 angstroms, step S230 first deposits 22,000 angstroms of thickness
Albronze.
S240, removes wafer the second cavity cooling, the second cavity is carried out cooling process simultaneously, until the
Two cavity temperatures are less than the second temperature threshold.
In the present embodiment, the second temperature threshold is set to 245 degrees Celsius.
S250, by the albronze of physical vapor deposition process deposit residue one half thickness in the second cavity
Layer.
It is to be appreciated that the deposition thickness in step S230, S250 can also be distributed in other embodiments
Replaced to other ratio by each 50%, such as prior to step S230 deposits the albronze layer of 40% thickness,
Remaining 60% is deposited then at step S250.
In other embodiments, it is also possible to Fig. 4 and Fig. 6 two schemes is combined, by the shallow lake of albronze layer
Integration be two steps, such as embodiment illustrated in fig. 6 the first depositing step in first deposit half, the second deposit step
Suddenly second half is deposited again.If the first depositing step detects that temperature is higher than first threshold, then the first deposit step
Suddenly after completing, wafer and the second cavity are cooled down, after being cooled to the second temperature threshold, perform the second deposit again
Step；If detecting that temperature is higher than first threshold in the second depositing step, then treat this wafer albronze
Second cavity is cooled down after completing by the deposit of layer again.
Above-mentioned gate pads and the forming method of source pad, it is possible to the deposition temperature of albronze layer is controlled
Target temperature (250 degrees Celsius) ± 6 degrees Celsius in, as shown in Figure 7.Fig. 8 respectively illustrates employing
Comparative example and traditional 300 degrees Celsius of technology of temperature data shown in embodiment, Fig. 3 described in Fig. 6 are formed
Grid and the photo of source pad.The most above-mentioned gate pads and the formation side of source pad
Between grid and source pad that method is formed, color distortion is relatively big, therefore meets the identification requirement of bonding machine platform,
Can reduce rework rate, and simple to operate, use original production equipment just can implement, it is not necessary to add new
Equipment, will not increase the cost purchasing new equipment.
Although above example introduction is gate pads and the forming method of source pad of DMOS device,
But those skilled in the art will envision that other device similar for structure and material, need to use bonder
Grid and source pad are carried out being bonded by platform with gold thread, it is possible to use the method for the present invention is more aobvious to obtain
Color distortion between the grid and the source pad that write.
Embodiment described above only have expressed the several embodiments of the present invention, and it describes more concrete and detailed,
But therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that, for this area
Those of ordinary skill for, without departing from the inventive concept of the premise, it is also possible to make some deformation and
Improving, these broadly fall into protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be with appended
Claim is as the criterion.
Claims (14)
1. gate pads and a forming method for source pad, formed on wafer including physical vapor deposition
The step of the albronze layer of gate pads and source pad, it is characterised in that the deposit of described depositing step
Temperature maintains 250 ± 10 degrees Celsius, is deposited in the second cavity and carries out, and under also including after this step
Row step:
Whether monitor the temperature in described second cavity more than the first temperature threshold, until described albronze layer
Deposit complete；Once more than the first temperature threshold, interrupt the deposit of described albronze layer, and by described crystalline substance
Circle removes described second cavity and lowers the temperature, and described second cavity is carried out cooling process simultaneously；
Monitor whether the temperature in described second cavity is less than the second temperature threshold, once less than the second temperature threshold
Described wafer is then retracted described second cavity and is proceeded deposit by value.
Gate pads the most according to claim 1 and the forming method of source pad, it is characterised in that
Described first temperature threshold is 255 degrees Celsius.
Gate pads the most according to claim 1 and the forming method of source pad, it is characterised in that
Described second temperature threshold is 245 degrees Celsius.
Gate pads the most according to claim 1 and the forming method of source pad, it is characterised in that
Described physical vapor deposition formed on wafer the albronze layer of gate pads and source pad step it
Before, be additionally included in the first cavity by physical vapor deposition process deposit on described wafer titanium coating with
The step of titanium nitride layer.
Gate pads the most according to claim 4 and the forming method of source pad, it is characterised in that
Described in the first cavity by physical vapor deposition process deposit titanium coating and titanium nitride layer step it
Before, it is additionally included in the step toasting described wafer in degassing cavity.
Gate pads the most according to claim 5 and the forming method of source pad, it is characterised in that
In the described step toasting described wafer in degassing cavity, baking temperature is 150 ± 10 degrees Celsius.
Gate pads the most according to claim 4 and the forming method of source pad, it is characterised in that
The step of described deposit titanium coating and titanium nitride layer is to be deposited at normal temperatures.
8. gate pads and a forming method for source pad, formed on wafer including physical vapor deposition
The step of the albronze layer of gate pads and source pad, it is characterised in that the deposit of described depositing step
Temperature maintains 250 ± 10 degrees Celsius, and described physical vapor deposition forms gate pads and source electrode on wafer
The step of the albronze layer of pad is included in and deposits the albronze layer of the first thickness in the second cavity and
Two cavitys deposit two steps of the albronze layer of the second thickness, and also includes between said two step
Wafer removes described second cavity lower the temperature, described second cavity is carried out cooling process simultaneously, until
Temperature in described second cavity is less than the step of the second temperature threshold.
Gate pads the most according to claim 8 and the forming method of source pad, it is characterised in that
Described first thickness and the second thickness are 22,000 angstroms.
Gate pads the most according to claim 8 and the forming method of source pad, it is characterised in that
Described second temperature threshold is 245 degrees Celsius.
11. gate pads according to claim 8 and the forming method of source pad, it is characterised in that
Described physical vapor deposition formed on wafer the albronze layer of gate pads and source pad step it
Before, be additionally included in the first cavity by physical vapor deposition process deposit on described wafer titanium coating with
The step of titanium nitride layer.
12. gate pads according to claim 11 and the forming method of source pad, it is characterised in that
Described in the first cavity by physical vapor deposition process deposit titanium coating and titanium nitride layer step it
Before, it is additionally included in the step toasting described wafer in degassing cavity.
13. gate pads according to claim 12 and the forming method of source pad, it is characterised in that
In the described step toasting described wafer in degassing cavity, baking temperature is 150 ± 10 degrees Celsius.
14. gate pads according to claim 11 and the forming method of source pad, it is characterised in that
The step of described deposit titanium coating and titanium nitride layer is to be deposited at normal temperatures.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210132712.XA CN103377954B (en) | 2012-04-28 | 2012-04-28 | Gate pads and the forming method of source pad |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210132712.XA CN103377954B (en) | 2012-04-28 | 2012-04-28 | Gate pads and the forming method of source pad |
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| CN103377954A CN103377954A (en) | 2013-10-30 |
| CN103377954B true CN103377954B (en) | 2016-12-14 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1922726A (en) * | 2004-02-20 | 2007-02-28 | 微米技术有限公司 | Methods of fabricating interconnects for semiconductor components |
| CN1921071A (en) * | 2005-08-26 | 2007-02-28 | 三菱电机株式会社 | Semiconductor device manufacturing apparatus, semiconductor device manufacturing method and semiconductor device |
| CN101640179A (en) * | 2008-07-31 | 2010-02-03 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing weld pad structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970053037U (en) * | 1996-02-17 | 1997-09-08 | Eccentric motion prevention device of control box |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1922726A (en) * | 2004-02-20 | 2007-02-28 | 微米技术有限公司 | Methods of fabricating interconnects for semiconductor components |
| US7189642B2 (en) * | 2004-02-20 | 2007-03-13 | Micron Technology, Inc. | Methods of fabricating interconnects including depositing a first material in the interconnect with a thickness of angstroms and a low temperature for semiconductor components |
| CN1921071A (en) * | 2005-08-26 | 2007-02-28 | 三菱电机株式会社 | Semiconductor device manufacturing apparatus, semiconductor device manufacturing method and semiconductor device |
| CN101640179A (en) * | 2008-07-31 | 2010-02-03 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing weld pad structure |
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| CN103377954A (en) | 2013-10-30 |
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