CN102437046A - Common manufacturing process of metal silicide barrier layer and stress memory layer - Google Patents
Common manufacturing process of metal silicide barrier layer and stress memory layer Download PDFInfo
- Publication number
- CN102437046A CN102437046A CN2011102502634A CN201110250263A CN102437046A CN 102437046 A CN102437046 A CN 102437046A CN 2011102502634 A CN2011102502634 A CN 2011102502634A CN 201110250263 A CN201110250263 A CN 201110250263A CN 102437046 A CN102437046 A CN 102437046A
- Authority
- CN
- China
- Prior art keywords
- stress memory
- metal silicide
- processing procedure
- layer
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention relates to a common manufacturing process of a metal silicide barrier layer and a stress memory layer, and the method comprises the following steps: a stress memory technical manufacturing process: depositing a stress memory film layer, and carrying out a thermal budget manufacturing process; and a metal silicide barrier region manufacturing process: utilizing the stress memory film layer to replace the metal silicide barrier region film in the manufacturing process. According to the common manufacturing process of the metal silicide barrier layer and the stress memory layer, the stress memory film is reserved after the stress memory technical manufacturing process is finished, and photoetching, etching and other techniques are carried out by using the stress memory film instead of the metal silicide barrier film in the subsequent silicide barrier layer manufacturing process, thereby eliminating the stress memory film removal and intermediate cleaning process and the metal silicide single-layer deposition technical step in the prior art; and the two manufacturing processes are organically combined, thereby reducing the technical steps and further lowering the manufacturing cost.
Description
Technical field
The present invention relates to a kind of manufacture of semiconductor, relate in particular to a kind of blocking layer of metal silicide and the shared processing procedure of stress memory layer.
Background technology
Present 45 nanometers and 55 nanometer high-property logic product processing procedures generally all comprise stress memory technique (Stress Memorization Technique; Be called for short SMT) and two the different processing procedures in metal silicide block area (Salicide Block is called for short SAB).
SMT (Stress Memorization Technique) is a kind of technology that increases the semiconductor carriers mobility; Thereby reach the purpose of the performance of improving CMOS; Mainly be used in the semiconductor manufacturing of high performance logic product; And SAB (Salicide Block) is one technology that semiconductor is made, and mainly is to be used for distinguishing metal silicide and non-metallic suicides zone in the chip.
Fig. 1 is the flow chart of SMT processing procedure and SAB processing procedure in the prior art, sees also Fig. 1, wherein, mainly comprises following eight steps:
Step 1: carry out the deposit of stress memory thin layer;
Step 2: carry out the heat budget processing procedure;
Step 3: the stress memory film is removed;
Step 4: carry out the centre cleaning process;
Step 5: carry out the thin layer deposit of metal silicide block area;
Step 6: spin coating photoresist on the thin layer of metal silicide block area, and carry out photoetching;
Step 7: metal silicide block area thin layer is carried out etching;
Step 8: photoresistance is removed.
Wherein, step 1 ~ 3 belong to the stress memory technique processing procedure, and step 5 ~ 8 belong to metal silicide block area processing procedure.
The semiconductor fabrications of the overwhelming majority all have this manufacturing process, and so far, these two processing procedures are two paths fully independently in the process of chip production, still both reports of organically combining of no-trump.
Summary of the invention
The invention discloses a kind of blocking layer of metal silicide and the shared processing procedure of stress memory layer, in order to stress memory technique of the prior art and metal silicide block area are merged into the processing procedure in a path, to simplify processing step.
Above-mentioned purpose of the present invention realizes through following technical scheme:
A kind of blocking layer of metal silicide and the shared processing procedure of stress memory layer wherein, may further comprise the steps:
Carry out the stress memory technique processing procedure, the stress memory technique processing procedure is specially: at first, carry out the deposit of stress memory thin layer, afterwards, carry out the heat budget processing procedure;
Carry out metal silicide block area processing procedure, in the process that this processing procedure carries out, the stress memory thin layer is replaced metal silicide block area film.
Aforesaid blocking layer of metal silicide and the shared processing procedure of stress memory layer wherein, adopt the mode of chemical meteorological deposit to form the stress memory film.
Aforesaid blocking layer of metal silicide and the shared processing procedure of stress memory layer, wherein, the heavily stressed silicon nitride film of deposit is to form the stress memory film.
Aforesaid blocking layer of metal silicide and the shared processing procedure of stress memory layer; Wherein, Metal silicide block area processing procedure specifically comprises: as barrier film, spin coating photoresistance and carry out photoetching on the stress memory film carries out etching afterwards with the stress memory film.
Aforesaid blocking layer of metal silicide and the shared processing procedure of stress memory layer wherein, are accomplished and after counter stress is remembered the etching of film photoresistance are removed.
Aforesaid blocking layer of metal silicide and the shared processing procedure of stress memory layer wherein, are adjusted the etch step in the processing procedure of metal silicide block area according to the thickness and the character of stress memory film.
In sum; Blocking layer of metal silicide of the present invention and the shared processing procedure of stress memory layer keep the stress memory film after accomplishing the stress memory technique processing procedure; And in follow-up silicide barrier layer processing procedure, stop film to carry out technologies such as photoetching, etching on the alternative planning of stress memory film metal; Thereby removed the processing step of stress memory film removal of the prior art, middle cleaning process and metal silicide group monolayer deposition; Two processing procedures are organically combined, reduced processing step, and then reduced manufacturing cost.
Description of drawings
Through reading the detailed description of non-limiting example being done with reference to following accompanying drawing, it is more obvious that the present invention and characteristic thereof, profile and advantage will become.Mark identical in whole accompanying drawings is indicated identical part.Painstakingly proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.
Fig. 1 is the flow chart of SMT processing procedure and SAB processing procedure in the prior art;
Fig. 2 is the flow chart of blocking layer of metal silicide of the present invention and the shared processing procedure of stress memory layer.
Embodiment
Be further described below in conjunction with the accompanying drawing specific embodiments of the invention:
Fig. 2 is the flow chart of blocking layer of metal silicide of the present invention and the shared processing procedure of stress memory layer, sees also Fig. 2, and a kind of blocking layer of metal silicide and the shared processing procedure of stress memory layer wherein, may further comprise the steps:
Carry out the stress memory technique processing procedure, the stress memory technique processing procedure is specially: at first, carry out the deposit of stress memory thin layer, afterwards, carry out the heat budget processing procedure; Different with prior art is need the stress memory film not removed after the compression behind the completion heat budget processing procedure among the present invention.
Adopt the mode of chemical meteorological deposit to form the stress memory film among the present invention.
Further, the heavily stressed silicon nitride film of deposit is to form the stress memory film.
After accomplishing the stress memory technique processing procedure; Carry out metal silicide block area processing procedure; In the process that this processing procedure carries out, the stress memory thin layer is replaced metal silicide block area film; Thereby be different from the prior art and after accomplishing the stress memory technique processing procedure, need clean and in the processing procedure of metal silicide block area, need at first depositing metal silicide trapping layer film; The present invention skips above-mentioned middle manufacturing process for cleaning and two steps of metal silicide trapping layer thin film deposition, directly carries out subsequent technique.
Further, metal silicide block area processing procedure specifically comprises: as barrier film, spin coating photoresistance and carry out photoetching on the stress memory film carries out etching afterwards with the stress memory film.
Further, after the etching of accomplishing counter stress memory film, the photoresistance on the stress memory film is removed.
In addition; Because applied stress memory film of the present invention replaces the metal silicide trapping layer in the existing technology; Therefore need reaffirm the condition of photoetching on the basis of existing technology, and the etch step in the processing procedure of metal silicide block area adjusted according to the thickness and the character of stress memory film.
In sum; Owing to adopted technique scheme; Blocking layer of metal silicide of the present invention and the shared processing procedure of stress memory layer keep the stress memory film after accomplishing the stress memory technique processing procedure; And in follow-up silicide barrier layer processing procedure, stop film to carry out technologies such as photoetching, etching on the alternative planning of stress memory film metal, thus removed the processing step of stress memory film removal of the prior art, middle cleaning process and metal silicide group monolayer deposition, two processing procedures are organically combined; Reduce processing step, and then reduced manufacturing cost.
It should be appreciated by those skilled in the art that those skilled in the art combine prior art and the foregoing description can realize said variant, do not repeat them here.Such variant does not influence flesh and blood of the present invention, does not repeat them here.
More than preferred embodiment of the present invention is described.It will be appreciated that the present invention is not limited to above-mentioned specific implementations, equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention; Or being revised as the equivalent embodiment of equivalent variations, this does not influence flesh and blood of the present invention.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (6)
1. blocking layer of metal silicide and the shared processing procedure of stress memory layer is characterized in that, may further comprise the steps:
Carry out the stress memory technique processing procedure, the stress memory technique processing procedure is specially: at first, carry out the deposit of stress memory thin layer, afterwards, carry out the heat budget processing procedure;
Carry out metal silicide block area processing procedure, in the process that this processing procedure carries out, the stress memory thin layer is replaced metal silicide block area film.
2. blocking layer of metal silicide according to claim 1 and the shared processing procedure of stress memory layer is characterized in that, adopt the mode of chemical meteorological deposit to form the stress memory film.
3. blocking layer of metal silicide according to claim 1 and the shared processing procedure of stress memory layer is characterized in that, the heavily stressed silicon nitride film of deposit is to form the stress memory film.
4. blocking layer of metal silicide according to claim 1 and the shared processing procedure of stress memory layer; It is characterized in that; Metal silicide block area processing procedure specifically comprises: as barrier film, spin coating photoresistance and carry out photoetching on the stress memory film carries out etching afterwards with the stress memory film.
5. blocking layer of metal silicide according to claim 4 and the shared processing procedure of stress memory layer is characterized in that, accomplish and after counter stress is remembered the etching of film photoresistance are removed.
6. blocking layer of metal silicide according to claim 1 and the shared processing procedure of stress memory layer is characterized in that, according to the thickness and the character of stress memory film the etch step in the processing procedure of metal silicide block area are adjusted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011102502634A CN102437046A (en) | 2011-08-29 | 2011-08-29 | Common manufacturing process of metal silicide barrier layer and stress memory layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011102502634A CN102437046A (en) | 2011-08-29 | 2011-08-29 | Common manufacturing process of metal silicide barrier layer and stress memory layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102437046A true CN102437046A (en) | 2012-05-02 |
Family
ID=45985042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011102502634A Pending CN102437046A (en) | 2011-08-29 | 2011-08-29 | Common manufacturing process of metal silicide barrier layer and stress memory layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102437046A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104952797A (en) * | 2014-03-26 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Method for preparing semiconductor device |
| US11289604B2 (en) | 2019-08-02 | 2022-03-29 | United Microelectronics Corp. | Method for fabricating a semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6444404B1 (en) * | 2000-08-09 | 2002-09-03 | Taiwan Semiconductor Manufacturing Company | Method of fabricating ESD protection device by using the same photolithographic mask for both the ESD implantation and the silicide blocking regions |
| US20060228843A1 (en) * | 2005-04-12 | 2006-10-12 | Alex Liu | Method of fabricating semiconductor devices and method of adjusting lattice distance in device channel |
| CN101179028A (en) * | 2006-11-08 | 2008-05-14 | 联华电子股份有限公司 | Metal-oxide-semiconductor transistor and manufacturing method thereof |
-
2011
- 2011-08-29 CN CN2011102502634A patent/CN102437046A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6444404B1 (en) * | 2000-08-09 | 2002-09-03 | Taiwan Semiconductor Manufacturing Company | Method of fabricating ESD protection device by using the same photolithographic mask for both the ESD implantation and the silicide blocking regions |
| US20060228843A1 (en) * | 2005-04-12 | 2006-10-12 | Alex Liu | Method of fabricating semiconductor devices and method of adjusting lattice distance in device channel |
| CN101179028A (en) * | 2006-11-08 | 2008-05-14 | 联华电子股份有限公司 | Metal-oxide-semiconductor transistor and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104952797A (en) * | 2014-03-26 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Method for preparing semiconductor device |
| US11289604B2 (en) | 2019-08-02 | 2022-03-29 | United Microelectronics Corp. | Method for fabricating a semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104979223A (en) | Wafer bonding process | |
| CN103681846A (en) | Semiconductor device and manufacturing method thereof | |
| CN102437046A (en) | Common manufacturing process of metal silicide barrier layer and stress memory layer | |
| TW200707753A (en) | Flat panel display and method for fabricating the same | |
| CN104078478B (en) | Back-illuminated type CMOS and its manufacture method | |
| CN102779784A (en) | Thin film transistor array substrate manufacturing method | |
| KR20090072035A (en) | High voltage mosfet device, method of extracting capacitance thereof | |
| CN103972052A (en) | Method for preventing linear distribution defects from happening through wafer edge scanning | |
| CN101335271A (en) | Disposal programmable device and manufacturing method therefor | |
| US8569137B1 (en) | Method of improving PMOS performance in a contact etch stop layer process | |
| CN104078351A (en) | Semiconductor structure manufacturing method | |
| CN102446832B (en) | Method for avoiding contact hole blockage caused by dual etching barrier layers | |
| CN102691050A (en) | Cleaning method for tungsten chemical vapor deposition system | |
| CN103972147A (en) | Narrow trench manufacturing method | |
| CN102176414A (en) | Preparation method of metal silicide | |
| US9006090B2 (en) | Method for forming shielded gate of MOSFET | |
| CN103094188B (en) | A kind of method and fuse window making fuse window on chip | |
| CN105140199A (en) | Top-layer metal thin film structure and aluminum process method | |
| CN102610571B (en) | Method for forming double-stress etching barrier layer and front metal dielectric layers | |
| CN205248281U (en) | Ditch cell type FRD chip | |
| CN105280647A (en) | Thin film transistor array panel and manufacturing method thereof | |
| CN104157579B (en) | A kind of preparation method of the semiconductor device structure of many raceway groove all-around-gate poles | |
| CN102386138B (en) | Through hole etching method, integrated circuit manufacturing method and integrated circuit | |
| CN102610513A (en) | Method for forming silicon nitride film on dual-stress layer | |
| FR2969813B1 (en) | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20120502 |