CN102610571B - Method for forming double-stress etching barrier layer and front metal dielectric layers - Google Patents
Method for forming double-stress etching barrier layer and front metal dielectric layers Download PDFInfo
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- CN102610571B CN102610571B CN201210064639.7A CN201210064639A CN102610571B CN 102610571 B CN102610571 B CN 102610571B CN 201210064639 A CN201210064639 A CN 201210064639A CN 102610571 B CN102610571 B CN 102610571B
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Abstract
The invention discloses a method for forming a double-stress etching barrier layer and front metal dielectric layers. The method comprises the following steps of: supplying a substrate with an N-channel metal oxide semiconductor (NMOS) transistor region and a P-channel metal oxide semiconductor (PMOS) transistor region; depositing the front metal dielectric layer with pull stress in the NMOS region; and depositing a second front metal dielectric layer with pressure stress in the PMOS region. According to the method for forming the double-stress etching barrier layer and the front metal dielectric layers, a process for forming the front metal dielectric layers is simplified effectively; and furthermore, the carrier migration rates of NMOS and PMOS are improved, so that the performance of a semiconductor device is improved.
Description
Technical field
The present invention relates to a kind of lithographic method, particularly relate to a kind of method forming two stress etching barrier layers and front metal dielectric layer.
Background technology
Along with integrated circuit feature live width narrows down to below 90nm, people introduce heavily stressed silicon nitride technology gradually to improve the electromobility of charge carrier.By depositing high drawing with high pressure stress silicon nitride as via etch stop-layer (Contact Etch Stop Layer is called for short CESL) on NMOS and PMOS.Especially below 65nm processing procedure, in order to improve the electromobility of NPMOS and PMOS simultaneously, sometimes need to deposit high drawing with high pressure stress silicon nitride on different MOS simultaneously.
After etch stop layer has deposited, need subsequently to deposit front metal dielectric layer, current employing be utilize the method for high-density plasma (HDP) CVD to deposit, also have and adopt high-aspect-ratio processing procedure (High Aspect Ratio Process is called for short HARP) to carry out depositing.The membrane stress of these two kinds of processing procedure depositions is different, and wherein HDP processing procedure film has compression, and HARP processing procedure film has tension stress.
As shown in Figure 1A-1E, the processing step of pmd layer prepared by existing method is as follows: as shown in Figure 1A, step one, first provides the substrate with NMOS area 1 and PMOS area 2 transistor; Step 2, NMOS and PMOS transistor deposited on substrates silica resilient coating 3 and there is the etch stop layer 4 of high tensile stress; As shown in Figure 1B, step 3, carries out photoresist layer deposition at the upper surface being positioned at etch stop layer above NMOS area 1, and by photoetching, the resilient coating 3 above PMOS area 2 and barrier layer is carved 4 eating aways, until after exposing PMOS area 2, the photoresist layer 5 of NMOS area 1 disposed thereon is removed; As shown in Figure 1 C, step 4, barrier layer above NMOS area 1 and the PMOS area exposed are carried out again to the deposition of resilient coating 3, the PMOS area 2 making resilient coating 3 be covered in barrier layer 5 above NMOS area 1 and expose, carries out the deposition on high pressure barrier layer 6 afterwards again to the upper surface of resilient coating 3; As shown in figure ip, step 5, to high pressure barrier layer 6 upper surface deposition photoresist layer 5 above PMOS area 2, and falls high pressure barrier layer 6 and resilient coating 3 above NMOS area 1 by chemical wet etching; As referring to figure 1e, step 6, remove the photoresist layer 5 that above PMOS area 2, high pressure barrier layer upper surface deposits, and last thin film deposition is carried out to high pressure barrier layer 6 upper surface above high-tensile strength barrier layer 4 above NMOS area 1 and PMOS area 2, but the tension stress required for PMOS and NMOS is different, same film can only to the performance boost of a kind of transistor in PMOS and NMOS.
Due to single deposition HDP or HARP film, can only be favourable to the carrier mobility of a kind of transistor wherein, therefore this method limit the performance improving transistor to the full extent.
Summary of the invention
A kind of method forming two stress etching barrier layers and front metal dielectric layer of disclosure of the invention.In order to solve in prior art, because single deposition HDP or HARP film to the performance boost of a kind of transistor in PMOS and NMOS, therefore can only limit the serviceability of transistor to a great extent.
For achieving the above object, the technical scheme that invention adopts is:
Form a method for two stress etching barrier layers and front metal dielectric layer, comprising: the substrate in NMOS and PMOS transistor region, wherein, also comprise following processing step:
Step one, first at the deposited on substrates resilient coating of NMOS and PMOS area, secondly on upper surface deposition high tensile stress barrier layer of deposited resilient coating, finally at high tensile stress barrier layer upper surface deposition HARP film;
Step 2, metal dielectric layer before the HARP film upper surface deposition tension stress above described NMOS area;
Step 3, carries out photoetching to the top of described PMOS area, until expose PMOS area, removes metal dielectric layer before the tension stress of HARP film upper surface above NMOS area afterwards;
Step 4, HARP film upper surface and PMOS area upper surface deposition high pressure etching barrier layer above described NMOS;
Step 5, metal dielectric layer before the high pressure etching barrier layer upper surface deposition compression in PMOS area;
Step 6, carries out cmp until removed completely on the high pressure barrier layer be covered on HARP film to the high pressure barrier layer of metal dielectric layer before compression and lower surface.
The method of the two stress etching barrier layers of above-mentioned formation and front metal dielectric layer, wherein, the buffer layer thickness deposited in described step one is 50-200 dust.
The method of the two stress etching barrier layers of above-mentioned formation and front metal dielectric layer, wherein, described high tensile stress barrier layer thickness and described high pressure stress barrier layer thickness are 200-800 dust.
The method of the two stress etching barrier layers of above-mentioned formation and front metal dielectric layer, wherein, before tension and compression stress, before metal dielectric layer thickness and compression, metal dielectric layer thickness is 1000-10000 dust.
The method of the two stress etching barrier layers of above-mentioned formation and front metal dielectric layer, wherein, before described tension stress, metal dielectric layer does not cover the high tensile stress etch stop layer above PMOS.
The method of the two stress etching barrier layers of above-mentioned formation and front metal dielectric layer, wherein, in described step one to step 5, the depositing temperature of all depositing operations is 300-500 DEG C.
The method of the two stress etching barrier layers of above-mentioned formation and front metal dielectric layer, wherein, before described tension stress, the deposition process of metal dielectric layer is time atmospheric pressure chemical vapor deposition HARP film, and its tension stress scope is between 100 ~ 200MPa.
The method of the two stress etching barrier layers of above-mentioned formation and front metal dielectric layer, wherein, before described compression, the deposition process of metal dielectric layer is high density plasma enhanced chemical vapor deposition system, and its compression scope is between 100 ~ 300MPa.
The method of the two stress etching barrier layers of above-mentioned formation and front metal dielectric layer, wherein, the material of described resilient coating is silica.
The method of the two stress etching barrier layers of above-mentioned formation and front metal dielectric layer, wherein, the material of described high tensile stress etch stop layer and high pressure stress etch stop layer is silicon nitride.
A kind of method forming two stress etching barrier layers and front metal dielectric layer in the present invention, the as above scheme that have employed has following effect:
1, the technical process of formed front metal dielectric layer is effectively made to become simple;
2, be conducive to the carrier mobility improving NMOS and PMOS simultaneously, thus improve the performance of semiconductor device.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to following accompanying drawing, the further feature of invention, object and advantage will become more obvious.
Figure 1A-1E is the processing step schematic diagram of the pmd layer that under regular situation prepared by existing method;
Fig. 2 A-2E is a kind of schematic diagram forming the method processing step of two stress etching barrier layers and front metal dielectric layer;
Fig. 3 is a kind of process flow diagram forming the method for two stress etching barrier layers and front metal dielectric layer;
Reference diagram sequence: metal dielectric layer 9 before metal dielectric layer 8, tension stress before NMOS area 1, PMOS area 2, resilient coating 3, high tensile stress barrier layer 4, photoresist layer 5, high pressure stress barrier layer 6, HARP film 7, compression.
Embodiment
The technological means realized to make invention, creating feature, reach object and effect is easy to understand, lower combination specifically illustrates, and sets forth the present invention further.
As shown in Fig. 2 A-2E, a kind of method forming two stress etching barrier layers and front metal dielectric layer, comprising: be provided with NMOS area 1 and PMOS area 2 in crystalline substrates, wherein, also comprise following processing step:
As shown in Figure 2 A, step one, first at the deposited on substrates resilient coating 3 of NMOS area 1 with PMOS area 2, secondly on the upper surface deposition high tensile stress barrier layer 4 of deposited resilient coating 3, finally at high tensile stress barrier layer 4 upper surface deposition HARP film 7;
As shown in Figure 2 B, step 2, metal dielectric layer 9 before the HARP film 7 upper surface deposition tension stress above NMOS area 1, further, before the tension stress deposited, metal dielectric layer 9 is only covered in above NMOS area 1;
Step 3, carries out photoetching to the top of PMOS area 2, until expose PMOS area 2, removes metal dielectric layer 9 before the tension stress of HARP film 7 upper surface above NMOS area 1 afterwards;
As shown in Figure 2 C, step 4, HARP film 7 upper surface and PMOS area 2 upper surface deposition high pressure barrier layer 6 above NMOS area 2, further, high pressure barrier layer 6 is covered in HARP film 7 upper surface, HARP film 7 side and PMOS area 2 upper surface completely;
As shown in Figure 2 D, step 5, metal dielectric layer 8 before the high pressure barrier layer 6 upper surface deposition compression in PMOS area 2;
As shown in Figure 2 E, step 6, cmp is carried out until removed completely on the high pressure barrier layer be covered on HARP film 7 to the high pressure barrier layer 6 of metal dielectric layer before compression 8 and lower surface, further, be in order to metal dielectric layer 8 before making compression and HARP film 7 reach required thickness and planarization.
In a particular embodiment of the present invention, resilient coating 3 thickness deposited in step one is 50-200 dust.
In a particular embodiment of the present invention, high tensile stress barrier layer 4 thickness and high pressure stress barrier layer 4 thickness are 200-800 dust.
In a particular embodiment of the present invention, before tension stress, before metal dielectric layer 8 thickness and compression, metal dielectric layer thickness 9 is 1000-10000 dust.
In a particular embodiment of the present invention, before tension stress, metal dielectric layer 8 does not cover the high tensile stress barrier layer 4 above PMOS area 2.
In a particular embodiment of the present invention, in step one to step 5, the depositing temperature of all depositing operations is 300-500 DEG C.
In a particular embodiment of the present invention, before tension stress, the deposition process of metal dielectric layer 8 is time atmospheric pressure chemical vapor deposition HARP film 7, and its tension stress scope is between 100 ~ 200MPa.
In a particular embodiment of the present invention, before compression, the deposition process of metal dielectric layer 9 is high density plasma enhanced chemical vapor deposition system, and its compression scope is between 100 ~ 300MPa.
In a particular embodiment of the present invention, the material of resilient coating 3 is silica.
In a particular embodiment of the present invention, tension stress barrier layer 4 is silicon nitride with the material on compression barrier layer 6.
In sum, invent a kind of method forming two stress etching barrier layers and front metal dielectric layer, effectively make the technical process of formed front metal dielectric layer become simple; Be conducive to the carrier mobility improving NMOS and PMOS simultaneously, thus improve the performance of semiconductor device.
Above the specific embodiment of invention is described.It is to be appreciated that invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Those skilled in the art can make various distortion or amendment within the scope of the claims, and this does not affect essence of an invention content.
Claims (9)
1. form a method for two stress etching barrier layers and front metal dielectric layer, comprising: the substrate in NMOS and PMOS transistor region, is characterized in that, also comprise following processing step:
Step one, first at the deposited on substrates resilient coating of NMOS and PMOS area, secondly on upper surface deposition high tensile stress barrier layer of deposited resilient coating, finally at high tensile stress barrier layer upper surface deposition HARP film;
Step 2, metal dielectric layer before the HARP film upper surface deposition tension stress above described NMOS area;
Step 3, carries out photoetching to the top of described PMOS area, until expose PMOS area, removes metal dielectric layer before the tension stress of HARP film upper surface above NMOS area afterwards;
Step 4, HARP film upper surface and PMOS area upper surface deposition high pressure etching barrier layer above described NMOS;
Step 5, metal dielectric layer before the high pressure etching barrier layer upper surface deposition compression in PMOS area;
Step 6, carries out cmp to the high pressure barrier layer of metal dielectric layer before compression and lower surface until will be covered in high pressure barrier layer on HARP film and remove completely;
Wherein, carry out cmp in described step 6, before making compression, metal dielectric layer and HARP film reach required thickness and planarization;
Before described compression, the deposition process of metal dielectric layer is high density plasma enhanced chemical vapor deposition system, and its compression scope is between 100 ~ 300MPa.
2. the method for the two stress etching barrier layers of formation according to claim 1 and front metal dielectric layer, it is characterized in that, the buffer layer thickness deposited in described step one is 50-200 dust.
3. the method for the two stress etching barrier layers of formation according to claim 1 and front metal dielectric layer, it is characterized in that, described high tensile stress barrier layer thickness and described high pressure stress barrier layer thickness are 200-800 dust.
4. the method for the two stress etching barrier layers of formation according to claim 1 and front metal dielectric layer, is characterized in that, before tension and compression stress, before metal dielectric layer thickness and compression, metal dielectric layer thickness is 1000-10000 dust.
5. the method for the two stress etching barrier layers of formation according to claim 1 and front metal dielectric layer, it is characterized in that, before described tension stress, metal dielectric layer does not cover the high tensile stress etch stop layer above PMOS.
6. the method for the two stress etching barrier layers of formation according to claim 1 and front metal dielectric layer, it is characterized in that, in described step one to step 5, the depositing temperature of all depositing operations is 300-500 DEG C.
7. the method for the two stress etching barrier layers of formation according to claim 1 and front metal dielectric layer, it is characterized in that, before described tension stress, the deposition process of metal dielectric layer is time atmospheric pressure chemical vapor deposition HARP film, and its tension stress scope is between 100 ~ 200MPa.
8. the method for the two stress etching barrier layers of formation according to claim 1 and front metal dielectric layer, it is characterized in that, the material of described resilient coating is silica.
9. the method for the two stress etching barrier layers of formation according to claim 1 and front metal dielectric layer, it is characterized in that, the material of described high tensile stress etch stop layer and high pressure stress etch stop layer is silicon nitride.
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