CN103021947B - Manufacture method for semiconductor device - Google Patents
Manufacture method for semiconductor device Download PDFInfo
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- CN103021947B CN103021947B CN201110301067.5A CN201110301067A CN103021947B CN 103021947 B CN103021947 B CN 103021947B CN 201110301067 A CN201110301067 A CN 201110301067A CN 103021947 B CN103021947 B CN 103021947B
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Abstract
The invention relates to a manufacture method for a semiconductor device. A metal silicide layer on a core device area and another metal silicide layer on an I/O (input/output) area are formed simultaneously. Compared with the prior art, one step of an annealing technology necessary for forming the metal silicide layer is reduced, the adverse effect of the high temperature annealing technology on the semiconductor device is reduced, and the process steps are saved and the process cost is lowered. Furthermore, grooves are filled with reserved packing layers, an organosilicone bottom anti-reflection coating or an inorganic oxygen anti-reflection coating is selected as the material of the packing players, so that the third patterning photoresist can be removed completely in the following step, the metal silicide layer in the groove can be further protected from being eroded and damaged.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor device, particularly relate to a kind of for having I/O (I/O) structure, and adopt the last formation process of grid (Gate-Last) to form the method, semi-conductor device manufacturing method of the grid in core devices region.
Background technology
Along with the integrated level of semiconductor device is more and more higher, the voltage and current of semiconductor device need of work constantly reduces, and the speed of transistor switch is also accelerated thereupon, requires significantly to improve to semiconductor technology each side thereupon.The semiconductor device part of transistor and other kinds has been accomplished the thickness of several molecule and atom by prior art processes, and the material of composition semiconductor has reached the limit of physical electrical characteristic.
Industry proposes the material-high dielectric constant material (High-K Material) than silicon dioxide with higher dielectric constant and better field effect characteristic, in order to better to separate grid and other parts of transistor, significantly reduces electrical leakage quantity.Meanwhile, in order to compatible with high dielectric constant material, adopt the original polysilicon of metal material instead as grid conductive layer material, thus define new grid structure.The grid structure of metal material is in high-temperature annealing process process, and its work function (Work Function) can occur significantly to change, cause the problems affect performance of semiconductor device such as gate depletion and RC delay.For solving the problem of the grid structure of above-mentioned metal material, define gate last process (Gate-Last Process), namely the dummy gate electrode of polycrystalline silicon material is first formed, after carrying out source/drain injection and high-temperature annealing process, remove dummy gate electrode polysilicon layer again, and deposit metallic material, finally form metal gates.
Core devices region and I/O region are generally included for the semiconductor device structure with I/O (I/O) equipment, for saving size, improving performance, the grid in core devices region selects metal gates-High K grid structure, and due to the requirement of cut-in voltage, the grid still choice for use polysilicon gate in I/O region.For the polysilicon gate on source/drain region in the Semiconductor substrate in core devices region and I/O region according to circuit design, need to carry out electrode extraction, drawing performance for improving electrode, needing source/drain region to be drawn in the Semiconductor substrate in core devices region and polysilicon gate form metal silicide layer.In the prior art, behind formation source/drain region, namely on source/drain region to be drawn, form metal silicide layer, and the polysilicon gate on I/O region forms another metal silicide layer after formation first medium layer.Prior art has not only carried out the forming process of twice metal silicide layer, add process time and process costs, and be repeated the high-temperature annealing process forming metal silicide layer, increase high temperature to the harmful effect of semiconductor device, reduce the performance of semiconductor device; In addition, in formation via process, etching technics damage metal silicide layer, reduces the thickness of metal silicide layer, reduce further the performance of semiconductor device.
Summary of the invention
The object of this invention is to provide a kind of manufacture method of semiconductor device, adopt that the last formation process of grid (Gate-Last) is formed to improve and there is the performance of the semiconductor device of I/O (I/O) structure.
For solving the problem, the invention provides.A manufacture method for semiconductor device, comprising:
The Semiconductor substrate that one comprises core devices region and I/O region is provided, described core devices region is formed with at least one metal gates, described I/O region is formed with at least one polysilicon gate, the Semiconductor substrate of described metal gates and polysilicon gate both sides is formed with first medium layer;
Described metal gates, polysilicon gate and first medium layer form silicon nitride layer;
Described silicon nitride layer is formed the first patterned photo glue, and with described first patterned photo glue for silicon nitride layer described in mask etching, to expose the surface of described polysilicon gate, then removes described first patterned photo glue;
Described silicon nitride layer and polysilicon gate are formed the second patterned photo glue, and with described second patterned photo glue for silicon nitride layer described in mask etching and first medium layer, form groove, described groove exposes the region of metal silicide layer to be formed in described Semiconductor substrate, then removes described second patterned photo glue; Simultaneously on the region of the metal silicide layer to be formed of described polysilicon gate and described Semiconductor substrate, form metal silicide layer;
Packed layer is formed in described groove;
Described core devices region and I/O region form second dielectric layer.
Further, after the step covering described second dielectric layer, also comprise:
Form the 3rd patterned photo glue, and with described 3rd patterned photo glue for second dielectric layer described in mask etching, to form through hole, then remove described 3rd patterned photo glue and packed layer;
Metal level is formed in described through hole.
Further, the material of described metal silicide layer is one in nickel silicide, cobalt silicide, tungsten silicide, Titanium silicide and tantalum silicide or its combination.
Further, simultaneously formed in the step of metal silicide layer on the region of the metal silicide layer to be formed of described polysilicon gate and described Semiconductor substrate, comprising:
Utilize chemical vapour deposition (CVD) or physical vaporous deposition, depositing metal layers on the region of the metal silicide layer to be formed of described polysilicon gate and described Semiconductor substrate;
Carry out annealing process.
Further, the temperature of described annealing process is 500 DEG C ~ 800 DEG C.
Further, the thickness of described metal silicide layer is 60 dust ~ 150 dusts.
Further, the material of described packed layer is organosilicon bottom antireflective coating or inorganic oxygen antireflecting coating.
Further, the Semiconductor substrate in described core devices region is formed with two metal gates, described metal gates comprises at least one NFET metal gates and at least one PFET metal gates.
Further, the material of described first medium layer and second dielectric layer is one in silica, silicon nitride or silicon oxynitride or its combination.
Compared to prior art, the manufacture method of described semiconductor device of the present invention, form the metal silicide layer on described core devices region and the metal silicide layer on I/O region simultaneously, thus reduce by an annealing process, and then the annealing process reducing high temperature has a negative impact to semiconductor device, save processing step simultaneously, reduce process costs.
Further; after forming packed layer film; carry out back etching technics again; remaining packed layer film is utilized to fill described groove; and select organosilicon bottom antireflective coating or inorganic oxygen antireflecting coating as the material of packed layer film; in the process of follow-up removal the 3rd patterned photo glue, packed layer can be removed in the lump, metal silicified layer in groove can be protected further not to be etched damage.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the manufacture method of semiconductor device in one embodiment of the invention.
Fig. 2 ~ Figure 15 is the structural representation in the manufacture process of semiconductor device in one embodiment of the invention.
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
Secondly, the present invention's detailed statement that utilized schematic diagram to carry out, when describing example of the present invention in detail, for convenience of explanation, schematic diagram, should in this, as limitation of the invention not according to general ratio partial enlargement.
Core concept of the present invention is: the manufacture method of semiconductor device of the present invention mainly for having I/O (I/O) structure, and adopts the last formation process of grid (Gate-Last) to form the semiconductor device structure of the grid in core devices region.The manufacture method of semiconductor device of the present invention is compared to prior art, form the metal silicide layer on described core devices region and the metal silicide layer on I/O region simultaneously, thus reduce by an annealing process, and then the annealing process reducing high temperature has a negative impact to semiconductor device, save processing step simultaneously, reduce process costs.
Fig. 1 is the schematic flow sheet of the manufacture method of semiconductor device in one embodiment of the invention.As shown in Figure 1, the invention provides a kind of manufacture method of semiconductor device, comprising:
Step S01: the Semiconductor substrate that comprises core devices region and I/O region is provided, described core devices region is formed with at least one metal gates, described I/O region is formed with at least one polysilicon gate, the Semiconductor substrate of described metal gates and polysilicon gate both sides is formed with first medium layer;
Step S02: form silicon nitride layer on described metal gates, polysilicon gate and first medium layer;
Step S03: form the first patterned photo glue on described silicon nitride layer, and with described first patterned photo glue for silicon nitride layer described in mask etching, to expose the surface of described polysilicon gate, then remove described first patterned photo glue;
Step S04: form the second patterned photo glue on described silicon nitride layer and polysilicon gate, and with described second patterned photo glue for silicon nitride layer described in mask etching and first medium layer, form groove, described groove exposes the region of metal silicide layer to be formed in described Semiconductor substrate, then removes described second patterned photo glue;
Step S05: simultaneously form metal silicide layer on the region of the metal silicide layer to be formed of described polysilicon gate and described Semiconductor substrate;
Step S06: form packed layer in described groove;
Step S07: form second dielectric layer on described core devices region and I/O region.
Then, after the described second dielectric layer of formation, also comprise: form the 3rd patterned photo glue, and with described 3rd patterned photo glue for second dielectric layer described in mask etching, to form through hole, then remove described 3rd patterned photo glue and packed layer; Metal level is formed in described through hole.
Below in conjunction with the structural representation of the manufacture process of the semiconductor device of the present embodiment described in Fig. 2 ~ Figure 15, describe the manufacture method of semiconductor device in one embodiment of the invention in detail.
As shown in Figure 2, in described step S01, described Semiconductor substrate 300 comprises adjacent core devices region 10 and I/O region 20.Described core devices region 10 comprises at least one metal gates 106, and the present embodiment comprises two metal gates, is respectively NFET metal gates and PFET metal gates (only schematically identifying a metal gates 106 in accompanying drawing).Due to the requirement of different cut-in voltage, described I/O region 20 is formed with polysilicon gate 206.Between described metal gates 106 and described Semiconductor substrate 300, be also formed with High-K dielectric layer 104, between described polysilicon gate 206 and described Semiconductor substrate 300, be also formed with oxide or nitride dielectric layer 204.
Said structure can utilize following steps to be formed: first, deposition oxide or nitride dielectric film and polysilicon membrane successively in described Semiconductor substrate 300, and utilize polysilicon membrane described in photoetching and etching technics patterning and described oxide or nitride dielectric film, form at least two grid structures, one of them is formed on described I/O region 20 as polysilicon gate 206, and at least one is arranged on core devices region 10 as dummy gate electrode (figure does not indicate) in addition; Then, the both sides of described dummy gate electrode both sides and polysilicon gate 206 form first grid side wall 102 and second grid side wall 202; Then, carry out source/drain ion implantation and high-temperature annealing process, in described Semiconductor substrate, form source/drain region 301; Then chemical vapor deposition first medium layer 302 is utilized, and carry out cmp until expose described dummy gate electrode and described polysilicon gate 206, the thickness of wherein said first medium layer 302 is greater than the thickness of described polysilicon gate 206 and described dummy gate electrode, and the material of described first medium layer 302 can be silica, silicon nitride or silicon oxynitride one or its combination; Finally, remove the dummy gate electrode and described oxide or nitride dielectric layer that are positioned on described core devices region 10, form metal gates groove; Finally, in described metal gates groove, form High-K dielectric layer 104 and metal gates 106, structure shown in Fig. 2 can be formed.
As shown in Figure 3, in described step S02, described metal gates 106 in described core devices region 10 and I/O region 20, polysilicon gate 206 and first medium layer 302 form silicon nitride layer 304, described silicon nitride layer 304 plays barrier effect in subsequent metal silicide layer forming process, avoid unnecessary region forms metal silicide, cause unnecessary being electrically connected.
As shown in Figure 4, in described step S03, spin coating first photoresist 306a on described silicon nitride layer 304, mask plate is utilized to expose the first photoresist 306a, and the first photoresist 306a is developed, form the first patterned photo glue 306 as shown in Figure 5, described first patterned photo glue 306 exposes the surface being positioned at described polysilicon gate 206; Then, with described first patterned photo glue 306 for mask, dry etching is utilized to remove part silicon nitride layer 304, wherein silicon nitride layer 304 and described polysilicon gate 206 have good etching ratio, therefore etching can stop at described polysilicon gate 206, form structure as shown in Figure 6, then remove described first patterned photo glue 306;
As shown in Figure 7, then, continue spin coating second photoresist on described silicon nitride layer 304 and polysilicon gate 206, mask plate is utilized to expose the second photoresist, and by the second photoresist developing, form the second patterned photo glue 308, metal silicide layer 308 to be formed on described second patterned photo glue 308 exposing semiconductor substrate 300, then with described second patterned photo glue 308 for mask, etch described silicon nitride layer 304 and first medium layer 302, form groove 110, and the region of metal silicide layer 308 to be formed on exposing semiconductor substrate 300, form structure as shown in Figure 8, remove described second patterned photo glue 308 subsequently.
As shown in Figure 9, after the described second patterned photo glue 308 of removal, namely expose the region of metal silicide layer to be formed in described polysilicon gate 206 and Semiconductor substrate 300, metal silicide layer 310 can be formed on polysilicon gate 206 and Semiconductor substrate 300 simultaneously.
Wherein, the material of described metal silicide layer 310 can be one in nickel silicide, cobalt silicide, tungsten silicide, Titanium silicide and tantalum silicide or its combination.Described metal silicide layer preferably utilizes the mode of chemical vapour deposition (CVD) (CVD) or physical vapour deposition (PVD) (PVD), metal level is deposited on the surface of Semiconductor substrate and polysilicon gate metal silicide layer to be formed, then carry out annealing process, the temperature of described annealing process is 500 DEG C ~ 800 DEG C.Metal, in the annealing process procedure of high temperature, forms metal silicide with pasc reaction.In the present embodiment, the material of described metal silicide layer is nickel-silicon compound, utilizes nickel beam-plasma to be sputtered onto in described Semiconductor substrate, in subsequent anneal process, and the silicon generation chemical reaction in nickel and described Semiconductor substrate, thus form nickel-silicon compound.Described metal silicide layer preferably thickness is 60 dust ~ 150 dusts, described metal silicide layer preferably thickness contribute to improving source/drain region 301 to be drawn in Semiconductor substrate 300 and polysilicon gate 206 and follow-up formation metal interconnecting wires between the resistance characteristic at interface.
Then, as shown in step S06, form packed layer film, described packed layer film is filled in groove 110 and the surface of silicon nitride layer 304, carry out back etching technics again, the packed layer film be positioned on described silicon nitride layer 304 and described polysilicon gate 206 can be removed, thus form packed layer 108 as shown in Figure 10; The material of described packed layer film is organosilicon bottom antireflective coating or inorganic oxygen antireflecting coating, the mode of spin coating can be adopted to form packed layer film, described packed layer 108, when follow-up formation metal throuth hole (Via), can adopt ashing method (Ashing) or wet etching method to remove.
Then, as shown in step S07, described core devices region 10 and I/O region 20 cover second dielectric layer 312, chemical vapour deposition technique can be adopted to form described second dielectric layer 312, the material of described second dielectric layer 312 can be one in silica, silicon nitride or silicon oxynitride or its combination, can form structure as shown in figure 11.
In the present embodiment, as shown in figure 12, then, form the 3rd patterned photo glue 314, described 3rd patterned photo glue 314 exposes the region of metal silicide layer to be formed in region on polysilicon gate 206 and Semiconductor substrate 300.Then, with the 3rd patterned photo glue 314 shown in Figure 12 for mask, etch described second dielectric layer 314, form the through hole 320 that electricity is drawn, recycling plasma ashing or wet etching remove described 3rd patterned photo glue 314 and packed layer 108, form structure as shown in figure 14.
In an alternative embodiment of the invention, as shown in figure 13, described 3rd patterned photo glue 314 also can region on exposed polysilicon grid 206, metal silicide layer to be formed Semiconductor substrate 300 on region and subregion on metal gates; Then, with the 3rd patterned photo glue 314 shown in Figure 13 for mask, etch described second dielectric layer 314 and silicon nitride layer 302, form the through hole 320 that electricity is drawn, utilize plasma ashing or wet etching to remove described 3rd patterned photo glue 314 and packed layer 108, thus form structure as shown in figure 15.
Finally, the through hole 320 shown in described Figure 13 or Figure 14 can be filled by depositing metal layers, and carry out cmp (CMP), remove the metal level outside described through hole 32, thus form metal connecting line in described through hole.In addition, in other embodiments, the shape of described through hole of described 3rd patterned photo glue 314 and definition thereof is determined according to the technique of reality, not limit by the embodiment shown in the present invention.
Compared to prior art, the manufacture method of semiconductor device of the present invention, be formed on Shang HeI/O region, described core devices region simultaneously and form metal silicide layer, thus reduce by an annealing process, and then the annealing process reducing high temperature has a negative impact to semiconductor device, save processing step, reduce process costs.
Further; after forming packed layer film; carry out back etching technics again; remaining packed layer film is utilized to fill described groove; and select organosilicon bottom antireflective coating or inorganic oxygen antireflecting coating as the material of packed layer film; in the process of follow-up removal the 3rd patterned photo glue, packed layer can be removed in the lump, metal silicified layer in groove can be protected further not to be etched damage.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (8)
1. a manufacture method for semiconductor device, comprising:
The Semiconductor substrate that one comprises core devices region and I/O region is provided, described core devices region is formed with at least one metal gates, described I/O region is formed with at least one polysilicon gate, the Semiconductor substrate of described metal gates and polysilicon gate both sides is formed with first medium layer;
Described metal gates, polysilicon gate and first medium layer form silicon nitride layer;
Described silicon nitride layer is formed the first patterned photo glue, and with described first patterned photo glue for silicon nitride layer described in mask etching, to expose the surface of described polysilicon gate, then removes described first patterned photo glue;
Described silicon nitride layer and polysilicon gate are formed the second patterned photo glue, and with described second patterned photo glue for silicon nitride layer described in mask etching and first medium layer, form groove, described groove exposes the region of metal silicide layer to be formed in described Semiconductor substrate, then removes described second patterned photo glue;
Simultaneously on the region of the metal silicide layer to be formed of described polysilicon gate and described Semiconductor substrate, form metal silicide layer;
Packed layer is formed in described groove;
Described core devices region and I/O region form second dielectric layer;
Form the 3rd patterned photo glue, and with described 3rd patterned photo glue for second dielectric layer described in mask etching, to form through hole, then remove described 3rd patterned photo glue and packed layer;
Metal level is formed in described through hole.
2. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, the material of described metal silicide layer is one in nickel silicide, cobalt silicide, tungsten silicide, Titanium silicide and tantalum silicide or its combination.
3. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, is formed in the step of metal silicide layer simultaneously, comprising on the region of the metal silicide layer to be formed of described polysilicon gate and described Semiconductor substrate:
Utilize chemical vapour deposition (CVD) or physical vaporous deposition, depositing metal layers on the region of the metal silicide layer to be formed of described polysilicon gate and described Semiconductor substrate;
Carry out annealing process.
4. the manufacture method of semiconductor device as claimed in claim 3, it is characterized in that, the temperature of described annealing process is 500 DEG C ~ 800 DEG C.
5. the manufacture method of the semiconductor device according to any one of Claims 1-4, is characterized in that, the thickness of described metal silicide layer is 60 dust ~ 150 dusts.
6. the manufacture method of the semiconductor device according to any one of Claims 1-4, is characterized in that, the material of described packed layer is organosilicon bottom antireflective coating or inorganic oxygen antireflecting coating.
7. the manufacture method of the semiconductor device according to any one of Claims 1-4, is characterized in that, described core devices region is formed with at least one NFET metal gates and at least one PFET metal gates.
8. the manufacture method of the semiconductor device according to any one of Claims 1-4, is characterized in that, the material of described first medium layer and second dielectric layer is one in silica, silicon nitride or silicon oxynitride or its combination.
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| CN201110301067.5A CN103021947B (en) | 2011-09-28 | 2011-09-28 | Manufacture method for semiconductor device |
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| CN201110301067.5A CN103021947B (en) | 2011-09-28 | 2011-09-28 | Manufacture method for semiconductor device |
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| CN103021947A CN103021947A (en) | 2013-04-03 |
| CN103021947B true CN103021947B (en) | 2015-03-18 |
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| CN105470293B (en) * | 2014-08-28 | 2020-06-02 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1481025A (en) * | 2002-08-06 | 2004-03-10 | 国际商业机器公司 | Semiconductor chip adopting polysilicon gate and metallic grid element |
| CN1591829A (en) * | 2003-08-28 | 2005-03-09 | 力晶半导体股份有限公司 | Automatic-aligning method silicide mfg. method |
| US7098114B1 (en) * | 2004-06-22 | 2006-08-29 | Integrated Device Technology, Inc. | Method for forming cmos device with self-aligned contacts and region formed using salicide process |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1481025A (en) * | 2002-08-06 | 2004-03-10 | 国际商业机器公司 | Semiconductor chip adopting polysilicon gate and metallic grid element |
| CN1591829A (en) * | 2003-08-28 | 2005-03-09 | 力晶半导体股份有限公司 | Automatic-aligning method silicide mfg. method |
| US7098114B1 (en) * | 2004-06-22 | 2006-08-29 | Integrated Device Technology, Inc. | Method for forming cmos device with self-aligned contacts and region formed using salicide process |
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