JP2007018498A5 - - Google Patents

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Publication number
JP2007018498A5
JP2007018498A5 JP2006086647A JP2006086647A JP2007018498A5 JP 2007018498 A5 JP2007018498 A5 JP 2007018498A5 JP 2006086647 A JP2006086647 A JP 2006086647A JP 2006086647 A JP2006086647 A JP 2006086647A JP 2007018498 A5 JP2007018498 A5 JP 2007018498A5
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JP
Japan
Prior art keywords
serial interface
channels
range
circuit board
data rates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006086647A
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English (en)
Japanese (ja)
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JP2007018498A (ja
JP5161429B2 (ja
Filing date
Publication date
Priority claimed from US11/177,007 external-priority patent/US7698482B2/en
Application filed filed Critical
Publication of JP2007018498A publication Critical patent/JP2007018498A/ja
Publication of JP2007018498A5 publication Critical patent/JP2007018498A5/ja
Application granted granted Critical
Publication of JP5161429B2 publication Critical patent/JP5161429B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2006086647A 2005-07-08 2006-03-27 プログラマブルロジックデバイスのシリアルインタフェースにおけるマルチプルデータレート Expired - Fee Related JP5161429B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/177,007 US7698482B2 (en) 2005-07-08 2005-07-08 Multiple data rates in integrated circuit device serial interface
US11/177,007 2005-07-08

Publications (3)

Publication Number Publication Date
JP2007018498A JP2007018498A (ja) 2007-01-25
JP2007018498A5 true JP2007018498A5 (https=) 2009-04-16
JP5161429B2 JP5161429B2 (ja) 2013-03-13

Family

ID=36889175

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006086647A Expired - Fee Related JP5161429B2 (ja) 2005-07-08 2006-03-27 プログラマブルロジックデバイスのシリアルインタフェースにおけるマルチプルデータレート

Country Status (4)

Country Link
US (1) US7698482B2 (https=)
EP (1) EP1742363A3 (https=)
JP (1) JP5161429B2 (https=)
CN (1) CN101056101A (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7925793B2 (en) * 2007-05-31 2011-04-12 Ixia Reconfigurable test system
CN101493801B (zh) * 2008-01-24 2011-07-27 鸿富锦精密工业（深圳）有限公司 通用串行总线驱动装置及方法
US8477831B2 (en) * 2010-02-17 2013-07-02 Altera Corporation Multi-protocol multiple-data-rate auto-speed negotiation architecture for a device
US8397096B2 (en) * 2010-05-21 2013-03-12 Altera Corporation Heterogeneous physical media attachment circuitry for integrated circuit devices
US8464088B1 (en) * 2010-10-29 2013-06-11 Altera Corporation Multiple channel bonding in a high speed clock network
US8571059B1 (en) 2011-07-29 2013-10-29 Altera Corporation Apparatus and methods for serial interfaces with shared datapaths
US8700825B1 (en) * 2012-11-16 2014-04-15 Altera Corporation Heterogeneous high-speed serial interface system with phase-locked loop architecture and clock distribution system
US9032358B2 (en) * 2013-03-06 2015-05-12 Qualcomm Incorporated Integrated circuit floorplan for compact clock distribution
CN104426698B (zh) * 2013-08-30 2017-08-04 东硕资讯股份有限公司 端口配置方法及配置有多端口的组合式电路板模块
US11075624B2 (en) 2019-06-25 2021-07-27 Stmicroelectronics International N.V. Hybrid driver having low output pad capacitance
US12375102B2 (en) * 2023-04-11 2025-07-29 Avago Technologies International Sales Pte. Limited Hybrid rate interface to reduce power consumption and area in high-speed DACs and digital transmitters

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6487620B1 (en) * 1999-06-11 2002-11-26 Telefonaktiebolaget Lm Ericsson (Publ) Combined low speed and high speed data bus
JP4639420B2 (ja) * 2000-03-08 2011-02-23 ソニー株式会社 信号伝送装置および信号伝送方法
US6650140B2 (en) * 2001-03-19 2003-11-18 Altera Corporation Programmable logic device with high speed serial interface circuitry
US6983342B2 (en) * 2002-10-08 2006-01-03 Lsi Logic Corporation High speed OC-768 configurable link layer chip
US6831480B1 (en) 2003-01-07 2004-12-14 Altera Corporation Programmable logic device multispeed I/O circuitry
US6894530B1 (en) 2003-04-28 2005-05-17 Lattice Semiconductor Corporation Programmable and fixed logic circuitry for high-speed interfaces
TW586713U (en) * 2003-05-01 2004-05-01 Power Quotient Int Co Ltd Dual channel universal serial bus system architecture
US6888376B1 (en) * 2003-09-24 2005-05-03 Altera Corporation Multiple data rates in programmable logic device serial interface
US8856401B2 (en) * 2003-11-25 2014-10-07 Lsi Corporation Universal controller for peripheral devices in a computing system
US7183797B2 (en) * 2004-10-29 2007-02-27 Altera Corporation Next generation 8B10B architecture

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