JP2007012755A - Semiconductor device and semiconductor device assembly - Google Patents

Semiconductor device and semiconductor device assembly Download PDF

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JP2007012755A
JP2007012755A JP2005189571A JP2005189571A JP2007012755A JP 2007012755 A JP2007012755 A JP 2007012755A JP 2005189571 A JP2005189571 A JP 2005189571A JP 2005189571 A JP2005189571 A JP 2005189571A JP 2007012755 A JP2007012755 A JP 2007012755A
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resin layer
semiconductor device
resin material
surface side
back surface
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JP4939002B2 (en
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Masaki Kasai
正樹 葛西
Osamu Miyata
修 宮田
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to KR1020077029817A priority patent/KR20080031192A/en
Priority to CN2010101666401A priority patent/CN101847611B/en
Priority to US11/988,030 priority patent/US8164201B2/en
Priority to PCT/JP2006/312882 priority patent/WO2007001018A1/en
Priority to CN2006800239853A priority patent/CN101213658B/en
Priority to TW095123600A priority patent/TW200707701A/en
Publication of JP2007012755A publication Critical patent/JP2007012755A/en
Priority to US13/441,019 priority patent/US8664779B2/en
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Publication of JP4939002B2 publication Critical patent/JP4939002B2/en
Priority to US14/083,492 priority patent/US8723339B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which the warpage of a semiconductor chip due to a sudden temperature change can be prevented without causing an increase in thickness, and a semiconductor device assembly. <P>SOLUTION: The semiconductor device 1 is provided with a semiconductor chip 10; a front side resin layer 11 formed using a first resin material on a front surface 10a of the semiconductor chip 10; and a backside resin layer 12 formed so as to be thinner than the resin layer 11 using a second resin material having a thermal expansion coefficient larger than that of the first resin material on a backside 10b of the semiconductor chip 10. The second resin material has a elastic modulus smaller than that of the first resin material. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は、ＷＬ−ＣＳＰ（ウエハレベルチップサイズパッケージ：Wafer Level-Chip Size Package）を採用した半導体装置および半導体装置を個片に切り出す前のウエハ状態である半導体装置集合体に関する。   The present invention relates to a semiconductor device employing a WL-CSP (Wafer Level-Chip Size Package) and a semiconductor device assembly in a wafer state before the semiconductor device is cut into individual pieces.

最近、半導体装置の小型化、高機能化および高性能化を可能にするＷＬ−ＣＳＰの実用化が進んでいる。ＷＬ−ＣＳＰでは、ウエハ状態でパッケージング工程が完了され、ダイシングによって切り出された個々のチップサイズがパッケージサイズとなる。
すなわち、ＷＬ−ＣＳＰが採用された半導体装置の製造工程では、複数の半導体チップが作りこまれたウエハの表面上に、ポリイミド層および再配線が形成された後、それらを封止するための表面側樹脂層が形成される。そして、表面側樹脂層上に外部端子が形成された後、各半導体チップ間に設定されたダイシングラインに沿って、パッシベーション膜および封止樹脂とともにウエハが切断（ダイシング）されることにより、半導体チップと同じパッケージサイズを有するＷＬ−ＣＳＰの半導体装置が得られる。
特開２００３−６０１１９号公報 Recently, practical application of WL-CSP that enables miniaturization, high functionality, and high performance of semiconductor devices has been advanced. In the WL-CSP, the packaging process is completed in the wafer state, and the individual chip size cut out by dicing becomes the package size.
That is, in a manufacturing process of a semiconductor device employing WL-CSP, a polyimide layer and a rewiring are formed on the surface of a wafer on which a plurality of semiconductor chips are formed, and then a surface for sealing them. A side resin layer is formed. Then, after the external terminals are formed on the surface-side resin layer, the wafer is cut (diced) together with the passivation film and the sealing resin along the dicing line set between the semiconductor chips, whereby the semiconductor chip WL-CSP semiconductor device having the same package size is obtained.
JP 2003-60119 A

表面側樹脂層は、ウエハの表面に表面側樹脂層の材料である樹脂を塗布した後、一旦加熱した後に冷却して、そのウエハの表面上の樹脂を硬化させることにより形成される。このとき、ウエハの表面上の樹脂に熱収縮が生じる。このような熱収縮が生じると、ウエハの表面に対して応力がかかるため、ウエハに反りが生じ、その結果、ウエハ内の機能素子がダメージを受けることがある。   The surface-side resin layer is formed by applying a resin, which is a material of the surface-side resin layer, to the surface of the wafer, heating it once, cooling it, and curing the resin on the surface of the wafer. At this time, heat shrinkage occurs in the resin on the surface of the wafer. When such heat shrinkage occurs, stress is applied to the surface of the wafer, causing the wafer to warp, and as a result, the functional elements in the wafer may be damaged.

このようなウエハの反りを防止するため、ウエハの裏面上に、表面側樹脂層と同じ材料で同じ厚さの樹脂層を形成することが考えられる。これにより、樹脂硬化のための加熱後の冷却時に、ウエハの表面上および裏面上の樹脂が同様に熱収縮するので、ウエハに反りが生じることを防止することができる。
しかし、ウエハの裏面上に、表面側樹脂層と同じ厚みの樹脂層を形成すると、そのウエハを切断して得られる半導体装置の厚みが大きくなってしまう。 In order to prevent such warpage of the wafer, it is conceivable to form a resin layer having the same thickness and the same material as the front-side resin layer on the back surface of the wafer. Thereby, at the time of cooling after heating for resin curing, the resin on the front surface and the back surface of the wafer is similarly thermally contracted, so that it is possible to prevent the wafer from being warped.
However, if a resin layer having the same thickness as the front-side resin layer is formed on the back surface of the wafer, the thickness of the semiconductor device obtained by cutting the wafer increases.

そこで、この発明の目的は、厚みの増大を招くことなく、急激な温度変化に起因する半導体チップの反りを防止することができる半導体装置を提供することである。
また、この発明の他の目的は、半導体装置の厚みの増大を招くことなく、急激な温度変化に起因する基板の反りを防止することができる半導体装置集合体を提供することである。 SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of preventing a semiconductor chip from warping due to a rapid temperature change without causing an increase in thickness.
Another object of the present invention is to provide a semiconductor device assembly capable of preventing substrate warpage caused by a rapid temperature change without increasing the thickness of the semiconductor device.

上記の目的を達成するための請求項１記載の発明は、半導体チップと、前記半導体チップの表面上に、第１樹脂材料を用いて形成された表面側樹脂層と、前記半導体チップの裏面上に、前記第１樹脂材料よりも大きな熱膨張係数を有する第２樹脂材料を用いて、前記表面側樹脂層よりも薄く形成された裏面側樹脂層とを含むことを特徴とする、半導体装置である。   In order to achieve the above object, an invention according to claim 1 includes a semiconductor chip, a surface-side resin layer formed using a first resin material on the surface of the semiconductor chip, and a back surface of the semiconductor chip. And a back side resin layer formed thinner than the front side resin layer using a second resin material having a larger thermal expansion coefficient than the first resin material. is there.

この構成によれば、半導体チップの表面側に、第１樹脂材料を用いて表面側樹脂層が形成され、その裏面側には、第１樹脂材料よりも大きな熱膨張係数を有する第２樹脂材料を用いて、表面側樹脂層よりも薄い裏面側樹脂層が形成されている。裏面側樹脂層を表面側樹脂層よりも薄く形成することによって、半導体チップの表面側および裏面側に同じ厚みを有する樹脂層を形成する場合に比べて、半導体装置の厚みを小さくすることができる。また、裏面側樹脂層が表面側樹脂層よりも薄くても、裏面側樹脂層の材料として、表面側樹脂層を形成する第１樹脂材料よりも熱膨張係数が大きな第２樹脂材料が用いられることにより、急激な温度変化に伴って、表面側樹脂層および裏面側樹脂層が熱膨張または熱収縮したときに、裏面側樹脂層から半導体チップの裏面に加わる応力を、表面側樹脂層から半導体チップの表面に加わる応力とほぼ等しくすることができる。よって、半導体装置の厚みが大きくなるのを防止することができながら、急激な温度変化による半導体チップの反りの発生を防止することができる。   According to this configuration, the front surface side resin layer is formed on the front surface side of the semiconductor chip using the first resin material, and the second resin material having a larger thermal expansion coefficient than the first resin material is formed on the back surface side thereof. Is used to form a back side resin layer thinner than the front side resin layer. By forming the back surface side resin layer thinner than the front surface side resin layer, the thickness of the semiconductor device can be reduced as compared with the case where the resin layer having the same thickness is formed on the front surface side and the back surface side of the semiconductor chip. . Moreover, even if the back surface side resin layer is thinner than the front surface side resin layer, the second resin material having a larger thermal expansion coefficient than the first resin material forming the front surface side resin layer is used as the material of the back surface side resin layer. As a result, when the front side resin layer and the rear side resin layer thermally expand or contract due to a rapid temperature change, the stress applied from the rear side resin layer to the back side of the semiconductor chip is changed from the front side resin layer to the semiconductor. The stress applied to the surface of the chip can be made almost equal. Therefore, it is possible to prevent the semiconductor chip from warping due to a rapid temperature change while preventing the semiconductor device from becoming thick.

また、請求項２記載の発明は、前記第２樹脂材料は、前記第１樹脂材料よりも小さな弾性率を有するものであることを特徴とする、請求項１記載の半導体装置である。
この構成によれば、裏面側樹脂層の材料として、小さな弾性率を有する第２樹脂材料が用いられているので、裏面側樹脂層が薄く形成されていても、その裏面側樹脂層に加わる衝撃を十分に吸収することができ、半導体チップを十分に保護することができる。 The invention according to claim 2 is the semiconductor device according to claim 1, wherein the second resin material has an elastic modulus smaller than that of the first resin material.
According to this configuration, since the second resin material having a small elastic modulus is used as the material of the back surface side resin layer, even if the back surface resin layer is formed thin, the impact applied to the back surface side resin layer Can be sufficiently absorbed, and the semiconductor chip can be sufficiently protected.

なお、請求項３に記載のように、たとえば、前記第１樹脂材料がビスフェノールＡ型エポキシ樹脂であり、前記第２樹脂材料がポリイミドアミドであれば、第１樹脂材料の熱膨張係数よりも第２樹脂材料の熱膨張係数が大きく、かつ、第１樹脂材料の弾性率よりも第２樹脂材料の弾性率の方が小さくなる。
また、上記半導体装置は、請求項４に記載のように、前記表面側樹脂層上に配置され、前記半導体装置が実装基板に実装されたときに、前記実装基板上の電極に当接する外部端子をさらに含むものであってもよい。 For example, if the first resin material is a bisphenol A type epoxy resin and the second resin material is polyimide amide, the coefficient of thermal expansion of the first resin material is larger than that of the first resin material. The thermal expansion coefficient of the second resin material is large, and the elastic modulus of the second resin material is smaller than the elastic modulus of the first resin material.
The semiconductor device according to claim 4, wherein the external terminal is disposed on the surface-side resin layer and contacts an electrode on the mounting substrate when the semiconductor device is mounted on the mounting substrate. May further be included.

また、請求項５記載の発明は、複数の半導体チップが作り込まれた基板と、前記基板の表面上に、第１樹脂材料を用いて形成された表面側樹脂層と、前記基板の裏面上に、前記第１樹脂材料よりも大きな熱膨張係数を有する第２樹脂材料を用いて、前記表面側樹脂層よりも薄く形成された裏面側樹脂層とを含むことを特徴とする、半導体装置集合体である。   According to a fifth aspect of the present invention, there is provided a substrate on which a plurality of semiconductor chips are formed, a surface-side resin layer formed using a first resin material on the surface of the substrate, and a back surface of the substrate. And a back side resin layer formed thinner than the front side resin layer using a second resin material having a larger thermal expansion coefficient than the first resin material. Is the body.

この構成によれば、基板の表面側に、第１樹脂材料を用いて表面側樹脂層が形成され、その裏面側には、第１樹脂材料よりも大きな熱膨張係数を有する第２樹脂材料を用いて、表面側樹脂層よりも薄い裏面側樹脂層が形成されている。裏面側樹脂層を表面側樹脂層よりも薄く形成することによって、基板の表面側および裏面側に同じ厚みを有する樹脂層を形成する場合に比べて、半導体装置集合体を切断して得られる半導体装置の厚みを小さくすることができる。また、裏面側樹脂層が表面側樹脂層よりも薄くても、裏面側樹脂層の材料として、表面側樹脂層を形成する第１樹脂材料よりも熱膨張係数が大きな第２樹脂材料を用いられることにより、表面側樹脂層および裏面側樹脂層の材料を硬化させるための加熱後の冷却時において、それらの材料が熱収縮したときに基板の裏面に加わる応力を、基板の表面に加わる応力とほぼ等しくすることができる。よって、半導体装置集合体から得られる半導体装置の厚みが大きくなるのを防止することができながら、基板に反りが生じることを防止することができる。   According to this configuration, the front-side resin layer is formed using the first resin material on the front surface side of the substrate, and the second resin material having a larger thermal expansion coefficient than the first resin material is formed on the back surface side. The back side resin layer thinner than the front side resin layer is used. A semiconductor obtained by cutting a semiconductor device assembly as compared with the case where a resin layer having the same thickness is formed on the front surface side and the back surface side of the substrate by forming the back surface side resin layer thinner than the front surface side resin layer. The thickness of the device can be reduced. Moreover, even if the back surface side resin layer is thinner than the front surface side resin layer, the second resin material having a larger thermal expansion coefficient than the first resin material forming the front surface side resin layer is used as the material of the back surface side resin layer. Thus, during cooling after heating to cure the materials of the front surface side resin layer and the back surface side resin layer, the stress applied to the back surface of the substrate when those materials are thermally contracted is the stress applied to the surface of the substrate. Can be approximately equal. Therefore, the thickness of the semiconductor device obtained from the semiconductor device assembly can be prevented from increasing, and the substrate can be prevented from warping.

また、請求項６記載の発明は、前記第２樹脂材料は、前記第１樹脂材料よりも小さな弾性率を有するものであることを特徴とする、請求項５記載の半導体装置集合体である。
この構成によれば、裏面側樹脂層の材料として、小さな弾性率を有する第２樹脂材料が用いられているので、裏面側樹脂層が薄く形成されていても、その裏面側樹脂層に加わる衝撃を十分に吸収することができる。そのため、半導体装置集合体の状態において、各半導体チップを十分に保護することができ、また、半導体装置集合体から得られる半導体装置において、半導体チップを十分に保護することができる。 The invention according to claim 6 is the semiconductor device assembly according to claim 5, wherein the second resin material has a smaller elastic modulus than the first resin material.
According to this configuration, since the second resin material having a small elastic modulus is used as the material of the back surface side resin layer, even if the back surface resin layer is formed thin, the impact applied to the back surface side resin layer Can be sufficiently absorbed. Therefore, each semiconductor chip can be sufficiently protected in the state of the semiconductor device assembly, and the semiconductor chip can be sufficiently protected in the semiconductor device obtained from the semiconductor device assembly.

なお、請求項７に記載のように、たとえば、前記第１樹脂材料がビスフェノールＡ型エポキシ樹脂であり、前記第２樹脂材料がポリイミドアミドであれば、第１樹脂材料の熱膨張係数よりも第２樹脂材料の熱膨張係数が大きく、かつ、第１樹脂材料の弾性率よりも第２樹脂材料の弾性率の方が小さくなる。   As described in claim 7, for example, when the first resin material is a bisphenol A type epoxy resin and the second resin material is polyimide amide, the coefficient of thermal expansion is larger than the thermal expansion coefficient of the first resin material. The thermal expansion coefficient of the second resin material is large, and the elastic modulus of the second resin material is smaller than the elastic modulus of the first resin material.

以下では、この発明の実施の形態を、添付図面を参照して詳細に説明する。
図１は、この発明にかかる半導体装置１の構成を図解的に示す側面図である。
この半導体装置１は、ＷＬ−ＣＳＰ（ウエハレベルチップサイズパッケージ：Wafer Level-Chip Size Package）を採用した半導体装置であって、その表面に機能素子（図示せず）が作りこまれた半導体チップ１０を備えている。半導体チップ１０は、たとえば、３００〜４００μｍの厚さを有している。 Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a side view schematically showing the configuration of a semiconductor device 1 according to the present invention.
This semiconductor device 1 is a semiconductor device adopting a WL-CSP (Wafer Level-Chip Size Package), and a semiconductor chip 10 having functional elements (not shown) formed on the surface thereof. It has. The semiconductor chip 10 has a thickness of 300 to 400 μm, for example.

図示しないが、半導体チップ１０の表面１０ａは、パッシベーション膜で覆われており、そのパッシベーション膜には、ポリイミド層や再配線が形成されている。そして、半導体チップ１０の表面１０ａ上には、再配線などを封止するための表面側樹脂層１１が形成されている。この表面側樹脂層１１は、およそ４０〜１００μｍの厚みを有している。
表面側樹脂層１１は、たとえば、弾性率が１６ＧＰａであり、ガラス転移点（１３５℃）よりも低い温度における熱膨張係数が２．５〜８．５ｐｐｍ／℃であり、ガラス転移点以上の温度における熱膨張係数が１９．０〜４４．０ｐｐｍ／℃である第１樹脂材料としてのビスフェノールＡ型エポキシ樹脂を用いて形成されている。 Although not shown, the surface 10a of the semiconductor chip 10 is covered with a passivation film, and a polyimide layer and a rewiring are formed on the passivation film. And on the surface 10a of the semiconductor chip 10, the surface side resin layer 11 for sealing rewiring etc. is formed. The surface side resin layer 11 has a thickness of about 40 to 100 μm.
For example, the surface-side resin layer 11 has an elastic modulus of 16 GPa, a thermal expansion coefficient at a temperature lower than the glass transition point (135 ° C.) of 2.5 to 8.5 ppm / ° C., and a temperature equal to or higher than the glass transition point. Is formed using bisphenol A type epoxy resin as the first resin material having a thermal expansion coefficient of 19.0 to 44.0 ppm / ° C.

一方、半導体チップ１０の裏面１０ｂ上には、表面側樹脂層１１の材料であるビスフェノールＡ型エポキシ樹脂よりも大きな熱膨張係数を有し、かつ、それよりも小さな弾性率を有する樹脂材料、たとえば、弾性率が２．５ＧＰａであり、熱膨張係数が６０．０ｐｐｍ／℃である第２樹脂材料としてのポリイミドアミドを用いて、裏面側樹脂層１２が形成されている。裏面側樹脂層１２は、およそ１０〜３０μｍの厚みを有しており、表面側樹脂層１１よりも薄く形成されている。   On the other hand, on the back surface 10b of the semiconductor chip 10, a resin material having a thermal expansion coefficient larger than that of the bisphenol A type epoxy resin that is a material of the front surface side resin layer 11, and having a smaller elastic modulus, for example, The back-side resin layer 12 is formed using polyimide amide as the second resin material having an elastic modulus of 2.5 GPa and a thermal expansion coefficient of 60.0 ppm / ° C. The back surface side resin layer 12 has a thickness of approximately 10 to 30 μm and is formed thinner than the front surface side resin layer 11.

また、表面側樹脂層１１上には、実装基板２と接続するための複数の外部端子１３が設けられている。複数の外部端子１３は、たとえば、表面側樹脂層１１側の中央部において、格子状に配列されている。各外部端子１３は、ボール状に形成されており、半導体装置１に備えられた半導体チップ１０と電気的に接続されている。この半導体装置１では、各外部端子１３が実装基板２上の各ランド２１に当接されることにより、実装基板２に対する実装が達成される。   A plurality of external terminals 13 for connecting to the mounting substrate 2 are provided on the front surface side resin layer 11. The plurality of external terminals 13 are arranged in a lattice pattern, for example, in the central portion on the surface side resin layer 11 side. Each external terminal 13 is formed in a ball shape and is electrically connected to the semiconductor chip 10 provided in the semiconductor device 1. In the semiconductor device 1, the external terminals 13 are brought into contact with the lands 21 on the mounting substrate 2, whereby the mounting on the mounting substrate 2 is achieved.

このように、裏面側樹脂層１２を表面側樹脂層１１よりも薄く形成することによって、半導体チップ１０の表面１０ａ側および裏面１０ｂ側に同じ厚みを有する樹脂層を形成する場合に比べて、その厚みを小さくすることができる。また、裏面側樹脂層１２が表面側樹脂層１１よりも薄くても、裏面側樹脂層１２の材料として、表面側樹脂層１１を形成する樹脂材料よりも熱膨張係数が大きな樹脂材料を用いられることにより、表面側樹脂層１１および裏面側樹脂層１２が熱膨張または熱収縮したときに、裏面側樹脂層１２から半導体チップ１０の裏面に加わる応力を、表面側樹脂層１１から半導体チップ１０の表面に加わる応力とほぼ等しくすることができる。よって、半導体装置１の厚みが大きくなるのを防止することができながら、急激な温度変化による半導体チップ１０の反りの発生を防止することができる。   Thus, by forming the back surface side resin layer 12 thinner than the front surface side resin layer 11, compared with the case where the resin layer having the same thickness is formed on the front surface 10a side and the back surface 10b side of the semiconductor chip 10, The thickness can be reduced. Moreover, even if the back surface side resin layer 12 is thinner than the front surface side resin layer 11, a resin material having a larger thermal expansion coefficient than the resin material forming the front surface side resin layer 11 is used as the material of the back surface side resin layer 12. Thus, when the front surface side resin layer 11 and the back surface side resin layer 12 are thermally expanded or contracted, the stress applied from the back surface side resin layer 12 to the back surface of the semiconductor chip 10 is changed from the front surface side resin layer 11 to the semiconductor chip 10. It can be made approximately equal to the stress applied to the surface. Therefore, it is possible to prevent warping of the semiconductor chip 10 due to a rapid temperature change while preventing an increase in the thickness of the semiconductor device 1.

また、裏面側樹脂層１２の材料として、比較的小さな弾性率を有するポリイミドアミドが用いられているので、裏面側樹脂層１２が薄く形成されていても、その裏面側樹脂層１２に加わる衝撃を十分に吸収することができ、半導体チップ１０を十分に保護することができる。
図２は、図１に示す半導体装置１が集合してなる半導体装置集合体３の表面３０ａ側斜視図であり、図３は、その図解的な側面図である。 Moreover, since the polyimideamide which has a comparatively small elasticity modulus is used as a material of the back surface side resin layer 12, even if the back surface side resin layer 12 is formed thinly, the impact applied to the back surface side resin layer 12 is exerted. The semiconductor chip 10 can be sufficiently protected and can be sufficiently protected.
2 is a perspective view of the surface 30a side of the semiconductor device assembly 3 formed by assembling the semiconductor devices 1 shown in FIG. 1, and FIG. 3 is a schematic side view thereof.

半導体装置１は、複数の半導体装置１が集合してなる半導体装置集合体３を、図示しないダイシングブレードなどにより、各半導体チップ１０間に設定されたダイシングラインＬに沿って切断し、各１個の半導体チップ１０を含む個片に切り分けることで得られる。
半導体装置集合体３は、複数の半導体チップ１０が作り込まれた基板３０と、その基板３０の表面３０ａ（各半導体チップ１０の表面１０ａ）上に、ビスフェノールＡ型エポキシ樹脂を用いて形成された表面側樹脂層１１と、基板３０の裏面３０ｂ上に、ポリイミドアミドを用いて表面側樹脂層１１よりも薄く形成された裏面側樹脂層１２とを備えている。 The semiconductor device 1 is formed by cutting a semiconductor device assembly 3 formed by a plurality of semiconductor devices 1 along a dicing line L set between the semiconductor chips 10 with a dicing blade (not shown). It is obtained by cutting into individual pieces including the semiconductor chip 10.
The semiconductor device assembly 3 is formed using a bisphenol A type epoxy resin on a substrate 30 on which a plurality of semiconductor chips 10 are formed and on a surface 30a of the substrate 30 (a surface 10a of each semiconductor chip 10). The front surface side resin layer 11 and the back surface side resin layer 12 formed thinner than the front surface side resin layer 11 using polyimide amide on the back surface 30b of the substrate 30 are provided.

表面側樹脂層１１および裏面側樹脂層１２は、次のようにして形成される。すなわち、表面側樹脂層１１および裏面側樹脂層１２を形成する際には、基板３０の表面３０ａに、表面側樹脂層１１の材料であるビスフェノールＡ型エポキシ樹脂が塗布される。また、基板３０の裏面３０ｂに、裏面側樹脂層１２の材料であるポリイミドアミドが塗布される。このとき、ポリイミドアミドは、基板３０の表面３０ａ上に塗布されたビスフェノールＡ型エポキシ樹脂よりも薄く塗布される。その後、それらの樹脂が、基板３０ごと、約１７０℃〜１８０℃まで加熱された後、常温（約２５℃）まで冷却される。これにより、基板３０の表面３０ａ上のビスフェノールＡ型エポキシ樹脂および基板３０の裏面３０ｂ上のポリイミドアミドが硬化し、基板３０の表面３０ａ上および裏面３０ｂ上に、それぞれ表面側樹脂層１１および裏面側樹脂層１２が形成される。   The front surface side resin layer 11 and the back surface side resin layer 12 are formed as follows. That is, when forming the front surface side resin layer 11 and the back surface side resin layer 12, a bisphenol A type epoxy resin that is a material of the front surface side resin layer 11 is applied to the front surface 30 a of the substrate 30. In addition, polyimide amide, which is the material of the back surface side resin layer 12, is applied to the back surface 30 b of the substrate 30. At this time, the polyimide amide is applied thinner than the bisphenol A type epoxy resin applied on the surface 30 a of the substrate 30. Thereafter, the resins are heated to about 170 ° C. to 180 ° C. together with the substrate 30 and then cooled to room temperature (about 25 ° C.). Thereby, the bisphenol A type epoxy resin on the front surface 30a of the substrate 30 and the polyimide amide on the back surface 30b of the substrate 30 are cured, and the front surface side resin layer 11 and the back surface side are respectively formed on the front surface 30a and the back surface 30b of the substrate 30. A resin layer 12 is formed.

表面側樹脂層１１および裏面側樹脂層１２を形成するための加熱後の冷却時には、基板３０の表面３０ａに塗布されたビスフェノールＡ型エポキシ樹脂が熱収縮し、また、基板３０の裏面３０ｂに塗布されたポリイミドアミドが熱収縮する。基板３０の裏面３０ｂには、ポリイミドアミドが、基板３０の表面３０ａ上のビスフェノールＡ型エポキシ樹脂よりも薄く塗布されているが、ポリイミドアミドはビスフェノールＡ型エポキシ樹脂よりも大きな熱膨張係数を有するので、基板３０の裏面３０ｂには、ビスフェノールＡ型エポキシ樹脂から基板３０の表面３０ａに作用する応力とほぼ同じ大きさの応力がポリイミドアミドから与えられる。そのため、基板３０に反りを生じるおそれがない。   At the time of cooling after heating to form the front surface side resin layer 11 and the back surface side resin layer 12, the bisphenol A type epoxy resin applied to the front surface 30a of the substrate 30 is thermally contracted and applied to the back surface 30b of the substrate 30. The resulting polyimide amide shrinks by heat. On the back surface 30b of the substrate 30, polyimide amide is applied thinner than the bisphenol A type epoxy resin on the front surface 30a of the substrate 30, but the polyimide amide has a larger thermal expansion coefficient than the bisphenol A type epoxy resin. The back surface 30b of the substrate 30 is given a stress of approximately the same magnitude as the stress acting on the front surface 30a of the substrate 30 from the bisphenol A type epoxy resin. Therefore, there is no possibility that the substrate 30 is warped.

また、裏面側樹脂層１２を表面側樹脂層１１よりも薄く形成することによって、基板３０の表面３０ａ側および裏面３０ｂ側に同じ厚みを有する樹脂層を形成する場合に比べて、半導体装置集合体３を切断して得られる半導体装置１の厚みを小さくすることができる。
さらに、裏面側樹脂層１２の材料として、小さな弾性率を有する樹脂材料が用いられているので、裏面側樹脂層１２が薄く形成されていても、裏面側樹脂層１２に加わる衝撃を十分に吸収することができる。そのため、半導体装置集合体３の状態において各半導体チップ１０を十分保護することができ、また、半導体装置集合体３から得られる半導体装置１において、半導体チップ１０を十分に保護することができる。 Further, by forming the back surface side resin layer 12 thinner than the front surface side resin layer 11, the semiconductor device assembly is compared with the case where the resin layers having the same thickness are formed on the front surface 30 a side and the back surface 30 b side of the substrate 30. The thickness of the semiconductor device 1 obtained by cutting 3 can be reduced.
Further, since a resin material having a small elastic modulus is used as the material of the back surface side resin layer 12, even if the back surface side resin layer 12 is formed thin, the impact applied to the back surface side resin layer 12 is sufficiently absorbed. can do. Therefore, each semiconductor chip 10 can be sufficiently protected in the state of the semiconductor device assembly 3, and the semiconductor chip 10 can be sufficiently protected in the semiconductor device 1 obtained from the semiconductor device assembly 3.

なお、第１樹脂材料として、ビスフェノールＡ型エポキシ樹脂を例示し、第２樹脂材料として、ポリイミドアミドを例示したが、第１樹脂材料の熱膨張係数よりも第２樹脂材料の熱膨張係数が大きく、かつ、第１樹脂材料の弾性率よりも第２樹脂材料の弾性率の方が小さければ、第１樹脂材料および第２樹脂材料として、例示した材料以外の材料を用いてもよい。   In addition, although the bisphenol A type epoxy resin was illustrated as 1st resin material and the polyimide amide was illustrated as 2nd resin material, the thermal expansion coefficient of 2nd resin material is larger than the thermal expansion coefficient of 1st resin material. If the elastic modulus of the second resin material is smaller than that of the first resin material, materials other than the exemplified materials may be used as the first resin material and the second resin material.

その他、特許請求の範囲に記載された事項の範囲で種々の設計変更を施すことが可能である。   In addition, various design changes can be made within the scope of matters described in the claims.

この発明にかかる半導体装置の構成を図解的に示す側面図である。1 is a side view schematically showing a configuration of a semiconductor device according to the present invention. 図１に示す半導体装置が集合してなる半導体装置集合体の表面側斜視図である。FIG. 2 is a front perspective view of a semiconductor device assembly formed by aggregating the semiconductor devices shown in FIG. 1. 図２に示す半導体装置集合体の図解的な側面図である。FIG. 3 is a schematic side view of the semiconductor device assembly shown in FIG. 2.

符号の説明Explanation of symbols

１ 半導体装置
１０ 半導体チップ
１０ａ 半導体チップの表面
１０ｂ 半導体チップの裏面
１１ 表面側樹脂層
１２ 裏面側樹脂層
１３ 外部端子
２ 実装基板
２１ ランド DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Semiconductor chip 10a The surface of a semiconductor chip 10b The back surface of a semiconductor chip 11 Front surface side resin layer 12 Back surface side resin layer 13 External terminal 2 Mounting substrate 21 Land

Claims (7)

半導体チップと、
前記半導体チップの表面上に、第１樹脂材料を用いて形成された表面側樹脂層と、
前記半導体チップの裏面上に、前記第１樹脂材料よりも大きな熱膨張係数を有する第２樹脂材料を用いて、前記表面側樹脂層よりも薄く形成された裏面側樹脂層とを含むことを特徴とする、半導体装置。 A semiconductor chip;
On the surface of the semiconductor chip, a surface-side resin layer formed using a first resin material;
And a back side resin layer formed thinner on the back side of the semiconductor chip than the front side resin layer using a second resin material having a thermal expansion coefficient larger than that of the first resin material. A semiconductor device. 前記第２樹脂材料は、前記第１樹脂材料よりも小さな弾性率を有するものであることを特徴とする、請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the second resin material has a smaller elastic modulus than the first resin material. 前記第１樹脂材料は、ビスフェノールＡ型エポキシ樹脂であり、
前記第２樹脂材料は、ポリイミドアミドであることを特徴とする、請求項２記載の半導体装置。 The first resin material is a bisphenol A type epoxy resin,
The semiconductor device according to claim 2, wherein the second resin material is polyimide amide. 前記表面側樹脂層上に配置され、前記半導体装置が実装基板に実装されたときに、前記実装基板上の電極に当接する外部端子をさらに含むことを特徴とする、請求項１ないし３のいずれかに記載の半導体装置。   4. The semiconductor device according to claim 1, further comprising an external terminal disposed on the surface-side resin layer and contacting an electrode on the mounting substrate when the semiconductor device is mounted on the mounting substrate. A semiconductor device according to claim 1. 複数の半導体チップが作り込まれた基板と、
前記基板の表面上に、第１樹脂材料を用いて形成された表面側樹脂層と、
前記基板の裏面上に、前記第１樹脂材料よりも大きな熱膨張係数を有する第２樹脂材料を用いて、前記表面側樹脂層よりも薄く形成された裏面側樹脂層とを含むことを特徴とする、半導体装置集合体。 A substrate on which a plurality of semiconductor chips are built, and
A surface-side resin layer formed using a first resin material on the surface of the substrate;
And a back side resin layer formed thinner than the front side resin layer using a second resin material having a larger thermal expansion coefficient than the first resin material on the back side of the substrate. A semiconductor device assembly. 前記第２樹脂材料は、前記第１樹脂材料よりも小さな弾性率を有するものであることを特徴とする、請求項５記載の半導体装置集合体。   6. The semiconductor device assembly according to claim 5, wherein the second resin material has a smaller elastic modulus than that of the first resin material. 前記第１樹脂材料は、ビスフェノールＡ型エポキシ樹脂であり、
前記第２樹脂材料は、ポリイミドアミドであることを特徴とする、請求項６記載の半導体装置集合体。 The first resin material is a bisphenol A type epoxy resin,
The semiconductor device assembly according to claim 6, wherein the second resin material is polyimide amide.
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CN2010101666401A CN101847611B (en) 2005-06-29 2006-06-28 Semiconductor device
US11/988,030 US8164201B2 (en) 2005-06-29 2006-06-28 Semiconductor device with front and back side resin layers having different thermal expansion coefficient and elasticity modulus
PCT/JP2006/312882 WO2007001018A1 (en) 2005-06-29 2006-06-28 Semiconductor device and semiconductor device assembly
KR1020077029817A KR20080031192A (en) 2005-06-29 2006-06-28 Semiconductor device and semiconductor device assembly
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US13/441,019 US8664779B2 (en) 2005-06-29 2012-04-06 Semiconductor device with front and back side resin layers having different thermal expansion coefficient and elasticity modulus
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KR102541134B1 (en) * 2015-11-04 2023-06-08 린텍 가부시키가이샤 A kit of a thermosetting resin film and a second protective film forming film, a thermosetting resin film, a sheet for forming a first protective film, and a method for forming a first protective film for semiconductor wafers
CN112635410A (en) * 2019-09-24 2021-04-09 株式会社东芝 Power module
JP7374039B2 (en) 2020-03-30 2023-11-06 三井化学東セロ株式会社 Method of manufacturing electronic devices

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