WO2014192430A1

WO2014192430A1 - Semiconductor device

Info

Publication number: WO2014192430A1
Application number: PCT/JP2014/060244
Authority: WO
Inventors: 中磯俊幸; 加藤登
Original assignee: 株式会社村田製作所
Priority date: 2013-05-31
Filing date: 2014-04-09
Publication date: 2014-12-04
Also published as: CN205282460U

Abstract

An ESD protection device (1) comprises the following: an Si substrate (10) on which an ESD protection circuit (10A) has been formed; pads (P1, P2) formed on the Si substrate (10) and for conduction with the ESD protection circuit (10A); a resin layer (22) formed on the Si substrate (10); interlayer connection conductors (232, 242) which conduct electricity to the pads (P1, P2) and which are disposed in contact holes formed in the part of the resin layer (22) where the pads (P1, P2) are positioned; wiring electrodes (231, 241) connected to an outer circumferential part of the interlayer connection conductors (232, 242); external electrodes (25A, 25B) formed on a part of the wiring electrodes (231, 241) at a position different from the interlayer connection conductors (232, 242) in plan view; and a resin layer (26) that is a light transmitting resin in which are formed openings (26A, 26B) for partially exposing the external electrodes (25A, 25B) in plan view. Due to this configuration, provided is a semiconductor device with which breakage of the wiring electrodes or interlayer connection conductors can be confirmed from outside of the device.

Description

Semiconductor device

The present invention relates to a semiconductor device including a rewiring layer on a semiconductor substrate on which a functional element is formed.

One of the semiconductor devices is an ESD (Electro-Static-Discharge) protection device. The ESD protection device protects semiconductor ICs and the like from surges such as electrostatic discharge. Various electronic devices such as a mobile communication terminal, a digital camera, and a notebook PC are provided with a semiconductor integrated circuit constituting a logic circuit or a memory circuit. Such a semiconductor integrated circuit is a low-voltage driving circuit composed of a fine wiring pattern formed on a semiconductor substrate, and is generally vulnerable to a surge caused by electrostatic discharge or the like. Therefore, an ESD protection device is used to protect such a semiconductor integrated circuit from a surge.

Patent Document 1 discloses an ESD protection device in which a rewiring layer containing an epoxy resin is formed on the surface of a Si substrate on which an ESD protection circuit is configured. A wiring electrode that is electrically connected to the Si substrate is formed on the resin layer of the rewiring layer. This Patent Document 1 is a CSP (Chip Size Package) type device, which realizes miniaturization.

International Publication No. 2012/023394 Pamphlet

In the case of a CSP type device as in Patent Document 1, it is necessary to make the wiring electrodes and the interlayer connection conductors thinner in order to reduce the thickness of the device. However, in such a case, a part of the wiring electrode or the interlayer connection conductor may be broken. In particular, since the joint portion between the wiring electrode and the interlayer connection conductor is discontinuous, the thickness of the electrode at the joint portion becomes thin, and there is a risk of disconnection at the joint portion. In general, the wiring electrodes of the rewiring layer are covered with an insulating layer (resin layer). For this reason, even if the wiring electrode or the interlayer connection conductor is disconnected, it is difficult to confirm from the appearance. Such a problem cannot be solved by Patent Document 1.

Therefore, an object of the present invention is to provide a semiconductor device capable of confirming a breakage of a wiring electrode or an interlayer connection conductor from the appearance.

The semiconductor device according to the present invention includes a semiconductor substrate on which a functional element is formed, a metal film formed on the functional element formation surface of the semiconductor substrate and electrically connected to the functional element, and the functional element formation surface of the semiconductor substrate. A first insulating layer formed on the first insulating layer; an interlayer connection conductor provided in a contact hole formed in a portion of the first insulating layer where the metal film is located; and the function of the semiconductor substrate. A wiring electrode formed on the first insulating layer so as to face the element forming surface and conducting to the interlayer connection conductor, and formed on a part of the wiring electrode at a position different from the interlayer connection conductor in a plan view. An external electrode and an opening for exposing a part of the external electrode in plan view, and a second insulating layer formed on the first insulating layer, wherein the wiring electrode is formed of the interlayer connection conductor. Connected to the outer periphery, Serial second insulating layer is characterized in that it is a translucent resin.

In this configuration, since the second insulating layer covering the wiring electrode and the interlayer connection conductor is made of a translucent resin, the wiring electrode, the interlayer connection conductor, or a joint portion thereof is externally (from the top of the second insulating layer). Can be confirmed. Thereby, the presence or absence of the disconnection of the electrical connection part of the semiconductor device can be confirmed, and it can be optically determined whether or not the semiconductor device is defective.

The second insulating layer is preferably a photosensitive resin.

This configuration enables high-precision pattern formation.

The functional element preferably includes a diode.

In this configuration, the function of the diode can be used reliably.

It is preferable that the functional element is an ESD protection circuit and the wiring electrode is an ESD current path.

In this configuration, by making it easy to confirm the disconnection of part or all of the wiring electrodes and interlayer connection conductors that are the current paths of the ESD current, it is possible to avoid an increase in the clamp voltage during electrostatic discharge, and as an ESD protection element It can function reliably.

The first insulating layer is preferably translucent.

In this configuration, it becomes easy to confirm the breakage (breakage) of the semiconductor substrate on which the first insulating layer is formed or the metal film formed on the semiconductor substrate during the manufacturing process.

It is preferable that a resin layer is provided on the surface opposite to the functional element formation surface of the semiconductor substrate.

In this configuration, the warpage of the semiconductor substrate due to the difference in the thermal expansion coefficient between the first and second insulating layers and the semiconductor substrate can be suppressed.

According to the present invention, the wiring electrodes, the interlayer connection conductors, or their joint portions can be confirmed from the outside (from the top of the second insulating layer). Thereby, the presence or absence of the disconnection of the electrical connection part of the semiconductor device can be confirmed, and it can be optically determined whether or not the semiconductor device is defective.

Front sectional view of an ESD protection device according to an embodiment Plan view of each layer of ESD protection device The figure which shows the planar structure of the ESD protection circuit formed in Si substrate Circuit diagram of ESD protection circuit The figure which shows the case where there is a disconnection at the joint between the wiring electrode and the interlayer connection conductor Diagram showing the case where there is no disconnection at the joint between the wiring electrode and the interlayer connection conductor The figure which shows the example of a connection of the ESD protection device which concerns on embodiment The figure which shows the example of a connection of the ESD protection device which concerns on embodiment The figure for demonstrating the principle of operation of the ESD protection device which concerns on embodiment The figure for demonstrating the principle of operation of the ESD protection device which concerns on embodiment Diagram showing manufacturing process of ESD protection device The figure which shows the mounting aspect of the ESD protection device which concerns on embodiment Plan view of the substrate on which the ESD protection device is mounted Plan view of another example of a substrate mounting an ESD protection device Diagram showing an example of another substrate mounting an ESD protection device

Hereinafter, the semiconductor device according to the present invention will be described using an ESD protection device as an example.

FIG. 1 is a front sectional view of an ESD protection device 1 according to this embodiment. FIG. 2 is a plan view of each layer of the ESD protection device 1. The ESD protection device 1 is a CSP type device, and a rewiring layer 20 including a plurality of resin layers and the like is formed on a Si substrate 10 on which an ESD protection circuit 10A including a diode and a Zener diode is configured. The Si substrate 10 corresponds to the semiconductor substrate according to the present invention, but the semiconductor substrate according to the present invention is not limited to the Si substrate, and may be a GaAs substrate or the like.

3 is a diagram showing a planar configuration of the ESD protection circuit 10A formed on the Si substrate 10, and FIG. 4 is a circuit diagram of the ESD protection circuit 10A.

The Si substrate 10 is a p + type substrate, an n epitaxial layer is formed on the surface thereof, and an n well and a p well are formed in the epitaxial layer. A p-type diffusion layer and an n-type diffusion layer are further formed in the n well and the p well. A diode and a Zener diode are formed by the p + type substrate, the well, and the diffusion layer.

In this embodiment, diodes D1a, D1b, D3a, and D3b are formed on the surface of the Si substrate 10. In the thickness direction of the Si substrate 10, diodes D2 and D4 and a Zener diode are formed. Each of these elements forms the circuit shown in FIG. In FIG. 4, the diodes D1a and D1b are one diode D1, and the diodes D3a and D3b are one diode D3.

The formed diodes D1, D2 are aligned in the forward direction and connected in series, and the diodes D3, D4 are aligned in the forward direction and connected in series. The diodes D1 and D2 and the diodes D3 and D4 connected in series are aligned in the forward direction and connected in parallel to the Zener diode Dz. Further, a Zener diode Dz is interposed between the formation positions of the diodes D1 and D4 and between the formation positions of the diodes D2 and D3. A connection point between the formed diodes D1a and D1b and the diode D2 serves as a first input / output terminal of the ESD protection circuit 10A and is connected to an Al pad (hereinafter referred to as a pad) P1 formed on the Si substrate 10. Yes. A connection point between the formed diodes D3a and D3b and the diode D4 serves as a second input / output terminal of the ESD protection circuit 10A and is connected to an Al pad (hereinafter referred to as a pad) P2 formed on the Si substrate 10. is doing. The pads P1 and P2 correspond to the metal film according to the present invention.

The rewiring layer 20 formed on the surface layer of the Si substrate 10 is SiN or SiO ₂ formed on the surface (functional element formation surface) of the Si substrate 10 so as to cover a part of the peripheral edge of the pads P1 and P2. The protective film 21 and the resin layer 22 covering the protective film 21 and the pads P1 and P2 are included. The protective film 21 is formed by sputtering, and the resin layer 22 is formed by spin coating of epoxy (or polyimide) solder girest. In the resin layer 22, openings (contact holes) 22A and 22B (see FIG. 2) for exposing parts of the pads P1 and P2 are formed. The resin layer 22 is a translucent insulating layer. However, as will be described later, the resin layer 22 may be a non-transmissive insulating layer in order to suppress the incidence of light on the ESD protection circuit 10A.

Ti / Cu /

Ti electrodes

23 and 24 are formed in the

openings

22A and 22B and the peripheral regions of the

openings

22A and 22B. The Ti / Cu /

Ti electrodes

23 and 24 are planar electrodes facing the surface of the Si substrate 10 (hereinafter referred to as wiring electrodes 231 and 241) and electrodes formed in the contact holes 22 A and 22 B of the resin layer 22. (Hereinafter, referred to as interlayer connection conductors 232 and 242). The

interlayer connection conductors

232 and 242 are recessed at the center during the manufacturing process. The

wiring electrodes

231 and 241 are connected to the

interlayer connection conductors

232 and 242 at the periphery of the depression. The

wiring electrodes

231 and 241 are electrically connected to the pads P1 and P2 through the

interlayer connection conductors

232 and 242, respectively.

External electrodes

25A and 25B made of Au / Ni are formed on the

wiring electrodes

231 and 241 of the Ti / Cu /

Ti electrodes

23 and 24, respectively. The portions of the

wiring electrodes

231 and 241 where the

external electrodes

25A and 25B are formed are etched to expose Cu, and the

external electrodes

25A and 25B are plated on the exposed Cu portions. The

external electrodes

25A and 25B are terminal electrodes for input / output terminals of the ESD protection device 1.

The rewiring layer 20 includes a resin layer 26 further formed on the resin layer 22. The resin layer 26 is a translucent resin, for example, a photosensitive epoxy (photosensitive resin) that can ensure high insulation. Openings (via holes) 26 A and 26 B are formed in the resin layer 26. The

openings

26A and 26B expose part of the

external electrodes

25A and 25B.

Since the resin layer 26 is a translucent resin, for example, infrared rays are irradiated from above the resin layer 26, and the

wiring electrodes

231 and 241 of the Ti / Cu /

Ti electrodes

23 and 24 or the

interlayer connection conductors

232 and 242, particularly The presence or absence of disconnection at these joints can be confirmed. By confirming the presence or absence of disconnection, it is possible to determine whether the ESD protection device 1 is good or bad.

FIG. 5A is a diagram showing a case where there is a disconnection at the junction between the wiring electrode 231 and the interlayer connection conductor 232, and FIG. 5B shows a case where there is no disconnection at the junction between the wiring electrode 231 and the interlayer connection conductor 232. FIG. 5A and 5B, a front view and a plan view of the Ti / Cu / Ti electrode 23 are shown. In the following, the wiring electrode 231 and the interlayer connection conductor 232 will be described with reference to FIGS. 5A and 5B, but the wiring electrode 241 and the interlayer connection conductor 242 can be described in the same manner.

Ti / Cu / Ti electrode 23 is formed by sputtering and then wet etching. Due to this manufacturing process, the interlayer connection conductor 232 has a recess 232 A formed in the center. When the Ti / Cu / Ti electrode 23 is to be made thinner, the lower part (pad P1 side) of the interlayer connection conductor 232 connected to the pad P1 is thicker and the upper part (wiring electrode 231 side) is thinner. For this reason, since the upper part of the interlayer connection conductor 232 becomes thin, the joint portion between the wiring electrode 231 and the interlayer connection conductor 232 may be disconnected. As shown in FIG. 5A, a disconnection portion 232B occurs at the joint portion. On the other hand, when the junction between the wiring electrode 241 and the interlayer connection conductor 232 is not disconnected, the disconnection 232B does not occur at the junction as shown in FIG. 5B.

Thus, since the resin layer 26 is a translucent resin, it is easy to confirm from the appearance whether or not the disconnection portion 232B shown in FIG. 5A is present, and it is possible to determine whether the ESD protection device 1 is good or bad.

Referring back to FIG. 1, a resin layer 27 is further formed on the back surface of the Si substrate 10 opposite to the surface on which the rewiring layer 20 is formed. The resin layer 27 is formed by spin coating of an epoxy (or polyimide) solder girest. By forming the resin layer 27 on the back surface of the Si substrate 10, it is possible to suppress warpage of the Si substrate 10 due to a difference in thermal expansion coefficient between the Si substrate 10 and the epoxy resin of the rewiring layer 20.

In the present embodiment, an example in which the Zener diode Dz or the like is formed on the Si substrate 10 to configure the ESD protection circuit 10A has been shown. However, for example, a PNP type semiconductor or an NPN type semiconductor is formed on the Si substrate 10. A circuit using the same may be configured.

Hereinafter, a connection example and an operation principle of the ESD protection device according to this embodiment will be described.

6A and 6B are diagrams showing connection examples of the ESD protection device 1 according to the present embodiment. The ESD protection device 1 is mounted on an electronic device. Examples of electronic devices include notebook PCs, tablet terminal devices, mobile phones, digital cameras, and portable music players.

FIG. 6A shows an example in which the ESD protection device 1 is connected between the signal line connecting the I / O port 100 and the IC 101 to be protected and GND. The I / O port 100 is a port to which an antenna is connected, for example. The ESD protection device 1 according to the present embodiment is a bidirectional type, and either the first input / output terminal or the second input / output terminal may be on the input side. For example, when the first input / output terminal is the input side, the first input / output terminal is connected to the signal line, and the second input / output terminal is connected to the GND.

When a surge voltage exceeding the Zener voltage of the ESD protection device 1 Zener diode Dz is applied from the signal line, the surge current (ESD current) is discharged from the ESD protection device 1 to the ground. The ESD protection device 1 can confirm the presence / absence of disconnection of the Ti / Cu /

Ti electrodes

23 and 24 that are current paths of surge current. For this reason, if the Ti / Cu /

Ti electrodes

23 and 24 are disconnected, no surge current flows through the ESD protection device 1, and the ESD protection device 1 does not function normally. In this embodiment, since it is easy to confirm the presence / absence of disconnection of the Ti / Cu /

Ti electrodes

23 and 24 and the defect of the ESD protection device 1 can be identified, the ESD protection device 1 can reliably discharge a surge current to the ground. .

FIG. 6A shows an example in which the ESD protection device 1 is connected between the signal line connecting the connector 102 and the IC 101 and the GND line. The signal line in this example is, for example, a high-speed transmission line (differential transmission line), and the ESD protection device 1 is connected between each of the plurality of signal lines and the GND line.

7 and 8 are diagrams for explaining the operating principle of the ESD protection device 1 according to the present embodiment. The ESD protection device 1 uses the

external electrodes

25A and 25B as the first input / output terminal and the second input / output terminal, and is connected between the signal line and the GND line. This signal line is a line connected to an input / output terminal of an IC (not shown) to be protected from electrostatic discharge voltage. The ESD protection device according to this embodiment is a bidirectional type, and either the first input / output terminal or the second input / output terminal may be on the input side. For example, when the first input / output terminal is the input side, the first input / output terminal is connected to the signal line, and the second input / output terminal is connected to the GND line.

FIG. 7 is a diagram for explaining a case where a current flows from the pad P1 connected to the first input / output terminal (external electrode 23A) to the pad P2 connected to the second input / output terminal (external electrode 23B). When a surge voltage exceeding the Zener voltage of the Zener diode Dz is applied, the surge current that has entered from the first input terminal is routed from the pad P1 to the diode D1, the Zener diode Dz, and the diode D4, as indicated by the broken line in the figure. And discharged from the pad P2 to the ground.

FIG. 8 is a diagram for explaining a case where a current flows from the pad P2 connected to the second input / output terminal (external electrode 23B) to the pad P1 connected to the first input / output terminal (external electrode 23A). In this case, as indicated by a broken line in the figure, the surge current that has entered from the second input terminal flows from the pad P2 through the diode D3, the Zener diode Dz, and the diode D2, and is discharged from the pad P1 to the ground.

Hereinafter, the manufacturing process of the ESD protection device 1 will be described. FIG. 9 is a diagram illustrating a manufacturing process of the ESD protection device 1. The ESD protection device 1 is manufactured by the following process.

(A) First, pads P1 and P2 that are electrically connected to the ESD protection circuit 10A are formed on the Si substrate 10 on which the ESD protection circuit 10A is formed by photolithography. Also, the protective film 21 is sputtered on the substrate surface, and

openings

21A and 21B are formed by etching.

Note that the parasitic capacitance formed between the pads P1 and P2 and the opposing substrate (ESD protection circuit 10A) can be reduced by reducing their area. By reducing the parasitic capacitance, it is possible to suppress the deviation of the impedance, and as a result, it is possible to reduce the loss in the signal line.

(B) Next, the resin layer 22 is formed on the Si substrate 10 by spin coating with an epoxy solder girest, and then the

openings

22A and 22B are formed. The resin layer 22 may be a light-transmitting resin, like the resin layer 26. In this case, it is possible to confirm the damage of the Si substrate 10 on which the resin layer 22 is formed or the pads P1 and P2 from the upper side of the resin layer 22 during the manufacturing.

(C) Ti / Cu / Ti is formed on the surface of the resin layer 22 by sputtering with a thickness of about 0.1 μm / 1.0 μm / 0.1 μm, and then wet etched to form the

electrodes

23 and 24. The

(D) A part of the surface of the Ti / Cu /

Ti electrodes

23, 24 is etched to expose Cu, and the exposed Cu portions are Au / Ni

external electrodes

25A, 25B of about 0.1 μm / 3. The film is formed by electrolytic plating (electroplating) with a thickness of 0.0 μm. The

external electrodes

25A and 25B are selectively plated only on the exposed Cu surface. By forming the

external electrodes

25A and 25B by selective plating, a resist film is not formed, and masking is not required, so that manufacturing is facilitated.

(E) Thereafter, resin layers 26 and 27 are formed on the front surface of the resin layer 22 and the back surface of the Si substrate 10 by spin coating with a light-transmitting epoxy solder girest. Openings 26 A and 26 B are formed in the resin layer 26.

In the embodiment described above, the resin layer 26 is a translucent resin. Conventionally, however, the surface of the ESD protection device is protected in order to ensure mechanical strength and block light from entering the ESD protection circuit 10A. Therefore, the resin layer 26 is generally a black filler-filled epoxy resin. When light enters the semiconductor, carriers are generated by the photoelectric effect. For this reason, when light is incident on the ESD protection circuit 10A, the leakage current of the ESD protection circuit 10A may increase due to the generated carriers.

However, when an epoxy resin with a filler is used, it is necessary to grind the epoxy resin with a filler in order to expose the electrode after forming the epoxy resin with a filler. Therefore, if the resin layer 26 is made of a translucent resin without a filler, it is not necessary to grind and manufacture is facilitated. Further, by adopting a mounting mode described below, it is possible to prevent light from entering.

FIG. 10 is a diagram showing a mounting mode of the ESD protection device 1 according to the embodiment. FIG. 11 is a plan view of the substrate 50 on which the ESD protection device 1 is mounted.

The ESD protection device 1 is mounted on the substrate 50 so that the

openings

26A and 26B are on the substrate 50 side. The substrate 50 on which the ESD protection device 1 is mounted has

wiring patterns

51 and 52 formed on the surface with a gap. When the ESD protection device 1 is mounted on the substrate 50, the external electrode 25A is connected to the wiring pattern 51 by the solder 45A, and the external electrode 25B is connected to the wiring pattern 52 by the solder 45B. In this example, the wiring pattern 52 is connected to the ground. That is, the current path flowing through the ESD protection circuit 10A is a broken line arrow shown in FIG.

As shown in FIG. 11, a resist 53 is provided between the

wiring patterns

51 and 52 on the surface of the substrate 50. The resist 53 is a color that hardly reflects light, for example, black. The

wiring patterns

51 and 52 and the resist 53 are provided at positions facing the ESD protection circuit 10A of the ESD protection device 1, and prevent light from entering the ESD protection circuit 10A.

When light is incident on the ESD protection circuit 10A, in the circuit diagram shown in FIG. 7, current flows from the cathodes to the anodes of the diodes D2 and D3 that are reversely biased, and the current flows from the anode to the cathode of the Zener diode Dz. Flowing. Specifically, the boundary surface between the p + type substrate and the n epitaxial layer in the region forming the diode D2, the boundary surface between the p well and the n type diffusion layer in the region forming the Zener diode Dz, and the diode D3 are formed. A reverse current (leakage current) flows due to the generation of carriers at each of the boundary surfaces between the n-well and the p-type diffusion layer in the region to be processed.

Therefore, by providing an insulating resin 53 such as a resist or underfill on the substrate 50, it is possible to prevent light reflected by the substrate 50 or light from the back side of the substrate 50 from entering the ESD protection circuit 10A. Can do. Thereby, the problem that leakage current flows into the diodes D2 and D3 and the Zener diode Dz described above can be prevented. The resist 53 may be colored, but a black resist is the best.

FIG. 12 is a plan view of another example of the substrate 50 on which the ESD protection device 1 is mounted. In this example, an insulating resin 54 such as a resist or underfill is provided on the surface of the substrate 50 so that the entire ESD protection device 1 mounted on the substrate 50 faces the substrate 50. The resist 54 is a color that hardly reflects light, for example, black. In this case, light incident on the surface of the substrate 50 from an oblique direction can be prevented, and an increase in leakage current of the ESD protection circuit 10A caused by carrier generation can be suppressed.

FIG. 13 is a diagram illustrating an example of another substrate 50 on which the ESD protection device 1 is mounted. In this example, the substrate 50 has an antireflection electrode 55 on the inner layer. The antireflection electrode 55 is provided at a position facing the ESD protection circuit 10 A of the ESD protection device 1. The antireflection electrode 55 is provided at a position facing the ESD protection circuit 10A of the ESD protection device 1 together with the

wiring patterns

51 and 52, and prevents light from being reflected and entering the ESD protection circuit 10A. It is out.

The antireflection electrode 55 may be provided on the inner layer of the substrate 50, or may be provided on the back surface of the substrate 50. Further, the antireflection electrode 55 may use a ground electrode of the substrate 50 or the like. Furthermore, the substrate 50 may be provided with both the antireflection electrode 55 and the resists 53 and 54 described with reference to FIG.

1-ESD protection device 10-Si substrate 10A-ESD protection circuit 20-redistribution layer 21-protection film 23, 24-Ti / Cu / Ti electrode 22-resin layer (second insulating layer)
26-resin layer (first insulating layer)
22A, 22B-

openings

25A, 25B-external electrode 27-resin layer (second insulating layer)
26A, 26B-openings 231,241-wiring electrodes 232,242-interlayer connection conductor 232A-depression 232B-disconnection D1, D2, D3, D4-diode (functional element)
Dz-Zener diode (functional element)
P1, P2-pad (metal film)

Claims

A semiconductor substrate on which functional elements are formed;
A metal film formed on the functional element forming surface of the semiconductor substrate and electrically connected to the functional element;
A first insulating layer formed on the functional element formation surface of the semiconductor substrate;
An interlayer connection conductor provided in a contact hole formed in the portion of the first insulating layer where the metal film is located, and conducting to the metal film;
A wiring electrode formed on the first insulating layer so as to face the functional element formation surface of the semiconductor substrate and electrically connected to the interlayer connection conductor;
An external electrode formed in a part on the wiring electrode at a position different from the interlayer connection conductor in plan view,
An opening that exposes a portion of the external electrode in plan view, and a second insulating layer formed on the first insulating layer;
With
The wiring electrode is connected to the outer periphery of the interlayer connection conductor,
The second insulating layer is a translucent resin.
Semiconductor device.
The semiconductor device according to claim 1, wherein the second insulating layer is a photosensitive resin.
The semiconductor device according to claim 1, wherein the functional element includes a diode.
4. The semiconductor device according to claim 1, wherein the functional element is an ESD protection circuit, and the wiring electrode is a current path of an ESD current.
The semiconductor device according to claim 1, wherein the first insulating layer is translucent.
6. The semiconductor device according to claim 1, further comprising a resin layer formed on a surface opposite to the functional element formation surface of the semiconductor substrate.