WO2014192429A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2014192429A1
WO2014192429A1 PCT/JP2014/060243 JP2014060243W WO2014192429A1 WO 2014192429 A1 WO2014192429 A1 WO 2014192429A1 JP 2014060243 W JP2014060243 W JP 2014060243W WO 2014192429 A1 WO2014192429 A1 WO 2014192429A1
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WO
WIPO (PCT)
Prior art keywords
esd protection
electrode
resin layer
substrate
electrodes
Prior art date
Application number
PCT/JP2014/060243
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French (fr)
Japanese (ja)
Inventor
加藤登
中磯俊幸
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to CN201490000315.XU priority Critical patent/CN205282447U/en
Publication of WO2014192429A1 publication Critical patent/WO2014192429A1/en

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    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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Definitions

  • the present invention relates to a semiconductor device including a rewiring layer on a semiconductor substrate on which a functional element is formed.
  • One of the semiconductor devices is an ESD (Electro-Static-Discharge) protection device.
  • the ESD protection device protects semiconductor ICs and the like from surges such as electrostatic discharge.
  • Various electronic devices such as a mobile communication terminal, a digital camera, and a notebook PC are provided with a semiconductor integrated circuit constituting a logic circuit or a memory circuit.
  • Such a semiconductor integrated circuit is a low-voltage driving circuit composed of a fine wiring pattern formed on a semiconductor substrate, and is generally vulnerable to a surge caused by electrostatic discharge or the like. Therefore, an ESD protection device is used to protect such a semiconductor integrated circuit from a surge.
  • Patent Document 1 discloses an ESD protection device in which a rewiring layer containing an epoxy resin is formed on the surface of a Si substrate on which an ESD protection circuit is configured. A wiring electrode that is electrically connected to the Si substrate is formed on the resin layer of the rewiring layer.
  • This Patent Document 1 is a CSP (Chip Size Package) type device, which realizes miniaturization.
  • Patent Document 1 there may be a gap between the wiring electrode and the resin layer in the rewiring layer during manufacturing, and impurities such as moisture may enter from the gap, and the wiring electrode may be oxidized or corroded. is there. In this case, there is a problem that the resistance value of the wiring electrode increases due to the corrosion, and the clamp voltage during electrostatic discharge cannot be lowered.
  • an object of the present invention is to provide a semiconductor device that avoids an increase in resistance value of the wiring electrode due to oxidation or corrosion of the wiring electrode.
  • the semiconductor device includes a semiconductor substrate on which a functional element is formed, a metal film formed on the functional element formation surface of the semiconductor substrate and connected to the functional element, and the functional element formation on the semiconductor substrate.
  • An insulating layer formed on the surface; a wiring electrode formed on the insulating layer so as to oppose the functional element formation surface of the semiconductor substrate; and a conductive electrode connected to the metal film; and formed on a part of the wiring electrode.
  • an insulating resin layer formed on the insulating layer. The opening is formed so as to expose a part of the inner side of the outer electrode in a plan view.
  • the wiring electrode has a Ti film on a surface layer other than a portion where the external electrode is formed, a main material is Cu, and the external electrode is a film formed by plating the wiring electrode Is preferred.
  • the bonding strength between the insulating resin layer and the wiring electrode is increased by forming the Ti film.
  • the external electrode can be selectively plated without forming a resist film by having a Ti film on the surface layer other than the portion where the external electrode is formed, the manufacture is facilitated.
  • the functional element is an ESD protection circuit and the wiring electrode is an ESD current path.
  • the present invention since no gap is formed between the external electrode and the resin layer, it is possible to prevent a problem such that an impurity such as moisture enters the gap and the electrode is oxidized or corroded. As a result, an increase in the resistance value of the wiring electrode can be prevented, and an increase in loss at the wiring electrode can be avoided.
  • FIG. 1 Front sectional view of an ESD protection device according to an embodiment Plan view of each layer of ESD protection device
  • the figure which shows the example of a connection of the ESD protection device which concerns on embodiment The figure which shows the example of a connection of the ESD protection device which concerns on embodiment
  • the figure for demonstrating the principle of operation of the ESD protection device which concerns on embodiment The figure for demonstrating the principle of operation of the ESD protection device which concerns on embodiment
  • the figure which shows another example of the opening which exposes a part of external electrode The figure which shows another example of the opening which exposes a part of external electrode
  • FIG. 1 is a front sectional view of an ESD protection device 1 according to this embodiment.
  • FIG. 2 is a plan view of each layer of the ESD protection device 1.
  • the ESD protection device 1 is a CSP type device, and a rewiring layer 20 including a plurality of resin layers and the like is formed on a Si substrate 10 on which an ESD protection circuit 10A including a diode and a Zener diode is configured.
  • the Si substrate 10 corresponds to the semiconductor substrate according to the present invention, but the semiconductor substrate according to the present invention is not limited to the Si substrate, and may be a GaAs substrate or the like.
  • FIG. 3 is a diagram showing a planar configuration of the ESD protection circuit 10A formed on the Si substrate 10
  • FIG. 4 is a circuit diagram of the ESD protection circuit 10A.
  • FIG. 5 is a cross-sectional view of a main part of the ESD protection device 1 according to this embodiment.
  • an element formation layer 10 ⁇ / b> L for forming a plurality of elements is provided on the surface of a p + Si substrate 10.
  • An element isolation region 110 is formed. These element isolation regions 110 are trench isolations in which a Si oxide film (SiOx) is formed on the inner surface of a trench and polysilicon is filled therein. Two elements separated by the element isolation region 110 (two elements sandwiching the element isolation region 110) are n epitaxial layers that are opposite to the type (p +) of the semiconductor substrate 10 on the surface of the element formation layer 10L. I have. Thus, diodes D1a, D1b, D3a, D3b, D2, D4, and Zener diodes are formed on the surface and thickness direction of the Si substrate 10.
  • An Al electrode 10B and Al pads (hereinafter referred to as pads) P1 and P2 are provided on the surface layer of the Si substrate 10, and these elements form the circuit shown in FIG.
  • the diodes D1a and D1b are represented as one diode D1
  • the diodes D3a and D3b are represented as one diode D3.
  • the formed diodes D1, D2 are aligned in the forward direction and connected in series, and the diodes D3, D4 are aligned in the forward direction and connected in series.
  • the diodes D1 and D2 and the diodes D3 and D4 connected in series are aligned in the forward direction and connected in parallel to the Zener diode Dz.
  • a Zener diode Dz is interposed between the formation positions of the diodes D1 and D4 and between the formation positions of the diodes D2 and D3.
  • a connection point between the formed diodes D1a and D1b and the diode D2 serves as a first input / output terminal of the ESD protection circuit 10A and is connected to a pad P1 formed on the Si substrate 10.
  • a connection point between the formed diodes D3a and D3b and the diode D4 serves as a second input / output terminal of the ESD protection circuit 10A and is connected to an Al pad (hereinafter referred to as a pad) P2 formed on the Si substrate 10. is doing.
  • the pads P1 and P2 correspond to the metal film according to the present invention.
  • the rewiring layer 20 formed on the surface layer of the Si substrate 10 is SiN (or SiO 2 ) formed on the surface (functional element formation surface) of the Si substrate 10 so as to cover a part of the peripheral portion of the pads P1 and P2.
  • the protective film 21 and the resin layer 22 covering the SiN protective film 21 and the pads P1 and P2 are included.
  • the SiN protective film 21 is formed by sputtering, and the resin layer 22 is formed by spin coating of an epoxy (or polyimide) solder girest.
  • openings (contact holes) 22A and 22B for exposing parts of the pads P1 and P2 are formed.
  • Ti / Cu / Ti electrodes 21A and 21B are formed in the openings 22A and 22B and the peripheral regions of the openings 22A and 22B.
  • FIG. 1 only the Ti / Cu / Ti electrode 21B is illustrated, but the Ti / Cu / Ti electrode 21B is formed by laminating a Ti electrode 211, a Cu electrode 212, and a Ti electrode 213 in order from the resin layer 22 side.
  • the Ti / Cu / Ti electrode 21A has the same structure.
  • Ti / Cu / Ti electrodes 21 ⁇ / b> A and 21 ⁇ / b> B have a planar portion facing the surface of Si substrate 10, and are electrically connected to pads P ⁇ b> 1 and P ⁇ b> 2 through the opening of resin layer 22.
  • the Ti / Cu / Ti electrodes 21 ⁇ / b> A and 21 ⁇ / b> B are current paths for surge current (ESD current) of the ESD protection device 1.
  • External electrodes 23A and 23B are formed on part of the planar portions of the Ti / Cu / Ti electrodes 21A and 21B. Although only the external electrode 23B is shown in FIG. 1, the external electrode 23B has a Ni electrode 231 formed on the Ti / Cu / Ti electrode 21B side, and an Au electrode 232 formed on the surface of the Ni electrode 231. Yes.
  • the external electrode 23A has a similar structure. The portions of the Ti / Cu / Ti electrodes 21A and 21B where the external electrodes 23A and 23B are formed are such that the Ti electrode 213 is etched and the Cu electrode 212 is exposed, and the external electrodes 23A and 23B are exposed Cu electrodes 212. Part is selectively plated.
  • the external electrodes 23A and 23B are electrodes for input / output terminals of the ESD protection device 1.
  • the rewiring layer 20 includes a resin layer 26 further formed on the resin layer 22.
  • the resin layer 26 is, for example, a low dielectric constant epoxy resin (or polyimide resin, liquid crystal polymer, or the like) layer. Since the Ti / Cu / Ti electrodes 21A and 21B have the Ti electrode 213 on the surface layer, the bonding strength between the Ti / Cu / Ti electrodes 21A and 21B and the resin layer 26 is high. Openings (via holes) 26 ⁇ / b> A and 26 ⁇ / b> B are formed in the resin layer 26. The openings 26A and 26B expose part of the external electrodes 23A and 23B. In the figure showing the resin layer 26 in FIG.
  • the external electrodes 23A and 23B are indicated by broken lines, and the relationship with the openings 26A and 26B is shown. As shown, the peripheral portions of the external electrodes 23A and 23B are covered with the resin layer 26, and the inner sides of the peripheral portions are exposed from the openings 26A and 26B.
  • the distance from the openings 26A and 26B of the resin layer 26 to the joints of the Ti / Cu / Ti electrodes 21A and 21B and the external electrodes 23A and 23B is increased. . For this reason, impurities such as moisture that have entered from the openings 26A and 26B are unlikely to enter the joint portions, and corrosion of the exposed Cu portions of the Ti / Cu / Ti electrodes 21A and 21B can be prevented.
  • the ESD protection device 1 when the ESD protection device 1 is soldered and mounted on a substrate, a load is generated on the external electrodes 23A and 23B due to a deflection of the substrate to be mounted or an impact on the substrate, and the external electrodes 23A and 23B are caused by the load. There is a possibility that the edge portion of 23B is turned over. Therefore, by covering the peripheral portions of the external electrodes 23A and 23B with the resin layer 26, the edge portions of the external electrodes 23A and 23B can be prevented from being turned over, and the intrusion of impurities can be further avoided. Even if a gap is formed at the interface due to the difference in thermal expansion coefficient between the external electrodes 23A and 23B and the resin layer 26, the peripheral edges of the external electrodes 23A and 23B are covered with the resin layer. Intrusion can be avoided.
  • the Zener diode Dz or the like is formed on the Si substrate 10 to configure the ESD protection circuit 10A.
  • a variable capacitance element or the like is formed on the Si substrate 10 and used. May be configured.
  • FIGS 6A and 6B are diagrams showing connection examples of the ESD protection device 1 according to the present embodiment.
  • the ESD protection device 1 is mounted on an electronic device. Examples of electronic devices include notebook PCs, tablet terminal devices, mobile phones, digital cameras, DVC (Digital Video Cassette), and portable music players.
  • electronic devices include notebook PCs, tablet terminal devices, mobile phones, digital cameras, DVC (Digital Video Cassette), and portable music players.
  • FIG. 6A shows an example in which the ESD protection device 1 is connected between the signal line connecting the I / O port 100 and the IC 101 to be protected and GND.
  • the I / O port 100 is a port to which an antenna is connected, for example.
  • the ESD protection device 1 according to the present embodiment is a bidirectional type, and either the first input / output terminal or the second input / output terminal may be on the input side. For example, when the first input / output terminal is the input side, the first input / output terminal is connected to the signal line, and the second input / output terminal is connected to the GND.
  • the surge current is discharged from the ESD protection device 1 to the ground.
  • the ESD protection device 1 prevents corrosion of exposed Cu. If Cu corrodes due to the intrusion of impurities, the resistance value of the current path of the ESD protection device 1 indicated by the broken line in FIG. 6A increases. In this case, the surge current is not discharged to the ground by this resistance, and the ESD protection device 1 does not function normally. In this embodiment, since corrosion of Cu is prevented, an increase in the resistance value indicated by the broken line in FIG. 6A can be prevented, and the ESD protection device 1 can function normally by lowering the clamp voltage at the time of occurrence of ESD. Can do.
  • FIG. 6B shows an example in which the ESD protection device 1 is connected between the signal line connecting the connector 102 and the IC 101 and the GND line.
  • the signal line in this example is, for example, a high-speed transmission line (differential transmission line), and the ESD protection device 1 is connected between each of the plurality of signal lines and the GND line.
  • the ESD protection device 1 uses the external electrodes 23A and 23B as the first input / output terminal and the second input / output terminal, and is connected between the signal line and the GND line.
  • This signal line is a line connected to an input / output terminal of an IC (not shown) to be protected from electrostatic discharge voltage.
  • the ESD protection device according to this embodiment is a bidirectional type, and either the first input / output terminal or the second input / output terminal may be on the input side. For example, when the first input / output terminal is the input side, the first input / output terminal is connected to the signal line, and the second input / output terminal is connected to the GND line.
  • FIG. 7 is a diagram for explaining a case where a current flows from the pad P1 connected to the first input / output terminal (external electrode 23A) to the pad P2 connected to the second input / output terminal (external electrode 23B).
  • a surge voltage exceeding the Zener voltage of the Zener diode Dz is applied, the surge current that has entered from the first input terminal is routed from the pad P1 to the diode D1, the Zener diode Dz, and the diode D4, as indicated by the broken line in the figure. And discharged from the pad P2 to the ground.
  • FIG. 8 is a diagram for explaining a case where a current flows from the pad P2 connected to the second input / output terminal (external electrode 23B) to the pad P1 connected to the first input / output terminal (external electrode 23A).
  • the surge current that has entered from the second input terminal flows from the pad P2 through the diode D3, the Zener diode Dz, and the diode D2, and is discharged from the pad P1 to the ground.
  • FIG. 9 is a diagram illustrating a manufacturing process of the ESD protection device 1.
  • the ESD protection device 1 is manufactured by the following process.
  • pads P1 and P2 that are electrically connected to the ESD protection circuit 10A are formed on the Si substrate 10 on which the ESD protection circuit 10A is formed by photolithography. Further, the SiN protective film 21 is sputtered on the substrate surface, and openings H1 and H2 are formed by etching.
  • the parasitic capacitance formed between the pads P1 and P2 and the opposing substrate can be reduced by reducing their area.
  • By reducing the parasitic capacitance it is possible to suppress an impedance shift, and as a result, it is possible to reduce the loss of the high-frequency signal in the signal line.
  • the resin layer 22 is formed on the Si substrate 10 by spin coating with an epoxy solder girest, and then the openings 22A and 22B are formed.
  • a Ti electrode 211, a Cu electrode 212, and a Ti electrode 213 are formed on the surface of the resin layer 22 by sputtering at a thickness of about 0.1 ⁇ m / 1.0 ⁇ m / 0.1 ⁇ m. After that, wet etching is performed to form the electrodes 21A and 21B.
  • a part of the surface of the Ti / Cu / Ti electrodes 21A and 21B is etched to expose Cu, and the exposed Cu portion is exposed to Au on the surface of the Ni electrode 231 as described in FIG.
  • the Au / Ni external electrodes 23A and 23B formed by the electrode 232 are formed by electrolytic plating (electroplating) with a thickness of about 0.1 ⁇ m / 3.0 ⁇ m.
  • the external electrodes 23A and 23B are selectively plated only on the exposed Cu surface. By forming the external electrodes 23A and 23B by selective plating, a resist film is not formed, and masking is not required, so that manufacturing is facilitated.
  • the resin layer 26 is formed on the surface of the resin layer 22 by spin coating with epoxy solder girest. Openings 26A and 26B are formed in the resin layer 26. At this time, the peripheral portions of the external electrodes 23A and 23B are covered with the resin layer 26, and the inner sides of the peripheral portions are exposed from the openings 26A and 26B.
  • the external electrodes 23A and 23B by electrolytic plating and then forming the resin layer 26, it is possible to avoid the possibility that the plating solution remains and the Ti / Cu / Ti electrodes 21A and 21B are corroded. By avoiding the corrosion, it is possible to prevent an increase in the resistance value of the Ti / Cu / Ti electrodes 21A and 21B that become a path of the surge current of the device 1 by ESD protection.
  • FIG. 10A, 10B, and 10C are diagrams showing another example of the openings 26A and 26B that expose part of the external electrodes 23A and 23B.
  • the corners of the openings 26A and 26B may be curved to protect the portions (corners) where cracks are likely to occur.
  • FIG. 10B only the opening 26A may have a shape in which the central portion protrudes inward. In this case, for example, by making the openings 26A and 26B have different shapes, the direction of the ESD protection element 1 can be easily recognized. Further, as shown in FIG.
  • each of the openings 26A and 26B may be divided (subdivided) into two.
  • the ESD protection element 1 may be mounted with an inclination due to the difference in the amount of solder when the ESD protection element 1 is mounted, but the inclination can be suppressed by subdividing the openings 26A and 26B.

Abstract

An electrostatic discharge (ESD) protection device (1) is provided with: an Si substrate (10) having, formed therein, an ESD protection circuit (10A); pads (P1, P2) which are formed on the Si substrate (10), and which serve as input and output terminals of the ESD protection circuit (10A); a resin layer (22) formed on the Si substrate (10); Ti/Cu/Ti electrodes (21A, 21B) which are formed on the resin layer (22), and which are electrically connected to the pads (P1, P2); external electrodes (23A, 23B) which are formed on portions of the Ti/Cu/Ti electrodes (21A, 21B); and a resin layer (26) having, formed therein, openings (26A, 26B) for exposing portions of the external electrodes (23A, 23B), said portions being located further inwards than peripheral edge portions thereof in a planar view. Accordingly, provided is a semiconductor device with which an increase in the resistance values of wiring electrodes caused by oxidation or corrosion of the wiring electrodes is avoided.

Description

半導体装置Semiconductor device
　本発明は、機能素子が形成された半導体基板上に再配線層を備える半導体装置に関する。 The present invention relates to a semiconductor device including a rewiring layer on a semiconductor substrate on which a functional element is formed.
　半導体装置の一つとしてＥＳＤ（Electro-Static-Discharge）保護デバイスがある。ＥＳＤ保護デバイスは半導体ＩＣ等を静電気放電などのサージから保護する。移動体通信端末、デジタルカメラ、ノート型ＰＣをはじめとする各種電子機器には、ロジック回路又はメモリー回路等を構成する半導体集積回路が備えられている。このような半導体集積回路は、半導体基板上に形成された微細配線パターンで構成された低電圧駆動回路であるため、一般に、静電気放電などによるサージに対しては脆弱である。そこで、このような半導体集積回路をサージから保護するため、ＥＳＤ保護デバイスが用いられる。 One of the semiconductor devices is an ESD (Electro-Static-Discharge) protection device. The ESD protection device protects semiconductor ICs and the like from surges such as electrostatic discharge. Various electronic devices such as a mobile communication terminal, a digital camera, and a notebook PC are provided with a semiconductor integrated circuit constituting a logic circuit or a memory circuit. Such a semiconductor integrated circuit is a low-voltage driving circuit composed of a fine wiring pattern formed on a semiconductor substrate, and is generally vulnerable to a surge caused by electrostatic discharge or the like. Therefore, an ESD protection device is used to protect such a semiconductor integrated circuit from a surge.
　特許文献１には、ＥＳＤ保護回路が構成されたＳｉ基板の表面に、エポキシ樹脂を含む再配線層が形成されたＥＳＤ保護デバイスが開示されている。再配線層の樹脂層には、Ｓｉ基板と導通する配線電極が形成されている。この特許文献１は、ＣＳＰ（Chip Size Package）タイプのデバイスであり小型化を実現している。 Patent Document 1 discloses an ESD protection device in which a rewiring layer containing an epoxy resin is formed on the surface of a Si substrate on which an ESD protection circuit is configured. A wiring electrode that is electrically connected to the Si substrate is formed on the resin layer of the rewiring layer. This Patent Document 1 is a CSP (Chip Size Package) type device, which realizes miniaturization.
国際公開２０１２/０２３３９４号パンフレットInternational Publication 2012/023394 Pamphlet
　しかしながら、特許文献１において、製造時に、再配線層における配線電極と樹脂層との間に隙間が生じる場合があり、その隙間から水分などの不純物が侵入し、配線電極が酸化又は腐食するおそれがある。この場合、その腐食により、配線電極の抵抗値が大きくなり、静電気放電時のクランプ電圧を低くできないといった問題がある。 However, in Patent Document 1, there may be a gap between the wiring electrode and the resin layer in the rewiring layer during manufacturing, and impurities such as moisture may enter from the gap, and the wiring electrode may be oxidized or corroded. is there. In this case, there is a problem that the resistance value of the wiring electrode increases due to the corrosion, and the clamp voltage during electrostatic discharge cannot be lowered.
　そこで、本発明の目的は、配線電極の酸化又は腐食による配線電極の抵抗値増大を回避した半導体装置を提供することにある。 Therefore, an object of the present invention is to provide a semiconductor device that avoids an increase in resistance value of the wiring electrode due to oxidation or corrosion of the wiring electrode.
　本発明に係る半導体装置は、機能素子が形成された半導体基板と、前記半導体基板の前記機能素子形成面に形成され、前記機能素子と接続された金属膜と、前記半導体基板の前記機能素子形成面に形成された絶縁層と、前記半導体基板の前記機能素子形成面に対向するように前記絶縁層に形成され、前記金属膜に導通する配線電極と、前記配線電極上の一部に形成された外部電極と、平面視で前記外部電極の周縁部より内側の一部を露出させる開口が形成され、前記絶縁層に形成された絶縁樹脂層と、を備えることを特徴とする。 The semiconductor device according to the present invention includes a semiconductor substrate on which a functional element is formed, a metal film formed on the functional element formation surface of the semiconductor substrate and connected to the functional element, and the functional element formation on the semiconductor substrate. An insulating layer formed on the surface; a wiring electrode formed on the insulating layer so as to oppose the functional element formation surface of the semiconductor substrate; and a conductive electrode connected to the metal film; and formed on a part of the wiring electrode. And an insulating resin layer formed on the insulating layer. The opening is formed so as to expose a part of the inner side of the outer electrode in a plan view.
　この構成では、少なくとも外部電極周縁部と樹脂層との間に隙間が生じない。仮に外部電極の側面に隙間が形成されていても、外部電極周縁部に樹脂層（レジスト）が形成されることで、隙間から水分などの不純物が侵入して、電極が酸化又は腐食するといった不具合を防止できる。この結果、配線電極の抵抗値の増加を防止できるため、配線電極での損失の増大が回避できる。また、例えば基板上に半導体装置をはんだ付け実装する際、基板のたわみ、または基板への衝撃などにより、外部電極へ負荷が生じ、その負荷によって、外部電極のエッジ部がめくれるおそれがあるが、配線電極の周縁部を樹脂層で覆うことで、そのめくれを防止でき、外部電極と樹脂層との間に隙間が生じることをさらに回避できる。 In this configuration, there is no gap at least between the peripheral edge of the external electrode and the resin layer. Even if a gap is formed on the side surface of the external electrode, the resin layer (resist) is formed on the peripheral edge of the external electrode, so that impurities such as moisture enter from the gap and the electrode is oxidized or corroded. Can be prevented. As a result, an increase in the resistance value of the wiring electrode can be prevented, and an increase in loss at the wiring electrode can be avoided. In addition, when soldering and mounting a semiconductor device on a substrate, for example, a load is generated on the external electrode due to the deflection of the substrate or an impact on the substrate, and the edge portion of the external electrode may be turned by the load. By covering the peripheral edge portion of the wiring electrode with the resin layer, the turning-up can be prevented, and the generation of a gap between the external electrode and the resin layer can be further avoided.
　前記配線電極は、前記外部電極が形成された部分以外の表層にＴｉの膜を有し、主材がＣｕであり、前記外部電極は、前記配線電極に対してめっき形成された膜である構成が好ましい。 The wiring electrode has a Ti film on a surface layer other than a portion where the external electrode is formed, a main material is Cu, and the external electrode is a film formed by plating the wiring electrode Is preferred.
　この構成では、Ｔｉの膜を形成することによって絶縁樹脂層と配線電極との接合強度が高まる。また、外部電極が形成された部分以外の表層にＴｉの膜を有することによってレジスト膜を形成することなく外部電極を選択的めっきできるので、製造が容易となる。 In this configuration, the bonding strength between the insulating resin layer and the wiring electrode is increased by forming the Ti film. Moreover, since the external electrode can be selectively plated without forming a resist film by having a Ti film on the surface layer other than the portion where the external electrode is formed, the manufacture is facilitated.
　前記機能素子はＥＳＤ保護回路であり、前記配線電極はＥＳＤ電流の電流路であることが好ましい。 It is preferable that the functional element is an ESD protection circuit and the wiring electrode is an ESD current path.
　この構成では、ＥＳＤ電流の電流路である配線電極の抵抗値の増加を防ぐことができるので、静電気放電時のクランプ電圧を低くできる。 In this configuration, it is possible to prevent an increase in the resistance value of the wiring electrode, which is the current path of the ESD current, so that the clamp voltage during electrostatic discharge can be lowered.
　本発明によれば、外部電極と樹脂層との間に隙間が生じないので、その隙間に水分などの不純物が侵入して、電極が酸化又は腐食するといった不具合を防止できる。この結果、配線電極の抵抗値の増加を防止できるため、配線電極での損失の増大が回避できる。 According to the present invention, since no gap is formed between the external electrode and the resin layer, it is possible to prevent a problem such that an impurity such as moisture enters the gap and the electrode is oxidized or corroded. As a result, an increase in the resistance value of the wiring electrode can be prevented, and an increase in loss at the wiring electrode can be avoided.
実施形態に係るＥＳＤ保護デバイスの正面断面図Front sectional view of an ESD protection device according to an embodiment ＥＳＤ保護デバイスの各層の平面図Plan view of each layer of ESD protection device Ｓｉ基板に形成されたＥＳＤ保護回路の平面構成を示す図The figure which shows the planar structure of the ESD protection circuit formed in Si substrate ＥＳＤ保護回路の回路図Circuit diagram of ESD protection circuit 実施形態に係るＥＳＤ保護デバイス１の要部断面図Sectional drawing of the principal part of the ESD protection device 1 which concerns on embodiment 実施形態に係るＥＳＤ保護デバイスの接続例を示す図The figure which shows the example of a connection of the ESD protection device which concerns on embodiment 実施形態に係るＥＳＤ保護デバイスの接続例を示す図The figure which shows the example of a connection of the ESD protection device which concerns on embodiment 実施形態に係るＥＳＤ保護デバイスの動作原理を説明するための図The figure for demonstrating the principle of operation of the ESD protection device which concerns on embodiment 実施形態に係るＥＳＤ保護デバイスの動作原理を説明するための図The figure for demonstrating the principle of operation of the ESD protection device which concerns on embodiment ＥＳＤ保護デバイスの製造工程を示す図Diagram showing manufacturing process of ESD protection device 外部電極の一部を露出させる開口の別の例を示す図The figure which shows another example of the opening which exposes a part of external electrode 外部電極の一部を露出させる開口の別の例を示す図The figure which shows another example of the opening which exposes a part of external electrode 外部電極の一部を露出させる開口の別の例を示す図The figure which shows another example of the opening which exposes a part of external electrode
　以下では、本発明に係る半導体装置についてＥＳＤ保護デバイスを例に挙げて説明する。 Hereinafter, the semiconductor device according to the present invention will be described using an ESD protection device as an example.
　図１は本実施形態に係るＥＳＤ保護デバイス１の正面断面図である。図２はＥＳＤ保護デバイス１の各層の平面図である。ＥＳＤ保護デバイス１は、ＣＳＰタイプのデバイスであり、ダイオードおよびツェナーダイオードを含むＥＳＤ保護回路１０Ａが構成されたＳｉ基板１０に、複数の樹脂層等を含む再配線層２０が形成されている。Ｓｉ基板１０は、本発明に係る半導体基板に相当するが、本発明に係る半導体基板はＳｉ基板には限定されず、ＧａＡｓ基板などであってもよい。 FIG. 1 is a front sectional view of an ESD protection device 1 according to this embodiment. FIG. 2 is a plan view of each layer of the ESD protection device 1. The ESD protection device 1 is a CSP type device, and a rewiring layer 20 including a plurality of resin layers and the like is formed on a Si substrate 10 on which an ESD protection circuit 10A including a diode and a Zener diode is configured. The Si substrate 10 corresponds to the semiconductor substrate according to the present invention, but the semiconductor substrate according to the present invention is not limited to the Si substrate, and may be a GaAs substrate or the like.
　図３はＳｉ基板１０に形成されたＥＳＤ保護回路１０Ａの平面構成を示す図であり、図４はＥＳＤ保護回路１０Ａの回路図である。図５は本実施形態に係るＥＳＤ保護デバイス１の要部断面図である。 3 is a diagram showing a planar configuration of the ESD protection circuit 10A formed on the Si substrate 10, and FIG. 4 is a circuit diagram of the ESD protection circuit 10A. FIG. 5 is a cross-sectional view of a main part of the ESD protection device 1 according to this embodiment.
　このＥＳＤ保護デバイス１は、ｐ＋のＳｉ基板１０の表面に、複数の素子を形成する素子形成層１０Ｌが設けられ、素子形成層１０Ｌの表面から半導体基板１０内部へ素子形成層１０Ｌより深い複数の素子分離領域１１０が形成されている。これらの素子分離領域１１０は、トレンチの内面に酸化Ｓｉ膜（SiOx）が形成され、内部にポリシリコンが充填されたトレンチアイソレーションである。素子分離領域１１０で分離された２つの素子（素子分離領域１１０を挟む２つの素子）は、素子形成層１０Ｌの表面において、半導体基板１０の型（ｐ＋）とは逆型であるｎエピタキシャル層を備えている。これにより、Ｓｉ基板１０の表面及び厚み方向に、ダイオードＤ１ａ，Ｄ１ｂ，Ｄ３ａ，Ｄ３ｂ，Ｄ２，Ｄ４及びツェナーダイオードが形成されている。そして、Ｓｉ基板１０の表層には、Ａｌ電極１０Ｂ、Ａｌパッド（以下、パッドという。）Ｐ１，Ｐ２が設けられ、これら各素子は、図４に示す回路を形成している。なお、図４では、ダイオードＤ１ａ、Ｄ１ｂを一つのダイオードＤ１として表し、ダイオードＤ３ａ，Ｄ３ｂを一つのダイオードＤ３として表している。 In the ESD protection device 1, an element formation layer 10 </ b> L for forming a plurality of elements is provided on the surface of a p + Si substrate 10. An element isolation region 110 is formed. These element isolation regions 110 are trench isolations in which a Si oxide film (SiOx) is formed on the inner surface of a trench and polysilicon is filled therein. Two elements separated by the element isolation region 110 (two elements sandwiching the element isolation region 110) are n epitaxial layers that are opposite to the type (p +) of the semiconductor substrate 10 on the surface of the element formation layer 10L. I have. Thus, diodes D1a, D1b, D3a, D3b, D2, D4, and Zener diodes are formed on the surface and thickness direction of the Si substrate 10. An Al electrode 10B and Al pads (hereinafter referred to as pads) P1 and P2 are provided on the surface layer of the Si substrate 10, and these elements form the circuit shown in FIG. In FIG. 4, the diodes D1a and D1b are represented as one diode D1, and the diodes D3a and D3b are represented as one diode D3.
　形成されたダイオードＤ１，Ｄ２は順方向が揃って直列接続されていて、ダイオードＤ３，Ｄ４は順方向が揃って直列接続されている。また、直列接続したダイオードＤ１，Ｄ２及びダイオードＤ３，Ｄ４それぞれは、順方向が揃ってツェナーダイオードＤｚに対し並列接続されている。さらに、ダイオードＤ１，Ｄ４の形成位置の間及びダイオードＤ２，Ｄ３の形成位置の間に、ツェナーダイオードＤｚが介在している。形成されたダイオードＤ１ａ，Ｄ１ｂとダイオードＤ２との接続点が、ＥＳＤ保護回路１０Ａの第１の入出力端となり、Ｓｉ基板１０に形成されたパッドＰ１に接続している。また、形成されたダイオードＤ３ａ，Ｄ３ｂとダイオードＤ４との接続点が、ＥＳＤ保護回路１０Ａの第２の入出力端となり、Ｓｉ基板１０に形成されたＡｌパッド（以下、パッドという。）Ｐ２に接続している。パッドＰ１，Ｐ２は、本発明に係る金属膜に相当する。 The formed diodes D1, D2 are aligned in the forward direction and connected in series, and the diodes D3, D4 are aligned in the forward direction and connected in series. The diodes D1 and D2 and the diodes D3 and D4 connected in series are aligned in the forward direction and connected in parallel to the Zener diode Dz. Further, a Zener diode Dz is interposed between the formation positions of the diodes D1 and D4 and between the formation positions of the diodes D2 and D3. A connection point between the formed diodes D1a and D1b and the diode D2 serves as a first input / output terminal of the ESD protection circuit 10A and is connected to a pad P1 formed on the Si substrate 10. A connection point between the formed diodes D3a and D3b and the diode D4 serves as a second input / output terminal of the ESD protection circuit 10A and is connected to an Al pad (hereinafter referred to as a pad) P2 formed on the Si substrate 10. is doing. The pads P1 and P2 correspond to the metal film according to the present invention.
　Ｓｉ基板１０の表層に形成された再配線層２０は、パッドＰ１，Ｐ２の周縁部の一部を覆うように、Ｓｉ基板１０の表面（機能素子形成面）に形成されたＳｉＮ（又はＳｉＯ２）保護膜２１と、ＳｉＮ保護膜２１およびパッドＰ１，Ｐ２を覆う樹脂層２２とを含んでいる。ＳｉＮ保護膜２１はスパッタリングにより形成され、樹脂層２２は、エポキシ系（またはポリイミド系）ソルダージレストのスピンコーティングにより形成されている。樹脂層２２には、パッドＰ１，Ｐ２の一部を露出させる開口（コンタクトホール）２２Ａ，２２Ｂ（図２参照）が形成されている。 The rewiring layer 20 formed on the surface layer of the Si substrate 10 is SiN (or SiO 2 ) formed on the surface (functional element formation surface) of the Si substrate 10 so as to cover a part of the peripheral portion of the pads P1 and P2. ) The protective film 21 and the resin layer 22 covering the SiN protective film 21 and the pads P1 and P2 are included. The SiN protective film 21 is formed by sputtering, and the resin layer 22 is formed by spin coating of an epoxy (or polyimide) solder girest. In the resin layer 22, openings (contact holes) 22A and 22B (see FIG. 2) for exposing parts of the pads P1 and P2 are formed.
　この開口２２Ａ，２２Ｂおよびこの開口２２Ａ，２２Ｂの周辺領域には、Ｔｉ／Ｃｕ／Ｔｉ電極２１Ａ，２１Ｂが形成されている。図１では、Ｔｉ／Ｃｕ／Ｔｉ電極２１Ｂについてのみ図示しているが、Ｔｉ／Ｃｕ／Ｔｉ電極２１Ｂは、樹脂層２２側から順にＴｉ電極２１１、Ｃｕ電極２１２、Ｔｉ電極２１３が積層されて形成されている。なお、Ｔｉ／Ｃｕ／Ｔｉ電極２１Ａも同様の構造である。Ｔｉ／Ｃｕ／Ｔｉ電極２１Ａ，２１Ｂは、Ｓｉ基板１０の表面に対向する平面部分を有し、かつ、樹脂層２２の開口を通じてパッドＰ１，Ｐ２に導通している。Ｔｉ／Ｃｕ／Ｔｉ電極２１Ａ，２１Ｂは、ＥＳＤ保護デバイス１のサージ電流（ＥＳＤ電流）の電流経路である。 Ti / Cu / Ti electrodes 21A and 21B are formed in the openings 22A and 22B and the peripheral regions of the openings 22A and 22B. In FIG. 1, only the Ti / Cu / Ti electrode 21B is illustrated, but the Ti / Cu / Ti electrode 21B is formed by laminating a Ti electrode 211, a Cu electrode 212, and a Ti electrode 213 in order from the resin layer 22 side. Has been. The Ti / Cu / Ti electrode 21A has the same structure. Ti / Cu / Ti electrodes 21 </ b> A and 21 </ b> B have a planar portion facing the surface of Si substrate 10, and are electrically connected to pads P <b> 1 and P <b> 2 through the opening of resin layer 22. The Ti / Cu / Ti electrodes 21 </ b> A and 21 </ b> B are current paths for surge current (ESD current) of the ESD protection device 1.
　Ｔｉ／Ｃｕ／Ｔｉ電極２１Ａ，２１Ｂの平面部分の一部には、外部電極２３Ａ，２３Ｂが形成されている。図１では、外部電極２３Ｂについてのみ図示しているが、外部電極２３Ｂは、Ｔｉ／Ｃｕ／Ｔｉ電極２１Ｂ側にＮｉ電極２３１が形成され、そのＮｉ電極２３１の表面にＡｕ電極２３２が形成されている。外部電極２３Ａも同様の構造である。外部電極２３Ａ，２３Ｂが形成されるＴｉ／Ｃｕ／Ｔｉ電極２１Ａ，２１Ｂの部分は、Ｔｉ電極２１３がエッチングされてＣｕ電極２１２が露出されていて、外部電極２３Ａ，２３Ｂは、露出したＣｕ電極２１２部分に選択的めっきされている。この外部電極２３Ａ，２３Ｂは、ＥＳＤ保護デバイス１の入出力端子用の電極である。 External electrodes 23A and 23B are formed on part of the planar portions of the Ti / Cu / Ti electrodes 21A and 21B. Although only the external electrode 23B is shown in FIG. 1, the external electrode 23B has a Ni electrode 231 formed on the Ti / Cu / Ti electrode 21B side, and an Au electrode 232 formed on the surface of the Ni electrode 231. Yes. The external electrode 23A has a similar structure. The portions of the Ti / Cu / Ti electrodes 21A and 21B where the external electrodes 23A and 23B are formed are such that the Ti electrode 213 is etched and the Cu electrode 212 is exposed, and the external electrodes 23A and 23B are exposed Cu electrodes 212. Part is selectively plated. The external electrodes 23A and 23B are electrodes for input / output terminals of the ESD protection device 1.
　再配線層２０は、樹脂層２２にさらに形成された樹脂層２６を含んでいる。樹脂層２６は、例えば低誘電率のエポキシ樹脂（または、ポリイミド樹脂、液晶ポリマー等）の層である。なお、Ｔｉ／Ｃｕ／Ｔｉ電極２１Ａ，２１Ｂは表層にＴｉ電極２１３を有しているため、Ｔｉ／Ｃｕ／Ｔｉ電極２１Ａ，２１Ｂと樹脂層２６との接合強度は高い。この樹脂層２６には、開口（ビアホール）２６Ａ，２６Ｂが形成されている。開口２６Ａ，２６Ｂは外部電極２３Ａ，２３Ｂの一部を露出させている。図２の樹脂層２６を表す図では、外部電極２３Ａ，２３Ｂを破線で示し、開口２６Ａ，２６Ｂとの関係を示している。これに示すように、外部電極２３Ａ，２３Ｂの周縁部は樹脂層２６に覆われていて、その周縁部より内側が開口２６Ａ，２６Ｂから露出している。 The rewiring layer 20 includes a resin layer 26 further formed on the resin layer 22. The resin layer 26 is, for example, a low dielectric constant epoxy resin (or polyimide resin, liquid crystal polymer, or the like) layer. Since the Ti / Cu / Ti electrodes 21A and 21B have the Ti electrode 213 on the surface layer, the bonding strength between the Ti / Cu / Ti electrodes 21A and 21B and the resin layer 26 is high. Openings (via holes) 26 </ b> A and 26 </ b> B are formed in the resin layer 26. The openings 26A and 26B expose part of the external electrodes 23A and 23B. In the figure showing the resin layer 26 in FIG. 2, the external electrodes 23A and 23B are indicated by broken lines, and the relationship with the openings 26A and 26B is shown. As shown, the peripheral portions of the external electrodes 23A and 23B are covered with the resin layer 26, and the inner sides of the peripheral portions are exposed from the openings 26A and 26B.
　外部電極２３Ａ，２３Ｂの周縁部を樹脂層２６で覆うことにより、樹脂層２６の開口２６Ａ，２６ＢからＴｉ／Ｃｕ／Ｔｉ電極２１Ａ，２１Ｂおよび外部電極２３Ａ，２３Ｂの接合部までの距離が長くなる。このため、開口２６Ａ，２６Ｂから侵入した水分等の不純物は、その接合部分まで侵入しにくく、Ｔｉ／Ｃｕ／Ｔｉ電極２１Ａ，２１Ｂの露出したＣｕ部分の腐食を防止できる。 By covering the peripheral portions of the external electrodes 23A and 23B with the resin layer 26, the distance from the openings 26A and 26B of the resin layer 26 to the joints of the Ti / Cu / Ti electrodes 21A and 21B and the external electrodes 23A and 23B is increased. . For this reason, impurities such as moisture that have entered from the openings 26A and 26B are unlikely to enter the joint portions, and corrosion of the exposed Cu portions of the Ti / Cu / Ti electrodes 21A and 21B can be prevented.
　また、例えば基板上にＥＳＤ保護デバイス１をはんだ付け実装する際、実装する基板のたわみ、またはその基板への衝撃などにより、外部電極２３Ａ，２３Ｂへ負荷が生じ、その負荷によって、外部電極２３Ａ，２３Ｂのエッジ部がめくれるおそれがある。そこで、外部電極２３Ａ，２３Ｂの周縁部を樹脂層２６で覆うことにより、外部電極２３Ａ，２３Ｂのエッジ部のめくれを防止でき、不純物の侵入をさらに回避できる。また、外部電極２３Ａ，２３Ｂと樹脂層２６との熱膨張係数の違いによって界面に隙間が出来たとしても外部電極２３Ａ，２３Ｂの周縁部が樹脂層で覆われているため、水分などの不純物の浸入を回避することが出来る。 Further, for example, when the ESD protection device 1 is soldered and mounted on a substrate, a load is generated on the external electrodes 23A and 23B due to a deflection of the substrate to be mounted or an impact on the substrate, and the external electrodes 23A and 23B are caused by the load. There is a possibility that the edge portion of 23B is turned over. Therefore, by covering the peripheral portions of the external electrodes 23A and 23B with the resin layer 26, the edge portions of the external electrodes 23A and 23B can be prevented from being turned over, and the intrusion of impurities can be further avoided. Even if a gap is formed at the interface due to the difference in thermal expansion coefficient between the external electrodes 23A and 23B and the resin layer 26, the peripheral edges of the external electrodes 23A and 23B are covered with the resin layer. Intrusion can be avoided.
　なお、本実施形態では、Ｓｉ基板１０にツェナーダイオードＤｚなど形成して、ＥＳＤ保護回路１０Ａを構成した例を示したが、例えば、可変容量素子等をＳｉ基板１０に形成して、それを用いた回路を構成してもよい。 In the present embodiment, an example is shown in which the Zener diode Dz or the like is formed on the Si substrate 10 to configure the ESD protection circuit 10A. For example, a variable capacitance element or the like is formed on the Si substrate 10 and used. May be configured.
　以下に、本実施形態に係るＥＳＤ保護デバイスの接続例及び動作原理を説明する。 Hereinafter, a connection example and an operation principle of the ESD protection device according to this embodiment will be described.
　図６Ａ及び図６Ｂは、本実施形態に係るＥＳＤ保護デバイス１の接続例を示す図である。ＥＳＤ保護デバイス１は電子機器に搭載される。電子機器の例として、ノートＰＣ、タブレット型端末装置、携帯電話機、デジタルカメラ、ＤＶＣ（Digital Video Cassette）、携帯型音楽プレーヤなどが挙げられる。 6A and 6B are diagrams showing connection examples of the ESD protection device 1 according to the present embodiment. The ESD protection device 1 is mounted on an electronic device. Examples of electronic devices include notebook PCs, tablet terminal devices, mobile phones, digital cameras, DVC (Digital Video Cassette), and portable music players.
　図６Ａでは、Ｉ／Ｏポート１００と保護すべきＩＣ１０１とを接続する信号ラインと、ＧＮＤとの間にＥＳＤ保護デバイス１を接続した例を示す。Ｉ／Ｏポート１００は、例えばアンテナが接続されるポートである。本実施形態に係るＥＳＤ保護デバイス１は双方向型であって、第１入出力端及び第２入出力端の何れが入力側であってもよい。例えば第１入出力端を入力側とした場合、信号ラインに第１入出力端が接続され、第２入出力端がＧＮＤに接続される。 FIG. 6A shows an example in which the ESD protection device 1 is connected between the signal line connecting the I / O port 100 and the IC 101 to be protected and GND. The I / O port 100 is a port to which an antenna is connected, for example. The ESD protection device 1 according to the present embodiment is a bidirectional type, and either the first input / output terminal or the second input / output terminal may be on the input side. For example, when the first input / output terminal is the input side, the first input / output terminal is connected to the signal line, and the second input / output terminal is connected to the GND.
　ＥＳＤ保護デバイス１ツェナーダイオードＤｚのツェナー電圧を超えるサージ電圧が信号ラインから印加されると、サージ電流はＥＳＤ保護デバイス１からグランドへ放電される。ＥＳＤ保護デバイス１は、前記の通り、露出したＣｕの腐食を防止している。仮に不純物の侵入によりＣｕが腐食した場合、図６Ａの破線で示す、ＥＳＤ保護デバイス１の電流経路の抵抗値が増大する。この場合、この抵抗によりサージ電流がグランドへ放電されなくなり、ＥＳＤ保護デバイス１は正常に機能しなくなる。本実施形態では、Ｃｕの腐食を防止しているため、図６Ａの破線で示す抵抗値の増大を防止でき、ＥＳＤ発生時のクランプ電圧を低くして、ＥＳＤ保護デバイス１を正常に機能させることができる。 When the surge voltage exceeding the Zener voltage of the ESD protection device 1 Zener diode Dz is applied from the signal line, the surge current is discharged from the ESD protection device 1 to the ground. As described above, the ESD protection device 1 prevents corrosion of exposed Cu. If Cu corrodes due to the intrusion of impurities, the resistance value of the current path of the ESD protection device 1 indicated by the broken line in FIG. 6A increases. In this case, the surge current is not discharged to the ground by this resistance, and the ESD protection device 1 does not function normally. In this embodiment, since corrosion of Cu is prevented, an increase in the resistance value indicated by the broken line in FIG. 6A can be prevented, and the ESD protection device 1 can function normally by lowering the clamp voltage at the time of occurrence of ESD. Can do.
　図６Ｂでは、コネクタ１０２とＩＣ１０１とを接続する信号ラインと、ＧＮＤラインとの間にＥＳＤ保護デバイス１を接続した例を示す。この例の信号ラインは、例えば、高速伝送線路（差動伝送線路）であって、複数の信号ラインそれぞれと、ＧＮＤラインとの間にＥＳＤ保護デバイス１が接続されている。 FIG. 6B shows an example in which the ESD protection device 1 is connected between the signal line connecting the connector 102 and the IC 101 and the GND line. The signal line in this example is, for example, a high-speed transmission line (differential transmission line), and the ESD protection device 1 is connected between each of the plurality of signal lines and the GND line.
　図７及び図８は、本実施形態に係るＥＳＤ保護デバイス１の動作原理を説明するための図である。ＥＳＤ保護デバイス１は、外部電極２３Ａ，２３Ｂを第１入出力端及び第２入出力端とし、信号ラインとＧＮＤラインとの間に接続される。この信号ラインは、静電気放電の電圧から保護すべきＩＣ（不図示）の入出力端子に繋がるラインである。本実施形態に係るＥＳＤ保護デバイスは双方向型であって、第１入出力端及び第２入出力端の何れが入力側であってもよい。例えば第１入出力端を入力側とした場合、信号ラインに第１入出力端が接続され、第２入出力端がＧＮＤラインに接続される。 7 and 8 are diagrams for explaining the operating principle of the ESD protection device 1 according to the present embodiment. The ESD protection device 1 uses the external electrodes 23A and 23B as the first input / output terminal and the second input / output terminal, and is connected between the signal line and the GND line. This signal line is a line connected to an input / output terminal of an IC (not shown) to be protected from electrostatic discharge voltage. The ESD protection device according to this embodiment is a bidirectional type, and either the first input / output terminal or the second input / output terminal may be on the input side. For example, when the first input / output terminal is the input side, the first input / output terminal is connected to the signal line, and the second input / output terminal is connected to the GND line.
　図７は、第１入出力端（外部電極２３Ａ）に繋がるパッドＰ１から、第２入出力端（外部電極２３Ｂ）に繋がるパッドＰ２へ電流が流れる場合を説明するための図である。ツェナーダイオードＤｚのツェナー電圧を超えるサージ電圧が印加されると、図中破線で示すように、第１入力端から入ってきたサージ電流は、パッドＰ１からダイオードＤ１、ツェナーダイオードＤｚ及びダイオードＤ４の経路を流れ、パッドＰ２からグランドへ放電される。 FIG. 7 is a diagram for explaining a case where a current flows from the pad P1 connected to the first input / output terminal (external electrode 23A) to the pad P2 connected to the second input / output terminal (external electrode 23B). When a surge voltage exceeding the Zener voltage of the Zener diode Dz is applied, the surge current that has entered from the first input terminal is routed from the pad P1 to the diode D1, the Zener diode Dz, and the diode D4, as indicated by the broken line in the figure. And discharged from the pad P2 to the ground.
　図８は、第２入出力端（外部電極２３Ｂ）に繋がるパッドＰ２から、第１入出力端（外部電極２３Ａ）に繋がるパッドＰ１へ電流が流れる場合を説明するための図である。この場合、図中破線で示すように、第２入力端から入ってきたサージ電流は、パッドＰ２からダイオードＤ３、ツェナーダイオードＤｚ及びダイオードＤ２の経路を流れ、パッドＰ１からグランドへ放電される。 FIG. 8 is a diagram for explaining a case where a current flows from the pad P2 connected to the second input / output terminal (external electrode 23B) to the pad P1 connected to the first input / output terminal (external electrode 23A). In this case, as indicated by a broken line in the figure, the surge current that has entered from the second input terminal flows from the pad P2 through the diode D3, the Zener diode Dz, and the diode D2, and is discharged from the pad P1 to the ground.
　以下に、ＥＳＤ保護デバイス１の製造工程について説明する。図９はＥＳＤ保護デバイス１の製造工程を示す図である。ＥＳＤ保護デバイス１は次の工程で製造される。 Hereinafter, the manufacturing process of the ESD protection device 1 will be described. FIG. 9 is a diagram illustrating a manufacturing process of the ESD protection device 1. The ESD protection device 1 is manufactured by the following process.
（Ａ）まず、ＥＳＤ保護回路１０Ａが形成されたＳｉ基板１０に、ＥＳＤ保護回路１０Ａと導通するパッドＰ１，Ｐ２がフォトリソグラフィにより形成される。また、基板表面にＳｉＮ保護膜２１がスパッタリングされ、エッチングにより開口Ｈ１，Ｈ２が形成される。 (A) First, pads P1 and P2 that are electrically connected to the ESD protection circuit 10A are formed on the Si substrate 10 on which the ESD protection circuit 10A is formed by photolithography. Further, the SiN protective film 21 is sputtered on the substrate surface, and openings H1 and H2 are formed by etching.
　なお、パッドＰ１，Ｐ２は、それらの面積を小さくすることで、対向する基板（ＥＳＤ保護回路１０Ａ）との間に形成される寄生容量を小さくできる。この寄生容量を小さくすることで、インピーダンスのずれを抑制でき、その結果、信号ラインにおける高周波信号の損失を低減できる。 Note that the parasitic capacitance formed between the pads P1 and P2 and the opposing substrate (ESD protection circuit 10A) can be reduced by reducing their area. By reducing the parasitic capacitance, it is possible to suppress an impedance shift, and as a result, it is possible to reduce the loss of the high-frequency signal in the signal line.
（Ｂ）次に、Ｓｉ基板１０にエポキシ系ソルダージレストのスピンコーティングにより、樹脂層２２が形成され、その後、開口２２Ａ，２２Ｂが形成される。 (B) Next, the resin layer 22 is formed on the Si substrate 10 by spin coating with an epoxy solder girest, and then the openings 22A and 22B are formed.
（Ｃ）樹脂層２２の表面に、図１で説明したように、Ｔｉ電極２１１、Ｃｕ電極２１２、Ｔｉ電極２１３が約０．１μｍ／１．０μｍ／０．１μｍの厚みでスパッタリングにより成膜された後、ウエットエッチングされて、電極２１Ａ，２１Ｂが形成される。 (C) As described with reference to FIG. 1, a Ti electrode 211, a Cu electrode 212, and a Ti electrode 213 are formed on the surface of the resin layer 22 by sputtering at a thickness of about 0.1 μm / 1.0 μm / 0.1 μm. After that, wet etching is performed to form the electrodes 21A and 21B.
（Ｄ）Ｔｉ／Ｃｕ／Ｔｉ電極２１Ａ，２１Ｂの表面の一部をエッチングして、Ｃｕを露出させ、その露出したＣｕ部分には、図１で説明したように、Ｎｉ電極２３１の表面にＡｕ電極２３２が形成したＡｕ／Ｎｉの外部電極２３Ａ，２３Ｂが約０．１μｍ／３．０μｍの厚みで電解めっき（電気めっき）により成膜される。この外部電極２３Ａ，２３Ｂは、露出されたＣｕ表面にのみ選択めっきされる。選択めっきにより外部電極２３Ａ，２３Ｂを成膜することで、レジスト膜を形成することなく、また、マスキングを必要としないため、製造が容易となる。 (D) A part of the surface of the Ti / Cu / Ti electrodes 21A and 21B is etched to expose Cu, and the exposed Cu portion is exposed to Au on the surface of the Ni electrode 231 as described in FIG. The Au / Ni external electrodes 23A and 23B formed by the electrode 232 are formed by electrolytic plating (electroplating) with a thickness of about 0.1 μm / 3.0 μm. The external electrodes 23A and 23B are selectively plated only on the exposed Cu surface. By forming the external electrodes 23A and 23B by selective plating, a resist film is not formed, and masking is not required, so that manufacturing is facilitated.
（Ｅ）その後、樹脂層２２の表面に、エポキシ系ソルダージレストのスピンコーティングにより樹脂層２６が形成される。この樹脂層２６には、開口２６Ａ，２６Ｂが形成される。このとき、外部電極２３Ａ，２３Ｂの周縁部は樹脂層２６で覆われ、その周縁部の内側が開口２６Ａ，２６Ｂから露出する。 (E) Thereafter, the resin layer 26 is formed on the surface of the resin layer 22 by spin coating with epoxy solder girest. Openings 26A and 26B are formed in the resin layer 26. At this time, the peripheral portions of the external electrodes 23A and 23B are covered with the resin layer 26, and the inner sides of the peripheral portions are exposed from the openings 26A and 26B.
　このように、電解めっきにより外部電極２３Ａ，２３Ｂを製膜した後に、樹脂層２６を形成することで、めっき液が残り、Ｔｉ／Ｃｕ／Ｔｉ電極２１Ａ，２１Ｂが腐食するおそれを回避できる。腐食を回避することで、ＥＳＤ保護でデバイス１のサージ電流の経路となるＴｉ／Ｃｕ／Ｔｉ電極２１Ａ，２１Ｂの抵抗値の増大を防止できる。 Thus, by forming the external electrodes 23A and 23B by electrolytic plating and then forming the resin layer 26, it is possible to avoid the possibility that the plating solution remains and the Ti / Cu / Ti electrodes 21A and 21B are corroded. By avoiding the corrosion, it is possible to prevent an increase in the resistance value of the Ti / Cu / Ti electrodes 21A and 21B that become a path of the surge current of the device 1 by ESD protection.
　なお、外部電極２３Ａ，２３Ｂの一部を露出させる樹脂層２６に形成された開口２６Ａ，２６Ｂの形状は、適宜変更可能である。図１０Ａ、図１０Ｂ及び図１０Ｃは、外部電極２３Ａ，２３Ｂの一部を露出させる開口２６Ａ，２６Ｂの別の例を示す図である。図１０Ａに示すように、開口２６Ａ，２６Ｂの角部を曲状として、クラックの生じやすい個所（角部）を保護するようにしてもよい。また、図１０Ｂに示すように、開口２６Ａのみ、中央部を内側に突出させた形状としてもよい。この場合、例えば、開口２６Ａ，２６Ｂそれぞれを異なる形状とすることで、ＥＳＤ保護素子１の方向を認識しやすくできる。さらに、図１０Ｃに示すように、開口２６Ａ，２６Ｂそれぞれを二つに分割（細分化）してもよい。この場合、ＥＳＤ保護素子１の実装時におけるはんだ量の違いから、ＥＳＤ保護素子１が傾いて実装される場合があるが、開口２６Ａ，２６Ｂを細分化することで、その傾きを抑制できる。 It should be noted that the shapes of the openings 26A and 26B formed in the resin layer 26 exposing part of the external electrodes 23A and 23B can be changed as appropriate. 10A, 10B, and 10C are diagrams showing another example of the openings 26A and 26B that expose part of the external electrodes 23A and 23B. As shown in FIG. 10A, the corners of the openings 26A and 26B may be curved to protect the portions (corners) where cracks are likely to occur. Further, as shown in FIG. 10B, only the opening 26A may have a shape in which the central portion protrudes inward. In this case, for example, by making the openings 26A and 26B have different shapes, the direction of the ESD protection element 1 can be easily recognized. Further, as shown in FIG. 10C, each of the openings 26A and 26B may be divided (subdivided) into two. In this case, the ESD protection element 1 may be mounted with an inclination due to the difference in the amount of solder when the ESD protection element 1 is mounted, but the inclination can be suppressed by subdividing the openings 26A and 26B.
１－ＥＳＤ保護デバイス
１０－Ｓｉ基板
１０Ａ－ＥＳＤ保護回路
２０－再配線層
２１－ＳｉＮ保護膜
２１Ａ，２１Ｂ－Ｔｉ／Ｃｕ／Ｔｉ電極
２２－樹脂層
２２Ａ，２２Ｂ－開口
２３Ａ，２３Ｂ－外部電極
２６－樹脂層
２６Ａ，２６Ｂ－開口
Ｄ１，Ｄ２，Ｄ３，Ｄ４－ダイオード（機能素子）
Ｄｚ－ツェナーダイオード（機能素子）
Ｐ１，Ｐ２－パッド（金属膜） 1-ESD protection device 10-Si substrate 10A-ESD protection circuit 20-redistribution layer 21- SiN protection film 21A, 21B-Ti / Cu / Ti electrode 22- resin layer 22A, 22B- openings 23A, 23B-external electrode 26 - Resin layers 26A, 26B-Openings D1, D2, D3, D4-diodes (functional elements)
Dz-Zener diode (functional element)
P1, P2-pad (metal film)

Claims (3)

  1. 　機能素子が形成された半導体基板と、
    　前記半導体基板の前記機能素子形成面に形成され、前記機能素子と接続された金属膜と、
    　前記半導体基板の前記機能素子形成面に形成された絶縁層と、
    　前記半導体基板の前記機能素子形成面に対向するように前記絶縁層に形成され、前記金属膜に導通する配線電極と、
    　前記配線電極上の一部に形成された外部電極と、
    　平面視で前記外部電極の周縁部より内側の一部を露出させる開口が形成され、前記絶縁層に形成された絶縁樹脂層と、
    　を備える、半導体装置。     A semiconductor substrate on which functional elements are formed;
    A metal film formed on the functional element forming surface of the semiconductor substrate and connected to the functional element;
    An insulating layer formed on the functional element forming surface of the semiconductor substrate;
    A wiring electrode formed on the insulating layer so as to oppose the functional element formation surface of the semiconductor substrate and conducting to the metal film;
    An external electrode formed on a part of the wiring electrode;
    An opening that exposes a part of the inner side of the peripheral edge of the external electrode in plan view is formed, and an insulating resin layer formed on the insulating layer;
    A semiconductor device comprising:
  2. 　前記配線電極は、前記外部電極が形成された部分以外の表層にＴｉの膜を有し、主材がＣｕであり、
    　前記外部電極は、前記配線電極に対してめっき形成された膜である、
    　請求項１に記載の半導体装置。     The wiring electrode has a Ti film on the surface layer other than the portion where the external electrode is formed, and the main material is Cu,
    The external electrode is a film formed by plating on the wiring electrode.
    The semiconductor device according to claim 1.
  3. 　前記機能素子はＥＳＤ保護回路であり、前記配線電極はＥＳＤ電流の電流路である、請求項１または２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the functional element is an ESD protection circuit, and the wiring electrode is a current path of an ESD current.
PCT/JP2014/060243 2013-05-31 2014-04-09 Semiconductor device WO2014192429A1 (en)

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CN115831961A (en) * 2023-02-15 2023-03-21 成都吉莱芯科技有限公司 Low-capacitance ESD protection device and manufacturing method thereof

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JP2006005325A (en) * 2004-05-20 2006-01-05 Denso Corp Power composite integrated semiconductor device and manufacturing method of the same
JP2010050177A (en) * 2008-08-20 2010-03-04 Sharp Corp Semiconductor device

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CN115831961B (en) * 2023-02-15 2023-04-28 成都吉莱芯科技有限公司 Low-capacitance ESD protection device and manufacturing method thereof

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