JP2007004581A - Regulator circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a regulator circuit for quickly making a reply to load fluctuation or the like. <P>SOLUTION: The regulator circuit is provided with a differential amplifier circuit 10 for amplifying an error between a reference voltage and a feedback voltage, an output circuit 30 including a final stage for supplying current to an output terminal and a drive stage for driving the final stage for supplying current to an output terminal according to the output voltage of the differential amplifier circuit, feedback circuits R1 and R2 for generating a feedback voltage based on a voltage to be generated in the output terminal, and for inputting the feedback voltage to the differential amplifier circuit and a bias control circuit 20 for making the voltage of an output terminal close to a set value by changing bias current in the drive stage of the output circuit when the voltage of the output terminal is changed from a set value. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a regulator circuit (series regulator) that stabilizes a power supply voltage supplied from the outside and supplies the stabilized power supply voltage to another circuit serving as a load.

  The regulator circuit is a circuit that outputs a constant power supply voltage even when the input power supply voltage or load varies, and is used in various home appliances. FIG. 3 shows a configuration example of a conventional regulator circuit. This regulator circuit includes a differential amplifier 10, an N-channel MOS transistor QN31 that generates a drain current according to the output voltage of the differential amplifier 10, a P-channel MOS transistor QP31 that functions as a constant current source, a transistor QN31, and a transistor QP31. P channel MOS transistor QP32 for supplying current to the output terminal according to the drain potential. A large size power transistor is used as the transistor QP32 in order to obtain a large output current.

A reference voltage V _REF is applied to the non-inverting input terminal of the differential amplifier 10, and the voltage V _{REG of the} output terminal is _divided by the feedback resistors R1 and R2 to the inverting input terminal of the differential amplifier 10. Applied. Thus, the regulator circuit performs a feedback operation, and stabilizes the voltage V _REG at the output terminal based on the reference voltage V _REF .

  Here, various loads are connected to the output terminal, but the regulator circuit must continue to supply a constant output voltage to the load even if the load or the power supply voltage fluctuates. In order to increase the output voltage of the regulator circuit when the output voltage of the regulator circuit once decreases due to load fluctuation or the like, the drain current of the N-channel MOS transistor QN31 that drives the power transistor QP32 may be increased.

  On the other hand, in order to decrease the output voltage of the regulator circuit once the output voltage of the regulator circuit increases due to load fluctuation or the like, it is necessary to increase the drain current of the P-channel MOS transistor QP31 that drives the power transistor QP32. However, the transistor QP31 operates as a constant current source, and it takes time for the output voltage of the regulator circuit to drop. Here, if the constant current value is increased, a certain degree of improvement is possible, but this is not a good idea because it causes an increase in current consumption.

As a related technique, Japanese Patent Application Laid-Open Publication No. 2004-228561 prevents a current flowing in a bias circuit of a control transistor that controls an output voltage of a constant voltage circuit from increasing when a load driven by the constant voltage circuit is light. Therefore, a power supply circuit is disclosed in which a circuit for changing the bias current according to the state of the load driven by the constant voltage circuit is provided in the path of the bias current. According to this power supply circuit, even if the current consumption can be reduced when the load is light, the response to the load fluctuation or the like cannot be accelerated.
JP-A-9-319442 (first page, FIG. 1)

  Accordingly, in view of the above points, an object of the present invention is to provide a regulator circuit that can respond to load fluctuations and the like at high speed.

  In order to solve the above problems, a regulator circuit according to the present invention is a regulator circuit that stabilizes a power supply voltage supplied from the outside based on a reference voltage and supplies the stabilized power supply voltage to a load from an output terminal. A differential amplifier circuit that amplifies an error between the reference voltage and the feedback voltage, a final stage that supplies current to the output terminal, and a drive stage that drives the final stage, and the output voltage of the differential amplifier circuit An output circuit for supplying current to the output terminal, a feedback voltage is generated based on the voltage generated at the output terminal, and the feedback voltage is input to the differential amplifier circuit. And a bias control circuit that brings the voltage of the output terminal close to a set value by changing the bias current in the drive stage of the output circuit when it changes.

  Here, the output circuit supplies a negative current to the final stage having a P-channel or N-channel MOS transistor, a P-channel MOS transistor that supplies a positive current to the gate of the final-stage transistor, and a gate of the final-stage transistor. And a drive stage having an N-channel MOS transistor.

  The bias control circuit increases the bias current of the N-channel MOS transistor in the drive stage when the output terminal voltage is lower than the set value, and when the output terminal voltage is higher than the set value, The bias current of the P channel MOS transistor may be increased.

  Further, the bias control circuit reduces the bias current of the P-channel MOS transistor of the drive stage when the output terminal voltage is smaller than the set value, and when the output terminal voltage is larger than the set value, The bias current of the N channel MOS transistor may be reduced.

  According to the present invention, by providing a bias control circuit that brings the voltage of the output terminal closer to the set value by changing the bias current in the drive stage of the output circuit when the voltage of the output terminal changes from the set value, It can respond to fluctuations at high speed.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.
FIG. 1 is a circuit diagram showing a configuration of a regulator circuit according to the first embodiment of the present invention. The regulator circuit according to the first embodiment of the present invention stabilizes the positive power supply voltage V _DD supplied from the outside based on the reference voltage V _REF, and supplies the stabilized power supply voltage V _REG from the output terminal to the load. Supply. As shown in FIG. 1, the regulator circuit includes a differential amplifier 10, a bias control circuit 20, an output circuit 30, and feedback resistors R1 and R2.

  The differential amplifier 10 includes P-channel MOS transistors QP1 to QP4 and N-channel MOS transistors QN1 to QN4, and supplies a single-end amplified signal generated at the drains of the transistors QP4 and QN4 to the transistor QP11 of the output circuit 30. To do.

The reference voltage V _REF is applied to the non-inverting input terminal of the differential amplifier 10, and the voltage V _{REG of the} output terminal is _{divided and} applied to the inverting input terminal of the differential amplifier 10 by the resistors R1 and R2. The Thus, the regulator circuit performs a feedback operation, and stabilizes the voltage V _REG at the output terminal based on the reference voltage V _REF . The voltage V _REG output from the regulator circuit is approximately expressed by the following equation.
V _REG = V _REF · (R1 + R2) / R2

  The bias control circuit 20 includes P-channel MOS transistors QP5 to QP9 and N-channel MOS transistors QN5 to QN11. Based on the magnitude relationship of the differential signals in the differential amplifier 10, the transistors QP10 and QN12 of the output circuit 30 Are supplied with respective bias voltages.

In the steady state, according to the principle of virtual ground by negative feedback operation, equal gate voltages of the transistors QP1 and QP2 of the differential amplifier 10, as a result, the drain current _{I N6} of the drain current _{I N5} and transistor QN6 transistor QN5 equal. Further, since the resistance values of the resistors R3 and R4 are equal, the voltage drop across the resistor R3 and R4 When _{V R3} and _{V R4,} the following equation is established.
V _R3 = V _R4 (1)

Regarding the gate-source voltages V _GSN7 and V _GSN8 of the transistors QN7 and QN8, the following equation is established.
V _GSN7 = V _GSN8 = V _GSN (2)
Further, with respect to the gate-source voltages V _GSP5 and V _GSP6 of the transistors _QP5 and _QP6 , the following equation is established.
V _GSP5 = V _GSP6 = V _GSP (3)

Therefore, the gate voltage of the transistor QN9 is equal to the gate voltage of the transistor QN10, and the gate voltage of the transistor QP7 is equal to the gate voltage of the transistor QP8. Thus, between the gates of the transistor QP8 transistor QN9 it is biased by a voltage _(V GSN ₊ V _GSP), also between the gates of the transistor QP7 transistor QN10, with the voltage _(V GSN ₊ V _GSP) Biased.

This is because the drain current I _N7 of the transistor QN7 and the drain current I _N8 of the transistor QN8 are multiplied by a value corresponding to the ratio W / L of the gate width W to the gate length L of the transistor QN9 and QN10. Means moved. These currents are supplied as bias currents to the output circuit 30 via the transistors QP9 and QP10 constituting the current mirror and the transistors QN11 and QN12 constituting the current mirror.

The output circuit 30 includes P-channel MOS transistors QP10 to QP12 and N-channel MOS transistors QN12 and QN13, and supplies a stabilized power supply voltage V _REG to a load via an output terminal. A power transistor is used as the final stage transistor QP12 in order to obtain a large output current.

  Here, the P-channel MOS transistor QP11 and the N-channel MOS transistor QN13 constitute a cascode amplifier circuit. The transistor QP11 generates a drain current according to the voltage applied from the differential amplifier 10 to the gate. A constant voltage is applied to the gate of the transistor QN13, and the drain current of the transistor QN13 changes according to the drain current of the transistor QP11. The drain voltages of the transistors QP10 and QN13 are applied to the gate of the power transistor QP12.

  Further, a bias current is supplied to the drain of the transistor QN13 via the transistors QP9 and QP10 forming the current mirror, and the source of the transistor QN13 and the drain of the transistor QP11 are connected via the transistors QN11 and QN12 forming the current mirror. Bias current is supplied.

  Although various loads are connected to the output terminal, the regulator circuit must continue to supply a constant output voltage to the load even if the load or the power supply voltage fluctuates. Next, the operation when the output voltage of the regulator circuit changes from the set value due to load fluctuation or the like will be described. In the regulator circuit shown in FIG. 1, the change in the output voltage is fed back to the inverting input terminal of the differential amplifier 10 via the feedback resistors R1 and R2. This causes a difference between the gate voltages of the transistors QP1 and QP2.

  For example, when the output voltage of the regulator circuit becomes lower than the set value, the gate voltage of the transistor QP1 decreases and the drain current of the transistor QP1 increases, so that the drain current of the transistor QN6 also increases. The gate voltage of the transistors QN10 and QP8 decreases due to the increase in the drain current and the increase in the voltage drop in the resistor R4. On the other hand, since the drain current of the transistor QP2 decreases, the drain current of the transistor QN5 also decreases. Due to the decrease in the drain current and the decrease in the voltage drop in the resistor R3, the gate voltages of the transistors QN9 and QP7 increase.

  That is, the difference between the gate voltage of the transistor QN9 and the gate voltage of the transistor QP8 widens, and the difference between the gate voltage of the transistor QN10 and the gate voltage of the transistor QP7 narrows. As a result, the drain currents of the transistors QN9 and QP8 increase, and this is folded back by the transistors QN11 and QN12 forming the current mirror, thereby reducing the gate voltage of the power transistor QP12 via the transistor QN13. At the same time, the drain currents of the transistors QN10 and QP7 decrease, and this is folded back by the transistors QP9 and QP10 constituting the current mirror, thereby reducing the gate voltage of the power transistor QP12. As a result, the drain voltage of the power transistor QP12, that is, the output voltage of the regulator circuit is increased to return to the original value.

  On the other hand, when the output voltage of the regulator circuit becomes higher than the set value, the operation reverse to the above is performed to increase the drain current of the transistor QP10 and decrease the drain current of the transistor QN13. An attempt is made to raise the gate voltage of QP12 and lower the output voltage of the regulator circuit to restore it. In any case, when the output voltage of the regulator circuit changes from the set value, the bias currents (operating currents) of the two transistors QP10 and QN13 in the drive stage that drives the power transistor QP12 are changed as necessary. , Speeding up response to load fluctuations. In other normal states, the current consumption is reduced by supplying a small constant current to the drive stage.

Next, a second embodiment of the present invention will be described.
FIG. 2 is a circuit diagram showing a configuration of a regulator circuit according to the second embodiment of the present invention. Regulator circuit according to the present embodiment, stabilized on the basis of the reference voltage V _REF to negative supply voltage V _SS supplied from the outside, supplied from the output terminal to a load a regulated supply voltage V _REG.

The reference voltage V _REF is applied to the non-inverting input terminal of the differential amplifier 10, and the voltage V _{REG of the} output terminal is _{divided and} applied to the inverting input terminal of the differential amplifier 10 by the resistors R1 and R2. The Thus, the regulator circuit performs a feedback operation, and stabilizes the voltage V _REG at the output terminal based on the reference voltage V _REF . The voltage V _REG output from the regulator circuit is approximately expressed by the following equation.
V _REG = −V _REF · (R1 + R2) / R2

In the second embodiment shown in FIG. 2, the configurations of the differential amplifier 10 and the bias control circuit 20 are the same as those of the first embodiment shown in FIG. 1, but the configuration of the output circuit 40 is the same as that of the first embodiment. It is different from the embodiment. The output circuit 40 includes a P-channel MOS transistors QP10 and QP21, is constituted by an N-channel MOS transistors QN12, QN21 and QN22, a stabilized power supply voltage _{V REG,} supplied to the load via the output terminal. A power transistor is used as the final stage transistor QN22 in order to obtain a large output current.

  Here, the N channel MOS transistor QN21 and the P channel MOS transistor QP21 constitute a cascode amplifier circuit. The transistor QN21 generates a drain current according to the voltage applied from the differential amplifier 10 to the gate. A constant voltage is applied to the gate of the transistor QP21, and the drain current of the transistor QP21 changes according to the drain current of the transistor QN21. The drain voltages of the transistors QP21 and QN12 are applied to the gate of the power transistor QN22.

  Further, a bias current is supplied to the source of the transistor QP21 and the drain of the transistor QN21 via the transistors QP9 and QP10 forming the current mirror, and the drain of the transistor QP21 is connected to the transistors QN11 and QN12 forming the current mirror. Bias current is supplied.

  Next, the operation when the output voltage of the regulator circuit changes from the set value due to load fluctuation or the like will be described. In the regulator circuit shown in FIG. 2, the change in the output voltage is fed back to the inverting input terminal of the differential amplifier 10 via feedback resistors R1 and R2. This causes a difference between the gate voltages of the transistors QP1 and QP2.

  For example, when the output voltage of the regulator circuit becomes lower than the set value, the gate voltage of the transistor QP1 decreases and the drain current of the transistor QP1 increases, so that the drain current of the transistor QN6 also increases. The gate voltage of the transistors QN10 and QP8 decreases due to the increase in the drain current and the increase in the voltage drop in the resistor R4. On the other hand, since the drain current of the transistor QP2 decreases, the drain current of the transistor QN5 also decreases. Due to the decrease in the drain current and the decrease in the voltage drop in the resistor R3, the gate voltages of the transistors QN9 and QP7 increase.

  That is, the difference between the gate voltage of the transistor QN9 and the gate voltage of the transistor QP8 widens, and the difference between the gate voltage of the transistor QN10 and the gate voltage of the transistor QP7 narrows. As a result, the drain currents of the transistors QN9 and QP8 increase, and this is folded back by the transistors QN11 and QN12 constituting the current mirror, thereby reducing the gate voltage of the power transistor QN22. At the same time, the drain currents of the transistors QN10 and QP7 decrease and are turned back by the transistors QP9 and QP10 constituting the current mirror, thereby reducing the gate voltage of the power transistor QN22 via the transistor QP21. As a result, the drain voltage of the power transistor QN22, that is, the output voltage of the regulator circuit is raised to return to the original value.

  On the other hand, when the output voltage of the regulator circuit becomes higher than the set value, the operation reverse to the above is performed to increase the drain current of the transistor QP21 and decrease the drain current of the transistor QN12. The gate voltage of QN22 is raised, and the output voltage of the regulator circuit is lowered to return to the original state. In any case, when the output voltage of the regulator circuit changes from the set value, the bias currents (operating currents) of the two transistors QP21 and QN12 in the drive stage that drives the power transistor QN22 are changed as necessary. , Speeding up response to load fluctuations. In other normal states, the current consumption is reduced by supplying a small constant current to the drive stage.

1 is a circuit diagram showing a configuration of a regulator circuit according to a first embodiment of the present invention. The circuit diagram which shows the structure of the regulator circuit which concerns on the 2nd Embodiment of this invention. The circuit diagram which shows the structural example of the conventional regulator circuit.

Explanation of symbols

  10 differential amplifier, 20 bias control circuit, 30 output circuit, QP1-QP21 P-channel MOS transistor, QN1-QN22 N-channel MOS transistor, R1, R2 resistance

Claims (4)

A regulator circuit that stabilizes a power supply voltage supplied from the outside based on a reference voltage, and supplies the stabilized power supply voltage from an output terminal to a load.
A differential amplifier circuit for amplifying an error between the reference voltage and the feedback voltage;
An output circuit for supplying a current to the output terminal according to an output voltage of the differential amplifier circuit, including a final stage for supplying current to the output terminal and a drive stage for driving the final stage;
A feedback circuit that generates a feedback voltage based on a voltage generated at the output terminal, and inputs the feedback voltage to the differential amplifier circuit;
A bias control circuit that brings the voltage of the output terminal closer to a set value by changing a bias current in a drive stage of the output circuit when the voltage of the output terminal changes from a set value;
A regulator circuit comprising: The output circuit is
A final stage having P-channel or N-channel MOS transistors;
A drive stage having a P-channel MOS transistor for supplying a positive current to the gate of the final-stage transistor and an N-channel MOS transistor for supplying a negative current to the gate of the final-stage transistor;
The regulator circuit according to claim 1, comprising:   The bias control circuit increases the bias current of the N-channel MOS transistor of the drive stage when the voltage of the output terminal is smaller than a set value, and when the voltage of the output terminal is larger than the set value, 3. The regulator circuit according to claim 2, wherein the bias current of the P-channel MOS transistor in the drive stage is increased.   The bias control circuit reduces the bias current of the P-channel MOS transistor of the drive stage when the voltage of the output terminal is smaller than a set value, and when the voltage of the output terminal is larger than the set value, 4. The regulator circuit according to claim 3, wherein the bias current of the N-channel MOS transistor in the drive stage is reduced.

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