JP7402707B2 - Error amplifier and power circuit - Google Patents

Description

The present invention relates to a power supply circuit.

Power supply circuits such as linear regulators and DC/DC converters (switching power supplies) have a soft start function in order to prevent rush current and suppress overshoot of output voltage.

FIG. 1 is a circuit diagram showing a conventional power supply circuit 1R (conventional example 1) having a soft start function. The power supply circuit 1R includes a main circuit 10, an output capacitor C1, resistors R1 and R2, an error amplifier 20, and a soft start circuit 30.

The main circuit 10 includes a main part of a linear regulator or a switching regulator (DC/DC converter). The main circuit 10 is configured such that the output voltage V _OUT varies depending on the error signal V _ERR .

An output capacitor C1 is connected to the output line of the power supply circuit 1R. A feedback voltage V _FB corresponding to the output voltage V _OUT of the power supply circuit 1R is input to the error amplifier 20. For example, the feedback voltage V _FB is a voltage obtained by dividing the output voltage V _OUT by resistors R1 and R2.

The error amplifier 20 amplifies the error between the feedback voltage V _FB and the reference voltage V _REF to generate an error signal V _ERR . A feedback loop including the main circuit 10, resistors R1, R2, and error amplifier 20 applies feedback so that the feedback voltage V _FB matches the reference voltage V _REF , thereby stabilizing the output voltage V _OUT .

Reference voltage V _REF is generated by soft start circuit 30 . The soft start circuit 30 receives a bandgap voltage _VBGR generated by a bandgap reference circuit or the like. In steady state, the reference voltage V _REF is equal to the bandgap voltage V _BGR . The soft start circuit 30 uses the shutdown signal SD as a trigger to gradually increase the reference voltage V _REF from 0V toward V _BGR over time.

FIG. 2 is an operational waveform diagram of the soft start circuit 30 of FIG. 1. When the shutdown signal SD becomes high at time _t0 , the reference voltage V _REF is reset, and thereafter increases at a constant slope. When the reference voltage V _REF reaches the bandgap voltage V _BGR at time t ₁ , it is maintained at a constant level from then on.

FIG. 3 is a circuit diagram showing a power supply circuit 1S (conventional example 2) having a soft start function. The power supply circuit 1S includes a main circuit 10, an output capacitor C1, resistors R1 and R2, a soft start circuit 40, and an error amplifier 50.

The main circuit 10 in FIG. 3 is that of a linear regulator and includes an output transistor 12. The soft start circuit 40 uses the shutdown signal SD as a trigger to gradually increase the soft start voltage _VSS from 0V over time. The error amplifier 50 has three inputs, one non-inverting input terminal (+) and two inverting input terminals (-). A feedback signal V _FB is input to the non-inverting input terminal, and a bandgap voltage V _BGR and a soft start voltage V _SS are input to the two inverting input terminals. The output voltage V _ERR of the error amplifier 50 corresponds to the error between the feedback voltage V FB and the lower one of _the soft start voltage V _SS and the bandgap voltage V _BGR .

Japanese Patent Application Publication No. 2018-133915

As a result of studying the power supply circuit 1R of FIG. 1 and the power supply circuit 1S of FIG. 3, the inventor has come to recognize the following problem.

(Issues of conventional example 1)
FIG. 4 is a circuit diagram showing a configuration example of the soft start circuit 30 of FIG. 1. The soft start circuit 30 includes a capacitor C2, a current source CS1, a reset switch SW1, and a clamp circuit 32.

When the reset switch SW1 is turned on, the capacitor C2 is discharged, and the reference voltage V _REF generated in the capacitor C2 is reset to 0V. When the reset switch SW1 is turned off, the capacitor C2 is charged by the current source CS1, and the reference voltage V _REF is Gradually increases over time. The clamp circuit 32 is a shunt regulator, and adjusts the current flowing through the transistor 33 so that the voltage V _REF generated in the capacitor C2 approaches the bandgap voltage V _BGR .

When the soft start circuit 30 of FIG. 4 is employed, two differential amplifiers (error amplifiers) 20 and 34 are required, so there is a problem that the circuit area increases. Further, if the error amplifier 34 has an input offset voltage, there is a problem that the output voltage V _OUT varies due to the input offset voltage.

(Issues of conventional example 2)
FIG. 5 is a circuit diagram of the soft start circuit 40 and error amplifier 50 of FIG. 3. The differential input stage of the error amplifier 50 includes three PMOS transistors MP1 to MP3. A bandgap voltage V _BGR and a soft start voltage V _SS are input to the gates of the two PMOS transistors MP2 and MP3 corresponding to the two inverting input terminals. In a region where the soft start voltage V _SS is lower than the bandgap voltage V _BGR , current flows predominantly through the PMOS transistor MP3, and the transistor MP2 can be ignored. In a region where the soft start voltage _VSS is close to the bandgap voltage _VBGR , current flows through both PMOS transistors MP2 and MP3. In a region where the soft start voltage V _SS is higher than the bandgap voltage V _BGR , current flows predominantly through the PMOS transistor MP2, and the transistor MP3 can be ignored.

This error amplifier 50 has a problem in that it is difficult to design a switching point between the operations of the two transistors MP2 and MP3. Furthermore, since the soft start voltage _VSS increases from 0V, the differential input transistors cannot be constructed from NMOS transistors.

The present invention has been made in view of such problems, and one exemplary objective of a certain aspect of the present invention is to provide a power supply circuit with a soft start function and an error amplifier that can be used therein.

One aspect of the present invention relates to an error amplifier. The error amplifier includes an input differential pair including a first transistor whose gate is connected to the first input terminal and a second transistor whose gate is connected to the second input terminal, and a tail current source connected to the input differential pair. , a load circuit, a third transistor provided between the first transistor and the load circuit, a fourth transistor provided between the second transistor and the load circuit, and a gate of the third transistor that gradually a first voltage source that supplies a variable soft start voltage; and a second voltage source that supplies a bias voltage to the gate of the fourth transistor.

According to this configuration, soft start control is possible without being affected by offset. Furthermore, since only one differential amplifier is required, the circuit area can be reduced.

The bias voltage may be equal to the voltage level after the transition of the soft start voltage. Thereby, after the soft start operation is completed, the influence of the third transistor and the fourth transistor can be canceled.

The first voltage source includes a capacitor, a switch provided in parallel with the capacitor, and a first current source connected to the capacitor, and the voltage of the capacitor may be a soft start voltage.

The second voltage source may include a second current source having the same configuration as the first current source. Thereby, the bias voltage can be made equal to the voltage level after the transition of the soft start voltage.

The first to fourth transistors may be NMOS transistors. Since NMOS transistors can be used, the circuit can be made smaller than when PMOS transistors are used.

The load circuit may be a current mirror circuit composed of PMOS transistors. The load circuit may be a resistive load.

The first to fourth transistors may be PMOS transistors.

Another aspect of the present invention relates to a power supply circuit. The power supply circuit receives an output transistor whose one end is connected to an input line and the other end is connected to an output line, a reference voltage, and a feedback signal according to the voltage of the output line, and whose output terminal controls the output transistor. The above-mentioned error amplifier connected to the terminal may also be provided.

Another aspect of the present invention also relates to a power supply circuit. The power supply circuit includes a DC/DC converter main circuit including a switching transistor, the above-mentioned error amplifier which receives a reference voltage, and a feedback signal corresponding to the output voltage of the DC/DC converter main circuit, and a DC/DC converter main circuit including a switching transistor. The device may also include a pulse modulator that generates a pulse signal having a duty ratio of 1, and a driver that drives the switching transistor according to the pulse signal.

Note that arbitrary combinations of the above constituent elements and mutual substitution of constituent elements and expressions of the present invention among methods, devices, systems, etc. are also effective as aspects of the present invention.

According to an aspect of the present invention, it is possible to provide an error amplifier having a soft start function.

FIG. 2 is a circuit diagram showing a conventional power supply circuit (conventional example 1) having a soft start function. 2 is an operational waveform diagram of the soft start circuit of FIG. 1. FIG. FIG. 2 is a circuit diagram showing a power supply circuit (conventional example 2) having a soft start function. FIG. 2 is a circuit diagram showing a configuration example of the soft start circuit shown in FIG. 1. FIG. 4 is a circuit diagram of the soft start circuit and error amplifier of FIG. 3. FIG. FIG. 2 is a circuit diagram of a power supply circuit including an error amplifier according to an embodiment. 7 is an operation waveform diagram of the power supply circuit of FIG. 6. FIG. FIGS. 8A and 8B are circuit diagrams of configuration examples of error amplifiers. 3 is a circuit diagram of an error amplifier according to modification example 1. FIG. FIG. 7 is a circuit diagram of an error amplifier according to a second modification. 12 is a circuit diagram of a power supply circuit according to modification 6. FIG.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on preferred embodiments with reference to the drawings. Identical or equivalent components, members, and processes shown in each drawing are designated by the same reference numerals, and redundant explanations will be omitted as appropriate. Further, the embodiments are illustrative rather than limiting the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, "a state in which member A is connected to member B" refers to not only a case where member A and member B are physically directly connected, but also a state in which member A and member B are electrically connected. This also includes cases in which they are indirectly connected via other members that do not substantially affect the connection state or impair the functions and effects achieved by their combination.

Similarly, "a state in which member C is provided between member A and member B" refers to the case where member A and member C or member B and member C are directly connected, This also includes cases in which they are indirectly connected via other members that do not substantially affect the connection state or impair the functions and effects achieved by their combination.

FIG. 6 is a circuit diagram of a power supply circuit 200 including the error amplifier 100 according to the embodiment. The power supply circuit 200 includes a main circuit 210, an output capacitor C1, feedback resistors R1 and R2, and an error amplifier 100 with a soft start function.

In this embodiment, power supply circuit 200 is a linear regulator, and main circuit 210 includes an output transistor 212 that is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The source of output transistor 212 is connected to input line 202 and the drain is connected to output line 204. A smoothing capacitor is connected to the output line 204. The output voltage V _OUT generated on the output line 204 is divided by feedback resistors R1 and R2, and the divided feedback voltage V _FB is fed back to the input terminal INP(+) of the error amplifier 100.

The error amplifier 100 includes input terminals INP and INN, a shutdown terminal SD, and an output terminal OUT. The input terminal INP is a non-inverting input terminal (+), and a feedback voltage _VFB is input thereto. The input terminal INN is an inverting input terminal (-), and a reference voltage such as a bandgap voltage _VBGR is input thereto. The output terminal OUT of the error amplifier 100 is connected to the gate of the output transistor 212, and the output voltage V _ERR of the error amplifier 100 is supplied to the gate.

A shutdown signal SD is input to a shutdown terminal SD of the error amplifier 100.

The error amplifier 100 includes an input differential pair 102, a tail current source 104, a load circuit 106, a third transistor MN3, a fourth transistor MN4, a first voltage source 110, and a second voltage source 112.

Input differential pair 102 includes a first transistor MN1 and a second transistor MN2 that are N-channel MOSFETs. The gates of the first transistor MN1 and the second transistor MN2 are connected to input terminals INN and INP. The tail current source 104 is connected to the sources of the first transistor MN1 and the second transistor MN2.

The load circuit 106 is a current mirror circuit and includes transistors MP5 and MP6, which are P-channel MOSFETs whose gates are connected to each other.

The third transistor MN3 is an N-channel MOSFET, and is provided between the first transistor MN1 and the fifth transistor MP5 of the load circuit 106. The fourth transistor MN4 is an N-channel MOSFET and is provided between the second transistor MN2 and the sixth transistor MP6 of the load circuit 106. The drain of the third transistor MN3 is connected to the output terminal OUT of the error amplifier 100.

The first voltage source 110 supplies a soft start voltage V _SS that gradually changes over time to the gate of the third transistor MN3. The soft start voltage V _SS is initialized in response to assertion of the shutdown signal SD and then varies over time. In this embodiment, the soft start voltage _VSS increases with time.

The second voltage source 112 provides a bias voltage V _BIAS to the gate of the fourth transistor MPN. The bias voltage V _BIAS is preferably designed to be equal to the voltage level after the transition of the soft start voltage V _SS . That is, the bias voltage V _BIAS has a voltage level equal to the maximum voltage of the soft start voltage V _SS .

The above is the configuration of the error amplifier 100 and the power supply circuit 200 including the same. Next, its operation will be explained. FIG. 7 is an operational waveform diagram of the power supply circuit 200 of FIG. 6.

Before time _t0 , the normal state is _TNORM . During the normal period T _NORM , the soft start voltage V _SS is equal to the bias voltage V _BIAS , and the transistors MN3 and MN4 are balanced. Therefore, the influence of the input differential pair 102 is dominant, and feedback is applied so that the voltages V _BGR and V _FB of the two input terminals INP and INN are equal. As a result, the output voltage V _OUT of the power supply circuit 200 is stabilized at the target level (V _BGR × (R1+R2)/R2).

When the shutdown signal SD is asserted at time _t0 , the reset switch SW1 is turned on and the soft start voltage _VSS is reset to 0V. When the soft start voltage _VSS becomes 0V, the third transistor MN3 is turned off. Then, the error voltage V _ERR , which is the output of the error amplifier 100, instantly increases, the output transistor 212 is turned off, and the output voltage V _OUT (feedback voltage V _FB ) decreases to 0V. During the shutdown period TSD in which the shutdown signal _SD is asserted, the tail current _I0 generated by the tail current source 104 flows to the second transistor MN2 and the fourth transistor MN4.

Thereafter, when the shutdown signal SD is negated at time t1, the reset switch SW1 is turned off, the capacitor C11 is charged by the constant current Ic generated by the first current source CS1, and the soft start voltage V _SS increases at a constant slope. do. The period during which the soft start voltage V _SS gradually changes is referred to as a soft start period T _SS .

During the soft start period _TSS , the gate-source voltage of the third transistor MN3 increases with time, and the current flowing through the third transistor MN3 increases with time. As a result, the error voltage V _ERR , which is the drain voltage of the third transistor MN3, decreases over time. As a result, the output transistor 212 is gradually turned on, and the output voltage V _OUT (feedback voltage V _FB ) gradually increases.

At time _t2 , when the soft start period _TSS ends, the soft start voltage _VSS and the bias voltage _VBIAS become equal, resulting in a normal state _TNORM . In the normal state T _NORM , as described above, the influence of the input differential pair 102 is dominant, and feedback is applied so that the voltages V _BGR and V _FB of the two input terminals INP and INN are equal. As a result, the output voltage V _OUT of the power supply circuit 200 is stabilized at the target level (V _BGR × (R1+R2)/R2).

The above is the operation of the power supply circuit 200. Next, the advantages thereof will be explained based on comparison with Conventional Examples 1 and 2.

Comparison will be made with Conventional Example 1 (FIGS. 1 and 4). In conventional example 1, when the error amplifier 34 has an offset voltage, the reference voltage V _REF in the normal period after completion of soft start is not equal to the bandgap voltage V _BGR , and the target level of the output voltage VOUT is caused by the offset voltage. Affected by voltage V _OFS .
V _REF = V _BGR + V _OFS

In contrast, according to the present embodiment, since no error amplifier is used to generate the soft start voltage _VSS , the influence of offset can be reduced.

In addition, in conventional example 1, two differential amplifiers (error amplifiers) 20 and 34 are required, and the circuit area is large, whereas in the present embodiment, only one error amplifier is required, so the circuit The area can be reduced.

Compare with conventional example 2 (FIGS. 3 and 5). In conventional example 2, as shown in FIG. 5, the soft start period and the normal period are switched by the current balance of two transistors MP2 and MP3 connected in parallel. In other words, designing those switches is extremely difficult.

On the other hand, in the error amplifier 100 of this embodiment, the soft start period and the normal period are determined by the balance between the soft start voltage V _SS and the bias voltage V _BIAS , so the design is very easy.

In addition, in Conventional Example 2, the differential pair must be composed of PMOS transistors, but in this embodiment, it can be composed of NMOS transistors whose element size is relatively small. This also has the advantage of reducing the circuit area.

Next, a specific example of the configuration of the error amplifier 100 will be explained. FIGS. 8A and 8B are circuit diagrams of configuration examples of the error amplifier 100.

For example, the first voltage source 110 includes a capacitor C11, a first current source CS1, and a reset switch SW1. The potential at one end of the capacitor C11 is fixed, and the first current source CS1 is connected to the other end. Reset switch SW1 is connected in parallel with capacitor C11. A shutdown signal SD is input to the control terminal (gate) of the reset switch SW1, and in response to the assertion of the shutdown signal SD, the reset switch SW1 is turned on and the soft start voltage _VSS is reset to 0V. Thereafter, when the reset switch SW1 is turned off, the capacitor C11 is charged by the first current source CS1, and the soft start voltage _VSS gradually increases with time at a constant slope. Note that the configuration of the first voltage source 110 is not limited to that shown in FIG. 8(a).

As mentioned above, the voltage level after the transition of the soft start voltage V _SS is preferably equal to the bias voltage V _BIAS . For this purpose, the second voltage source 112 includes a second current source CS2 having the same configuration as the first current source CS1. As shown in FIG. 8(b), the first current source CS1 and the second current source CS2 may be constituted by a pair of transistors MP7 and MP8 whose gates are connected to each other.

Note that since the third transistor MN3 and the fourth transistor MN4 can be considered to be fully on during the normal period, the influence of their gate voltages on the current balance of the two transistors MN3 and MN4 is not so large. Therefore, a certain amount of error is allowed between the bias voltage V _BIAS and the voltage level after the soft start voltage V _SS transition.

Next, a modification will be explained.

(Modification 1)
FIG. 9 is a circuit diagram of an error amplifier 100A according to Modification 1. A bias voltage V _BIAS is supplied to the gate of the fourth transistor MN4. The first voltage source 110A that generates the soft start voltage _VSS includes a clamp circuit 114. The clamp circuit 114 clamps the soft start voltage V _SS so that it does not exceed the bias voltage V _BIAS . The configuration of clamp circuit 114 is not particularly limited.

With this configuration as well, it is possible to balance the currents of the third transistor MN3 and the fourth transistor MN4 during the normal period.

(Modification 2)
FIG. 10 is a circuit diagram of an error amplifier 100C according to a second modification. This error amplifier 100C replaces the NMOS transistors (MN1, MN2, MN3, MN4) of the error amplifier 100 in FIG. 6 with PMOS transistors (MP1, MP2, MP3, MP4), and replaces the PMOS transistors (MP5, MP6) with NMOS transistors. (MN5, MN6) and has an upside-down configuration. The first voltage source 110C may generate a soft start voltage VSS that decreases over time.

In FIG. 10, transistors MP3 and MP4 may be configured with NMOS transistors.

(Modification 3)
In the embodiment and the second modification, the drain of the third transistor MN3 or the fourth transistor MP4 is used as the output of the error amplifier 100, but the error amplifier 100 is not limited to this, and the error amplifier 100 may include an output stage or an amplification stage. .

(Modification 4)
In the embodiment, the error amplifier is composed of MOSFETs, but part or all of it may be composed of bipolar transistors.

(Modification 5)
The load circuit 106 may be a cascode current mirror circuit or a resistive load.

(Modification 6)
Although a linear regulator has been described in the embodiment, the power supply circuit 200 is not limited thereto, and the power supply circuit 200 may be a switching power supply such as a DC/DC converter. FIG. 11 is a circuit diagram of a power supply circuit 200B according to modification 6. Main circuit 210 has the topology of a step-down converter and includes a switching transistor (high-side transistor) MH, a synchronous rectifier transistor (low-side transistor) ML, an inductor L1, a pulse modulator 214, and a driver 216. In this embodiment, the bandgap voltage V _BGR is input to the non-inverting input terminal of the error amplifier 100, and the feedback voltage V _FB is input to the inverting input terminal of the error amplifier 100.

The pulse modulator 214 generates a pulse signal Sp having a duty cycle (or frequency, on time, off time) depending on the error voltage V _ERR generated by the error amplifier 100. The driver 216 drives the high-side transistor MH and the low-side transistor ML based on the pulse signal Sp.

(Modification 7)
In the embodiment, a case has been described in which the error amplifier is used in a power supply circuit, but the present invention is not limited to this, and the error amplifier can be used as an operational amplifier in various applications requiring soft start control.

Although the present invention has been described based on the embodiments, it goes without saying that the embodiments merely illustrate the principles and applications of the present invention. It goes without saying that many modifications and changes in arrangement are possible without departing from the spirit of the invention.

100 Error amplifier 102 Input differential pair 104 Tail current source 106 Load circuit MN1 First transistor MN2 Second transistor MN3 Third transistor MN4 Fourth transistor MP5 Fifth transistor MP6 Sixth transistor 110 First voltage source C11 Capacitor SW1 Reset switch CS1 First current source 112 Second voltage source CS2 Second current source 200 Power supply circuit 210 Main circuit 212 Output transistor 214 Pulse modulator 216 Driver

Claims (9)

an input differential pair including a first transistor having a gate connected to a first input terminal and a second transistor having a gate connected to a second input terminal;
a tail current source connected to the input differential pair;
a load circuit;
a third transistor provided between the first transistor and the load circuit;
a fourth transistor provided between the second transistor and the load circuit;
a first voltage source that supplies a soft start voltage that gradually changes over time to the gate of the third transistor;
a second voltage source that supplies a constant bias voltage to the gate of the fourth transistor;
An error amplifier characterized by comprising: The error amplifier according to claim 1, wherein the bias voltage is equal to a voltage level after the transition of the soft start voltage. The first voltage source is
capacitor and
a switch provided in parallel with the capacitor;
a first current source connected to the capacitor;
3. The error amplifier according to claim 1, wherein the voltage of the capacitor is the soft start voltage. 4. The error amplifier according to claim 3, wherein the second voltage source includes a second current source having the same configuration as the first current source. 5. The error amplifier according to claim 1, wherein the first to fourth transistors are NMOS transistors. 6. The error amplifier according to claim 5, wherein the load circuit is a current mirror circuit composed of PMOS transistors. 5. The error amplifier according to claim 1, wherein the first to fourth transistors are PMOS transistors. an output transistor having one end connected to the input line and the other end connected to the output line;
A reference voltage is received at one of the first input terminal and the second input terminal , a feedback signal corresponding to the voltage of the output line is received at the other of the first input terminal and the second input terminal, and the output terminal is The error amplifier according to any one of claims 1 to 7, connected to a control terminal of the output transistor;
A power supply circuit comprising: A DC/DC converter main circuit including a switching transistor,
A reference voltage is received at one of the first input terminal and the second input terminal , and a feedback signal corresponding to the output voltage of the DC/DC converter main circuit is received at the other of the first input terminal and the second input terminal. the error amplifier according to any one of claims 1 to 7,
a pulse modulator that generates a pulse signal having a duty ratio according to the output of the error amplifier;
a driver that drives the switching transistor according to the pulse signal;
A power supply circuit comprising:

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