JP2006527429A5 - - Google Patents

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Publication number
JP2006527429A5
JP2006527429A5 JP2006515054A JP2006515054A JP2006527429A5 JP 2006527429 A5 JP2006527429 A5 JP 2006527429A5 JP 2006515054 A JP2006515054 A JP 2006515054A JP 2006515054 A JP2006515054 A JP 2006515054A JP 2006527429 A5 JP2006527429 A5 JP 2006527429A5
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Japan
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design
circuit design
circuit
implementation
constraint
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JP2006515054A
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English (en)
Japanese (ja)
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JP2006527429A (ja
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Priority claimed from US10/850,808 external-priority patent/US7178118B2/en
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Publication of JP2006527429A publication Critical patent/JP2006527429A/ja
Publication of JP2006527429A5 publication Critical patent/JP2006527429A5/ja
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JP2006515054A 2003-05-30 2004-05-28 自動回路設計のための方法および装置 Pending JP2006527429A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US47505903P 2003-05-30 2003-05-30
US10/850,808 US7178118B2 (en) 2003-05-30 2004-05-21 Method and apparatus for automated circuit design
PCT/US2004/017207 WO2004109562A1 (en) 2003-05-30 2004-05-28 Method and apparatus for automated circuit design

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011002374A Division JP5197770B2 (ja) 2003-05-30 2011-01-07 回路設計ツール

Publications (2)

Publication Number Publication Date
JP2006527429A JP2006527429A (ja) 2006-11-30
JP2006527429A5 true JP2006527429A5 (https=) 2007-07-19

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JP2006515054A Pending JP2006527429A (ja) 2003-05-30 2004-05-28 自動回路設計のための方法および装置
JP2011002374A Expired - Lifetime JP5197770B2 (ja) 2003-05-30 2011-01-07 回路設計ツール

Family Applications After (1)

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JP2011002374A Expired - Lifetime JP5197770B2 (ja) 2003-05-30 2011-01-07 回路設計ツール

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US (3) US7178118B2 (https=)
EP (2) EP1629409A1 (https=)
JP (2) JP2006527429A (https=)
WO (1) WO2004109562A1 (https=)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6876940B2 (en) * 2003-07-17 2005-04-05 Texas Instruments Incorporated Measuring constraint parameters at different combinations of circuit parameters
KR100855434B1 (ko) * 2003-11-06 2008-09-01 클리어 쉐이프 테크날러지즈, 인크. 델타 정보를 이용한 회로 설계 특성화 프로그램을 기록한컴퓨터로 읽을 수 있는 매체
US7356784B1 (en) * 2003-12-05 2008-04-08 Cadence Design Systems, Inc. Integrated synthesis placement and routing for integrated circuits
US20050268268A1 (en) * 2004-06-01 2005-12-01 Tera Systems, Inc. Methods and systems for structured ASIC electronic design automation
US7487486B2 (en) * 2004-06-17 2009-02-03 Mustafa Celik Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations
US7401307B2 (en) * 2004-11-03 2008-07-15 International Business Machines Corporation Slack sensitivity to parameter variation based timing analysis
JP2006268479A (ja) * 2005-03-24 2006-10-05 Fujitsu Ltd 設計支援装置、設計支援方法、設計支援プログラム、および記録媒体
EP1907957A4 (en) * 2005-06-29 2013-03-20 Otrsotech Ltd Liability Company INVESTMENT METHODS AND SYSTEMS
US7752588B2 (en) * 2005-06-29 2010-07-06 Subhasis Bose Timing driven force directed placement flow
US7325215B2 (en) * 2005-08-31 2008-01-29 Lsi Logic Corporation Timing violation debugging inside place and route tool
JP4275659B2 (ja) * 2005-09-26 2009-06-10 富士通株式会社 遅延解析プログラム、遅延解析装置、および遅延解析方法
US7657859B2 (en) * 2005-12-08 2010-02-02 International Business Machines Corporation Method for IC wiring yield optimization, including wire widening during and after routing
US8332793B2 (en) * 2006-05-18 2012-12-11 Otrsotech, Llc Methods and systems for placement and routing
US7996797B1 (en) 2006-08-16 2011-08-09 Altera Corporation Method and apparatus for performing multiple stage physical synthesis
US8127260B1 (en) 2006-11-22 2012-02-28 Cadence Design Systems, Inc. Physical layout estimator
KR20090068569A (ko) * 2007-12-24 2009-06-29 주식회사 동부하이텍 반도체 소자의 테스트 패턴 및 테스트 패턴 형성 방법
US7996812B2 (en) * 2008-08-14 2011-08-09 International Business Machines Corporation Method of minimizing early-mode violations causing minimum impact to a chip design
US8024693B2 (en) * 2008-11-04 2011-09-20 Synopsys, Inc. Congestion optimization during synthesis
US20100257499A1 (en) * 2009-04-02 2010-10-07 International Business Machines Corporation Techniques for fast area-efficient incremental physical synthesis
JP5397083B2 (ja) * 2009-08-17 2014-01-22 富士通株式会社 回路設計支援方法、回路設計支援装置および回路設計支援プログラム
US8336015B2 (en) * 2009-09-08 2012-12-18 Synopsys, Inc. Pre-route and post-route net correlation with defined patterns
US8429589B2 (en) * 2009-09-08 2013-04-23 Synopsys, Inc. Generating net routing constraints for place and route
US8108821B2 (en) * 2010-01-12 2012-01-31 International Business Machines Corporation Reduction of logic and delay through latch polarity inversion
US9330222B2 (en) 2010-07-24 2016-05-03 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing electronic circuit designs with electro-migration awareness
US8782577B2 (en) 2010-07-24 2014-07-15 Cadence Design Systems, Inc. Method, apparatus, and article of manufacture for providing in situ, customizable information in designing electronic circuits with electrical awareness
JP5541011B2 (ja) * 2010-09-01 2014-07-09 富士通株式会社 最適化ネットリスト作成プログラム、最適化ネットリスト作成装置および最適化ネットリスト作成方法
US8386985B2 (en) 2011-05-06 2013-02-26 International Business Machines Corporation Timing driven routing in integrated circuit design
US8584070B2 (en) * 2011-10-04 2013-11-12 International Business Machines Corporation Evaluating routing congestion based on average global edge congestion histograms
US8595662B1 (en) 2011-12-30 2013-11-26 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing a physical design of an electronic circuit with automatic snapping
US8694943B1 (en) 2011-12-30 2014-04-08 Cadence Design Systems, Inc. Methods, systems, and computer program product for implementing electronic designs with connectivity and constraint awareness
US9064063B1 (en) * 2011-12-30 2015-06-23 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing interactive, real-time checking or verification of complex constraints
US8645902B1 (en) 2011-12-30 2014-02-04 Cadence Design Systems, Inc. Methods, systems, and computer program products for implementing interactive coloring of physical design components in a physical electronic design with multiple-patterning techniques awareness
US9053289B1 (en) 2012-04-12 2015-06-09 Cadence Design Systems, Inc. Method and system for implementing an improved interface for designing electronic layouts
US8640075B2 (en) 2012-06-01 2014-01-28 International Business Machines Corporation Early design cycle optimzation
WO2014064650A2 (en) * 2012-10-25 2014-05-01 Tiwari Satish Chandra Method and system for automated design of an integrated circuit using configurable cells
US8959467B2 (en) * 2012-11-07 2015-02-17 Lsi Corporation Structural rule analysis with TCL scripts in synthesis or STA tools and integrated circuit design tools
US9087172B2 (en) 2013-10-07 2015-07-21 International Business Machines Corporation Implementing enhanced net routing congestion resolution of non-rectangular or rectangular hierarchical macros
US9483597B1 (en) * 2015-03-24 2016-11-01 Xilinx, Inc. Opportunistic candidate path selection during physical optimization of a circuit design for an IC
US10169517B2 (en) 2016-03-29 2019-01-01 Wipro Limited Methods and systems for reducing congestion in very large scale integrated (VLSI) chip design
US10970445B2 (en) * 2017-06-28 2021-04-06 Intel Corporation Methods and apparatus for performing timing driven hardware emulation
EP4312403A3 (en) * 2017-11-09 2024-02-21 nChain Licensing AG Arithmetic enhancement of c-like smart contracts for verifiable computation
US10586005B1 (en) 2018-03-21 2020-03-10 Xilinx, Inc. Incremental synthesis for changes to a circuit design
US10831971B1 (en) * 2019-06-05 2020-11-10 International Business Machines Corporation Net layer promotion with swap capability in electronic design
US12175176B2 (en) * 2021-03-17 2024-12-24 Synopsys, Inc. Fast synthesis of logical circuit design with predictive timing
CN114118358B (zh) * 2021-10-15 2025-10-21 阿里巴巴（中国）有限公司 图像处理方法、装置、电子设备、介质及程序产品

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US655338A (en) * 1898-04-11 1900-08-07 Denis Gale Apparatus for separating solid bodies from liquids.
US5257201A (en) * 1987-03-20 1993-10-26 International Business Machines Corporation Method to efficiently reduce the number of connections in a circuit
JPH04104374A (ja) * 1990-08-24 1992-04-06 Hitachi Ltd 実装設計チェック方法
JP2679500B2 (ja) * 1990-12-17 1997-11-19 モトローラ・インコーポレイテッド 総合的なシステム歩留りを計算するための方法
US5381524B2 (en) * 1991-11-12 1997-07-08 Chronology Corp Automated development of timing diagrams for electrical circuits
US5301118A (en) * 1991-11-18 1994-04-05 International Business Machines Corporation Monte carlo simulation design methodology
JP3219500B2 (ja) * 1991-12-27 2001-10-15 株式会社東芝 自動配線方法
US5418974A (en) * 1992-10-08 1995-05-23 International Business Machines Corporation Circuit design method and system therefor
JP3193167B2 (ja) * 1992-12-11 2001-07-30 株式会社東芝 論理合成システム
US5666290A (en) 1995-12-27 1997-09-09 Vlsi Technology, Inc. Interactive time-driven method of component placement that more directly constrains critical paths using net-based constraints
JPH09198419A (ja) * 1996-01-22 1997-07-31 Toshiba Corp 半導体装置の設計方法及び設計装置
JP2874628B2 (ja) * 1996-01-30 1999-03-24 日本電気株式会社 論理回路の最適化装置及びその方法
JPH09232436A (ja) * 1996-02-22 1997-09-05 Fujitsu Ltd 論理合成方法及び装置並びに半導体集積回路設計方法
US5663891A (en) * 1996-04-03 1997-09-02 Cadence Design Systems, Inc. Optimization of multiple performance criteria of integrated circuits by expanding a constraint graph with subgraphs derived from multiple PWL convex cost functions
US5787008A (en) 1996-04-10 1998-07-28 Motorola, Inc. Simulation corrected sensitivity
US5696771A (en) 1996-05-17 1997-12-09 Synopsys, Inc. Method and apparatus for performing partial unscan and near full scan within design for test applications
US5978572A (en) 1996-08-21 1999-11-02 Matsushita Electric Industrial Co., Ltd. LSI wire length estimation and area estimation
JPH10125790A (ja) * 1996-10-17 1998-05-15 Matsushita Electric Ind Co Ltd ブロック間配線推定方法
JPH10163330A (ja) 1996-12-03 1998-06-19 Nec Corp レイアウト考慮遅延最適化装置および方法
JPH10223763A (ja) * 1997-02-12 1998-08-21 Fujitsu Ltd セル配置最適化処理方法および装置
US5999714A (en) * 1997-03-27 1999-12-07 International Business Machines Corporation Method for incorporating noise considerations in automatic circuit optimization
US6145117A (en) * 1998-01-30 2000-11-07 Tera Systems Incorporated Creating optimized physical implementations from high-level descriptions of electronic design using placement based information
US6286128B1 (en) * 1998-02-11 2001-09-04 Monterey Design Systems, Inc. Method for design optimization using logical and physical information
JP3005538B1 (ja) 1998-09-03 2000-01-31 日本電気アイシーマイコンシステム株式会社 機能ブロックのモデル作成によるｌｓｉ設計システム及びそのｌｓｉ設計方法
KR100846089B1 (ko) * 1998-09-30 2008-07-14 카덴스 디자인 시스템즈 인크 설계 블록들 사이에 다수의 글루 로직 엘리먼트들을 분배하는 방법 및 글루 로직 분배 효율을 증가시키는 방법
JP3223902B2 (ja) * 1999-02-03 2001-10-29 日本電気株式会社 半導体集積回路の配線方法
US7017043B1 (en) * 1999-03-19 2006-03-21 The Regents Of The University Of California Methods and systems for the identification of circuits and circuit designs
US6553338B1 (en) 1999-04-27 2003-04-22 Magma Design Automation, Inc. Timing optimization in presence of interconnect delays
US6993456B2 (en) * 1999-09-30 2006-01-31 Rockwell Automation Technologies, Inc. Mechanical-electrical template based method and apparatus
US6446240B1 (en) * 1999-11-30 2002-09-03 Synopsys, Inc. Evaluation of a technology library for use in an electronic design automation system that converts the technology library into non-linear, gain-based models for estimating circuit delay
US20020029370A1 (en) * 2000-04-20 2002-03-07 Zbigniew Michalewicz Test case generator
US6453451B1 (en) * 2000-10-02 2002-09-17 Lsi Logic Corporation Generating standard delay format files with conditional path delay for designing integrated circuits
US6532577B1 (en) * 2001-06-27 2003-03-11 Lsi Logic Corporation Timing driven interconnect analysis
US6618846B2 (en) 2001-08-31 2003-09-09 Synopsys, Inc. Estimating capacitance effects in integrated circuits using congestion estimations
US6807655B1 (en) * 2002-05-17 2004-10-19 Lsi Logic Corporation Adaptive off tester screening method based on intrinsic die parametric measurements
US6826733B2 (en) * 2002-05-30 2004-11-30 International Business Machines Corporation Parameter variation tolerant method for circuit design optimization
US7363099B2 (en) * 2002-06-07 2008-04-22 Cadence Design Systems, Inc. Integrated circuit metrology
AU2003274370A1 (en) * 2002-06-07 2003-12-22 Praesagus, Inc. Characterization adn reduction of variation for integrated circuits
US6854685B2 (en) 2002-07-09 2005-02-15 Sonoco Development, Inc. Yarn dye tube having opposite end portions adapted for nested stacking
US7000684B2 (en) 2002-11-01 2006-02-21 Cooligy, Inc. Method and apparatus for efficient vertical fluid delivery for cooling a heat producing device
US7487474B2 (en) * 2003-01-02 2009-02-03 Pdf Solutions, Inc. Designing an integrated circuit to improve yield using a variant design element
US20040236560A1 (en) * 2003-05-23 2004-11-25 Chen Thomas W. Power estimation using functional verification
US7251800B2 (en) 2003-05-30 2007-07-31 Synplicity, Inc. Method and apparatus for automated circuit design
US7111260B2 (en) * 2003-09-18 2006-09-19 International Business Machines Corporation System and method for incremental statistical timing analysis of digital circuits

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