JP2006526288A - ボディ固定soiトランジスタ及びその製造方法 - Google Patents
ボディ固定soiトランジスタ及びその製造方法 Download PDFInfo
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- JP2006526288A JP2006526288A JP2006508589A JP2006508589A JP2006526288A JP 2006526288 A JP2006526288 A JP 2006526288A JP 2006508589 A JP2006508589 A JP 2006508589A JP 2006508589 A JP2006508589 A JP 2006508589A JP 2006526288 A JP2006526288 A JP 2006526288A
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- 238000004519 manufacturing process Methods 0.000 title abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 47
- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 238000002513 implantation Methods 0.000 claims abstract description 30
- 239000002019 doping agent Substances 0.000 claims description 22
- 241000251131 Sphyrna Species 0.000 claims description 21
- 241000894007 species Species 0.000 claims description 15
- 238000002347 injection Methods 0.000 claims description 12
- 239000007924 injection Substances 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000007943 implant Substances 0.000 abstract description 19
- 125000001475 halogen functional group Chemical group 0.000 abstract description 14
- 238000005468 ion implantation Methods 0.000 abstract description 11
- 230000008569 process Effects 0.000 abstract description 6
- 230000008901 benefit Effects 0.000 description 11
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
- H01L29/78615—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect with a body contact
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
Claims (10)
- ゲート端を持つ半導体ウェハをイオン注入装置内に載置するステップと、
前記半導体ウェハを前記イオン注入装置のビームパスに対して第1の位置に向けることにより、該ビームパスと前記ゲート端との間で略非直交ツイスト姿勢を得るステップと、
前記半導体ウェハが前記第1の位置にある状態で少なくとも1つのイオン種を前記半導体ウェハの第1の注入領域に注入するステップとを有する方法。 - 前記半導体ウェハを第2の略非直交ツイスト姿勢へと回転するステップと、
前記半導体ウェハが前記第2の位置にある状態で少なくとも1つのイオン種を前記半導体ウェハの第2の注入領域に注入するステップとをさらに有する、請求項1記載の方法。 - 前記第1の注入領域及び前記第2の注入領域はトランジスタデバイスのハンマーヘッド部の下に位置しており、前記第2の注入領域は前記第1の注入領域に重なっている請求項2記載の方法。
- 前記略非直交ツイスト姿勢は45度である請求項1,8及び10に記載の方法。
- 前記略非直交ツイスト姿勢は30度から60度の間の範囲である請求項1,8及び10に記載の方法。
- 前記略非直交ツイスト姿勢は15度から75度の間の範囲である請求項1,8及び10に記載の方法。
- 互いの間の距離がゲートの幅である第1のゲート端及び第2のゲート端を備えたゲート部及びハンマーヘッド部を有するトランジスタデバイスを形成するステップと、
前記トランジスタデバイスの形成後に、前記ハンマーヘッド部の下にドーパントを注入するステップであって、前記ハンマーヘッド部の下にあり前記第1のゲート端に最も近い第1の箇所から前記ハンマーヘッド部の下にあり前記第2のゲート端に最も近い第2の位置まで広がる連続ドープ領域を形成するステップとを有する方法。 - 前記注入するステップはさらに、
前記トランジスタデバイスを第1の略非直交ツイスト姿勢に回転するステップと、
少なくとも1つのイオン種を前記トランジスタデバイスの第1の注入領域に注入するステップと、
前記トランジスタデバイスを第2の略非直交ツイスト姿勢に回転するステップと、
少なくとも1つのイオン種を前記トランジスタデバイスの第2の注入領域に注入するステップとを有する請求項7記載の方法。 - 互いの間の距離がゲートの幅である第1のゲート端及び第2のゲート端を備えたゲート部及びハンマーヘッド部を有するトランジスタデバイスと、
前記ハンマーヘッド部の下にあり前記第1のゲート端に最も近い第1の箇所から前記ハンマーヘッド部の下にあり前記第2のゲート端に最も近い第2の位置まで広がる連続ドープ領域と、
前記ハンマーヘッド部の下に位置するとともに、前記ハンマーヘッド部の下にあり前記第1のゲート端に最も近い第1の箇所から前記ハンマーヘッド部の下にあり前記第2のゲート端に最も近い第2の位置まで広がる連続ドープ領域を形成するドーパントとを備えた半導体デバイス。 - 前記ハンマーヘッド部の下に位置する前記ドーパントは、前記トランジスタデバイスが少なくとも1つの略非直交ツイスト姿勢に向けられていた間に注入された少なくとも1つのイオン種を備えている請求項9記載の半導体デバイス。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/447,047 US7138318B2 (en) | 2003-05-28 | 2003-05-28 | Method of fabricating body-tied SOI transistor having halo implant region underlying hammerhead portion of gate |
PCT/US2004/000486 WO2005015644A1 (en) | 2003-05-28 | 2004-01-09 | Body-tied soi transistor and method for fabrication thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2006526288A true JP2006526288A (ja) | 2006-11-16 |
Family
ID=33451154
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006508589A Pending JP2006526288A (ja) | 2003-05-28 | 2004-01-09 | ボディ固定soiトランジスタ及びその製造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7138318B2 (ja) |
EP (1) | EP1636852A1 (ja) |
JP (1) | JP2006526288A (ja) |
KR (1) | KR101016032B1 (ja) |
CN (1) | CN100477275C (ja) |
TW (1) | TWI344675B (ja) |
WO (1) | WO2005015644A1 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US20070048925A1 (en) * | 2005-08-24 | 2007-03-01 | International Business Machines Corporation | Body-Contacted Silicon on Insulation (SOI) field effect transistors |
US7335563B2 (en) * | 2005-11-09 | 2008-02-26 | International Business Machines Corporation | Rotated field effect transistors and method of manufacture |
US7635920B2 (en) * | 2006-02-23 | 2009-12-22 | Freescale Semiconductor, Inc. | Method and apparatus for indicating directionality in integrated circuit manufacturing |
US7601569B2 (en) * | 2007-06-12 | 2009-10-13 | International Business Machines Corporation | Partially depleted SOI field effect transistor having a metallized source side halo region |
US8426917B2 (en) * | 2010-01-07 | 2013-04-23 | International Business Machines Corporation | Body-tied asymmetric P-type field effect transistor |
US8643107B2 (en) * | 2010-01-07 | 2014-02-04 | International Business Machines Corporation | Body-tied asymmetric N-type field effect transistor |
US9741857B2 (en) * | 2015-08-07 | 2017-08-22 | Ahmad Tarakji | Approach for an area-efficient and scalable CMOS performance based on advanced Silicon-On-Insulator (SOI), Silicon-On-Sapphire (SOS) and Silicon-On-Nothing (SON) technologies |
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US5492847A (en) * | 1994-08-01 | 1996-02-20 | National Semiconductor Corporation | Counter-implantation method of manufacturing a semiconductor device with self-aligned anti-punchthrough pockets |
US5545913A (en) * | 1994-10-17 | 1996-08-13 | Xerox Corporation | Assembly for mounting semiconductor chips in a full-width-array image scanner |
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EP0905789A4 (en) | 1996-06-14 | 1999-08-25 | Mitsubishi Electric Corp | SEMICONDUCTOR COMPONENT HAVING SILICON-ON-INSULATION STRUCTURE AND METHOD OF MANUFACTURING SAME |
JPH10150204A (ja) * | 1996-09-19 | 1998-06-02 | Toshiba Corp | 半導体装置およびその製造方法 |
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JP3447927B2 (ja) * | 1997-09-19 | 2003-09-16 | 株式会社東芝 | 半導体装置およびその製造方法 |
US5811855A (en) * | 1997-12-29 | 1998-09-22 | United Technologies Corporation | SOI combination body tie |
US6353245B1 (en) * | 1998-04-09 | 2002-03-05 | Texas Instruments Incorporated | Body-tied-to-source partially depleted SOI MOSFET |
US5985726A (en) * | 1998-11-06 | 1999-11-16 | Advanced Micro Devices, Inc. | Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFET |
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JP2002246600A (ja) * | 2001-02-13 | 2002-08-30 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US6498371B1 (en) * | 2001-07-31 | 2002-12-24 | Advanced Micro Devices, Inc. | Body-tied-to-body SOI CMOS inverter circuit |
US6642579B2 (en) * | 2001-08-28 | 2003-11-04 | International Business Machines Corporation | Method of reducing the extrinsic body resistance in a silicon-on-insulator body contacted MOSFET |
-
2003
- 2003-05-28 US US10/447,047 patent/US7138318B2/en not_active Expired - Lifetime
-
2004
- 2004-01-09 JP JP2006508589A patent/JP2006526288A/ja active Pending
- 2004-01-09 KR KR1020057022736A patent/KR101016032B1/ko not_active IP Right Cessation
- 2004-01-09 EP EP04775719A patent/EP1636852A1/en not_active Withdrawn
- 2004-01-09 WO PCT/US2004/000486 patent/WO2005015644A1/en active Application Filing
- 2004-01-09 CN CNB2004800145749A patent/CN100477275C/zh not_active Expired - Fee Related
- 2004-03-04 TW TW093105659A patent/TWI344675B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR20060056894A (ko) | 2006-05-25 |
US20040241969A1 (en) | 2004-12-02 |
TWI344675B (en) | 2011-07-01 |
KR101016032B1 (ko) | 2011-02-23 |
US7138318B2 (en) | 2006-11-21 |
CN1795562A (zh) | 2006-06-28 |
TW200504841A (en) | 2005-02-01 |
CN100477275C (zh) | 2009-04-08 |
EP1636852A1 (en) | 2006-03-22 |
WO2005015644A1 (en) | 2005-02-17 |
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