JP2006525652A - Trench insulation structure having different rounding degree of semiconductor device corner and manufacturing method thereof - Google Patents

Abstract

In a trench isolation structure of a semiconductor device, an oxide liner is formed in the trenches 206A, 206B, and an unoxidized mask 221 is used during various oxidation steps, thereby different types of liner oxide, and hence corner chamfer phases. Generate different types and mechanical stresses. Accordingly, the corresponding isolation trench characteristics can be adjusted for individual types of circuit elements to achieve optimal device performance.

Description

  The present invention relates generally to trench isolation structures that are typically utilized in high performance semiconductor devices to electrically isolate adjacent circuit elements from each other, and more particularly to corner rounding. The present invention relates to a technique that enables adjustment of characteristics of a trench insulating structure such as so-called chamfering and residual stress generated therein.

  Traditionally, there has been a constant demand for improving the performance of microstructures such as integrated circuits, which not only ensures that feature sizes of circuit elements are reduced, but also ensures that adjacent circuit elements are electrically isolated from each other. There is a need for an insulating structure. As the feature size of the circuit element is reduced and the number of circuit elements is increased, the chip area that can be used for manufacturing the insulating structure is reduced. For integrated circuits having circuit elements with a feature size of approximately 1 μm and smaller, a well-established insulation structure such as a LOCOS structure (LOCOS) preferably requires less space and It is replaced by an insulating structure circuit that is relatively reliable and requires the formation of a vertical trench surrounding the element. In addition to the reduced chip area occupied by the trench isolation structure compared to the LOCOS structure, the former structure provides a substantially flat surface for subsequent photolithography processes. This significantly improves the resolution of the photolithographic process as compared to a LOCOS structure whose shape changes greatly.

Although the introduction of trench isolation structures into integrated circuit manufacturing processes significantly improves device reliability with increasing package density, in the manufacture of trench isolation structures, the isolation structure and associated circuit elements are particularly relevant in trench isolation structure manufacturing. Some issues arise when the approaching the deep submicron region.
With respect to size in this order, a relatively high electric field can be formed at the angular corners of the trench isolation structure. Therefore, it can adversely affect the operation of circuit elements such as field effect transistors (FETs) and capacitors, resulting in an increase in leakage current between adjacent circuit elements. The formation of the trench isolation structure generally requires the use of photolithography and anisotropic etching process techniques, and the upper corner of the trench exhibits a relatively angular corner, particularly due to this anisotropic etching process. . This angular corner may not be sufficiently rounded (corner portion) by controlling the process parameters of the etching process. Therefore, it is standard to form thermally grown oxide on the inner surface of the trench so as to increase the radius of curvature, particularly the radius of curvature of the upper corner of the insulating trench. However, an increase in the thickness of the thermally grown oxide can cause additional compressive stress and thus adversely affect device characteristics of adjacent circuit elements.

  With reference to FIGS. 1a to 1e, the manufacture of the conventional insulation structure will be described in more detail. FIG. 1 a shows that the semiconductor structure 100 includes a substrate 101, for example a semiconductor substrate such as a silicon wafer, or a dielectric substrate including a semiconductor layer such as an SOI (Silicon on Insulator) substrate. . For example, an oxide layer 102 is formed on the substrate 101 in the form of silicon dioxide, followed by a further dielectric layer 103, the material composition of which is a stop layer during the CMP process required in further manufacturing steps. Can be suitably selected to be used. For example, layer 103 can be provided as a silicon nitride layer. A resist mask layer 104 is formed on the silicon nitride layer 103, and an opening 105 is formed therein. This size represents the size of a trench that can be formed substantially in the substrate 101. It will be noted that depending on the type of photolithography technique utilized, the resist mask 104 may include an anti-reflective coating, improving the resolution of the photolithography step.

  A general process flow for forming the semiconductor structure 100 may include the following process flows. The oxide layer 102 may be formed by a conventional oxidation process or may be deposited by a suitable precursor gas chemical vapor deposition (CVD) technique. A silicon nitride layer 103 is then deposited and a resist layer is subsequently applied, which is then patterned by a photolithography process that forms openings 105. The lateral size of the opening 105 can depend on the particular design of the circuit being formed. For example, if feature sizes are produced in the range of approximately 0.2 μm and below, more advanced photolithography techniques will be required.

  FIG. 1 b schematically shows a semiconductor structure 100 comprising a silicon nitride layer 103, an oxide layer 102, and a trench 106 formed in a portion of the substrate 101. The trench 106 has a lower corner portion or an edge portion 107, and indicates the degree of rounding or the radius of curvature depending on the specification of the anisotropic etching process. However, at the top of the trench, the interface between the oxide layer 102, the substrate 101 and the trench 106 forms a relatively sharp and angular corner or edge, as indicated by 108, which is anisotropically etched. Due to the characteristics of the process, rounding or chamfering cannot be easily performed during the etching process. For example, a relatively strong electric field may be present in a region adjacent to the trench 106 immediately after application of a voltage at an angular corner such as the region 108, so that the corresponding corner 107 and specifically the region are typically present. Measures for chamfering 108 are taken to minimize any accidental impact in circuit elements manufactured in the vicinity of the isolation trench 106, such as a field effect transistor.

  Thus, in general, a thermal oxide liner grows on the inner surface of the trench 106 and provides a relatively large radius of curvature at the region 108 at the interface between the dielectric silicon dioxide 102 and the substrate 101 material. However, depositing bulk oxide to grow the thermal oxide within the trench 106 and thereby filling the trench 106 with dielectric material results in the quality of the deposited oxide adjacent to the thermal liner oxide. Can bring about a decline. And a high etch rate will become high. Thereby, a notch or so-called notch may be generated during the removal of the silicon nitride layer 103. Therefore, a process called “late liner” is frequently performed and bulk oxide is deposited prior to forming thermal oxide in trench 106.

FIG. 1 c schematically shows a semiconductor structure 100 with a silicon dioxide layer 109 formed on the surface of the trench 106 to such an extent that the trench 106 is filled at least to the silicon nitride layer 103. Appropriate deposition techniques, such as chemical vapor deposition deposition with the precursor gases TEOS, oxygen and ozone at a temperature range of approximately 350 ° C. to 650 ° C., substantially form the trench 106 without forming gaps therein. Can be used for filling.
FIG. 1 d schematically shows a semiconductor structure 100 with a thermal oxide layer 110 formed on the inner surface of the oxidizable material of the trench 106, specifically showing that the degree of rounding in the region 108 is significantly increased. It is.

The thermal oxide layer 110 can be formed by exposing the substrate 101 to a high temperature oxidizing atmosphere 112, while at the same time the density of the dielectric oxide material of the layer 109 is increased. The thickness of the thermal oxide layer 110 can be adjusted according to design requirements by appropriately adjusting the process parameters of this oxidation process. Increasing the thickness of the thermal oxide layer 110 provides an advantage from the viewpoint of increasing the degree of rounding of the region 108, that is, increasing the radius of curvature, but the amount of thermal oxide formed in the layer 110 is less than the substrate 101. It is known that the mechanical stress 111 is formed from exceeding the consumed silicon amount.
However, the mechanical stress 111 caused by the growth of the thermal oxide layer 110 can adversely affect the device characteristics of adjacent circuit elements, for example, causing lattice damage of the crystal structure, during further manufacturing steps. If a high temperature anneal cycle is performed, the mechanical stress 111 can further increase. Therefore, a trade-off must be made between the required degree of chamfering in the region 108 and the acceptable mechanical stress 111 caused by the thermal oxide layer 110. The isolation trench 106 is a compromise on the most sensitive type of circuit elements, since a plurality of different circuit elements are typically fabricated in an integrated circuit that have different sensitivities to unwanted electric fields and compressive stresses. Represents.

  FIG. 1e schematically illustrates the semiconductor structure 100 after the excess material of the oxide layer 109 has been removed by chemical mechanical polishing (CMP). The thickness of the silicon nitride layer 103 acting as a CMP stop layer is also reduced during CMP, and the initial thickness of the silicon nitride layer 103 is selected to substantially ensure the integrity of the substrate 101 across the substrate surface. The residual silicon nitride layer 103 and then the oxide layer 102 can then be removed by a suitable wet chemical etching process (not shown).

  Considering the problems that result from the trade-off in the formation of the thermal oxide layer 110, the thermal oxide layer must be tailored to the individual circuit elements, when applying trench isolation to the individual circuit elements. It would be highly desirable to provide a technique for forming trench isolation structures that can provide a relatively high degree of flexibility.

  The present invention generally forms a thermal liner oxide selectively on the oxidizable inner surface of a trench structure, wherein one or more trench structures are formed by an oxygen diffusion barrier in the form of non-oxidizing and / or oxygen-consuming materials. It is intended to be a technique that involves receiving thermal liner oxide at a specified film thickness that is covered and one or more other trench structures. Since certain types of trench structure masking can be performed in a way that results in two or more different liner oxide film thicknesses, and thus two or more different corner chamfers and mechanical stresses, The characteristics of each insulating structure can be adjusted to the corresponding circuit element.

  According to an exemplary embodiment of the present invention, a method of forming a trench isolation structure includes forming a plurality of trenches in a substrate and covering at least one of the plurality of trenches with an oxygen diffusion barrier layer. At least one of the plurality of trenches is covered with an oxygen diffusion barrier layer while the thermal oxide is selectively formed on the inner surface of the oxidizing material of one or more trenches.

  According to another exemplary embodiment of the present invention, a method for controlling the degree of chamfering of a corner of a trench insulation structure in a semiconductor device is performed by heating an inner surface portion of a first insulation trench filled with an insulation material. The second insulating trench filled with the insulating material is covered with the sacrificial oxygen diffusion barrier layer while being oxidized.

  In yet another embodiment of the invention, the trench structure of the semiconductor device includes a plurality of trenches formed of a semiconductor material, each trench having an upper corner portion and a lower corner portion. An insulating material is filled in each trench, and the radius of curvature of the upper corner of at least one trench is different from the radius of curvature of the upper corner of one or more remaining trenches.

  A trench isolation structure according to a further exemplary embodiment includes two or more different types of isolation trenches, each type being a separate thermal oxide layer formed at the interface between the semiconductor material and its oxide. The film thickness is as follows.

While the invention is amenable to various modifications and alternative embodiments, specific embodiments herein are shown by way of example in the drawings and are described in detail below. However, it should be understood that the specific embodiments described herein are not intended to limit the invention to the specific forms of the disclosure, and moreover, the invention is not It is intended to cover all modifications, equivalents, and alternatives within the spirit of the invention as defined by the appended claims. The invention will be understood with reference to the following description according to the attached drawings. The same reference numerals indicate the same elements.
Hereinafter, embodiments of the present invention will be described. For simplicity, not all features in a real implementation are described in this specification. Of course, in the development of such actual implementations, many specific implementation decisions are made, such as reconciliation with system and business limitations, to achieve specific goals for developers. . They vary depending on each embodiment. Further, such development efforts are naturally complex and time consuming, but still fall within the normal work for those skilled in the art having the benefit of this disclosure. .

  The present invention will now be described with reference to the attached figures. Various regions and structures of semiconductor devices are depicted in each drawing with very precise and sharp shapes and profiles, but those skilled in the art will actually see these regions and structures in the drawings. You will recognize that it is not accurate. In addition, the relative sizes of the various features depicted in the drawings and the doped regions are exaggerated or reduced compared to the size of the features and regions of the device being manufactured. However, the attached drawings are attached for the purpose of explaining and explaining embodiments of the present invention. Terms and phrases used herein are understood and interpreted to have a meaning consistent with words and phrases understood by those skilled in the relevant art. The consistent use of terms or phrases in this specification means definitions that are different from any particular definition of these terms or phrases, that is, from the ordinary and conventional meanings understood by those of ordinary skill in the art. Not what you want. When a term or phrase is used in a range that has a specific meaning, that is, when used in a different meaning than that understood by those skilled in the art, the specification directly and clearly identifies such words and phrases. Define.

An exemplary embodiment of the present invention will be described in more detail with reference to FIGS. FIG. 2a shows that the semiconductor structure 200 includes a substrate 201, which can be a semiconductor substrate, such as a silicon substrate suitable for the formation of semiconductor-based circuit elements. For example, the substrate 201 can include various forms of germanium, gallium arsenide, or II-VI or III-VI semiconductors. Furthermore, substrate 201 represents all suitable substrates and includes at least one layer of semiconductor material on which circuit elements can be formed. In particular, the substrate 201 may represent an SOI substrate, with a silicon layer typically formed on an insulating layer, typically a silicon dioxide layer, also referred to as a buried oxide.
Since many integrated circuits are manufactured on the basis of silicon, in the following, the substrate 201 will be referred to as a silicon substrate and form silicon dioxide immediately after exposure to an oxidizing atmosphere. The semiconductor structure 200 further includes a trench isolation structure 220, which in this embodiment is represented by a first trench 206a, a second trench 206b, and their sizes can vary according to design requirements. The trenches 206a, 206b can typically represent isolation trenches in significantly different regions of the substrate 201, or, as in the embodiment shown in FIG. 2a, isolation associated with adjacent circuit elements formed between the trenches. It will be appreciated that a trench may be represented. An oxide layer 202 is formed on the substrate 201 and subsequently a further dielectric layer 203 is formed and has the characteristics that allow the layer 203 to act as a stop layer in the next CMP process. For example, the layer 203 can be composed of silicon nitride. A dielectric oxide material layer 209 is formed over the layer 203 and substantially completely fills the trenches 206a, 206b. The trenches 206a, 206b have upper corner regions indicated by corresponding 208a, 206b.

  For a typical process flow for forming the semiconductor structure 200 as shown in FIG. 2a, a similar process as described above with reference to FIGS. 1a-1c may be utilized. If substrate 201 represents an SOI substrate, trenches 206a, 206b may extend to a buried oxide layer (not shown) or into the buried oxide layer. In one embodiment, after deposition of the dielectric layer 209, a heat treatment can be performed in an inert atmosphere including, for example, nitrogen and / or argon to increase the density of the dielectric material 209. The temperature of the heat treatment can range from about 700 ° C to about 1100 ° C.

  FIG. 2b schematically shows that a semiconductor structure 200 with a sacrificial mask layer 221 acting as an oxygen diffusion barrier is formed on the trench isolation structure 220 portion, and therefore the trench 206a is covered by the mask layer 221. FIG. The mask layer 221 is made of a material that does not oxidize, that is, a material that substantially does not supply or diffuse oxygen when exposed to the oxidizing atmosphere 212 at a high temperature. For example, the mask layer 221 can be made of silicon nitride. Another suitable material constituting the mask layer 221 may include silicon oxynitride (SiON). In a further embodiment, mask layer 221 is comprised of a substantially oxidizable material such as polysilicon, substantially depleting oxygen that penetrates mask layer 221, thereby oxygen to underlying trench isolation structure 220. Is substantially avoided. If the mask layer 221 is made of an oxidizing material, the film thickness is selected in order to substantially avoid oxidative diffusion while being entirely exposed to the oxidizing atmosphere 212. Since the oxidation process of a plurality of materials is well known, an appropriate film thickness of the mask layer 221 can be easily determined in advance.

  In forming the mask layer 221 on the trench isolation structure 220, well-known photolithography and etching techniques may be utilized, while the mask layer is substantially covered while the trench 206a is substantially covered and the trench 206b is substantially entirely exposed. These techniques are not critical because the lateral size of 221 can vary widely. While exposed to the oxidizing atmosphere 212, the thermal oxide layer 210b forms an internal surface portion of the oxidizable material in the trench 206b, resulting in increased chamfering in the region 208b, ie, increased radius of curvature. Process parameters such as the temperature, duration, oxygen concentration, etc. that form the oxidizing atmosphere can be adjusted to obtain the required film thickness when constructing the oxidizing atmosphere 212. Therefore, in combination with a second step of oxidizing the trench 206b as described with reference to FIG. 2c, can be adjusted to obtain the desired degree of rounding or chamfering of the corners in the region 208b. The final degree of corner chamfering is realized. Since the thermal oxide growth rate in silicon is well known, once the structural characteristics of structure 200, ie, temperature, oxygen concentration, pressure, etc., are set, the corner chamfer thickness in region 208b is It can be easily controlled by selecting the duration. For semiconductor materials other than silicon, the growth rate for individual structures can be determined by experiment.

  FIG. 2c schematically illustrates the semiconductor structure 200 with the sacrificial mask layer 221 removed. The semiconductor structure 200 is further exposed to an oxidizing atmosphere 213 to create a thermal oxide layer 210a in the trench 206a while further increasing the thickness of the thermal oxide layer 210b in the trench 206b. As described above, the process parameters utilized while exposing the semiconductor structure 200 to the oxidizing atmosphere 212, 213 are selected so that the thermal oxide layer 210a meets the requirements for the circuit elements associated with those parameters. For example, the mechanical stress generated by the thermal oxide layer 210a is negligible while the required film thickness of the thermal oxide layer 210b at the same time results in a decrease in electric field strength due to an increase in the radius of curvature of the region 208b. . For example, the thickness of the thermal oxide layer 210a can be adjusted to a thickness in the range of about 1 nm to about 30 nm, and the excess amount of the thermal oxide layer 210b from the thickness of the thermal oxide layer 210a is a predetermined amount. The This predetermined excess can be adjusted by correspondingly selecting the process parameters of the oxidizing atmosphere 213.

  A further embodiment is shown schematically in FIG. 2d, starting with a semiconductor structure 200 as shown in FIG. 2a, in which an oxidizing atmosphere 214 is formed instead of or in addition to a heat treatment in an inert atmosphere, and trenches 206a, It is shown that substantially the same thermal oxide layer 210a, 210b is provided in 206b. The density of the dielectric oxide layer 209 can be increased at the same time that the semiconductor structure 200 is exposed to the oxidizing atmosphere 214 so that the preceding heat treatment can be eliminated or the heat treatment period can be significantly shortened. The process parameters of the oxidizing atmosphere 214 are selected so that the thickness of the thermal oxide layer 210b, and hence the corner chamfering in the region 208b, matches the individual circuit elements formed adjacent to the insulating trench 206b.

  FIG. 2e schematically shows the semiconductor structure 200 after formation of a non-oxidizing sacrificial mask layer 221 covering the trench 206b, showing that the trench 206a is exposed to a further oxidizing atmosphere 215. FIG. Therefore, the thickness of the thermal oxide layer 210a increases to the specified degree of corner chamfering in the region 208a. In principle, the sequence shown in FIGS. 2d and 2e is a temporal inversion of the sequence shown in FIGS. 2b and 2c.

  FIG. 2f schematically illustrates a semiconductor structure 200 according to a further exemplary embodiment of the present invention. The semiconductor structure 200 includes similar components and parts as already shown and described in FIG. 2d, except for the dielectric oxide layer 209. The semiconductor structure 200 is exposed to an oxidizing atmosphere 214 and thermal oxide layers 210a and 210b having substantially the same characteristics are formed in the trenches 206a and 206b. This method places the dielectric oxide layer 209 directly on the crystal lattice (not shown in FIG. 2f) to perform the implantation step first without thermal oxide “curing” and oxide densification. May be selected if there is a risk of damage. A dielectric oxide layer 209 can then be deposited to fill the trenches 206a and 206b.

FIG. 2g schematically illustrates the semiconductor structure 200 after deposition of the dielectric oxide layer 209 and formation of a sacrificial mask layer 221 covering the trench 206b. The semiconductor structure 200 is exposed to an oxidizing atmosphere 215 and the thickness of the thermal oxide layer 210a is increased to the required final thickness, thus resulting in the final required chamfering of the region 208a. The process parameters of the oxidizing atmosphere 214 (FIG. 2f) can be selected to obtain the desired characteristics of the thermal oxide layer 210b without further oxidizing the trench 206b, or an additional mask can be formed, or other examples It will be noted that, after deposition of the dielectric oxide layer 209, the desired characteristics of the thermal oxide layer 210b are realized depending on which of the masks can be used to perform the oxidation step.
In other words, in some applications, relatively thin thermal oxide layers 210a, 210b are provided in the trenches 206a, 206b, and then a dielectric oxide layer 209 is deposited, and the thickness of the thermal oxide layer 210b is increased according to a “ray liner” process. Benefits can be gained in completing. Thereby, the possible defects of the “ray liner” process described above are substantially avoided.

  A further exemplary embodiment of the invention will now be described with reference to FIGS. 3a-3c. FIG. 3 a shows that the semiconductor structure 300 includes a trench isolation structure 320, represented in this example by three isolation trenches 306 a, 306 b, 306 c and formed in the substrate 301. This number of trenches is for illustrative purposes only, and the insulating structure 320 can include any number of insulating trenches and can accept different types of grown oxide layers. An oxide layer 302 is formed on the substrate 301, and then an upper layer 303 and a dielectric oxide layer 309 are formed. In addition, a sacrificial mask layer 321 is formed on the dielectric oxide layer 309, covering the trenches 306a and 306b and exposing the trench 306c. As already pointed out with reference to FIGS. 1a to 1e and 2a to 2g regarding the material types of the various components of the semiconductor structure 300 as well as the process flow to form the structure as shown in FIG. 3a. Similar criteria apply. The semiconductor structure 300 is exposed to an oxidizing atmosphere 312 to generate a thermal oxide layer 310c in the trench 306c.

  FIG. 3b shows a semiconductor structure 300 with a second sacrificial mask layer 322 formed on the structure 300 from which the sacrificial mask layer 321 has been removed, showing the trench 306a covered while exposing the trenches 306b, 306c. . The structure 300 is exposed to an oxidizing atmosphere 314 to form a thermal oxide layer 310b in the trench 306b while increasing the thickness of the thermal oxide layer 310c.

  FIG. 3c shows a structure 300 with trenches 306a, 306b, 306c that are ultimately exposed to an oxidizing atmosphere 315, with the thickness of the thermal oxide layers 310b, 310c forming the thermal oxide layer 310a in the trench 306a. Is shown to increase. Similar criteria are applied as described above with reference to previous examples for the selection of process parameters for the various oxidizing atmospheres 312, 314, 315. Further, the sequence shown in FIGS. 3a-3c can be reversed so that the trenches 306a, 306b, 306c are first unmasked and receive substantially the same thermal oxide layer. The initial oxidation can be preceded by a heat treatment that increases the density of the dielectric oxide layer 309 as described above. Next, the trench 306a is masked (FIG. 3b), and then the trenches 306a, 306b are masked (FIG. 3a) to obtain various required film thicknesses, and thus corners in the regions 308a, 308b, 308c of the trench insulating structure 320. Chamfering is performed. Further, all of the process sequences described above with reference to FIGS. 2a-2e can be utilized by the embodiments described with reference to FIGS. 3a-3c. That is, in some embodiments, a thermal oxide layer of the required thickness can be formed before the dielectric oxide layer 309 is deposited. All of the above-described sequences can then be applied to mask one or more of the trenches 306a, 306b, 306c, forming various types of isolation trenches.

  As a result, the present invention enables the formation of trench insulation with different types of thermally grown oxide liners in different insulating trenches by utilizing well-established deposition methods and non-critical photolithography, Gives the electrical and mechanical properties of trench isolation and is applied individually to the associated circuit elements.

  The particular embodiments described above are for illustrative purposes only, as the invention may be modified and practiced in ways that will be apparent to those skilled in the art who have the benefit of this disclosure from different but equivalent. is there. For example, the process steps described above may be performed in different procedures. Furthermore, it is not intended to be limited to the details of construction or design shown herein other than as limited by the claims. The particular embodiments described above may be altered or modified and all such alterations are considered to be within the spirit of the invention. Accordingly, the protection sought in the text is as stated in the claims.

1 is a schematic cross-sectional view of a semiconductor structure including a prior art isolation trench during various manufacturing steps. FIG. 1 is a schematic cross-sectional view of a semiconductor structure including a prior art isolation trench during various manufacturing steps. FIG. 1 is a schematic cross-sectional view of a semiconductor structure including a prior art isolation trench during various manufacturing steps. FIG. 1 is a schematic cross-sectional view of a semiconductor structure including a prior art isolation trench during various manufacturing steps. FIG. 1 is a schematic cross-sectional view of a semiconductor structure including a prior art isolation trench during various manufacturing steps. FIG. FIG. 3 is a schematic cross-sectional view showing an insulating structure having two different forms of trench isolation with variously grown thermal oxide layers, in accordance with an exemplary embodiment of the present invention. FIG. 3 is a schematic cross-sectional view showing an insulating structure having two different forms of trench isolation with variously grown thermal oxide layers, in accordance with an exemplary embodiment of the present invention. FIG. 3 is a schematic cross-sectional view showing an insulating structure having two different forms of trench isolation with variously grown thermal oxide layers, in accordance with an exemplary embodiment of the present invention. FIG. 3 is a schematic cross-sectional view showing an insulating structure having two different forms of trench isolation with variously grown thermal oxide layers, in accordance with an exemplary embodiment of the present invention. FIG. 3 is a schematic cross-sectional view showing an insulating structure having two different forms of trench isolation with variously grown thermal oxide layers, in accordance with an exemplary embodiment of the present invention. FIG. 3 is a schematic cross-sectional view showing an insulating structure having two different forms of trench isolation with variously grown thermal oxide layers, in accordance with an exemplary embodiment of the present invention. FIG. 3 is a schematic cross-sectional view showing an insulating structure having two different forms of trench isolation with variously grown thermal oxide layers, in accordance with an exemplary embodiment of the present invention. FIG. 4 is a cross-sectional view schematically illustrating an insulating structure having a plurality of insulating trenches and including a thermal oxide layer that is variously grown in accordance with yet another embodiment of the present invention. FIG. 4 is a cross-sectional view schematically illustrating an insulating structure having a plurality of insulating trenches and including a thermal oxide layer that is variously grown in accordance with yet another embodiment of the present invention. FIG. 4 is a cross-sectional view schematically illustrating an insulating structure having a plurality of insulating trenches and including a thermal oxide layer that is variously grown in accordance with yet another embodiment of the present invention.

Claims (18)

A method of forming a trench isolation structure, comprising:
Forming a plurality of trenches 206A, 206B in the substrate;
Covering at least one trench 206A of the plurality of trenches with an oxygen diffusion barrier layer 221;
At least one of the plurality of trenches 206A is covered with the oxygen nucleic acid barrier layer 221 while a thermal oxide 210B is formed on the oxidizing inner surface portion of one or more of the plurality of trenches 206B. Selectively form,
Method. Depositing an insulating layer 209 on the substrate before selectively forming a thermal oxide to fill the plurality of trenches;
The method of claim 1. Removing the oxygen diffusion barrier layer 221 covering the at least one trench 206A;
Thermally oxidizing the oxidizable inner surface portion of the pre-covered trench 206A;
The method of claim 1. Removing the oxygen diffusion barrier layer 221;
A second non-oxidation of at least one of the one or more trenches to substantially avoid further oxide growth on the sidewalls of the at least one trench 206B covered by the first dioxide diffusion barrier layer. Covering with a sex mask layer,
The method of claim 1. Thermal oxide on at least some oxidizing inner surface portions of the plurality of trenches prior to selectively forming thermal oxide on the one or more oxidizing inner surface portions of the plurality of trenches Forming,
The method of claim 1. Thermal oxidation on at least some oxidizable inner surface portions of the plurality of trenches after selectively forming thermal oxide on the one or more oxidizable inner surface portions of the plurality of trenches. Form things,
The method of claim 1. Forming a thermal oxide on the oxidizable inner surface portion of the plurality of trenches before selectively forming a thermal oxide in the one or more of the plurality of trenches, and Including filling multiple trenches,
The method of claim 1. Forming a thermal oxide after filling the plurality of trenches and before selectively forming a thermal oxide in the one or more of the plurality of trenches;
The method of claim 7. Heat treating the substrate in an inert atmosphere to increase the density of the inductive layer 209;
The method of claim 2. The oxidation diffusion barrier layer 221 includes a non-oxidizing material,
The method of claim 1. The non-oxidizing material includes at least one of silicon nitride and silicon oxynitride.
The method of claim 10. The oxidation diffusion barrier layer 221 includes an oxidizing material.
The method of claim 1. The film thickness of the oxidation diffusion barrier layer 221 is selected to substantially avoid complete oxidation of the oxidizable material during the formation of the thermal oxide.
The method of claim 12. A method for controlling the degree of corner rounding of a trench insulation structure in a semiconductor device,
Thermally oxidizing the inner surface portion of the first insulating trench 206B filled with the insulating material 209 and covering the second insulating trench 206A filled with the insulating material with the sacrificial oxygen diffusion barrier layer 221;
Method. Forming a thermal oxide layer in the first and second trenches before thermally oxidizing the first trench portion;
The method of claim 14. After thermally oxidizing the first trench portion, removing the oxygen diffusion barrier layer 221 and forming a thermal oxide layer in the first and second trenches;
The method of claim 14. Removing the oxygen diffusion barrier layer 221;
Forming a second oxygen diffusion barrier layer to cover the first trench; and
Thermally oxidizing a surface portion of the second trench;
The method of claim 14. A plurality of trenches 206A, 206B formed in the semiconductor material, each trench having an upper corner 208A, 208B;
An insulating material 209 filling each of the trenches;
The radius of curvature of at least one of the upper corner regions 208A, 208B of the trench is different from the radius of curvature of one or more of the remaining trenches,
Semiconductor device trench insulation structure.

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