JP2006502470A5 - - Google Patents

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Publication number
JP2006502470A5
JP2006502470A5 JP2004509742A JP2004509742A JP2006502470A5 JP 2006502470 A5 JP2006502470 A5 JP 2006502470A5 JP 2004509742 A JP2004509742 A JP 2004509742A JP 2004509742 A JP2004509742 A JP 2004509742A JP 2006502470 A5 JP2006502470 A5 JP 2006502470A5
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Japan
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context
register
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JP2004509742A
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Japanese (ja)
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JP4409427B2 (ja
JP2006502470A (ja
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Priority claimed from US10/159,386 external-priority patent/US7117346B2/en
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Publication of JP4409427B2 publication Critical patent/JP4409427B2/ja
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JP2004509742A 2002-05-31 2003-05-07 複数のレジスタ・コンテキストを有するデータ処理システムおよび該システムのための方法 Expired - Fee Related JP4409427B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/159,386 US7117346B2 (en) 2002-05-31 2002-05-31 Data processing system having multiple register contexts and method therefor
PCT/US2003/014215 WO2003102723A2 (en) 2002-05-31 2003-05-07 Data processing system having multiple register contexts and method therefor

Publications (3)

Publication Number Publication Date
JP2006502470A JP2006502470A (ja) 2006-01-19
JP2006502470A5 true JP2006502470A5 (https=) 2006-06-15
JP4409427B2 JP4409427B2 (ja) 2010-02-03

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004509742A Expired - Fee Related JP4409427B2 (ja) 2002-05-31 2003-05-07 複数のレジスタ・コンテキストを有するデータ処理システムおよび該システムのための方法

Country Status (8)

Country Link
US (1) US7117346B2 (https=)
EP (1) EP1573444A2 (https=)
JP (1) JP4409427B2 (https=)
KR (1) KR100989215B1 (https=)
CN (1) CN100472453C (https=)
AU (1) AU2003225300A1 (https=)
TW (1) TWI323847B (https=)
WO (1) WO2003102723A2 (https=)

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040098568A1 (en) * 2002-11-18 2004-05-20 Nguyen Hung T. Processor having a unified register file with multipurpose registers for storing address and data register values, and associated register mapping method
US7631307B2 (en) * 2003-12-05 2009-12-08 Intel Corporation User-programmable low-overhead multithreading
US7401206B2 (en) * 2004-06-30 2008-07-15 Sun Microsystems, Inc. Apparatus and method for fine-grained multithreading in a multipipelined processor core
US7516311B2 (en) * 2005-01-27 2009-04-07 Innovasic, Inc. Deterministic microcontroller context arrangement
US7562207B2 (en) * 2005-01-27 2009-07-14 Innovasic, Inc. Deterministic microcontroller with context manager
KR100728899B1 (ko) * 2005-10-27 2007-06-15 한국과학기술원 복수의 레지스터 집합과 하드웨어 작업 관리자를 가진고성능 멀티쓰레드 임베디드 프로세서
US7590774B2 (en) * 2005-12-01 2009-09-15 Kabushiki Kaisha Toshiba Method and system for efficient context swapping
EP2011018B1 (en) 2006-04-12 2016-07-13 Soft Machines, Inc. Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
CN107368285B (zh) * 2006-11-14 2020-10-09 英特尔公司 多线程架构
JPWO2009022371A1 (ja) * 2007-08-16 2010-11-04 ネットクリアスシステムズ株式会社 タスク処理装置
US9135144B2 (en) 2009-10-22 2015-09-15 Freescale Semiconductor, Inc. Integrated circuits and methods for debugging
EP3156896B1 (en) 2010-09-17 2020-04-08 Soft Machines, Inc. Single cycle multi-branch prediction including shadow cache for early far branch prediction
US20130275725A1 (en) * 2011-01-03 2013-10-17 Freescale Semiconductor, Inc. Integrated circuit device and method for performing conditional negation of data
CN108108188B (zh) 2011-03-25 2022-06-28 英特尔公司 用于通过使用由可分区引擎实例化的虚拟核来支持代码块执行的存储器片段
KR101620676B1 (ko) 2011-03-25 2016-05-23 소프트 머신즈, 인크. 분할가능한 엔진에 의해 인스턴스화된 가상 코어를 이용한 코드 블록의 실행을 지원하는 레지스터 파일 세그먼트
CN103547993B (zh) 2011-03-25 2018-06-26 英特尔公司 通过使用由可分割引擎实例化的虚拟核来执行指令序列代码块
WO2012131437A1 (en) * 2011-03-30 2012-10-04 Freescale Semiconductor, Inc. Integrated circuit device and method for enabling cross-context access
CN107729267B (zh) 2011-05-20 2022-01-25 英特尔公司 资源的分散分配以及用于支持由多个引擎执行指令序列的互连结构
US9442772B2 (en) 2011-05-20 2016-09-13 Soft Machines Inc. Global and local interconnect structure comprising routing matrix to support the execution of instruction sequences by a plurality of engines
US10078515B2 (en) * 2011-10-03 2018-09-18 International Business Machines Corporation Tracking operand liveness information in a computer system and performing function based on the liveness information
KR101703401B1 (ko) 2011-11-22 2017-02-06 소프트 머신즈, 인크. 다중 엔진 마이크로프로세서용 가속 코드 최적화기
WO2013077876A1 (en) 2011-11-22 2013-05-30 Soft Machines, Inc. A microprocessor accelerated code optimizer
JP5852677B2 (ja) * 2011-12-26 2016-02-03 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ レジスタ・マッピング方法
WO2014108747A1 (en) * 2013-01-10 2014-07-17 Freescale Semiconductor, Inc. Integrated circuit processor and method of operating a integrated circuit processor
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
WO2014151043A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for emulating a guest centralized flag architecture by using a native distributed flag architecture
EP2972845B1 (en) 2013-03-15 2021-07-07 Intel Corporation A method for executing multithreaded instructions grouped onto blocks
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
WO2014150971A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for dependency broadcasting through a block organized source view data structure
US10031770B2 (en) * 2014-04-30 2018-07-24 Intel Corporation System and method of delayed context switching in processor registers
US9971604B2 (en) 2015-02-26 2018-05-15 International Business Machines Corporation History buffer for multiple-field registers
US10067766B2 (en) * 2015-02-26 2018-09-04 International Business Machines Corporation History buffer with hybrid entry support for multiple-field registers
US9996353B2 (en) 2015-02-26 2018-06-12 International Business Machines Corporation Universal history buffer to support multiple register types
US10802866B2 (en) * 2015-04-30 2020-10-13 Microchip Technology Incorporated Central processing unit with DSP engine and enhanced context switch capabilities
JP2017037370A (ja) 2015-08-06 2017-02-16 富士通株式会社 計算機、プロセス制御方法およびプロセス制御プログラム
GB2577729C (en) * 2018-10-04 2021-10-27 Advanced Risc Mach Ltd Processor with Register Bank having Banked Versions of a Register each Associated with an Operating State of the Processor
CN110928574A (zh) * 2019-11-20 2020-03-27 深圳市汇顶科技股份有限公司 微控制器、中断处理芯片、设备及中断处理方法
US11663010B2 (en) * 2021-03-08 2023-05-30 Unisys Corporation System and method for securely debugging across multiple execution contexts
US11816486B2 (en) 2022-01-18 2023-11-14 Nxp B.V. Efficient inter-thread communication between hardware processing threads of a hardware multithreaded processor by selective aliasing of register blocks

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5142677A (en) * 1989-05-04 1992-08-25 Texas Instruments Incorporated Context switching devices, systems and methods
JPH04242433A (ja) * 1991-01-17 1992-08-31 Nec Corp マイクロプロセッサ
US5386563A (en) * 1992-10-13 1995-01-31 Advanced Risc Machines Limited Register substitution during exception processing
GB2281986B (en) * 1993-09-15 1997-08-06 Advanced Risc Mach Ltd Data processing reset
US5680588A (en) * 1995-06-06 1997-10-21 International Business Machines Corporation Method and system for optimizing illumination in an optical photolithography projection imaging system
US6029242A (en) * 1995-08-16 2000-02-22 Sharp Electronics Corporation Data processing system using a shared register bank and a plurality of processors
US5701508A (en) * 1995-12-19 1997-12-23 Intel Corporation Executing different instructions that cause different data type operations to be performed on single logical register file
US5812868A (en) * 1996-09-16 1998-09-22 Motorola Inc. Method and apparatus for selecting a register file in a data processing system
US6145049A (en) * 1997-12-29 2000-11-07 Stmicroelectronics, Inc. Method and apparatus for providing fast switching between floating point and multimedia instructions using any combination of a first register file set and a second register file set
US6154832A (en) * 1998-12-04 2000-11-28 Advanced Micro Devices, Inc. Processor employing multiple register sets to eliminate interrupts
WO2000079394A1 (en) 1999-06-21 2000-12-28 Bops Incorporated Methods and apparatus for providing manifold array (manarray) program context switch with array reconfiguration control
US7925869B2 (en) 1999-12-22 2011-04-12 Ubicom, Inc. Instruction-level multithreading according to a predetermined fixed schedule in an embedded processor using zero-time context switching

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