JP5852677B2 - レジスタ・マッピング方法 - Google Patents
レジスタ・マッピング方法 Download PDFInfo
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- JP5852677B2 JP5852677B2 JP2013551519A JP2013551519A JP5852677B2 JP 5852677 B2 JP5852677 B2 JP 5852677B2 JP 2013551519 A JP2013551519 A JP 2013551519A JP 2013551519 A JP2013551519 A JP 2013551519A JP 5852677 B2 JP5852677 B2 JP 5852677B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
- G06F9/5077—Logical partitioning of resources; Management or configuration of virtualized resources
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Storage Device Security (AREA)
Description
(b)CPU内で、GS、LPID、TIDの情報(値)が追加され、レジスタSave/Restore処理部に処理を依頼する。なお、GESRレジスタが1つしかない従来のシステムではこの時点で、現在のGESRの内容を退避する必要があるため、ハイパーバイザに処理が移り、ハイパーバイザにより現在のGESRをメモリに退避する処理が行われる。
(c)本発明ではハイパーバイザに処理は移らず、追加されたGS、LPID、TIDの情報を元にマッピング・テーブルの参照が行われ、特定されたマッピング・レジスタまたは通常のレジスタにアクセスして内容の保存が行われた後、CPU命令mtsprを発行したOSに処理が戻される。
12 記憶手段
14 バス
16 各種I/O
18 入力手段
20 表示手段
22 通信手段
24 外部記憶装置
50 システム
102、104 コア
106、108、110、112 ハードウェア・スレッド
114、116 レジスタ・プール
118、120、122、124 マッピング(用)・レジスタ
Claims (4)
- 少なくとも2つ以上のハードウェア・スレッドを用いて、ハイパーバイザと少なくとも2つ以上のOSとが動作可能な仮想化システムにおけるレジスタ・マッピング方法であって、
複数のマッピング用レジスタを含むレジスタ・プールを準備するステップと、
前記レジスタ・プール中の各マッピング用レジスタについて、レジスタIDと、前記仮想化システムの動作状態を表す複数のパラメータの各々とに関する情報を設定した、マッピング・テーブルを準備するステップと、
ハードウェア・スレッドによるレジスタ・アクセス要求があった際における、当該アクセス対象のレジスタIDと、動作中の前記動作状態を表す複数のパラメータの各々に関する情報を取得するステップと、
取得した前記レジスタIDおよび前記複数のパラメータの各々に関する情報が、前記マッピング・テーブル中の前記レジスタIDおよび前記複数のパラメータの各々についての情報に一致する前記マッピング用レジスタを、前記レジスタ・アクセス要求に対応してアクセスするレジスタとして設定するステップと、
を含み、
前記マッピング・テーブル中の前記動作状態を表す複数のパラメータは、前記ハイパーバイザの動作か前記OSの動作かを示す動作IDと、OSのIDと、前記ハードウェア・スレッドのIDとを含む、
レジスタ・マッピング方法。 - 前記マッピング・テーブルは、前記各マッピング用レジスタについて、前記動作ID、前記OSのID、および前記ハードウェア・スレッドのIDの中のどのパラメータの情報を前記一致するか否かのチェックに利用するかを指定するチェック・マスクをさらに含む、請求項1のレジスタ・マッピング方法。
- 前記レジスタ・アクセス要求に対応してアクセスするレジスタとして設定するステップは、前記マッピング・テーブル中の前記チェック・マスクにより指定された前記パラメータの情報についてのみ一致するか否かを判断することを含む、請求項2のレジスタ・マッピング方法。
- 前記取得したレジスタIDの情報が前記マッピング・テーブル中の前記レジスタIDの情報に一致しない場合、前記レジスタ・プール中の前記マッピング用レジスタ以外のレジスタを前記レジスタ・アクセス要求に対応してアクセスするレジスタとして設定する、請求項1〜3のいずれか1項のレジスタ・マッピング方法。
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JP2013551519A JP5852677B2 (ja) | 2011-12-26 | 2012-10-19 | レジスタ・マッピング方法 |
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JP2013551519A JP5852677B2 (ja) | 2011-12-26 | 2012-10-19 | レジスタ・マッピング方法 |
PCT/JP2012/077114 WO2013099414A1 (ja) | 2011-12-26 | 2012-10-19 | レジスタ・マッピング方法 |
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WO2013099414A1 (ja) | 2013-07-04 |
US20130232489A1 (en) | 2013-09-05 |
US20130167149A1 (en) | 2013-06-27 |
US9471342B2 (en) | 2016-10-18 |
JPWO2013099414A1 (ja) | 2015-04-30 |
US9430254B2 (en) | 2016-08-30 |
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