JP2006502470A5 - - Google Patents

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Publication number
JP2006502470A5
JP2006502470A5 JP2004509742A JP2004509742A JP2006502470A5 JP 2006502470 A5 JP2006502470 A5 JP 2006502470A5 JP 2004509742 A JP2004509742 A JP 2004509742A JP 2004509742 A JP2004509742 A JP 2004509742A JP 2006502470 A5 JP2006502470 A5 JP 2006502470A5
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JP
Japan
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context
register
contexts
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alternative
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JP2004509742A
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Japanese (ja)
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JP2006502470A (ja
JP4409427B2 (ja
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Priority claimed from US10/159,386 external-priority patent/US7117346B2/en
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Publication of JP2006502470A5 publication Critical patent/JP2006502470A5/ja
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Publication of JP4409427B2 publication Critical patent/JP4409427B2/ja
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JP2004509742A 2002-05-31 2003-05-07 複数のレジスタ・コンテキストを有するデータ処理システムおよび該システムのための方法 Expired - Fee Related JP4409427B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/159,386 US7117346B2 (en) 2002-05-31 2002-05-31 Data processing system having multiple register contexts and method therefor
PCT/US2003/014215 WO2003102723A2 (en) 2002-05-31 2003-05-07 Data processing system having multiple register contexts and method therefor

Publications (3)

Publication Number Publication Date
JP2006502470A JP2006502470A (ja) 2006-01-19
JP2006502470A5 true JP2006502470A5 (enExample) 2006-06-15
JP4409427B2 JP4409427B2 (ja) 2010-02-03

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ID=29582888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004509742A Expired - Fee Related JP4409427B2 (ja) 2002-05-31 2003-05-07 複数のレジスタ・コンテキストを有するデータ処理システムおよび該システムのための方法

Country Status (8)

Country Link
US (1) US7117346B2 (enExample)
EP (1) EP1573444A2 (enExample)
JP (1) JP4409427B2 (enExample)
KR (1) KR100989215B1 (enExample)
CN (1) CN100472453C (enExample)
AU (1) AU2003225300A1 (enExample)
TW (1) TWI323847B (enExample)
WO (1) WO2003102723A2 (enExample)

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JP5852677B2 (ja) * 2011-12-26 2016-02-03 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ レジスタ・マッピング方法
WO2014108747A1 (en) * 2013-01-10 2014-07-17 Freescale Semiconductor, Inc. Integrated circuit processor and method of operating a integrated circuit processor
WO2014150971A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for dependency broadcasting through a block organized source view data structure
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
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US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
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US10031770B2 (en) * 2014-04-30 2018-07-24 Intel Corporation System and method of delayed context switching in processor registers
US9971604B2 (en) 2015-02-26 2018-05-15 International Business Machines Corporation History buffer for multiple-field registers
US9996353B2 (en) 2015-02-26 2018-06-12 International Business Machines Corporation Universal history buffer to support multiple register types
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