JPH09244951A5 - - Google Patents

Info

Publication number
JPH09244951A5
JPH09244951A5 JP1997012344A JP1234497A JPH09244951A5 JP H09244951 A5 JPH09244951 A5 JP H09244951A5 JP 1997012344 A JP1997012344 A JP 1997012344A JP 1234497 A JP1234497 A JP 1234497A JP H09244951 A5 JPH09244951 A5 JP H09244951A5
Authority
JP
Japan
Prior art keywords
instructions
odd
address
receive
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1997012344A
Other languages
English (en)
Japanese (ja)
Other versions
JPH09244951A (ja
JP3876033B2 (ja
Filing date
Publication date
Priority claimed from US08/609,821 external-priority patent/US5761713A/en
Application filed filed Critical
Publication of JPH09244951A publication Critical patent/JPH09244951A/ja
Publication of JPH09244951A5 publication Critical patent/JPH09244951A5/ja
Application granted granted Critical
Publication of JP3876033B2 publication Critical patent/JP3876033B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP01234497A 1996-03-01 1997-01-27 順不同に命令を実行するコンピュータのためのシステム Expired - Fee Related JP3876033B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US609,821 1996-03-01
US08/609,821 US5761713A (en) 1996-03-01 1996-03-01 Address aggregation system and method for increasing throughput to a multi-banked data cache from a processor by concurrently forwarding an address to each bank

Publications (3)

Publication Number Publication Date
JPH09244951A JPH09244951A (ja) 1997-09-19
JPH09244951A5 true JPH09244951A5 (enExample) 2004-12-24
JP3876033B2 JP3876033B2 (ja) 2007-01-31

Family

ID=24442487

Family Applications (1)

Application Number Title Priority Date Filing Date
JP01234497A Expired - Fee Related JP3876033B2 (ja) 1996-03-01 1997-01-27 順不同に命令を実行するコンピュータのためのシステム

Country Status (4)

Country Link
US (1) US5761713A (enExample)
JP (1) JP3876033B2 (enExample)
DE (1) DE19650520A1 (enExample)
GB (1) GB2310741B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5895469A (en) * 1996-03-08 1999-04-20 Vlsi Technology, Inc. System for reducing access times for retrieving audio samples and method therefor
US5752259A (en) * 1996-03-26 1998-05-12 Advanced Micro Devices, Inc. Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache
US6016532A (en) * 1997-06-27 2000-01-18 Sun Microsystems, Inc. Method for handling data cache misses using help instructions
US5878252A (en) * 1997-06-27 1999-03-02 Sun Microsystems, Inc. Microprocessor configured to generate help instructions for performing data cache fills
US6101577A (en) * 1997-09-15 2000-08-08 Advanced Micro Devices, Inc. Pipelined instruction cache and branch prediction mechanism therefor
US6892294B1 (en) 2000-02-03 2005-05-10 Hewlett-Packard Development Company, L.P. Identifying execution ready instructions and allocating ports associated with execution resources in an out-of-order processor
US7664918B2 (en) * 2006-07-24 2010-02-16 Sun Microsystems, Inc. Handling fetch requests that return out-of-order at an instruction fetch unit
US8386753B2 (en) * 2009-04-14 2013-02-26 International Business Machines Corporation Completion arbitration for more than two threads based on resource limitations
US9158541B2 (en) * 2010-11-03 2015-10-13 Apple Inc. Register renamer that handles multiple register sizes aliased to the same storage locations

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3699533A (en) * 1970-10-29 1972-10-17 Rca Corp Memory system including buffer memories
US4381541A (en) * 1980-08-28 1983-04-26 Sperry Corporation Buffer memory referencing system for two data words
EP0055579B1 (en) * 1980-12-31 1991-03-20 Bull HN Information Systems Inc. Cache memories with double word access
US4439827A (en) * 1981-12-28 1984-03-27 Raytheon Company Dual fetch microsequencer
US4724518A (en) * 1983-07-29 1988-02-09 Hewlett-Packard Company Odd/even storage in cache memory
US4818932A (en) * 1986-09-25 1989-04-04 Tektronix, Inc. Concurrent memory access system
US4918587A (en) * 1987-12-11 1990-04-17 Ncr Corporation Prefetch circuit for a computer memory subject to consecutive addressing
CA2000031A1 (en) * 1988-10-20 1990-04-20 Robert W. Horst Cache memory supporting fast unaligned access
US5342990A (en) * 1990-01-05 1994-08-30 E-Mu Systems, Inc. Digital sampling instrument employing cache-memory
JPH0437935A (ja) * 1990-06-01 1992-02-07 Hitachi Ltd キャッシュメモリを有する計算機
US5434989A (en) * 1991-02-19 1995-07-18 Matsushita Electric Industrial Co., Ltd. Cache memory for efficient access with address selectors
JPH07502358A (ja) * 1991-12-23 1995-03-09 インテル・コーポレーション マイクロプロセッサーのクロックに依るマルチプル・アクセスのためのインターリーブ・キャッシュ
US5420997A (en) * 1992-01-02 1995-05-30 Browning; Gary A. Memory having concurrent read and writing from different addresses
JP2549256B2 (ja) * 1992-12-01 1996-10-30 インターナショナル・ビジネス・マシーンズ・コーポレイション 浮動小数点プロセッサへデータを転送する方法及び装置
JPH06242951A (ja) * 1992-12-22 1994-09-02 Toshiba Corp キャッシュメモリシステム
US5467473A (en) * 1993-01-08 1995-11-14 International Business Machines Corporation Out of order instruction load and store comparison
JPH0756815A (ja) * 1993-07-28 1995-03-03 Internatl Business Mach Corp <Ibm> キャッシュ動作方法及びキャッシュ

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