JP3876033B2 - 順不同に命令を実行するコンピュータのためのシステム - Google Patents

順不同に命令を実行するコンピュータのためのシステム Download PDF

Info

Publication number
JP3876033B2
JP3876033B2 JP01234497A JP1234497A JP3876033B2 JP 3876033 B2 JP3876033 B2 JP 3876033B2 JP 01234497 A JP01234497 A JP 01234497A JP 1234497 A JP1234497 A JP 1234497A JP 3876033 B2 JP3876033 B2 JP 3876033B2
Authority
JP
Japan
Prior art keywords
address
odd
instructions
processor
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP01234497A
Other languages
English (en)
Japanese (ja)
Other versions
JPH09244951A5 (enExample
JPH09244951A (ja
Inventor
グレッグ・レサルター
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JPH09244951A publication Critical patent/JPH09244951A/ja
Publication of JPH09244951A5 publication Critical patent/JPH09244951A5/ja
Application granted granted Critical
Publication of JP3876033B2 publication Critical patent/JP3876033B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0851—Cache with interleaved addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP01234497A 1996-03-01 1997-01-27 順不同に命令を実行するコンピュータのためのシステム Expired - Fee Related JP3876033B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US609,821 1996-03-01
US08/609,821 US5761713A (en) 1996-03-01 1996-03-01 Address aggregation system and method for increasing throughput to a multi-banked data cache from a processor by concurrently forwarding an address to each bank

Publications (3)

Publication Number Publication Date
JPH09244951A JPH09244951A (ja) 1997-09-19
JPH09244951A5 JPH09244951A5 (enExample) 2004-12-24
JP3876033B2 true JP3876033B2 (ja) 2007-01-31

Family

ID=24442487

Family Applications (1)

Application Number Title Priority Date Filing Date
JP01234497A Expired - Fee Related JP3876033B2 (ja) 1996-03-01 1997-01-27 順不同に命令を実行するコンピュータのためのシステム

Country Status (4)

Country Link
US (1) US5761713A (enExample)
JP (1) JP3876033B2 (enExample)
DE (1) DE19650520A1 (enExample)
GB (1) GB2310741B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5895469A (en) * 1996-03-08 1999-04-20 Vlsi Technology, Inc. System for reducing access times for retrieving audio samples and method therefor
US5752259A (en) * 1996-03-26 1998-05-12 Advanced Micro Devices, Inc. Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache
US6016532A (en) * 1997-06-27 2000-01-18 Sun Microsystems, Inc. Method for handling data cache misses using help instructions
US5878252A (en) * 1997-06-27 1999-03-02 Sun Microsystems, Inc. Microprocessor configured to generate help instructions for performing data cache fills
US6101577A (en) * 1997-09-15 2000-08-08 Advanced Micro Devices, Inc. Pipelined instruction cache and branch prediction mechanism therefor
US6892294B1 (en) 2000-02-03 2005-05-10 Hewlett-Packard Development Company, L.P. Identifying execution ready instructions and allocating ports associated with execution resources in an out-of-order processor
US7664918B2 (en) * 2006-07-24 2010-02-16 Sun Microsystems, Inc. Handling fetch requests that return out-of-order at an instruction fetch unit
US8386753B2 (en) * 2009-04-14 2013-02-26 International Business Machines Corporation Completion arbitration for more than two threads based on resource limitations
US9158541B2 (en) * 2010-11-03 2015-10-13 Apple Inc. Register renamer that handles multiple register sizes aliased to the same storage locations

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3699533A (en) * 1970-10-29 1972-10-17 Rca Corp Memory system including buffer memories
US4381541A (en) * 1980-08-28 1983-04-26 Sperry Corporation Buffer memory referencing system for two data words
EP0055579B1 (en) * 1980-12-31 1991-03-20 Bull HN Information Systems Inc. Cache memories with double word access
US4439827A (en) * 1981-12-28 1984-03-27 Raytheon Company Dual fetch microsequencer
US4724518A (en) * 1983-07-29 1988-02-09 Hewlett-Packard Company Odd/even storage in cache memory
US4818932A (en) * 1986-09-25 1989-04-04 Tektronix, Inc. Concurrent memory access system
US4918587A (en) * 1987-12-11 1990-04-17 Ncr Corporation Prefetch circuit for a computer memory subject to consecutive addressing
CA2000031A1 (en) * 1988-10-20 1990-04-20 Robert W. Horst Cache memory supporting fast unaligned access
US5342990A (en) * 1990-01-05 1994-08-30 E-Mu Systems, Inc. Digital sampling instrument employing cache-memory
JPH0437935A (ja) * 1990-06-01 1992-02-07 Hitachi Ltd キャッシュメモリを有する計算機
US5434989A (en) * 1991-02-19 1995-07-18 Matsushita Electric Industrial Co., Ltd. Cache memory for efficient access with address selectors
JPH07502358A (ja) * 1991-12-23 1995-03-09 インテル・コーポレーション マイクロプロセッサーのクロックに依るマルチプル・アクセスのためのインターリーブ・キャッシュ
US5420997A (en) * 1992-01-02 1995-05-30 Browning; Gary A. Memory having concurrent read and writing from different addresses
JP2549256B2 (ja) * 1992-12-01 1996-10-30 インターナショナル・ビジネス・マシーンズ・コーポレイション 浮動小数点プロセッサへデータを転送する方法及び装置
JPH06242951A (ja) * 1992-12-22 1994-09-02 Toshiba Corp キャッシュメモリシステム
US5467473A (en) * 1993-01-08 1995-11-14 International Business Machines Corporation Out of order instruction load and store comparison
JPH0756815A (ja) * 1993-07-28 1995-03-03 Internatl Business Mach Corp <Ibm> キャッシュ動作方法及びキャッシュ

Also Published As

Publication number Publication date
DE19650520A1 (de) 1997-09-04
GB9702534D0 (en) 1997-03-26
US5761713A (en) 1998-06-02
GB2310741B (en) 2000-09-20
JPH09244951A (ja) 1997-09-19
GB2310741A (en) 1997-09-03

Similar Documents

Publication Publication Date Title
US5809275A (en) Store-to-load hazard resolution system and method for a processor that executes instructions out of order
CN101221493B (zh) 用于并行处理的方法和设备
JP4045062B2 (ja) ロード命令を実行する方法、プロセッサ、およびシステム
US5251306A (en) Apparatus for controlling execution of a program in a computing device
CA2383528C (en) Branch instruction for processor
US7478225B1 (en) Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processor
JP3876034B2 (ja) 主メモリへの帯域幅を保持するシステム
HK1049899A1 (zh) 並行處理器體系結構的sdram控制器
JP2000259412A (ja) ストア命令転送方法およびプロセッサ
JPH10124391A (ja) マージされたストア・オペレーションによってストア集束を行うためのプロセッサ及び方法
WO2001016702A1 (en) Register set used in multithreaded parallel processor architecture
IE990754A1 (en) An apparatus for software initiated prefetch and method therefor
US6301654B1 (en) System and method for permitting out-of-order execution of load and store instructions
US20040216103A1 (en) Mechanism for detecting and handling a starvation of a thread in a multithreading processor environment
KR19990072272A (ko) 로드/로드검출및재정렬방법
US6324640B1 (en) System and method for dispatching groups of instructions using pipelined register renaming
JP3876033B2 (ja) 順不同に命令を実行するコンピュータのためのシステム
JPH02239331A (ja) データ処理システム及びその命令実行を促進する方法
US6240507B1 (en) Mechanism for multiple register renaming and method therefor
US5802340A (en) Method and system of executing speculative store instructions in a parallel processing computer system
US5956503A (en) Method and system for front-end and back-end gathering of store instructions within a data-processing system
US6209073B1 (en) System and method for interlocking barrier operations in load and store queues
US8683181B2 (en) Processor and method for distributing load among plural pipeline units
US5926645A (en) Method and system for enabling multiple store instruction completions in a processing system
US7191309B1 (en) Double shift instruction for micro engine used in multithreaded parallel processor architecture

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040123

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040123

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060705

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060718

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061011

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20061024

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20061030

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees