JP2001142789A5 - - Google Patents

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Publication number
JP2001142789A5
JP2001142789A5 JP2000320318A JP2000320318A JP2001142789A5 JP 2001142789 A5 JP2001142789 A5 JP 2001142789A5 JP 2000320318 A JP2000320318 A JP 2000320318A JP 2000320318 A JP2000320318 A JP 2000320318A JP 2001142789 A5 JP2001142789 A5 JP 2001142789A5
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JP
Japan
Prior art keywords
memory
word
error correction
computer system
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2000320318A
Other languages
English (en)
Japanese (ja)
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JP2001142789A (ja
Filing date
Publication date
Priority claimed from US09/429,749 external-priority patent/US6493843B1/en
Application filed filed Critical
Publication of JP2001142789A publication Critical patent/JP2001142789A/ja
Publication of JP2001142789A5 publication Critical patent/JP2001142789A5/ja
Withdrawn legal-status Critical Current

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JP2000320318A 1999-10-28 2000-10-20 ローエンドサーバまたはワークステーション用のチップキル Withdrawn JP2001142789A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/429749 1999-10-28
US09/429,749 US6493843B1 (en) 1999-10-28 1999-10-28 Chipkill for a low end server or workstation

Publications (2)

Publication Number Publication Date
JP2001142789A JP2001142789A (ja) 2001-05-25
JP2001142789A5 true JP2001142789A5 (enExample) 2005-03-17

Family

ID=23704584

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000320318A Withdrawn JP2001142789A (ja) 1999-10-28 2000-10-20 ローエンドサーバまたはワークステーション用のチップキル

Country Status (2)

Country Link
US (1) US6493843B1 (enExample)
JP (1) JP2001142789A (enExample)

Families Citing this family (27)

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US6370668B1 (en) * 1999-07-23 2002-04-09 Rambus Inc High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes
US7051166B2 (en) * 2003-04-21 2006-05-23 Hewlett-Packard Development Company, L.P. Directory-based cache coherency scheme for reducing memory bandwidth loss
US7065697B2 (en) * 2003-07-29 2006-06-20 Hewlett-Packard Development Company, L.P. Systems and methods of partitioning data to facilitate error correction
US7051265B2 (en) * 2003-07-29 2006-05-23 Hewlett-Packard Development Company, L.P. Systems and methods of routing data to facilitate error correction
US7143236B2 (en) * 2003-07-30 2006-11-28 Hewlett-Packard Development Company, Lp. Persistent volatile memory fault tracking using entries in the non-volatile memory of a fault storage unit
US7331010B2 (en) * 2004-10-29 2008-02-12 International Business Machines Corporation System, method and storage medium for providing fault detection and correction in a memory subsystem
US7577890B2 (en) 2005-01-21 2009-08-18 Hewlett-Packard Development Company, L.P. Systems and methods for mitigating latency associated with error detection and correction
US7546514B2 (en) 2005-04-11 2009-06-09 Hewlett-Packard Development Company, L.P. Chip correct and fault isolation in computer memory systems
US7360132B1 (en) * 2005-05-19 2008-04-15 Sun Microsystems, Inc. System and method for memory chip kill
US7734980B2 (en) * 2005-06-24 2010-06-08 Intel Corporation Mitigating silent data corruption in a buffered memory module architecture
US7307902B2 (en) * 2005-08-30 2007-12-11 Hewlett-Packard Development Company, L.P. Memory correction system and method
US7227797B2 (en) * 2005-08-30 2007-06-05 Hewlett-Packard Development Company, L.P. Hierarchical memory correction system and method
US7685392B2 (en) 2005-11-28 2010-03-23 International Business Machines Corporation Providing indeterminate read data latency in a memory system
US7975205B2 (en) * 2007-01-26 2011-07-05 Hewlett-Packard Development Company, L.P. Error correction algorithm selection based upon memory organization
US8706914B2 (en) * 2007-04-23 2014-04-22 David D. Duchesneau Computing infrastructure
US8848470B2 (en) 2012-08-29 2014-09-30 International Business Machines Corporation Memory operation upon failure of one of two paired memory devices
US8996935B2 (en) 2012-12-07 2015-03-31 International Business Machines Corporation Memory operation of paired memory devices
US9632862B2 (en) * 2014-12-20 2017-04-25 Intel Corporation Error handling in transactional buffered memory
US9697884B2 (en) 2015-10-08 2017-07-04 Rambus Inc. Variable width memory module supporting enhanced error detection and correction
US9891864B2 (en) 2016-01-19 2018-02-13 Micron Technology, Inc. Non-volatile memory module architecture to support memory error correction
KR20190062908A (ko) * 2017-11-29 2019-06-07 에스케이하이닉스 주식회사 에러 정정 방법 및 칩 킬 감지 방법
US10546628B2 (en) * 2018-01-03 2020-01-28 International Business Machines Corporation Using dual channel memory as single channel memory with spares
KR20210147131A (ko) 2020-05-27 2021-12-07 삼성전자주식회사 반도체 메모리 모듈을 액세스하는 방법
US11404136B2 (en) 2020-12-16 2022-08-02 Micron Technology, Inc. Memory device protection using interleaved multibit symbols
US11409601B1 (en) 2021-01-26 2022-08-09 Micron Technology, Inc. Memory device protection
CN114758696B (zh) * 2022-04-20 2025-06-10 芯动微电子科技(珠海)有限公司 存储系统及其操作方法
KR20250138266A (ko) * 2023-02-01 2025-09-19 마이크론 테크놀로지, 인크. 시스템 레벨 조정 회복성

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Publication number Priority date Publication date Assignee Title
US3585378A (en) * 1969-06-30 1971-06-15 Ibm Error detection scheme for memories
US5058116A (en) * 1989-09-19 1991-10-15 International Business Machines Corporation Pipelined error checking and correction for cache memories
US5335234A (en) * 1990-06-19 1994-08-02 Dell Usa, L.P. Error correction code pipeline for interleaved memory system
US5481552A (en) * 1993-12-30 1996-01-02 International Business Machines Corporation Method and structure for providing error correction code for 8-byte data words on SIMM cards
US5623506A (en) * 1994-01-28 1997-04-22 International Business Machines Corporation Method and structure for providing error correction code within a system having SIMMs
US5379304A (en) * 1994-01-28 1995-01-03 International Business Machines Corporation Method and structure for providing error correction code and parity for each byte on SIMM's
US5465262A (en) * 1994-01-28 1995-11-07 International Business Machines Corporation Method and structure for providing error correction code and automatic parity sensing
US6003144A (en) * 1997-06-30 1999-12-14 Compaq Computer Corporation Error detection and correction
US6304992B1 (en) * 1998-09-24 2001-10-16 Sun Microsystems, Inc. Technique for correcting single-bit errors in caches with sub-block parity bits
US6233716B1 (en) * 1998-09-24 2001-05-15 Sun Microsystems, Inc. Technique for partitioning data to correct memory part failures

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