CN100472453C - 具有多寄存器上下文的数据处理系统及其方法 - Google Patents
具有多寄存器上下文的数据处理系统及其方法 Download PDFInfo
- Publication number
- CN100472453C CN100472453C CNB038126249A CN03812624A CN100472453C CN 100472453 C CN100472453 C CN 100472453C CN B038126249 A CNB038126249 A CN B038126249A CN 03812624 A CN03812624 A CN 03812624A CN 100472453 C CN100472453 C CN 100472453C
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30134—Register stacks; shift registers
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/159,386 US7117346B2 (en) | 2002-05-31 | 2002-05-31 | Data processing system having multiple register contexts and method therefor |
| US10/159,386 | 2002-05-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1856770A CN1856770A (zh) | 2006-11-01 |
| CN100472453C true CN100472453C (zh) | 2009-03-25 |
Family
ID=29582888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB038126249A Expired - Fee Related CN100472453C (zh) | 2002-05-31 | 2003-05-07 | 具有多寄存器上下文的数据处理系统及其方法 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US7117346B2 (enExample) |
| EP (1) | EP1573444A2 (enExample) |
| JP (1) | JP4409427B2 (enExample) |
| KR (1) | KR100989215B1 (enExample) |
| CN (1) | CN100472453C (enExample) |
| AU (1) | AU2003225300A1 (enExample) |
| TW (1) | TWI323847B (enExample) |
| WO (1) | WO2003102723A2 (enExample) |
Families Citing this family (46)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040098568A1 (en) * | 2002-11-18 | 2004-05-20 | Nguyen Hung T. | Processor having a unified register file with multipurpose registers for storing address and data register values, and associated register mapping method |
| US7631307B2 (en) * | 2003-12-05 | 2009-12-08 | Intel Corporation | User-programmable low-overhead multithreading |
| US7401206B2 (en) * | 2004-06-30 | 2008-07-15 | Sun Microsystems, Inc. | Apparatus and method for fine-grained multithreading in a multipipelined processor core |
| US7562207B2 (en) * | 2005-01-27 | 2009-07-14 | Innovasic, Inc. | Deterministic microcontroller with context manager |
| US7516311B2 (en) * | 2005-01-27 | 2009-04-07 | Innovasic, Inc. | Deterministic microcontroller context arrangement |
| KR100728899B1 (ko) * | 2005-10-27 | 2007-06-15 | 한국과학기술원 | 복수의 레지스터 집합과 하드웨어 작업 관리자를 가진고성능 멀티쓰레드 임베디드 프로세서 |
| US7590774B2 (en) * | 2005-12-01 | 2009-09-15 | Kabushiki Kaisha Toshiba | Method and system for efficient context swapping |
| US8327115B2 (en) | 2006-04-12 | 2012-12-04 | Soft Machines, Inc. | Plural matrices of execution units for processing matrices of row dependent instructions in single clock cycle in super or separate mode |
| EP2527972A3 (en) | 2006-11-14 | 2014-08-06 | Soft Machines, Inc. | Apparatus and method for processing complex instruction formats in a multi- threaded architecture supporting various context switch modes and virtualization schemes |
| JPWO2009022371A1 (ja) * | 2007-08-16 | 2010-11-04 | ネットクリアスシステムズ株式会社 | タスク処理装置 |
| US9135144B2 (en) | 2009-10-22 | 2015-09-15 | Freescale Semiconductor, Inc. | Integrated circuits and methods for debugging |
| EP3156896B1 (en) | 2010-09-17 | 2020-04-08 | Soft Machines, Inc. | Single cycle multi-branch prediction including shadow cache for early far branch prediction |
| EP2661658B1 (en) * | 2011-01-03 | 2019-09-25 | NXP USA, Inc. | Integrated circuit device and method for performing conditional negation of data |
| US9842005B2 (en) | 2011-03-25 | 2017-12-12 | Intel Corporation | Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines |
| EP2689326B1 (en) | 2011-03-25 | 2022-11-16 | Intel Corporation | Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines |
| WO2012135031A2 (en) | 2011-03-25 | 2012-10-04 | Soft Machines, Inc. | Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines |
| US20140019990A1 (en) * | 2011-03-30 | 2014-01-16 | Freescale Semiconductor, Inc. | Integrated circuit device and method for enabling cross-context access |
| CN103649931B (zh) | 2011-05-20 | 2016-10-12 | 索夫特机械公司 | 用于支持由多个引擎执行指令序列的互连结构 |
| KR101639853B1 (ko) | 2011-05-20 | 2016-07-14 | 소프트 머신즈, 인크. | 복수의 엔진에 의해 명령어 시퀀스들의 실행을 지원하기 위한 자원들 및 상호접속 구조들의 비집중 할당 |
| US10078515B2 (en) * | 2011-10-03 | 2018-09-18 | International Business Machines Corporation | Tracking operand liveness information in a computer system and performing function based on the liveness information |
| KR101703401B1 (ko) | 2011-11-22 | 2017-02-06 | 소프트 머신즈, 인크. | 다중 엔진 마이크로프로세서용 가속 코드 최적화기 |
| EP2783281B1 (en) | 2011-11-22 | 2020-05-13 | Intel Corporation | A microprocessor accelerated code optimizer |
| WO2013099414A1 (ja) | 2011-12-26 | 2013-07-04 | インターナショナル・ビジネス・マシーンズ・コーポレーション | レジスタ・マッピング方法 |
| WO2014108747A1 (en) * | 2013-01-10 | 2014-07-17 | Freescale Semiconductor, Inc. | Integrated circuit processor and method of operating a integrated circuit processor |
| CN105210040B (zh) | 2013-03-15 | 2019-04-02 | 英特尔公司 | 用于执行分组成块的多线程指令的方法 |
| WO2014150806A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for populating register view data structure by using register template snapshots |
| US10275255B2 (en) | 2013-03-15 | 2019-04-30 | Intel Corporation | Method for dependency broadcasting through a source organized source view data structure |
| US9569216B2 (en) | 2013-03-15 | 2017-02-14 | Soft Machines, Inc. | Method for populating a source view data structure by using register template snapshots |
| US9811342B2 (en) | 2013-03-15 | 2017-11-07 | Intel Corporation | Method for performing dual dispatch of blocks and half blocks |
| US9891924B2 (en) | 2013-03-15 | 2018-02-13 | Intel Corporation | Method for implementing a reduced size register view data structure in a microprocessor |
| US9886279B2 (en) | 2013-03-15 | 2018-02-06 | Intel Corporation | Method for populating and instruction view data structure by using register template snapshots |
| CN105247484B (zh) | 2013-03-15 | 2021-02-23 | 英特尔公司 | 利用本地分布式标志体系架构来仿真访客集中式标志体系架构的方法 |
| US9904625B2 (en) | 2013-03-15 | 2018-02-27 | Intel Corporation | Methods, systems and apparatus for predicting the way of a set associative cache |
| WO2014150971A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for dependency broadcasting through a block organized source view data structure |
| US10140138B2 (en) | 2013-03-15 | 2018-11-27 | Intel Corporation | Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation |
| WO2014150991A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for implementing a reduced size register view data structure in a microprocessor |
| US10031770B2 (en) * | 2014-04-30 | 2018-07-24 | Intel Corporation | System and method of delayed context switching in processor registers |
| US9996353B2 (en) | 2015-02-26 | 2018-06-12 | International Business Machines Corporation | Universal history buffer to support multiple register types |
| US9971604B2 (en) | 2015-02-26 | 2018-05-15 | International Business Machines Corporation | History buffer for multiple-field registers |
| US10067766B2 (en) * | 2015-02-26 | 2018-09-04 | International Business Machines Corporation | History buffer with hybrid entry support for multiple-field registers |
| US10802866B2 (en) * | 2015-04-30 | 2020-10-13 | Microchip Technology Incorporated | Central processing unit with DSP engine and enhanced context switch capabilities |
| JP2017037370A (ja) | 2015-08-06 | 2017-02-16 | 富士通株式会社 | 計算機、プロセス制御方法およびプロセス制御プログラム |
| GB2577729C (en) * | 2018-10-04 | 2021-10-27 | Advanced Risc Mach Ltd | Processor with Register Bank having Banked Versions of a Register each Associated with an Operating State of the Processor |
| CN110928574A (zh) * | 2019-11-20 | 2020-03-27 | 深圳市汇顶科技股份有限公司 | 微控制器、中断处理芯片、设备及中断处理方法 |
| US11663010B2 (en) * | 2021-03-08 | 2023-05-30 | Unisys Corporation | System and method for securely debugging across multiple execution contexts |
| US11816486B2 (en) | 2022-01-18 | 2023-11-14 | Nxp B.V. | Efficient inter-thread communication between hardware processing threads of a hardware multithreaded processor by selective aliasing of register blocks |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5386563A (en) * | 1992-10-13 | 1995-01-31 | Advanced Risc Machines Limited | Register substitution during exception processing |
| US5426766A (en) * | 1991-01-17 | 1995-06-20 | Nec Corporation | Microprocessor which holds selected data for continuous operation |
| US5680588A (en) * | 1995-06-06 | 1997-10-21 | International Business Machines Corporation | Method and system for optimizing illumination in an optical photolithography projection imaging system |
| US6145049A (en) * | 1997-12-29 | 2000-11-07 | Stmicroelectronics, Inc. | Method and apparatus for providing fast switching between floating point and multimedia instructions using any combination of a first register file set and a second register file set |
| US6170997B1 (en) * | 1995-12-19 | 2001-01-09 | Intel Corporation | Method for executing instructions that operate on different data types stored in the same single logical register file |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5142677A (en) * | 1989-05-04 | 1992-08-25 | Texas Instruments Incorporated | Context switching devices, systems and methods |
| GB2281986B (en) * | 1993-09-15 | 1997-08-06 | Advanced Risc Mach Ltd | Data processing reset |
| US6029242A (en) * | 1995-08-16 | 2000-02-22 | Sharp Electronics Corporation | Data processing system using a shared register bank and a plurality of processors |
| US5812868A (en) * | 1996-09-16 | 1998-09-22 | Motorola Inc. | Method and apparatus for selecting a register file in a data processing system |
| US6154832A (en) * | 1998-12-04 | 2000-11-28 | Advanced Micro Devices, Inc. | Processor employing multiple register sets to eliminate interrupts |
| WO2000079394A1 (en) | 1999-06-21 | 2000-12-28 | Bops Incorporated | Methods and apparatus for providing manifold array (manarray) program context switch with array reconfiguration control |
| AU2597401A (en) | 1999-12-22 | 2001-07-03 | Ubicom, Inc. | System and method for instruction level multithreading in an embedded processor using zero-time context switching |
-
2002
- 2002-05-31 US US10/159,386 patent/US7117346B2/en not_active Expired - Lifetime
-
2003
- 2003-05-07 AU AU2003225300A patent/AU2003225300A1/en not_active Abandoned
- 2003-05-07 KR KR1020047019511A patent/KR100989215B1/ko not_active Expired - Fee Related
- 2003-05-07 JP JP2004509742A patent/JP4409427B2/ja not_active Expired - Fee Related
- 2003-05-07 WO PCT/US2003/014215 patent/WO2003102723A2/en not_active Ceased
- 2003-05-07 EP EP03722022A patent/EP1573444A2/en not_active Withdrawn
- 2003-05-07 CN CNB038126249A patent/CN100472453C/zh not_active Expired - Fee Related
- 2003-05-27 TW TW092114269A patent/TWI323847B/zh not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5426766A (en) * | 1991-01-17 | 1995-06-20 | Nec Corporation | Microprocessor which holds selected data for continuous operation |
| US5386563A (en) * | 1992-10-13 | 1995-01-31 | Advanced Risc Machines Limited | Register substitution during exception processing |
| US5680588A (en) * | 1995-06-06 | 1997-10-21 | International Business Machines Corporation | Method and system for optimizing illumination in an optical photolithography projection imaging system |
| US6170997B1 (en) * | 1995-12-19 | 2001-01-09 | Intel Corporation | Method for executing instructions that operate on different data types stored in the same single logical register file |
| US6145049A (en) * | 1997-12-29 | 2000-11-07 | Stmicroelectronics, Inc. | Method and apparatus for providing fast switching between floating point and multimedia instructions using any combination of a first register file set and a second register file set |
Non-Patent Citations (3)
| Title |
|---|
| A user-level process package for PVM. KONURU R.SCALABLE HIGH-PERFORMANCE COMPUTING CONFERENCE,1994.,PROCEEDINGS OF THE KNOXVILLE,TN,USA. 1994 * |
| PIM architectures to support petaflops level computation inthe HTMT machine. KOGGE P M.INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS. 1999 * |
| The Named-State Register File: implementation andperformance. NUTH P R.HIGH-PERFORMANCE COMPUTER ARCHITECTURE,1995. PROCEEDINGS., FIRST IEEE SYMPOSIUM ON RALEIGH,NC,USA. 1995 * |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20050010508A (ko) | 2005-01-27 |
| AU2003225300A1 (en) | 2003-12-19 |
| AU2003225300A8 (en) | 2003-12-19 |
| JP2006502470A (ja) | 2006-01-19 |
| TWI323847B (en) | 2010-04-21 |
| EP1573444A2 (en) | 2005-09-14 |
| WO2003102723A3 (en) | 2006-04-06 |
| KR100989215B1 (ko) | 2010-10-20 |
| US7117346B2 (en) | 2006-10-03 |
| US20030226001A1 (en) | 2003-12-04 |
| CN1856770A (zh) | 2006-11-01 |
| TW200401195A (en) | 2004-01-16 |
| WO2003102723A2 (en) | 2003-12-11 |
| JP4409427B2 (ja) | 2010-02-03 |
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Legal Events
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| C06 | Publication | ||
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| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: Texas in the United States Patentee after: NXP America Co Ltd Address before: Texas in the United States Patentee before: Fisical Semiconductor Inc. |
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| CP01 | Change in the name or title of a patent holder | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090325 Termination date: 20210507 |
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| CF01 | Termination of patent right due to non-payment of annual fee |