JP2006343342A - Semiconductor testing device and method, and method of manufacturing semiconductor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor testing device having a comparator of a high operation speed with low fluctuation of a leak current. <P>SOLUTION: In this semiconductor testing device for determining a logical value voltage of a response waveform from a semiconductor device, an input part of the comparator is provided with an input buffer circuit, and a pseudo-input buffer circuit of generating a leak current of the quantity same to that from the input buffer circuit. The operation speed of the comparator gets fast thereby, and the leak current is less fluctuated therein. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus for inspecting electrical characteristics of a semiconductor integrated circuit (semiconductor device). In particular, the present invention relates to a semiconductor test apparatus suitable for measuring a minute current. The present invention also relates to a method for testing electrical characteristics and functions of a semiconductor device and a method for manufacturing a semiconductor device.

  A semiconductor test apparatus gives a test waveform of predetermined pattern data to a device under test (a semiconductor device such as an IC or LSI), reads output data of the device under test thereby, and compares it with expected value data prepared in advance. This is to inspect whether there is any problem in the basic operation and function of the device under measurement. A plurality of drivers and comparators corresponding to the input / output terminals of the device under test are provided in the pin electronics of the semiconductor test apparatus that performs input / output to the device under test.

  On the other hand, in the semiconductor device inspection process in the manufacture of semiconductor devices, current consumption during device standby (device quiescent state) corresponding to each node state inside the LSI is one of the pass / fail judgment tests of the device under test by the semiconductor test equipment. There is a test method (Idddq test) for detecting an open, short circuit failure, insulation failure, or the like of the node by measuring (sleep current). FIG. 8 shows the configuration of a semiconductor test apparatus used for such an Iddq test. In FIG. 8, 21 is a device to be measured, 22 is a device drive power supply, 23 is a current measurement unit comprising a current detection unit 231 and a current determination unit 232, and 24 is a driver / comparator unit comprising a pin electronics driver 241 and a comparator 242 ( Pin electronics section 25 and 25 are relays for separating the device under test 21 and the driver / comparator section 24 of the pin electronics. The driver 241 is provided with an electrical switch 243 that sets the driver output impedance to a high impedance state when the comparator 242 receives a signal from the device under measurement 21.

  When performing the Iddq test with such a configuration, the switch 243 is opened to place the driver 241 in a high impedance state, and the current (sleep current) that flows when the device under measurement 21 is in a standby state (device stationary state) is measured by the current measurement unit 23. taking measurement. When a failure such as a short circuit or an open circuit occurs in the device under measurement 21, the current value measured by the current measurement unit 23 changes (detects an abnormal current), and thus the quality of the device under measurement 21 can be determined.

  In such an Iddq test, it is necessary to accurately measure the current flowing through the device under test 21. In the driver 241, the leakage current that flows out (or flows from the device under measurement 21) to the device under measurement 21 can be suppressed to 1 nA or less by the switch 243 set to the high impedance state. However, since the comparator 242 handles a small signal at high speed, it cannot incorporate a switch such as the switch 243 and is always in an operating state, and a leak current of several μA is generated in a comparator using a bipolar transistor. Thus, a large error occurs when measuring a small sleep current.

  As a conventional technique, there is a method of removing the influence of the leakage current of the comparator unit by opening the relay 25 shown in FIG. 8 at the time of the Iddq test, but there is a disadvantage that the operation of the relay 25 takes time and the measurement time becomes long. is there. Further, as described in Patent Document 1, the leakage current of each driver / comparator unit 24 is measured and stored in advance, and correction is performed by calculation based on the leakage current data stored during the Iddq test. However, since there are several thousand pins in the driver / comparator circuit of the semiconductor test equipment, it takes time to measure the leak current in advance, and the temperature fluctuation of the leak test current is large. It is necessary to measure and save the leak current each time the value changes.

  In order to reduce the leakage current of the comparator, a method of correcting a leakage current in a circuit by providing a comparator input circuit (comparator input unit) as a buffer circuit before the comparator has been proposed. FIG. 7 is a circuit diagram of a comparator input circuit of a conventional semiconductor test apparatus. The input / output terminal of the device under test is connected to the input terminal IN of the comparator input circuit. The comparator input circuit includes an input buffer circuit 1 that outputs the output of the device under test input from the input terminal IN to the comparator 10 and a leak current correction circuit 3. The input buffer circuit 1 constitutes a push-pull input unit using bipolar transistors Q1 and Q2, and can take a wide range of input voltages and has a high operating speed. However, the base currents Ibp and Ibn differ from each other between the pnp-type bipolar transistor Q1 and the npn-type bipolar transistor Q2 due to the difference in the current amplification factor, and the leakage current ΔIb = Ibp−Ibn is generated. It will flow as current.

When measuring a minute current such as a sleep current of a device under measurement, if a leakage current at an input / output terminal of a semiconductor test apparatus connected to the device under measurement is large, a measurement error increases. The leakage current correction circuit 3 adjusts the resistance value of the resistor R by wafer laser trimming after manufacturing the IC, and makes the correction current ΔIb ′ flowing into the leakage current correction circuit 3 equal to the leakage current ΔIb. The leakage current Ileak to the terminal IN is made zero.
JP 2001-208801 A

  In the conventional comparator input circuit shown in FIG. 7, the correction current ΔIb ′ of the leakage current correction circuit 3 changes greatly due to temperature changes. In addition, since the output voltage of the device under test changes over a wide range, the voltage between the emitter and collector of the bipolar transistors Q1 and Q2 changes due to the change in the input voltage of the push-pull section (the output voltage of the device under test). The leakage current ΔIb changes. Due to these causes, there is a problem that the fluctuation of the leakage current Ileak is large.

  Furthermore, in the conventional comparator input circuit shown in FIG. 7, the resistance value of the resistor R varies due to variations in wafer laser trimming after IC manufacturing, and variations occur in the correction current ΔIb ′ of the leakage current correction circuit 3. In addition, due to variations in diffusion within the wafer during IC manufacturing, the current amplification factors of the bipolar transistors Q1 and Q2 vary, resulting in variations in the leakage current ΔIb. Due to these causes, the leakage current Ileak has a variation in manufacturing.

  On the other hand, there is a JFET source follower type comparator input circuit in which the source of a junction FET (JFET) is connected to the input terminal. Since the JFET source follower system uses a junction FET as an input, the leakage current can be reduced to several nA or less. However, since the variation in threshold voltage is large, an offset voltage correction circuit is required. A semiconductor test apparatus having a junction FET (JFET) provided with this offset voltage correction circuit has a problem that the operation speed becomes slow particularly when a semiconductor device having a large output amplitude is tested.

  An object of the present invention is to provide a semiconductor test apparatus including a comparator having a high operating speed and a small change in leakage current accompanying a temperature change. Another object is to test a semiconductor device having a large output amplitude.

  Another object of the present invention is to provide a semiconductor test apparatus including a comparator having a high operating speed and a small change in leakage current accompanying a change in input voltage. Another object is to test a semiconductor device having a large output amplitude.

  Another object of the present invention is to provide a semiconductor test apparatus including a comparator having a high operating speed and a small variation in leakage current between the comparators.

  Another object of the present invention is to provide a semiconductor test method that suppresses a measurement error and has a short measurement time when measuring a minute current such as an Iddq test in a static state of a device.

  Another object of the present invention is to efficiently manufacture a semiconductor device.

  In order to achieve the above object, the outline of typical ones of the inventions disclosed in the present application will be briefly described as follows.

  In the semiconductor test apparatus, the comparator of the semiconductor test apparatus has a comparator input unit (comparator input circuit), and the comparator input unit includes an input buffer circuit and a pseudo input buffer circuit. The pseudo input buffer circuit produces substantially the same amount of leakage current as the leakage current from the input buffer circuit.

  Further, in the semiconductor test apparatus, the comparator is connected to the input buffer circuit and the pseudo input buffer circuit, and reduces leakage current generated in the input buffer circuit using leakage current generated in the pseudo input buffer circuit (leakage). Current correction means for reducing the current to zero or a magnitude that does not cause a problem in the test of the semiconductor test apparatus.

  Also, a semiconductor test apparatus having a comparator for determining a logical value voltage of a response waveform from a semiconductor device, wherein an input portion of the comparator has a leakage current equal to a leakage current from the input buffer circuit and the input buffer circuit Is provided with a pseudo input buffer circuit.

  A semiconductor test apparatus for measuring a consumption current of a semiconductor device in a stationary state, wherein a magnitude of a temperature change rate of a leakage current flowing into or out of the semiconductor device to be tested from the semiconductor test apparatus is 0.5 nA / ° C. or more and 5.0 nA / ° C. or less.

  A semiconductor test apparatus for measuring a consumption current of a semiconductor device in a stationary state, wherein a leak current flowing into or out of the semiconductor device to be tested from the semiconductor test apparatus is a temperature change of a comparator of the semiconductor test apparatus. Is 5 ° C. or more and 20 ° C. or less, the amount of the leakage current is 2.5 nA or more and 100 nA or less.

  Also, a semiconductor test method for measuring a consumption current of a semiconductor device in a stationary state, the semiconductor test device having a comparator having an input buffer circuit and a pseudo input buffer circuit, flowing into the semiconductor device to be tested, or the semiconductor device The current consumption in a stationary state of the semiconductor device is measured in a state where the ratio of the temperature change rate of the leakage current flowing out from the semiconductor device is 0.5 nA / ° C. or more and 5.0 nA / ° C. or less.

  A step of forming a circuit element on the semiconductor wafer; a step of forming a wiring for electrically connecting the electrode of the circuit element and an external connection terminal on the semiconductor wafer; and a step of forming a protective film on the semiconductor wafer A method of manufacturing a semiconductor device, the method comprising: dicing the semiconductor wafer; and inspecting the semiconductor device in a state of the semiconductor wafer or in a diced and individualized state. A temperature of a leakage current flowing into or out of a semiconductor device to be tested using a semiconductor test device having a first step of performing an operation test of the device and a comparator having an input buffer circuit and a pseudo input buffer circuit Measures the current consumption of the semiconductor device in a stationary state with a change rate of 0.5 nA / ° C. to 5.0 nA / ° C. That is one having a second step.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  (1) It is possible to provide a semiconductor test apparatus capable of efficiently (in a short time) inspecting a semiconductor device having a high operation speed when measuring a minute current of a device under measurement. For example, it is possible to provide a semiconductor test apparatus capable of efficiently (in a short time) inspecting a minute current measurement such as LSI logic.

  (2) It is possible to provide a test method for a semiconductor device in which a measurement error of a minute current of a device under measurement is suppressed and an inspection accuracy is improved.

  (3) A semiconductor device can be manufactured efficiently.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a diagram showing a schematic configuration of an input unit (comparator input circuit) of a comparator of a semiconductor test apparatus according to an embodiment of the present invention. The comparator input circuit includes an input buffer circuit 11, a pseudo input buffer circuit 12, and a leak current correction circuit 13. The input / output terminal of the device under test is connected to the input terminal IN of the comparator input circuit, and the comparator is connected to the output terminal OUT.

  The input buffer circuit 11 has a push-pull input unit using a bipolar transistor, and outputs the output of the device under test input from the input terminal IN to the comparator connected to the output terminal OUT. Since the input buffer circuit 11 uses a bipolar transistor in the push-pull input section, the operation speed is fast and the voltage range of the device under test can be widened. Due to the difference, a leakage current ΔIb1 is generated.

  The pseudo input buffer circuit 12 has the same push-pull input unit as the input buffer circuit 11 and is provided close to the input buffer circuit 11. Since the pseudo input buffer circuit 12 has the same push-pull input unit as the input buffer circuit 11, the pseudo input buffer circuit 12 generates a leakage current ΔIb 2 that is substantially the same amount as the leakage current ΔIb 1 of the input buffer circuit 11. Since the pseudo input buffer circuit 12 is provided close to the input buffer circuit 11, the fluctuation of the leakage current ΔIb2 due to the temperature change is almost the same as the fluctuation of the leakage current ΔIb1. Further, since the pseudo input buffer circuit 12 is provided close to the input buffer circuit 11, the diffusion in the wafer at the time of manufacturing the IC is almost the same, and the bipolar transistor of the push-pull input portion of the pseudo input buffer circuit 12 is the same. The current amplification factor is substantially the same as the current amplification factor of the bipolar transistor in the push-pull input section of the input buffer circuit 11. Therefore, the variation in the leakage current ΔIb2 due to the variation in the diffusion in the wafer at the time of manufacturing the IC is almost the same as the variation in the leakage current ΔIb1.

  The leak current correction circuit 13 is connected to the input of the input buffer circuit 11 and the input of the pseudo input buffer circuit 12, detects the leak current ΔIb2 flowing through the input of the pseudo input buffer circuit 12, and has the same amount as the detected leak current ΔIb2. The correction current ΔIb2 ′ is drawn from the input of the input buffer circuit 11. As a result, the leak current Ileak (= ΔIb1−ΔIb2 ′ = ΔIb1−ΔIb2) flowing through the input terminal IN of the comparator input circuit becomes almost zero.

  Note that leakage current from the comparator 10 excluding the comparator input section does not flow to the input terminal IN due to the presence of the input buffer circuit 11. Therefore, when the leakage current Ib1 from the input buffer circuit 11 becomes zero due to the leakage current Ib2 of the pseudo input buffer circuit 12, the leakage current from the entire comparator including the comparator input circuit becomes substantially zero.

  In the embodiment, the comparator input circuit is described separately from the comparator 10, but this does not necessarily mean that the comparator 10 and the comparator input circuit are provided separately. As long as the effect of each embodiment is achieved, the comparator input circuit may be included in the comparator or may be provided separately from the comparator.

  Furthermore, the present applicant examined the relationship between the operation speed of the elements constituting the comparator input circuit and the maximum output amplitude. The result is shown in FIG. In FIG. 12, when the operation speed and the maximum output amplitude are taken on a logarithmic axis, the range that can be realized by the JFET source follower system described in the prior art is as follows. It becomes the area | region B below the straight line which passes through this point. That is, even when the offset voltage correction circuit is provided, the operation speed is slow when the output amplitude of the device under measurement is large.

  On the other hand, if the semiconductor testing apparatus includes the comparator described in this embodiment and other embodiments according to the present invention and includes a comparator including a semiconductor element having the characteristics of the region A in FIG. It is possible to inspect a device under test (measured semiconductor device) that is fast and has a large output amplitude.

  FIG. 2 is a diagram showing a schematic configuration of a comparator input unit of a semiconductor test apparatus according to another embodiment of the present invention. The comparator input unit includes an input buffer circuit 11, a pseudo input buffer circuit 12, a leak current correction circuit 13, and a leak current gain adjustment circuit 14. The configuration and operation of the input buffer circuit 11, the pseudo input buffer circuit 12, and the leakage current correction circuit 13 are the same as those in the embodiment shown in FIG.

  Since the output voltage of the device under test changes over a wide range, the voltage between the emitter and the collector of the bipolar transistor of the input buffer circuit 11 changes due to the change in the input voltage at the input terminal IN, and the leakage current ΔIb1 changes. The leak current gain adjustment circuit 14 detects the input voltage of the input terminal IN and takes in the adjustment current Igain according to the input voltage from the input of the input buffer circuit 11 to adjust the current flowing through the input of the input buffer circuit 11. . Thereby, the leakage current gain adjustment circuit 14 absorbs the change of the leakage current ΔIb1 of the input buffer circuit 11 due to the change of the input voltage, and further reduces the fluctuation of the leakage current Ileak (= ΔIb1−ΔIb2′−Igain).

  In the embodiment described above, it is possible to further provide a leakage current offset adjusting means for adjusting the offset of the leakage current Ileak by adjusting the leakage current ΔIb2 of the pseudo input buffer circuit 12. As the leakage current offset adjusting means, an internal circuit of the pseudo input buffer circuit 12 can be used. The leakage current ΔIb2 of the pseudo input buffer circuit 12 can be further brought closer to the leakage current ΔIb1 of the input buffer circuit 11 by the leakage current offset adjusting means, and the leakage current Ileak can be further reduced.

  Examples of the present invention will be described below with reference to the accompanying drawings, but the present invention is not limited to these examples. FIG. 3 is a circuit diagram of an embodiment of the present invention. The bipolar transistors Q1 and Q2 of the input buffer circuit 11 constitute a push-pull input unit having a voltage gain of 1. The transistors Q3 and Qd3 and the transistors Q4 and Qd4 constitute an inverted Darlington unit for driving a comparator connected to the output terminal OUT. Here, the inverted Darlington section composed of the transistors Q3, Qd3, Q4, and Qd4 is not particularly limited to the inverted Darlington connection, and may be another buffer circuit. In the input buffer circuit 11, a leakage current ΔIb1 = Ibp1−Ibn1 is generated due to the difference between the base currents Ibp1 and Ibn1 of the bipolar transistors Q1 and Q2.

  The bipolar transistor Q5 of the pseudo input buffer circuit 12 is the same transistor as the bipolar transistor Q1, and its base current Ibp2 is substantially equal to the base current Ibp1 of the bipolar transistor Q1. The bipolar transistor Q6 is the same transistor as the bipolar transistor Q2, and its base current Ibn2 is substantially equal to the base current Ibn1 of the bipolar transistor Q2. The bipolar transistors Q5 and Q6 constitute the same push-pull input section as the push-pull input section of the input buffer circuit 11. In pseudo input buffer circuit 12, leakage current ΔIb2 = Ibp2−Ibn2 is generated due to the difference between base currents Ibp2 and Ibn2 of bipolar transistors Q5 and Q6. The generated leakage current ΔIb2 is substantially equal to the leakage current ΔIb1 of the input buffer circuit 11. The constant current sources I1 and I3, and I2 and I4 are constant current sources that allow the same amount of current to flow.

  The leak current correction circuit 13 is constituted by a current mirror circuit composed of transistors Q10 and Q11. Resistors R1 and R2 generate bias voltages for the transistors Q10 and Q11. When the leakage current ΔIb2 of the pseudo input buffer circuit 12 flows through the collector of the transistor Q11, the correction current ΔIb2 ′ having the same amount as the leakage current ΔIb2 flows through the collector of the transistor Q10. ΔIb1−ΔIb2 ′ (= ΔIb1−ΔIb2) obtained by subtracting the correction current ΔIb2 ′ from the leakage current ΔIb1 of the input buffer circuit 11 is almost zero. The leakage current correction circuit 13 is not limited to the configuration of the current mirror circuit, and may be any current correction circuit that can draw the same amount of current as the leakage current ΔIb2 of the pseudo input buffer circuit 12.

  When the input voltage at the input terminal IN increases, the base current Ibn1 of the bipolar transistor Q2 of the input buffer circuit 11 increases, and the leakage current ΔIb1 of the input buffer circuit 11 decreases. When the input voltage at the input terminal IN decreases, the base current Ibn1 of the bipolar transistor Q2 of the input buffer circuit 11 decreases and the leakage current ΔIb1 of the input buffer circuit 11 increases.

  The transistor Q12 of the leakage current gain adjustment circuit 14 detects the change in the input voltage as the change in the output of the input buffer circuit 11 by inputting the output of the input buffer circuit 11 to the base via the diode and the voltage dividing resistor. When the input voltage increases and the output of the input buffer circuit 11 increases, the base current of the transistor Q12 increases and the adjustment current Igain flowing through the collector of the transistor Q13 decreases. When the input voltage decreases and the output of the input buffer circuit 11 decreases, the base current of the transistor Q12 decreases and the adjustment current Igain flowing through the collector of the transistor Q13 increases. Thereby, the change of the leakage current ΔIb1 of the input buffer circuit 11 due to the change of the input voltage is absorbed, and the fluctuation of the leakage current Ileak (= ΔIb1−ΔIb2′−Igain) is reduced. The leakage current gain adjustment circuit 14 is not limited to the circuit configuration described above, and may be a circuit that detects a change in the input voltage and corrects an increase / decrease in the leakage current of the input buffer circuit due to the change in the input voltage. That's fine.

  The resistance value of the resistor R3 of the leakage current gain adjustment circuit 14 is adjusted such that, for example, the trimming resistor on the chip is adjusted in the IC operation state by wafer laser trimming after IC manufacture, and the leakage current Ileak is zero when the input voltage is maximum. Adjust so that Here, the wafer laser trimming has been described as an example of one means for changing the resistance value of the resistor R3. However, for example, at least a comparator input unit according to the present application is integrated and integrated using an adjusting means such as a variable resistor outside the chip. Any means that can change the amount of current may be used.

  This embodiment adjusts the leakage current ΔIb2 of the pseudo input buffer circuit 12 by adjusting the current of the constant current source I3 of the pseudo input buffer circuit 12 as an offset adjustment method of the leakage current Ileak. Thereby, leakage current ΔIb2 can be made closer to leakage current ΔIb1, and leakage current Ileak can be further reduced.

  The current of the constant current source I3 is adjusted so that the leakage current Ileak becomes zero when the input voltage is minimum, for example, by adjusting the trimming resistor on the chip by the wafer laser trimming after IC manufacture in the IC operation state. When the current of the constant current source I3 is trimmed, the collector current of the transistor Q5 decreases, the base current Ibp2 decreases, and the leakage current ΔIb2 of the pseudo input buffer circuit 12 decreases. If the current of the constant current source I3 is trimmed as a leakage current offset adjustment method, only one adjustment point is required, and the layout area of the trimming resistor for adjustment may be small.

  FIG. 4 is a circuit diagram of another embodiment of the present invention. The present embodiment adjusts the leakage current ΔIb2 of the pseudo input buffer circuit 12 by adjusting the current of the constant current source I4 of the pseudo input buffer circuit 12 as an offset adjustment method of the leakage current Ileak. Thereby, leakage current ΔIb2 can be made closer to leakage current ΔIb1, and leakage current Ileak can be further reduced. Other circuit configurations are the same as those of the embodiment of FIG.

  The current of the constant current source I4 is adjusted so that the leakage current Ileak becomes zero when the input voltage is minimum, for example, by adjusting the trimming resistance on the chip by the wafer laser trimming after manufacturing the IC in the IC operation state. When the current of the constant current source I4 is trimmed, the collector current of the transistor Q6 decreases, the base current Ibn2 decreases, and the leakage current ΔIb2 of the pseudo input buffer circuit 12 increases. If the current of the constant current source I4 is trimmed as a method for adjusting the offset of the leakage current, only one adjustment point is required, and the layout area of the trimming resistor for adjustment may be small.

  FIG. 5 is a circuit diagram of still another embodiment of the present invention. This embodiment adjusts the leakage current ΔIb2 of the pseudo input buffer circuit 12 by adjusting the currents of the constant current source I3 and the constant current source I4 of the pseudo input buffer circuit 12 as an offset adjustment method of the leak current Ileak. is there. Thereby, leakage current ΔIb2 can be made closer to leakage current ΔIb1, and leakage current Ileak can be further reduced. Other circuit configurations are the same as those of the embodiment of FIG.

  As for the currents of the constant current source I3 and the constant current source I4, the leakage current Ileak becomes zero when the input voltage is minimum, for example, by adjusting the trimming resistor on the chip by the wafer laser trimming after IC manufacturing in the IC operation state. Adjust as follows. When the current of the constant current source I3 is trimmed, the leakage current ΔIb2 of the pseudo input buffer circuit 12 decreases as in the embodiment of FIG. When the current of the constant current source I4 is trimmed, the leakage current ΔIb2 of the pseudo input buffer circuit 12 increases as in the embodiment of FIG. When the currents of the constant current source I3 and the constant current source I4 are trimmed as a leakage current offset adjustment method, the leakage current ΔIb2 can be adjusted to increase or decrease. Although the method of adjusting the current of the constant current sources I3 and I4 in FIGS. 3, 4 and 5 by using wafer laser trimming as one means has been described, it is not particularly limited to the wafer laser trimming. It is clear that the same effect can be obtained even if the current value is adjusted by the above means.

  FIG. 6 is a circuit diagram of still another embodiment of the present invention. This embodiment adjusts the correction current ΔIb2 ′ of the leak current correction circuit 13 by adjusting the resistance values of the resistors R1 and R2 of the leak current correction circuit 13 as an offset adjustment method of the leak current Ileak. As a result, the correction current ΔIb2 ′ of the leakage current correction circuit 13 can be made closer to the leakage current ΔIb1 of the input buffer circuit 11, and the leakage current Ileak can be further reduced. Other circuit configurations are the same as those of the embodiment of FIG.

  The resistance values of the resistors R1 and R2 are adjusted so that the leakage current Ileak becomes zero when the input voltage is minimum, for example, by adjusting the trimming resistor on the chip in the IC operation state by wafer laser trimming after IC manufacturing. . By trimming the resistance value of one of the resistors R1 and R2, the correction current ΔIb2 ′ flowing through the collector of the transistor Q10 can be adjusted to increase or decrease. Here, the resistance values of the resistors R1 and R2 are not limited to wafer laser trimming, but may be varied by other means, and the current flowing through the resistors R1 and R2 may be controlled as described above. It is clear from the explanation.

  In the above description, the circuit configuration and the like for reducing the leakage current flowing from the comparator into the semiconductor device (IC, LSI, etc.) that is the device to be measured or flowing out from the semiconductor device have been described. Next, the relationship between the amount of leakage current (leakage current value) measured using the circuit described above and the temperature of the comparator of the semiconductor test apparatus (temperature characteristics of leakage current) will be described with reference to FIG.

  The amount of leakage current is the amount of current that flows from the comparator to the device under test when the device under test is stationary, the driver of the semiconductor test device is in a high impedance state, and the comparator is connected to the device under test. Say. Note that the amount of leakage current may also mean the amount of current that flows out from the device under test to the comparator. Further, the temperature of the comparator (the temperature of the circuit element used for the comparator) is measured using an element for temperature measurement at the stage of manufacturing the comparator.

  As shown in FIG. 9, when a conventional IC (semiconductor device) is used as the comparator, it can be seen that the leakage current greatly increases with the temperature change of the semiconductor test device. In the conventional IC, the absolute value of the temperature change (characteristic) of the leak current flowing into the object to be measured is about 10 to 20 nA / ° C. If the leakage current flowing into the measurement target is large, measure the current consumption in the stationary state of the measurement target (consumption current (sleep current) during device standby corresponding to each internal node state such as LSI), and that node. A test (Iddq test) for detecting an open circuit or a short circuit failure is not accurately performed.

  When the temperature rise of the semiconductor test equipment (temperature rise of the comparator IC) is suppressed by the air cooling method, the temperature variation tolerance is about 10 to 30 ° C. by the air cooling method. For example, when the temperature variation tolerance is about 20 ° C., the semiconductor test The fluctuation amount of the leakage current accompanying the temperature rise of the apparatus is about 200 nA to 400 nA. When the temperature rise is suppressed by the water cooling method, the allowable temperature fluctuation amount is about 3 to 7 ° C. in the water cooling method. For example, when the allowable temperature fluctuation amount is about 5 ° C., the fluctuation amount of the leakage current accompanying the temperature rise of the semiconductor test apparatus is About 50 nA to 100 nA. However, the water cooling method has a problem that the cooling structure is complicated and it is difficult to reduce the size.

  On the other hand, when the device under test is a general semiconductor memory (DRAM or the like), the allowable leak current in the test of the semiconductor device varies depending on the type and is not as severe as LSI logic. For example, in the case of a semiconductor memory (DRAM or the like) having an allowable range of about ± 500 nA, even a semiconductor test apparatus having a conventional IC for a comparator is not a big problem. However, when inspecting a semiconductor device including LSI logic, the allowable leak current in the semiconductor device test varies depending on the type, but the allowable range is about ± 10 to 100 nA (smaller is better). In addition, measurement is difficult with a semiconductor test apparatus equipped with a conventional IC.

  The semiconductor test apparatus including the comparator described in the above embodiment (IC including the comparator) has the performance of the region A shown in FIG. 12, and the temperature change rate (temperature characteristic) of the leakage current is about 0.5 nA / ° C. It is characterized by being suppressed to 5.0 nA / ° C. or less. Desirably, the temperature change rate of the leakage current is suppressed to about 0.5 nA / ° C. to 2.0 nA / ° C. Thus, by providing a semiconductor test apparatus capable of increasing the allowable range of temperature control of a comparator in a semiconductor test apparatus when measuring a minute current in a stationary state of a device under test by reducing the temperature change rate of the leakage current. Can do.

  For example, when the temperature rise rate of an IC including a comparator having a leak current temperature change rate of about 0.5 nA / ° C. to 5.0 nA / ° C. is suppressed by an air cooling method with a temperature fluctuation tolerance of about 20 ° C. The temperature rise of the device is about 10 nA to 100 nA. In the case of using a water cooling method in which the allowable temperature variation is about 5 ° C., the temperature rise of the semiconductor test apparatus is about 2.5 nA to 25 nA. In addition, when the temperature rise rate of the IC including the comparator whose leak current temperature change rate is about 0.5nA / ° C or more and 2.0nA / ° C or less is suppressed by the air cooling method with a temperature fluctuation tolerance of about 20 ° C, The temperature rise of the device is about 10 nA to 40 nA. In the case of using the water cooling method in which the allowable temperature fluctuation is about 5 ° C., the temperature rise of the semiconductor test apparatus is about 2.5 nA to 10 nA.

  As described above, even if not only the water cooling method but also the air cooling method is used, the measurement of the minute current of the semiconductor device including the LSI logic can be inspected. In addition, the semiconductor test apparatus can be downsized by using the air cooling method.

  Finally, a semiconductor device test method and a semiconductor device manufacturing method using test waveforms from the semiconductor test device described in the above embodiment will be described.

  FIG. 10 is a flowchart showing a method of manufacturing a semiconductor device that is inspected and shipped using the test waveform formed in the above embodiment. In FIG. 10, the product wafer manufactured in the process of step S1 is subjected to initial defect selection by P inspection (Pellet inspection) in step S2. Then, the selected non-defective wafer proceeds to step S3 or S5. The selection of whether to proceed to step S3 or S5 is selected from the relationship of manufacturing equipment or the like.

  In step S3, the product wafer is diced, and only non-defective chips are individually packaged in CSP (Chip Size Package), BGA (Ball Grid Array) or the like in step S4. Then, the process proceeds to step S7. In step S5, the wiring pattern and the protective film are further formed on the wafer all at once, and further, solder balls are attached. Subsequently, in step S6, the wafer on which the wiring pattern or the like is formed is divided into individual pieces by dicing. Then, the process proceeds to step S7. In step S7, a semiconductor device inspection method is performed. In other words, the final shaped products divided individually are subjected to a burn-in test and finally selected. And what finally became a good product is shipped in step S8.

  In this embodiment, the inspection is performed in at least S2 or S7 in FIG. 10 using the semiconductor test apparatus and the test method described in the above embodiment. The inspection process includes measurement of an operation test and measurement of a minute current of a device under measurement. In the measurement of the operation test, a test waveform formed by the semiconductor test apparatus 100 shown in FIG. 11 is used to test the high speed operation of the IC under test 112 to be measured.

  The semiconductor test apparatus 100 gives a test waveform to the IC under test 112, compares the response waveform returned from the IC under test 112 with the expected value prepared in advance, and performs an operation test of the IC under test 112. It is a device to perform. Specifically, the timing generator 105 uses the original clock supplied from the reference signal generator 104 to determine a test clock cycle clock, applied test signal timing, and response signal determination timing (rising / rising). The edge clock that determines the timing of falling is generated. These edge clocks are supplied to the waveform formatter 107 and the digital comparator 108 through a delay circuit (not shown) for adjusting the phase shift between the edge clocks.

  The pattern generator 106 generates test pattern data including information on test waveforms and expected values. The waveform formatter 107 receives a test waveform timing edge indicating the rise / fall timing of the test waveform from the timing generator 105, receives test pattern data from the pattern generator 106, and serves as a reference for the test waveform. It is formed and output to the driver 102 as a test waveform. In the driver 102, the reference voltage and amplitude are adjusted and applied to the IC under test 112 so that the reference of the test waveform output from the waveform formatter 107 matches the signal level of the IC under test 112. The comparator 103 uses the reference voltage supplied from the comparison (reference) voltage generator 109 to match the response signal with the signal level of the comparison determination circuit, and outputs the logical value voltage (L / L) of the response waveform returned from the IC under test 112. H) is determined. If the determined voltage value is satisfied, the digital comparator 108 determines the expected value sent from the pattern generator 106. If the response result does not match the expected value, the IC is determined to be defective, and the defect determination result is written to the fail memory.

  On the other hand, the measurement of the minute current in the stationary state of the device under test (IC under test) is performed by the method described in the above embodiment. Here, a minute current in a stationary state of the device under measurement is measured using the same semiconductor test apparatus as that used for the operation test.

  In the manufacture of the semiconductor device according to this embodiment, the semiconductor test process can be performed efficiently and accurately, so that the semiconductor device can also be manufactured efficiently.

  Although the invention made by the present applicant has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Not too long.

  Representative aspects disclosed in the above embodiment are as follows.

  (1) A comparator having a push-pull input unit using a bipolar transistor, having a push-pull input unit that inputs the output of the device under test and outputs the measured device to the comparator, A pseudo buffer means provided close to the buffer means, and a current correction means for taking out from the input of the push-pull input section of the buffer means the same amount of current flowing through the input of the push-pull input section of the pseudo buffer means. It is a thing.

  Since the pseudo buffer means has the same push-pull input section as the buffer means, it is possible to generate a leakage current substantially equal to the leakage current of the buffer means. Further, since the pseudo buffer means is provided close to the buffer means, the fluctuation of the leakage current due to the temperature change is almost the same between the buffer means and the pseudo buffer means. In addition, since the diffusion in the wafer at the time of manufacturing the IC is almost the same, the current amplification factor of the bipolar transistor in the push-pull input portion is almost the same between the buffer means and the pseudo-buffer means. Accordingly, the variation in leakage current due to the variation in diffusion in the wafer during IC manufacturing is almost the same between the buffer means and the pseudo buffer means. By taking out the same amount of current as the leakage current of the pseudo buffer means from the leakage current of the buffer means by the current correction means, the leakage current as a whole can be made substantially zero.

  (2) Comparator having a push-pull input unit using a bipolar transistor, having a buffer means for inputting the output of the device under test and outputting it to the comparator, and a push-pull input part same as the buffer means Current correction for extracting from the input of the push-pull input section of the buffer means a current equivalent to the current flowing in the input of the push-pull input section of the pseudo-buffer means and the pseudo-buffer means provided close to the buffer means And a first current adjusting means for adjusting a current flowing through the input of the push-pull input section of the buffer means according to the input voltage of the push-pull input section of the buffer means.

  The first current adjusting means can absorb the change of the leakage current of the buffer means due to the change of the input voltage of the push-pull unit, and can further reduce the fluctuation of the entire leakage current.

  (3) The comparator described in (1) or (2) above, further comprising (second) current adjusting means for adjusting the current flowing to the input of the push-pull input unit of the pseudo buffer means. is there. By this current adjusting means, the leakage current of the pseudo buffer means can be made closer to the leakage current of the buffer means, and the overall leakage current can be further reduced.

  (4) A semiconductor test apparatus for inspecting the basic operation and function of the device under measurement, comprising the comparator according to any one of (1) to (3) above. As a result, an error caused by a leakage current at the time of measuring a minute current, which is a drawback of the conventional technique, is reduced, and it is not necessary to measure the leakage current in advance in order to reduce the error. In addition, it is possible to eliminate the disadvantage that the measurement time is increased by re-measuring the leak current every time the temperature environment changes at the time of measurement. Further, it is possible to prevent an increase in measurement time due to opening and closing of a relay between the device and the comparator input.

  (5) A semiconductor test apparatus having a comparator for determining a logical value voltage of a response waveform from a semiconductor device, wherein an input portion of the comparator has a leakage equivalent to a leakage current from the input buffer circuit and the input buffer circuit A pseudo input buffer circuit for generating a current is provided.

  (6) The semiconductor test apparatus according to (5), wherein the comparator of the semiconductor test apparatus is connected to the input buffer circuit and the pseudo input buffer circuit and generates a leakage current generated in the pseudo input buffer circuit. The current correction means is used to reduce the current flowing from the input buffer circuit to the semiconductor device to be tested.

  (7) In the semiconductor test apparatus described in (6) above, the comparator of the semiconductor test apparatus detects the voltage of the semiconductor device to be tested, and from the input buffer circuit to the semiconductor device to be tested A second current correction unit for further correcting the flowing current is provided.

  (8) A semiconductor test apparatus for measuring the consumption current of a semiconductor device in a stationary state, wherein the magnitude of the rate of change in temperature of the leak current flowing into or out of the semiconductor device to be tested from the semiconductor test apparatus is 0 0.5 nA / ° C. or more and 5.0 nA / ° C. or less.

  (9) A semiconductor test apparatus for measuring a consumption current of a semiconductor device in a stationary state, wherein a leak current flowing into or out of the semiconductor device to be tested from the semiconductor test apparatus is detected by a comparator of the semiconductor test apparatus. When the temperature change is 5 ° C. or more and 20 ° C. or less, the amount of the leakage current is 2.5 nA or more and 100 nA or less.

  (10) In the semiconductor test apparatus according to (8) or (9) above, when the relationship between the operation speed of the semiconductor test apparatus and the maximum output amplitude is expressed by logarithm, the operation speed is 50 MHz and the maximum amplitude is 18V. With a straight line passing through two points of an operating speed of 700 MHz and a maximum amplitude of 2V as a threshold value, the operating performance is higher than the threshold value.

  (11) The semiconductor test apparatus according to any one of (8) to (10), wherein the comparator of the semiconductor test apparatus includes an input buffer circuit and a pseudo input buffer circuit, and the input buffer circuit And the pseudo input buffer circuit have substantially the same leakage current.

  (12) The semiconductor test apparatus according to (11), wherein the comparator of the semiconductor test apparatus is connected to the input buffer circuit and the pseudo input buffer circuit and generates a leakage current generated in the pseudo input buffer circuit. And a current correcting means for reducing a current flowing from the input buffer circuit to the semiconductor device.

  (13) The semiconductor test apparatus according to (11) or (12) above, wherein the voltage of the semiconductor device to be tested is detected and flows from the input buffer circuit to the semiconductor device to be tested, or the semiconductor There is provided a second current correcting means for further correcting the current flowing out of the apparatus.

  (14) The semiconductor test apparatus according to any one of (4) to (13), wherein the semiconductor test apparatus includes an air cooling unit as a cooling unit.

  (15) The semiconductor test apparatus according to any one of (4) to (13), wherein the semiconductor apparatus includes an LSI logic circuit.

  (16) A semiconductor testing method for measuring a consumption current of a semiconductor device in a stationary state, wherein the semiconductor device flows from a semiconductor testing device having a comparator having an input buffer circuit and a pseudo input buffer circuit to a semiconductor device to be tested, or a semiconductor This is a semiconductor test method for measuring the static current consumption of a semiconductor device in a state where the rate of change in temperature of the leakage current flowing out of the device is 0.5 nA / ° C. or more and 5.0 nA / ° C. or less.

  (17) A step of forming circuit elements on the semiconductor wafer, a step of forming wirings for electrically connecting the electrodes of the circuit elements and external connection terminals on the semiconductor wafer, and a protective film being formed on the semiconductor wafer A method for manufacturing a semiconductor device, the method comprising: a step of dicing the semiconductor wafer; and a step of inspecting the semiconductor device in a state of the semiconductor wafer or in a diced and individualized state. First step of performing an operation test of a semiconductor device, and a temperature of a leakage current flowing into or out of the semiconductor device to be tested using a semiconductor test device having a comparator having an input buffer circuit and a pseudo input buffer circuit Measure the current consumption of the semiconductor device in a stationary state with the change rate being 0.5 nA / ° C. or more and 5.0 nA / ° C. or less. It is a manufacturing method of a semiconductor device having a second step.

It is a figure which shows schematic structure of the comparator input part of the semiconductor testing apparatus by one embodiment of this invention. It is a figure which shows schematic structure of the comparator input part of the semiconductor test apparatus by other embodiment of this invention. It is a circuit diagram of one example of the present invention. It is a circuit diagram of the other Example of this invention. FIG. 6 is a circuit diagram of still another embodiment of the present invention. FIG. 6 is a circuit diagram of still another embodiment of the present invention. It is a circuit diagram of the comparator input part of the conventional semiconductor test apparatus. It is a figure which shows the structure of the semiconductor test apparatus used for an Iddq test. It is a figure which shows the relationship between leakage current and the temperature of IC containing the comparator of a semiconductor device. It is a figure which shows the manufacturing process of a semiconductor device. It is a block diagram of a semiconductor test apparatus. It is a figure which shows the relationship between the operation speed of a comparator component, and the maximum output amplitude.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Input buffer circuit, 12 ... Pseudo input buffer circuit, 13 ... Leakage current correction circuit, 14 ... Leakage current gain adjustment circuit

Claims (13)

A semiconductor test apparatus having a comparator for determining a logical value voltage of a response waveform from a semiconductor device,
The semiconductor test apparatus characterized in that the input section of the comparator includes an input buffer circuit and a pseudo input buffer circuit that generates a leakage current of the same amount as the leakage current from the input buffer circuit. The semiconductor test apparatus according to claim 1,
The comparator of the semiconductor test apparatus is connected to the input buffer circuit and the pseudo input buffer circuit, and flows from the input buffer circuit to the semiconductor device to be tested using a leakage current generated in the pseudo input buffer circuit, or A semiconductor test apparatus comprising current correcting means for reducing a current flowing out of a semiconductor device. The semiconductor test apparatus according to claim 2,
The comparator of the semiconductor test apparatus detects a voltage of the semiconductor device to be tested, and a second current correction for further correcting a current flowing from the input buffer circuit to the semiconductor device to be tested or flowing out of the semiconductor device A semiconductor testing apparatus comprising means. A semiconductor test apparatus for measuring a consumption current of a semiconductor device in a stationary state,
A semiconductor test characterized in that the magnitude of the temperature change rate of the leakage current flowing into or out of the semiconductor device to be tested from the semiconductor test device is 0.5 nA / ° C. or more and 5.0 nA / ° C. or less. apparatus. A semiconductor test apparatus for measuring a consumption current of a semiconductor device in a stationary state,
The leak current that flows into or out of the semiconductor device to be tested from the semiconductor test apparatus is the amount of the leak current when the temperature change of the comparator of the semiconductor test apparatus is 5 ° C. or more and 20 ° C. or less. 5. A semiconductor test apparatus characterized by being 5 nA or more and 100 nA or less. A semiconductor test apparatus according to claim 4 or 5, wherein
When the relationship between the operation speed and the maximum output amplitude of the semiconductor test apparatus is expressed by logarithm, the threshold value is a straight line passing through two points of operation speed 50 MHz, maximum amplitude 18 V, operation speed 700 MHz, and maximum amplitude 2 V A semiconductor test apparatus characterized by having an operating performance higher than a threshold value. A semiconductor test apparatus according to any one of claims 4 to 6,
The comparator of the semiconductor test apparatus has an input buffer circuit and a pseudo input buffer circuit, and the leakage currents of the input buffer circuit and the pseudo input buffer circuit are substantially the same amount. The semiconductor test apparatus according to claim 7,
The comparator of the semiconductor test apparatus is connected to the input buffer circuit and the pseudo input buffer circuit, and uses current leakage generated in the pseudo input buffer circuit to reduce current flowing from the input buffer circuit to the semiconductor device. A semiconductor testing apparatus comprising means. A semiconductor test apparatus according to claim 7 or claim 8, wherein
And a second current correcting unit for detecting a voltage of the semiconductor device to be tested and further correcting a current flowing from the input buffer circuit to the semiconductor device to be tested or flowing out of the semiconductor device. Semiconductor test equipment. A semiconductor test apparatus according to any one of claims 1 to 9,
The semiconductor test apparatus comprises an air cooling means as a cooling means. A semiconductor test apparatus according to any one of claims 1 to 10,
A semiconductor test apparatus, wherein the semiconductor apparatus includes an LSI logic circuit.   4. The magnitude of the rate of change in temperature of the leak current flowing from the semiconductor test apparatus having the comparator having the input buffer circuit and the pseudo input buffer circuit to the semiconductor device to be tested or flowing out of the semiconductor apparatus is 0.5 nA / ° C. or more. A semiconductor test method, wherein the consumption current of the semiconductor device in a stationary state is measured in a state of 0 nA / ° C. or less. Forming a circuit element on a semiconductor wafer; forming a wiring for electrically connecting an electrode of the circuit element and an external connection terminal on the semiconductor wafer; forming a protective film on the semiconductor wafer; A method for manufacturing a semiconductor device, comprising: a step of dicing the semiconductor wafer; and a step of inspecting the semiconductor device in a state of the semiconductor wafer or in a diced and individualized state,
The inspection step flows into a semiconductor device to be tested using a first step of performing an operation test of the semiconductor device and a semiconductor test device having a comparator having an input buffer circuit and a pseudo input buffer circuit, or a semiconductor device And a second step of measuring the consumption current of the semiconductor device in a stationary state in a state where the ratio of the temperature change rate of the leakage current flowing out of the semiconductor device is 0.5 nA / ° C. or more and 5.0 nA / ° C. or less. A method for manufacturing a semiconductor device.

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