JP2003045929A - Method for testing semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a testing method on the basis of source current in static state of a semiconductor integrated circuit by which the determination of good or no-good is exactly made even if there are manufacturing variations. SOLUTION: The testing method for making the determination of good or no-good by means of a current test in static state in a wafer level testing step 5 of the semiconductor integrated circuit is characterized in that the reference current value for judging soundness is determined for each product on the basis of characteristic values of a transistor in a basic characteristics measurement step 2 for determination.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting a semiconductor integrated circuit, and more particularly to a method for inspecting the quality of a semiconductor integrated circuit constituting a CMOS logic circuit by a quiescent current test.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits typified by LSIs have become finer and more complicated, such as system-on-chip (SoC: so-called system LSI).
As the scale is increasing, the inspection and testing methods are becoming complicated. In particular, in a large-scale integrated circuit of CMOS, a method of measuring a leak current in a stationary state to detect a defect is becoming mainstream in order to simplify the inspection test method. A CMOS logic circuit has a property that a large current flows only when the state of an internal circuit or an internal node transits and almost no current flows when it is stationary. The quiescent-state current test method utilizes this property to detect a circuit abnormality by performing a test called Iddq for detecting an abnormal value of a quiescent-state power supply current. In CMOS logic circuits, Iddq is usually close to zero. CMO without abnormality
In the S logic circuit, the power supply current flows in pulses only when the internal state transitions, whereas when the internal circuit has a defect or the like, Iddq does not become 0, and a leak current flows even in a stationary state. The quality of the device can be determined by detecting this leak current.

However, when Iddq is used for actual product inspection, some difficulties are encountered. The subthreshold leakage current Ileak having a close relationship with Iddq can be approximated by the following equation.

Ileak = exp (-Vt (S / ln10)) where Vt is the threshold value of the MOSFET and S is the subthreshold coefficient. As can be seen from this equation, assuming that S is around 80 mV / decade, for example, if Vt changes by 0.1 V, Ileak changes by one or two digits. From another perspective,
As shown in FIG. 3, since the Vt is relatively uniform between the elements of a single lot, the judgment reference current value can be easily determined.
However, if the manufacturing variation is added to Vt as in the case of mass production of the product, as shown in FIG. 4, the judgment reference current value fluctuates greatly and the judgment cannot be made at all. Therefore, a method for making a pass / fail judgment of a quiescent current test that can be judged even in mass production of products has been desired.

[0005]

As described above, in the conventional inspection method for detecting the quiescent power supply current, the current value serving as the pass / fail judgment standard is easily determined for a single lot of products, and Although the effect is great, when a mass-produced product is inspected, there is a risk that the judgment reference value will fluctuate significantly due to manufacturing variations, and a good product will be judged as defective and removed, or conversely a defective product will be judged as good. Be done. An object of the present invention is to solve this problem by a relatively simple method and to realize an inspection method based on a quiescent state power supply current of a semiconductor integrated circuit in which a quality determination is correctly performed even if there is a manufacturing variation.

[0006]

In order to achieve the above object, the present invention provides a judgment reference current value, which is a quality judgment reference, in an inspection method by a quiescent current test of a semiconductor integrated circuit having a CMOS logic circuit. It is characterized in that it is determined for each product based on the characteristic value of the transistor and the quiescent current test is determined. As a result, it is possible to realize the inspection method based on the quiescent power supply current of the semiconductor integrated circuit in which the determination reference current value is determined for each lot and the quality determination is accurately performed even if there is manufacturing variation.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As a result of intensive studies made by the present inventor in view of the above-mentioned problems, in order to determine the quality of a quiescent current test even during mass production of products, a monitor transistor such as a threshold voltage is used. It has been found that it is preferable to determine the pass / fail judgment value for each chip based on the measurement results. The present invention is proposed based on this finding, and is characterized in that, in a quiescent current test of a CMOS logic circuit, its quality is judged for each product based on a transistor characteristic value. According to the present invention, a static current test (standby current or Iddq) that is minute and may cause overkill (a good product is determined to be defective) or defective product on the market (deteriorates early during use) unless properly set. (Referred to as “the value”) is determined for each chip or group of units by using the value of the transistor characteristic (threshold value, drain current or leak current) representative of the characteristic of the LSI measured in advance. Is the biggest point.

A semiconductor integrated circuit inspection method according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a conceptual diagram showing a work flow for manufacturing a semiconductor integrated circuit according to the present invention. Further, FIG. 2 is a conceptual diagram showing a work flow for manufacturing a conventional semiconductor integrated circuit. 1 and 2, reference numeral 1 is a wafer manufacturing process, and reference numeral 2 is a basic characteristic measuring process (1st pellet che).
ck: includes measurement of transistor characteristics), reference numeral 3 is a production test lot step, reference numeral 4 is a quality determination reference determination step, reference numeral 5 is a wafer state test step (including quiescent state current measurement), reference numeral 6 is selection (2nd) pelletchec
k) step, reference numeral 7 is a chip assembling step, reference numeral 8 is a shipping test step, reference numeral 9 is a final check step, and reference numeral 10 is a shipping step.

Conventionally, with respect to the wafer manufactured in the wafer manufacturing process 1, the judgment standard is determined in the pass / fail judgment standard process 4 in consideration of the variation grasped in the production test lot process 3, and the wafer state test 5 is stopped. The state current is measured, and the result is used for screening 6, and after the product is manufactured in the chip assembling step 7, a shipping test 8 is carried out, and the result is selected 9 for shipping. In the present invention, specifically, as described above, the fact that there is a correlation between the value of the transistor characteristic such as the threshold value and the current value in the quiescent state is utilized, and as shown in FIG. Before measuring the quiescent current in the wafer state test step 5 in the conventional manufacturing process, the basic characteristic measurement step 2 such as transistor characteristics is inserted, and the measured value and the test lot group for production in advance are inserted. The quality judgment value of the lot is obtained from the variation grasped in. Although not shown in FIG. 2, if the existing basic characteristic measuring step is used, the number of steps is not particularly increased in the present invention, and it can be said that the effect is great even though it is simple.

[Embodiment 1] An example in which the present invention is used for testing a large-scale LSI having a 0.15 μm process will be described. The work flow is as shown in FIG. 1. First, as a step of measuring the basic characteristics after completion of the wafer manufacturing test, the threshold Vt of the monitor transistor (L: 150 nm, W: 10 μm) is measured and NMOS: 300 mV. PMOS: -300m
A value of V was obtained. Therefore, the determination reference value of Iddq is set to 100 μA using the dependency relationship between the threshold of the production test lot group (100 lots) and Iddq.
As a result, according to the present embodiment, proper selection can be performed, and the market defect rate due to the current abnormality can be kept at a sufficiently low level.

[Second Embodiment] The present invention is similar to the first embodiment.
An example used for testing a large-scale LSI of 0.15 μm process will be shown. The work flow is as shown in FIG. 1. First, as a basic characteristic measurement process after the completion of wafer manufacturing, as a drain current of a monitor transistor (L: 150 nm, W: 10 μm), NMOS: 5.5 mA, PMOS: −1. ．
A value of 7 mA was obtained. Therefore, the drain current and Iddq of the pre-production test lot group (1000 lots)
Iddq judgment reference value is 100 μA
I decided. As a result, it is possible to perform proper selection according to the present embodiment as well, and it is possible to keep the market defect rate due to the current abnormality at a sufficiently low level.

[Embodiment 3] Similar to Embodiments 1 and 2, an example in which the present invention is used for testing a large-scale LSI having a 0.15 μm process will be described. The work flow is as shown in FIG. 1. First, as a basic characteristic measuring process after the completion of wafer manufacturing, a monitor transistor (L: 150 nm, W: 10
μm) leakage current value is NMOS: 5 nA, PMO
A value of S: -2 μA was obtained. Therefore, the leak current value and Id of the test lot group (100 lots) for production in advance are set.
The criterion value for dq was set to 100 μA. This allows
According to this example, proper selection could be performed, and the market defect rate due to current abnormality could be kept at a sufficiently low level.

Although the present invention has been described based on three embodiments, the present invention is not of course limited to the above-mentioned embodiments, and the type of LSI, the observed current, and the transistor to be selected. It goes without saying that the type of characteristics and the like can be appropriately selected without departing from the spirit of the present invention. By using the present invention, it is possible to make an appropriate determination without excess or deficiency of the semiconductor integrated circuit using the quiescent power supply current,
In addition, it is possible to realize product selection with significantly reduced market defects.

[0015]

As described above, according to the invention of claim 1 of the present invention, in the inspection method by the quiescent current test of the semiconductor integrated circuit, the reference current value serving as the pass / fail judgment criterion is based on the characteristic value of the transistor. It is characterized in that it is determined for each product and judged. As a result, it is possible to make an appropriate judgment without excess or deficiency in consideration of the variation between manufacturing lots, and to realize a semiconductor integrated circuit inspection method capable of product selection with significantly reduced overkill and market defects. be able to.

The invention according to claim 2 of the present invention is characterized in that the judgment reference current value serving as the quality judgment reference is changed according to a typical characteristic value of the transistor measured in advance. As a result, it is possible to select the optimum reference current value for the quiescent current from the transistor characteristic values, and to realize a semiconductor integrated circuit inspection method that enables product selection with significantly reduced overkill and market defects. it can.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing a manufacturing work flow of a semiconductor integrated circuit of the present invention.

FIG. 2 is a conceptual diagram showing a manufacturing work flow of a conventional semiconductor integrated circuit.

FIG. 3 is a diagram showing a chip distribution with respect to a quiescent current in a single lot.

FIG. 4 is a view showing a chip distribution with respect to a quiescent current in a plurality of lots in a manufacturing stage.

[Explanation of symbols]

1 ... Wafer manufacturing process, 2 ... Basic characteristic measuring process, 3 ... Production test lot process, 4 ... Pass / fail judgment standard determining process, 5
... Wafer state test process, 6 ... Sorting process, 7 ... Chip assembly process, 8 ... Shipping test process, 9 ... Sorting process, 10 ... Shipping process.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/8238 H01L 27/08 321Z 27/092 (72) Inventor Masago Sakai 2 Hyakudohama, Sawara-ku, Fukuoka-shi, Fukuoka C-No. 3-2 Sony Semiconductor Kyushu Co., Ltd. F term (reference) 2G003 AA10 AB01 AF06 AH02 2G132 AA01 AB00 AC03 AD01 AG09 AL12 4M106 AA01 AA07 AB01 BA14 CA04 CA32 CA56 CA70 5F048 AB10 AC03 BA01 BB14

Claims (2)

[Claims] 1. In a method for inspecting a semiconductor integrated circuit including a CMOS logic circuit by a quiescent state current test, a judgment reference current value serving as a pass / fail judgment standard is determined for each product based on a characteristic value of a transistor, and a quiescent state is determined. A method for inspecting a semiconductor integrated circuit, which comprises determining a current test. 2. The method for inspecting a semiconductor integrated circuit according to claim 1, wherein the judgment reference current value serving as the quality judgment reference is changed according to a typical characteristic value of the transistor measured in advance.