JP2008128949A - Method for determining static power supply current value of semiconductor device and failure detection method of semiconductor device using the above method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for determining value and also detecting failure of static power supply current which can detect abnormality in the static power supply current value with higher sensitivity and reliability, depending on increase and variation range of off-leak current capacity due to process miniaturization. <P>SOLUTION: This method is characterized by comprising a step of running simulations of the static power supply current of a semiconductor device in a plurality of logic states and then obtain an average value IDDgave, variation range a and standard deviation σ of the static power supply current from the results of these simulations, and a process to determine the static power supply current value ΔIDDq of the semiconductor device based on the above-obtained average value IDDgave, variation range a and standard deviation σ of the static power supply current. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a static power supply current value testing method for testing an abnormality of a static power supply current value of a semiconductor device.

  A CMOS circuit included in a semiconductor device has a structure in which no DC current path exists when there is no defect, and only a small off-leakage current flows in a steady state after the input is determined. For this reason, if there is a fault location that causes an abnormal current leak in a semiconductor device using a CMOS circuit, it can be distinguished from a normal state by measuring the power supply current value. Using this, the static power supply current IDDq, which is the current in the steady state of the semiconductor device, is measured to determine whether or not there is a failure. ).

  However, in a semiconductor device manufactured using a design rule of approximately 0.18 μm or less, the value of the static power supply current IDDq is in the range of 100 μA to several tens of mA. Therefore, in the pass / fail judgment method in which the judgment value for pass / fail is set to a fixed value that is uniformly determined, and the case where the judgment value deviates from the judgment value is defective, the pass / fail judgment value of the static power supply current IDDq is about several mA to several tens of mA. Set to For this reason, only a fault that generates an abnormal leak current of several mA or more can be detected. If the abnormal leak current is very small, the fault detection capability is greatly reduced.

Therefore, Patent Document 1 focuses on the measured value, variation, and abnormal outlier value of the static power supply current IDDq at a plurality of measurement points of the semiconductor device to be tested, and measures based on the static power supply current value at the measurement point. A measurement point grouping unit that groups points and sets a measurement point group, and a weighted average value calculation unit that calculates a weighted average value that minimizes the sum of variations in static power supply current values due to process condition differences between measurement point groups And a variation value part calculation unit that calculates the maximum value of the variation of the static power supply current value based on the weighted average value, a storage unit that stores the determination criteria for the measurement point group based on the static power supply current value, and the pass / fail determination A technique relating to a test apparatus provided with a pass / fail judgment unit for judging pass / fail of a semiconductor device according to a reference is disclosed.
JP 2005-134255 A

  However, in Patent Document 1, it is necessary to evaluate process variations in creating an algorithm for determining pass / fail, and in order to apply the technique disclosed in Patent Document 1 to a product group of a small variety of products, IDDq test condition setting Enormous time costs. Further, along with an increase in the amount of off-leakage due to process miniaturization, the fluctuation in the amount of off-leakage due to the logic state of the semiconductor device is large, which hinders non-defective product determination, and it is difficult to maintain the failure detection capability.

  The present invention has been made to solve the above problems, and can cope with an increase in the amount of off-leakage current due to process miniaturization and a fluctuation range, and can detect anomalies in static power supply current values with high sensitivity and reliability. A determination value of static power supply current and a failure detection method are provided.

  In order to solve the above problems, the inventors have come up with the idea of using a versatile power simulation that is used for designing semiconductor devices. That is, for each product, a predicted off-leakage current value is obtained by a general-purpose power simulation (also called power consumption simulation), and a plurality of logic states (a combination of signals given to external pins of a semiconductor device; hereinafter also referred to as an address). The simulation result in.) Is reflected in the judgment value of the IDDq test. Therefore, it was verified whether the simulation result of the static power supply current value matches the measurement result of the actual product.

  FIG. 5 shows the measurement results (symbols are marked with ■) and simulation results (symbols are marked with ○) of the 0.13 μm design rule product according to IDDq patterns. The vertical axis shows the obtained (or measured) static power supply current value IDDq, and the horizontal axis shows the number of measured logic states. Further, the vertical axis of the simulation result is corrected by multiplying it by an arbitrary number, and is adjusted to the vertical axis of the measurement result. As can be seen from FIG. 5, it was confirmed that the simulation result can reproduce the fluctuation state in the logic state by multiplying the obtained (or measured) static power supply current value IDDq with respect to the measurement result. If a normal power simulator is used, the average value IDDqave, the fluctuation range a, and the standard deviation σ can be calculated as parameters for representing these fluctuations depending on the logical state.

  Here, the average value IDDqave is the average value of the static power supply current values in all logic states, the fluctuation range a is the fluctuation range of the static power supply current values not caused by the failure depending on the logic state, and the standard deviation σ is the logical value The dispersibility of the static power supply current value depending on the state is shown. Among these, the relationship between the average value IDDqave and the fluctuation range a and the static power supply current value in each logic state is as shown in FIG. The comparison between the actual measurement results and the simulation results was performed for several other types of products, but all showed the same tendency.

  Furthermore, when various IDDq judgment value setting methods were examined, it was found that a method based on the fluctuation range a and the standard deviation σ was suitable.

The gist of the present invention based on the above findings is shown below.
(1) A method for determining a determination value of a static power supply current of a semiconductor device according to the present invention simulates the static power supply current of a semiconductor device in a plurality of logic states, and calculates an average value of the static power supply current from the result of the simulation. A step of obtaining a fluctuation range and a standard deviation, and a step of determining a determination value of the static power supply current of the semiconductor device based on the obtained average value, fluctuation range and standard deviation of the static power supply current. It is characterized by that.
(2) In the method for determining the determination value of the static power supply current of the semiconductor device according to the present invention, the static power supply current of the semiconductor device is simulated in a plurality of logic states, and the average value of the static power supply current is calculated from the result of the simulation. Based on the obtained IDDqave, fluctuation range a and standard deviation σ, and the average value IDDqave, fluctuation range a and standard deviation σ of the obtained static power supply current, a range ΔIDDq satisfying the following expression (a): And a step of determining and determining a static power supply current.
IDDqave− (a + 3 × σ) ≦ ΔIDDq ≦ IDDqave + (a + 3 × σ) (a)
(3) A failure detection method for a semiconductor device according to the present invention is a method for determining a determination value of a static power supply current as described in (1) or (2) above. Measuring the static power supply current of the device, calculating an average value of the static power supply current from the result of the measurement, comparing the calculated average value with the predetermined determination value, the average value is And a step of determining a non-defective product within the range of the determination value.

  According to the present invention, it is not necessary to evaluate the reference sample for determining the determination value of the static power supply current, so that determination criteria for a wide variety of products can be set on a uniform basis. In addition, since the determination value is determined using general-purpose simulation, it is easy to detect abnormal leakage due to a process failure, and it is possible to prevent detection sensitivity from deteriorating due to an increase in off-leakage current.

  The method for setting the judgment value in the IDDq test by power simulation was as follows.

Based on the product circuit information and process library information, the power simulation tool is executed to predict the logic state and off-leakage amount of the device using the static power supply current measurement logic test pattern. From this prediction result, the average IDDq for all logic states, the normal fluctuation range a of the semiconductor device (that is, the fluctuation range of the off-leakage amount not caused by the failure), and the standard deviation σ are calculated. A fluctuation range a of the normal off-leakage amount is added to each of the plus side and the minus side to the average value IDDq obtained by the simulation, and this is used as a reference value for detecting an abnormal leak. Further, 3σ is further added to the fluctuation range a as a guard band. This Guard Band concluded that the width 3σ was appropriate from the results of detailed analysis of errors caused by the equipment and sampling errors during measurement. That is, based on the average value IDDqave, fluctuation range a, and standard deviation σ of the static power supply current predicted from the simulation, a range ΔIDDq that satisfies the following equation (a) was determined as the determination value of the static power supply current.
IDDqave− (a + 3 × σ) ≦ ΔIDDq ≦ IDDqave + (a + 3 × σ) (A)
Then, IDDq is actually measured for several semiconductor devices to be tested, and the range of judgment values actually used is corrected by multiplying the range ΔIDDq obtained by the above equation (A) from the measurement result. Let ΔIDDq.

  Table 1 shows the calculation results based on the simulation of the product with the 0.13 μm design rule. FIG. 1 illustrates the setting state of the range ΔIDDq based on this value. The off-leakage current that is actually judged as defective is outside the range ΔIDDq.

  This determination range ΔIDDq is used as a determination value, and thereafter, an IDDq test is performed by a usual method to detect defective products.

  Note that the number of logical states used for prediction (also referred to as address count) is appropriately determined according to the failure rate of the semiconductor device to be tested.

  Table 2 shows the results of an example using the failure detection method according to the present invention. The target products were mass-produced products with a design rule of 0.13 μm, and 60 were tested. For comparison, a result obtained by a method using a uniform threshold as a conventional example is also shown. This product has a large fluctuation range a of the off-leakage current depending on the logic state, and the IDDq test cannot be performed by the conventional method. However, according to the present invention, it has become clear that the defect of IDDq alone can be solved dramatically and the so-called overkill of the product can be suppressed.

  Next, from the viewpoint of test quality, an IDDq signature was collected for a sample showing an IDDq failure according to the present invention, and is shown in FIG. The vertical axis indicates the absolute value of the difference between the actually measured maximum value of IDDq and the average address value, and the horizontal axis indicates the average value of the static power supply current at all actually measured addresses. ◇ mark indicates Function failure, ■ mark indicates Function pass, and the solid line in Fig. 2 is the test limit value according to the present invention, the area below this line is IDDq pass (Pass), and the area above this line is IDDq It becomes defective. From FIG. 2, it was found that the semiconductor device determined to be IDDq defective showed an abnormal off-leakage current value compared to that determined to be non-defective. Therefore, the test result according to the present invention confirmed that a defective product was detected without overkill. Note that the sample marked with 印 in the region below the solid line in FIG. 2 passes IDDq (Pass) in the test according to the present invention, but is finally determined to be defective in the Function test.

  An example using the failure detection method according to the present invention is also shown for products other than the first and second embodiments. Table 3 shows the results of testing 100 mass-produced products. For comparison, the result of a determination method using a uniform threshold is also shown as a conventional example. The product to be measured has been subjected to the IDDq test by the conventional method. In the IDDq test, neither the conventional method nor the method of the present invention caused a problem that the test could not be performed due to frequent IDDq defects. Focusing on IDDq defects, one sample that was determined to be non-defective by the conventional method was determined to be defective in the present invention. Therefore, it was investigated whether this sample was defective or overkill caused by the test method.

  FIG. 3 shows the result of collecting the IDDq signature for the sample determined to be IDDq defective. The vertical axis indicates the absolute value of the difference between the actually measured maximum value of IDDq and the average address value, and the horizontal axis indicates the average value of the static power supply current at all actually measured addresses. The ◇ mark indicates Function failure, the ■ mark indicates Function pass, and the solid line in Fig. 3 is the IDDq test limit value according to the present invention, the area below this line is IDDq pass (Pass), and the area above this line is IDDq failure (Fail). From FIG. 3, it was shown that the sample determined to be IDDq defective by the method according to the present invention is not overkill but likely to be a defective defective sample. From this result, it was considered that a defect that could not be detected by the conventional method was detected, and it became clear that this is an effective determination method not only in terms of yield loss but also in terms of test quality.

  The failure detection method according to the present invention was applied to mass production, and the transition of lot yield (sign is ■) and IDDq defect rate (sign is ○) was investigated. The transition result is shown in FIG. The vertical axis shows the defect rate of IDDq alone on the right and the lot yield on the left in%. The horizontal axis indicates numbers assigned in order from 1 for convenience as mass production lot names. This product was subjected to the IDDq test by a method of judging with a uniform threshold value as in Example 3. During the period in which the method using the uniform threshold was applied, the off-leakage current increased or decreased due to process variations, and a low yield due to IDDq failure caused by the uniform threshold setting occurred. However, after the application of the present invention, it has been clarified that the occurrence of low yield due to IDDq failure is suppressed and the yield loss due to mismatch of test conditions can be reduced.

It is explanatory drawing which showed the setting condition of range (DELTA) IDDq. This figure shows the relationship between the absolute value of the difference between the actual measured IDDq maximum value and the address average value obtained from the mass-produced IDDq signature, and the average value of the static power supply current at all measured addresses. is there. Shown is the relationship between the absolute value of the actual measured IDDq maximum value and the average address value obtained from the IDDq signature of another mass-produced product, and the average static power supply current value at all actual measured addresses. FIG. FIG. 6 is a diagram showing a transition of a lot yield and an IDDq defect rate of a mass production lot before and after application of the present invention. It is the figure which showed the measurement result and simulation result by IDDq pattern of a 0.13 micrometer design rule product.

Claims (3)

A step of simulating a static power supply current of a semiconductor device in a plurality of logic states, and obtaining an average value, a fluctuation range, and a standard deviation of the static power supply current from the result of the simulation;
And a step of determining a determination value of the static power supply current of the semiconductor device based on the obtained average value, fluctuation range and standard deviation of the static power supply current. A method for determining the current judgment value. A step of simulating a static power supply current of a semiconductor device in a plurality of logic states, and obtaining an average value IDDqave, a fluctuation range a, and a standard deviation σ of the static power supply current from a result of the simulation;
And a step of determining a range ΔIDDq satisfying the following equation (a) as a determination value of the static power supply current based on the obtained average value IDDqave, fluctuation range a, and standard deviation σ of the static power supply current. A method for determining a determination value of a static power supply current of a semiconductor device.
IDDqave− (a + 3 × σ) ≦ ΔIDDq ≦ IDDqave + (a + 3 × σ) (a) In the method for determining the determination value of the static power supply current according to claim 1 or 2, the determination value is determined in advance,
Then, measuring the static power supply current of the semiconductor device, calculating the average value of the static power supply current from the measurement results,
A failure detection of a semiconductor device, comprising: comparing the calculated average value with the predetermined determination value, and determining that the average value is within a range of the determination value, and determining that it is a non-defective product Method.

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