JP3696009B2

JP3696009B2 - Semiconductor test apparatus, semiconductor test method, and recording medium

Info

Publication number: JP3696009B2
Application number: JP32110599A
Authority: JP
Inventors: 佐知恵岩
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 1999-11-11
Filing date: 1999-11-11
Publication date: 2005-09-14
Anticipated expiration: 2019-11-11
Also published as: JP2001141775A

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体の試験装置、試験方法および記録媒体に関し、特に、実装後の半導体装置の静止電源電流を測定してその良否を判定するＩｄｄＱテスト（Idd Quiescent power current test）を対象とする。
【０００２】
【従来の技術】
近年、半導体デバイスの微細化に伴い、１チップ内に膨大な規模の回路が形成されるようになってきている。このように複雑化したデバイスで不良が発生するとこれを検知することは大変困難なことである。特に、故障を検出するためのテストパターンであるテストベクタの作成においては、人手により、または自動テストパターン生成ツール（ＡＴＰＧ）により作成する場合でも、検出率の高いテストベクタを作成することは大変な労力と時間が必要である。既存のテストベクタを使用して、さらに高い故障検出率を得るテスト手法としてＩｄｄＱテストが注目されている。
【０００３】
従来、ＩｄｄＱ測定を行うための測定ポイントは、既存のテストベクタを用いる場合は、回路設計者の判断により回路内で適当と思われる測定ポイントを選択し、これに対応するテストベクタを採用していた。また、最近行われている有効な方法としては、市販のＩｄｄＱ測定ポイント抽出ツールを用いて行っていた。
【０００４】
【発明が解決しようとする課題】
しかしながら、近年の複雑化した半導体集積回路において、回路設計者の判断でＩｄｄＱ測定において適当と思われるポイントを選択することは、非常に困難であり、推測により選択した測定ポイントが故障の検出にあたって必ずしも有効なものではなかった。その結果、本来有効な測定ポイントを見逃し、あまり検出効果がない測定ポイントでの測定を行うことに時間が費やされていた。また、市販のＩｄｄＱ測定ポイント抽出ツールを用いるためには、ツールを実行するための環境を整備することが必要である。即ち、まずツールを準備する必要があり、ツールをインストールするためのマシン・ディスクが必要であり、さらに、回路やパターン等の情報をツール実行用のフォーマットに変換する必要があった。このツール実行用のフォーマット変換には特に多くの作業が必要であり、そのための専用ツールを開発する必要すら生じている。この一方、市販のＩｄｄＱ測定ポイント抽出ツールは、コンピュータ上でシミュレーションを実行した結果、有効であると推測した測定ポイントを抽出しているにすぎない。このため、抽出した測定ポイントの全てが実際に有効であるとは言えない。実際の量産を経た後に問題となる不良品は、現象および不良の原因と考えられる回路部分が限定されることが多い。これに対して、上述したコンピュータシミュレーションにより抽出された測定ポイントは、回路全体を対象とした測定が条件となっているため、既に故障部分が限定された不良品を判別するためには、必要のない測定ポイントか含まれており、ＩｄｄＱ測定において無駄な時間を費やしていた。また、ＩｄｄＱ測定による不良品の判断基準としては電流値が用いられ、ある基準となる電流値を判定基準電流値として、これを超える値のサンプルを不良品として判別し、それ以外は良品と判断していた。このため、故障の現象が電流的傾向（電流値変化率）の異常として現れるサンプルであっても、各測定ポイントにおける電流値が上記判定基準値を超えないものであれば良品と判断され、不良の検出が見逃されていた。
【０００５】
本発明は上記事情に鑑みてなされたものであり、その目的は、故障検出率が高く、かつ、スループットに優れた半導体試験装置、半導体試験方法および記録媒体を提供することにある。
【０００６】
【課題を解決するための手段】
本願発明者は、複数の測定ポイントで測定した電流値についてその測定ポイント間での変化率が良品と不良品とで異なる点に着目し、以下の手段により上記課題の解決を図る半導体試験装置、半導体試験方法および記録媒体を案出した。
【０００７】
即ち、本発明によれば、
第１の数量のテストベクタを含む測定用データを読込む読込み手段と、半導体装置に上記テストベクタを入力し、上記半導体装置から出力される電流値を上記テストベクタのアドレスに対応づけて測定する測定手段と、２つの異なる上記アドレスをアドレス対としてこのアドレス対に対応する２つの上記電流値相互間の電流値変化率を上記アドレス対毎にそれぞれ算出する演算手段と、良品サンプルに上記第１の数量のテストベクタを入力して得られた第１の電流値変化率に基づいて被試験体である半導体装置の良否を判定する基準となる良否判定基準範囲を決定する決定手段と、被試験体に上記テストベクタを入力して得られた第２の電流値変化率と上記良否判定基準範囲とを上記アドレス対毎に比較し、この比較結果に基づいて上記被試験体が良品であるか不良品であるかを判定する判定手段と、を備える半導体試験装置が提供される。
【０００８】
上記半導体試験装置によれば、良品サンプルから得られた第１の電流値変化率に基づいて良否判定基準範囲が決定され、この良否判定基準範囲と被試験体から得られた第２の電流値変化率とを比較するので、従来の試験装置では検出できなかった不良品を検出することができる。
【０００９】
上記決定手段は、複数の良品サンプルについて得られた複数の上記第１の電流値変化率に基づいて上記良否判定基準範囲を決定することが望ましい。
【００１０】
上記決定手段は、複数の上記第１の電流値変化率について上記アドレス対毎に最大値と最小値を抽出し、これに基づいて良品変化率範囲を上記アドレス対毎に決定する。さらに、上記決定手段は、上記良品変化率範囲に所定の誤差を考慮することにより上記良否判定基準範囲を決定する。
【００１１】
また、上記決定手段は、不良品サンプルに上記第１の数量のテストベクタを入力して得られた第３の電流値変化率と上記良否判定基準範囲とを上記アドレス対毎に比較し、上記良否判定基準範囲の範囲外となる上記第３の電流値変化率に対応する上記アドレス対を上記第１の数量のテストベクタのアドレス対から抽出して、第１の組合わせのアドレス対群として決定する測定範囲決定手段を含み、上記測定手段は、上記被試験体に上記第１の組合わせのアドレス対群に対応する上記テストベクタを入力することが好ましい。
【００１２】
これにより、故障検出の見込みが極めて小さいアドレスを量産用のアドレスから除外することができる。この結果、実質的に有効な測定ポイントに対応するテストベクタを抽出することができる。
【００１３】
上記測定範囲決定手段は、複数の不良品サンプルについて得られた複数の上記第３の電流値変化率と上記良否判定基準範囲とを上記アドレス対毎に比較し、上記良否判定基準範囲の範囲外となる上記第３の電流値変化率が得られた上記不良品サンプルの数量に応じて上記被試験体に入力すべき第２の組合わせのアドレス対群を上記第１の組合わせのアドレス対群から選出するとさらに良い。
【００１４】
これにより、量産テストに用いるテストベクタを検出効率の高い順から選定することができる。この結果、測定ポイントを要求仕様に応じてさらに絞り込むことができる。
【００１５】
また、本発明によれば、
良品サンプルである第１の半導体装置に第１の数量のテストベクタを入力し、上記良品サンプルから出力される電流値を上記テストベクタのアドレスに対応づけて測定し、第１の電流値として出力する工程と、２つの異なる上記アドレスをアドレス対としてこのアドレス対に対応する２つの上記第１の電流値相互間の変化率を上記アドレス対毎にそれぞれ算出し、第１の電流値変化率として出力する工程と、
上記第１の電流値変化率に基づいて良否判定の基準となる良否判定基準範囲を上記アドレス対毎に決定する工程と、被試験体である第２の半導体装置に上記第１の数量のテストベクタを入力して上記第２の半導体装置から出力される電流値を上記アドレスに対応づけて測定し、第２の電流値として出力する工程と、上記アドレス対に対応する２つの上記第２の電流値相互間の変化率を上記アドレス対毎にそれぞれ算出し、第２の電流値変化率として出力する工程と、上記第２の電流値変化率と上記良否判定基準範囲とを上記アドレス対毎に比較し、この比較結果に基づいて上記第２の半導体装置が良品であるか不良品であるかを判定する工程と、を備える半導体試験方法が提供される。
【００１６】
上記半導体試験方法において、上記第１の半導体装置は、複数の良品サンプルでなり、上記第１の電流値と上記第１の電流値変化率は、上記良品サンプル毎に出力され、上記良否判定基準範囲は、複数の上記第１の電流値変化率に基づいて決定されることが望ましい。
【００１７】
また、上記半導体試験方法においては、不良品サンプルである第３の半導体装置に上記第１の数量の上記テストベクタを入力し、上記第３の半導体装置から出力される電流値を上記アドレスに対応づけて測定して第３の電流値として出力する工程と、上記アドレス対に対応する２つの上記第３の電流値相互間の変化率を上記アドレス対毎にそれぞれ算出し、第３の電流値変化率として出力する工程と、
上記第３の電流値変化率と上記良否判定基準範囲とを上記アドレス対毎に比較し、上記良否判定基準範囲の範囲外となる上記第３の電流値変化率に対応する上記アドレス対を第１の組合わせのアドレス対として上記第１の数量でなる上記アドレスから抽出する工程と、さらに備え、上記第２の電流値を測定する工程は、抽出された上記第１の組合わせのアドレス対に対応する上記テストベクタを上記第２の半導体装置に入力して測定する工程であると好適である。
【００１８】
また、上記第３の半導体装置は、複数の不良品サンプルでなり、上記第３の電流値と、上記第３の電流値変化率は、上記不良品サンプル毎に出力され、複数の上記不良品サンプルについて得られた上記第３の電流値変化率と上記良否判定基準範囲とを上記アドレス対毎に比較する工程と、上記良否判定基準範囲の範囲外となる上記第３の電流値変化率が得られた上記不良品サンプルの数量に応じて上記第１の組合わせのアドレス対から第２の組合わせのアドレス対を選出する工程と、をさらに備え、上記第２の電流値を測定する工程は、上記第２の組合わせのアドレス対に対応する上記テストベクタを上記第２の半導体装置に入力して測定する工程であると良い。
【００１９】
また、本発明によれば、
テストベクタを含む測定用データを読込む読込み手段と、半導体装置に上記テストベクタを入力し上記半導体装置から出力される電流値を測定する測定手段と、上記電流値に基づいて上記被試験体が良品であるか不良品であるかを判定する判定手段と、を備える半導体テストシステムに用いられ、良品サンプルである第１の半導体装置に第１の数量のテストベクタを入力し、上記良品サンプルから出力される電流値を上記テストベクタのアドレスに対応づけて測定し、第１の電流値として出力する手順と、２つの異なる上記アドレスをアドレス対としてこのアドレス対に対応する２つの上記第１の電流値相互間の変化率を上記アドレス対毎にそれぞれ算出し、第１の電流値変化率として出力する手順と、上記第１の電流値変化率に基づいて良否判定の基準となる良否判定基準範囲を上記アドレス対毎に決定する手順と、被試験体である第２の半導体装置に上記第１の数量のテストベクタを入力して上記第２の半導体装置から出力される電流値を上記アドレスに対応づけて測定し、第２の電流値として出力する手順と、上記アドレス対に対応する２つの上記第２の電流値相互間の変化率を上記アドレス対毎にそれぞれ算出し、第２の電流値変化率として出力する手順と、上記第２の電流値変化率と上記良否判定基準範囲とを上記アドレス対毎に比較し、この比較結果に基づいて上記第２の半導体装置が良品であるか不良品であるかを判定する手順と、を含む半導体試験方法をコンピュータに実行させるプログラムを記録したコンピュータ読取り可能な記録媒体が提供される。
【００２０】
本発明にかかる記録媒体によれば、汎用のコンピュータを有する半導体試験装置を用いて、スループットに優れかつ従来の試験方法では検出できなかった不良品を検出できる上述の半導体試験方法を実施することができる。
【００２１】
上記半導体試験方法において、上記第１の半導体装置は、複数の良品サンプルでなり、上記第１の電流値と上記第１の電流値変化率は、上記良品サンプル毎に出力され、上記良否判定基準範囲は、複数の上記第１の電流値変化率に基づいて決定されることが望ましい。
【００２２】
また、上記半導体試験方法においては、不良品サンプルである第３の半導体装置に上記第１の数量の上記テストベクタを入力し、上記第３の半導体装置から出力される電流値を上記アドレスに対応づけて測定して第３の電流値として出力する手順と、上記アドレス対に対応する２つの上記第３の電流値相互間の変化率を上記アドレス対毎にそれぞれ算出し、第３の電流値変化率として出力する手順と、上記第３の電流値変化率と上記良否判定基準範囲とを上記アドレス対毎に比較し、上記良否判定基準範囲の範囲外となる上記第３の電流値変化率に対応する上記アドレス対を第１の組合わせのアドレス対として上記第１の数量でなる上記アドレスから抽出する手順と、がさらに含まれ、上記第２の電流値を測定する手順は、抽出された上記第１の組合わせのアドレス対に対応する上記テストベクタを上記第２の半導体装置に入力して測定する手順であると好適である。
【００２３】
また、上記第３の半導体装置は、複数の不良品サンプルでなり、上記第３の電流値と上記第３の電流値変化率は、上記不良品サンプル毎に出力され、上記半導体試験方法には、複数の上記不良品サンプルについて得られた上記第３の電流値変化率と上記良否判定基準範囲とを上記アドレス対毎に比較する手順と、上記良否判定基準範囲の範囲外となる上記第３の電流値変化率が得られた上記不良品サンプルの数量に応じて上記第１の組合わせのアドレス対から第２の組合わせのアドレス対を選出する手順と、がさらに含まれ、上記第２の電流値を測定する手順は、上記第２の組合わせのアドレス対に対応する上記テストベクタを上記第２の半導体装置に入力して測定する手順であるとさらに良い。
【００２４】
【発明の実施の形態】
以下、本発明の実施形態のいくつかを試験方法、試験装置、および記録媒体の順で詳細に説明する。
【００２５】
（１）半導体試験方法の実施の一形態
本発明にかかる半導体試験方法の実施の一形態について図面を参照しながら説明する。本実施形態の第１の特徴は、異なる測定ポイントで得られた電流値相互間の変化率を半導体装置の良否判定基準として用いることにより故障検出率を向上させる点にある。また本実施形態の第２の特徴は、良品および不良品の各サンプルに対して多数のポイントにわたるＩｄｄＱ測定を行い、得られた測定結果情報を統計的に処理することにより、量産テストに有効な測定ポイントを抽出することにより、量産テストにおいて故障検出の見込みが低い測定ポイントを除外してＩｄｄＱテストのスループットを高める点にある。
【００２６】
まず、本実施形態の試験方法の概略を図１および図２のフローチャートを参照しながら説明する。
【００２７】
まず、図１に示すように、測定に必要なデータを読込む（ステップＳ１０）。測定用データには、既存のテストプログラムやテストベクタデータの他、予め用意した良品サンプルおよび不良品サンプルに関するデータ（サンプル名など）を含む。
【００２８】
続いて、電流値測定装置を用いて上述の良品サンプルと不良品サンプルのそれぞれについて多数の測定ポイント（以下、単に多ポイントという）にわたってＩｄｄＱ測定を行い（ステップＳ２０、Ｓ３０）、各測定ポイントにそれぞれ対応するテストベクタのアドレス毎に測定結果を取得する（ステップＳ。４０、５０）。
【００２９】
次に、これらの測定結果から各サンプル毎に電流値変化率を２つの測定アドレス（以下、アドレス対という）毎に算出し（ステップＳ６０）、良品サンプルの電流値変化率（第１の電流値変化率）と不良品サンプルの電流値変化率（第３の電流値変化率）に分けて抽出する（ステップＳ７０、８０）。
【００３０】
続いて良品サンプルの電流値変化率のデータから良品の電流値変化率の最大値と最小値とを各アドレス対毎に抽出し、これらに基づいて良品として許容できる変化率の範囲（以下、良品変化率範囲という）を取得する（ステップＳ９０）。
【００３１】
次に、各アドレス毎に不良品の電流値変化率を良品変化率範囲と比較し（ステップＳ１００）する。
【００３２】
次に、図２に示すように、比較の結果、良品変化率範囲の範囲外となる電流値変化率に対応するアドレス対を抽出し、故障検出に有効なアドレス対の組合わせ（以下、有効アドレス対という）として取得する（ステップＳ１１０）。
【００３３】
次に、良品変化率範囲に基づいて、抽出した有効アドレス対毎に量産テストにおける良否判定基準となる良否判定基準範囲Ｌを決定する（ステップＳ１２０）。
【００３４】
次に、不良品の電流値変化率と良否判定基準範囲Ｌとを比較して（ステップＳ１３０）、良否判定基準範囲Ｌの範囲外となる電流値変化率が得られた不良品の数量に基づいて上述した有効アドレス対から量産テスト用のアドレス対を要求仕様に応じて選出する（ステップＳ１４０）。
【００３５】
最後は、このようにして得られた量産テスト用アドレス対の情報と良否判定基準範囲Ｌの情報とを用いて量産テストにおけるＩｄｄＱ測定を実施する（ステップＳ１５０）。
【００３６】
上述の手順を図面を参照しながらより具体的に説明する。
【００３７】
まず、一般的なテストベクタの情報を図３を用いて説明する。テストベクタ情報は、テストベクタ（グループ）名５１と、入力パターンである入力信号群と出力パターンである出力信号群でなるテストベクタ５３とを含む。同図（ａ）はテストベクタ名ＡＡＡが与えられたテストベクタ情報の一例を示し、また、同図（ｂ）は、テストベクタ名ＢＢＢが与えられたテストベクタ情報の一例を示す。各テストベクタにはアドレス（ステップまたはサイクルとも呼ばれる）５５が付せられる。
【００３８】
多ポイントで測定する場合、これらのテストベクタのうち、どのアドレスのテストベクタを用いるかについては、ランダムなアドレスで測定しても、また、所定の方法で抽出されたアドレスで測定しても良い。但し、より信頼性の高いデータを取得するために、できる限り多くのポイントで測定するのが望ましいことは勿論である。なお、出力信号群は、ロジックテストにおける期待値の信号であるため、本実施形態では、テストベクタ５３のうち、入力信号群のみを用いる。
【００３９】
このようなテストベクタ（第１の数量のテストベクタ）を用いて取得した測定結果の具体例を図４および図５に示す。図４は３つの良品サンプルＰＡ、ＰＢ、ＰＣについて取得した測定結果を示し、また、図５は３つの不良品サンプルＦＡ、ＦＢ、ＦＣについて取得した測定結果を示す。両図に示すように、多ポイント測定により、各サンプル毎にパターン名（ＰＡＴ）、アドレス番号（ＡＤＲ）、電流値（ＩｄｄＱ）の情報が得られる。
【００４０】
図６は、図４および図５に示す測定結果情報に基づいて、連続するアドレス（アドレス対群）とそれぞれに対応する電流値との関係を視覚的に現したグラフである。同図（ａ）は良品サンプルＰＡ、ＰＢ、ＰＣの電流値と各測定ポイントとの関係、（ｂ）は不良品サンプルＦＡ、ＦＢ、ＦＣの電流値と各測定ポイントとの関係を示す。
【００４１】
同図（ａ）と（ｂ）との対比において明らかなように、同図に示す例においては良品の電流値が安定している区間（パターン名ＡＡＡのＡＤＲ８７〜パターン名ＢＢＢのＡＤＲ３０）内で不良品の電流値が不安定となっている部分、即ち、電流値の変化が大きくなっている部分があることが分る。
【００４２】
ここで、本実施形態において特徴的な電流値変化率の考え方の一例を、図７に示す。変化率とは、どのくらい変化するかということであり、本実施形態では、任意のアドレス対の組合わせについて、各アドレスに対応する測定ポイントで取得された電流値をａ，ｂとするとき、電流値変化率Ｃを（ｂ−ａ）／ａまたは（ａ−ｂ）／ｂと定義する。なお、電流値変化率の定義は、同図に示す方法に限ることなく、例えば微分値など、被試験体の種類や要求仕様に応じて決定できるのは勿論である。
【００４３】
図７に示す定義に従って電流値変化率を算出する手順（図１、ステップＳ６０）について図８のフローチャートを参照しながら具体的に説明する。
【００４４】
まず、多ポイントＩｄｄＱ測定（図１、ステップＳ２０およびＳ３０）により得られた各アドレス毎の電流値データに基づいて、アドレス対の組合わせを決定する（ステップＳ６１）。次に、各アドレス対において、各測定アドレスでの電流値データａ，ｂを図７に示す計算式に代入して（ステップＳ６２）、各アドレス対毎に電流値変化率Ｃを取得する（ステップＳ６３）。
【００４５】
次に、良品変化率範囲の算出方法（図１、ステップＳ９０）を説明する。
【００４６】
図９は、図４に示す良品サンプルにおける電流値変化率を各アドレス対毎に示す説明図である。同図の基準範囲の欄に示すように、３つの良品サンプルＰＡ、ＰＢ、ＰＣにおいて同一のアドレス対に対応する電流値変化率のうち、最小値をＣｓ、最大値をＣｌとすると、任意のアドレス対における良品変化率範囲Ｃ_Ｐは、Ｃｓ＜Ｃ_Ｐ＜Ｃｌとなる。
【００４７】
ここで、不良品サンプルの電流値変化率のうち、この良品変化率範囲Ｃ_Ｐ内に属する電流値変化率に対応するアドレス対については、量産テストにおいて故障を検出する可能性が極めて小さいものと判断できる。
【００４８】
そこで、良品変化率範囲Ｃ_Ｐと不良品サンプルの電流値変化率とを各アドレス対毎に比較し（図１、ステップＳ１００）、不良品の電流値変化率のうち、良品変化率範囲Ｃ_Ｐ内に属さないものに対応するアドレス対（第１の組合わせのアドレス対）を抽出することにより（図２ステップＳ１１０）、故障検出が見込める有効アドレス対を選定することができる。
【００４９】
このようにして有効アドレス対を選定した後は、選定されたアドレス対のそれぞれについて量産テストに用いる良否判定基準範囲Ｌを決定する（図２、ステップＳ１２０）。
【００５０】
図１０に良品判定基準範囲Ｌの一定義例を示す。量産テストは一般に誤差を考慮して実施するため、図１０に示す例においては、図９の電流値変化率を用いて算出した良品変化率範囲Ｃ_Ｐに誤差αを考慮して定義する。誤差αは、本実施形態では（最大値Ｃｌ−最小値Ｃｓ）／２とする。
【００５１】
さらに、本実施形態によれば、このように定義した良否判定基準範囲Ｌと不良品サンプルの電流値変化率とを比較することにより、量産テストにおける測定ポイントを要求仕様に応じてさらに絞り込むこともできる。
【００５２】
図１１は、図９に示す良品サンプルの各アドレス対に対応して図５に示す不良品サンプルの電流値の変化率を算出した結果を含む説明図である。同図においては、算出された不良品の電流値変化率を良否判定基準範囲Ｌとの比較で示している。
【００５３】
同図に示す例においては、ＰＡＴ＝ＡＡＡでのアドレス対２１，４３間、ＰＡＴ＝ＢＢＢでのアドレス対２８，３０間における電流値変化率は、いずれも良否判定基準範囲Ｌ内に含まれるため、これらのアドレス対で量産テストを実施しても故障の検出が見込めないことが分る。従って、これらのアドレス対は、上述した第１の組合わせのアドレス対には含まれない。
【００５４】
この一方、ＰＡＴ＝ＡＡＡでのアドレス対１０９，１１１間、ＰＡＴ＝ＡＡＡのアドレス１１３とＰＡＴ＝ＢＢＢのアドレス１７とのアドレス対間、ＰＡＴ＝ＢＢＢでのアドレス対１７，１９間、アドレス対２１，２４間、アドレス対２４，２６間、ＰＡＴ＝ＣＣＣでのアドレス対３６，３７間、アドレス対３７，４９間における電流値変化率は、いずれも不良品１サンプルが良否判定基準範囲Ｌの範囲外となり、従って、これらのアドレス対によれば、１つの不良品サンプルに対応する不良品を検出することが期待できる。
【００５５】
また、ＰＡＴ＝ＡＡＡでのアドレス対４３，６５間、６５，８７間、８７，１０９間、１１１，１１３間、ＰＡＴ＝ＢＢＢでのアドレス対２６，２８間、ＰＡＴ＝ＢＢＢのアドレス３０とＰＡＴ＝ＣＣＣのアドレス３３とのアドレス対間、ＰＡＴ＝ＣＣＣでのアドレス対３３，３６間における電流値変化率は、それぞれ不良品２サンプルが良否判定基準範囲Ｌの範囲外となる。このことから、これらのアドレス対によれば、２つの不良品サンプルに対応する不良品を検出することが期待できる。
【００５６】
さらに、ＰＡＴ＝ＢＢＢ１９，２１間の電流値変化率は、不良品３サンプルが全て良否判定基準範囲Ｌの範囲外となるので、この１対のアドレス対で３つの不良品サンプルに対応する不良品の検出が見込め、このアドレス対を用いた量産テストが最も効率的であることが分る。
【００５７】
このように、アドレス対の組合わせに応じて不良品を検出できる可能性が異なるため、要求仕様に応じてアドレス対（第３の組合わせのアドレス対）を選択した上で上述の良否判定基準範囲Ｌの情報を用いて量産テストでのＩｄｄＱ測定を実施すれば（図２、ステップＳ１３０）、電流値を判定基準とした従来のＩｄｄＱ測定による試験方法では検出できなかった不良品を高いスループットで検出できる。これにより従来検出できなかった故障を解析することが可能になり、設計部門、プロセス部門に対してより迅速にフィードバックできる。この結果、不良原因解明のための解析効率を向上させ、不具合に対する早期改善を図ることができる。
【００５８】
さらに、測定に用いるテストベクタのアドレス対は、適宜組合わせることができるので、試験に要する時間を要求仕様に応じて柔軟に調整することができる。
【００５９】
（２）半導体試験装置の実施の一形態
次に、本発明にかかる半導体試験装置の実施の一形態について図面を参照しながら説明する。
【００６０】
図１２は、本実施形態の半導体試験装置の概略構成を示すブロック図である。同図に示す半導体試験装置１は、データ読込み部１０と、決定手段である測定ポイント決定部２０と、ＩｄｄＱ測定部３０と、結果表示部４０とを備え、上述した本発明にかかる半導体試験方法に従って動作する。
【００６１】
データ読込み部１０は、テストプログラム、テストベクタ、並びに、良品および不良品サンプルに関するデータを読込んで測定ポイント決定部２０に供給する。
【００６２】
図１３は、測定ポイント決定部２０の詳細な構成を示すブロック図である。同図に示すように、測定ポイント決定部２０は、データ取得部２４、テスタ２２、メモリ２５、電流値変化率算出部２６、基準範囲決定部２７、データ比較部２８および、測定範囲決定手段である測定ポイント群決定部２９を含む。
【００６３】
データ取得部２４は、データ読込み部１０からテストプログラム、テストベクタデータ等の供給を受け、これらのデータに基づいてテスタ２２が予め準備された良品サンプルおよび不良品サンプルに対して多ポイントでのＩｄｄＱ測定を実行する。測定結果である電流値は、各テストベクタのアドレスと対応づけられてメモリ２５に格納される。電流値変化率算出部２６は、メモリ２５から電流値およびテストベクタアドレスなどのデータを引出して各アドレス対毎に電流値変化率を良品および不良品のそれぞれについて算出し、良品サンプルの算出結果を基準範囲決定部２７に供給し、また、不良品サンプルの算出結果をデータ比較部２８に供給する。
【００６４】
基準範囲決定部２７は、電流値変化率算出部２６から良品の電流値変化率の算出結果を受けて良品変化率範囲Ｃ_Ｐと良否判定基準範囲Ｌを算出し、データ比較部２８に供給する。
【００６５】
データ比較部２８は、電流値変化率算出部２６から供給された不良品サンプルの電流値変化率と、基準範囲決定部２７から供給された良否判定基準範囲Ｌとを各アドレス対毎に相互に比較し、良否判定基準範囲Ｌの範囲外となる電流値変化率が得られた不良品サンプルのサンプル名とそのときのテストベクタのアドレス対とを測定ポイント群決定部２９に供給する。
【００６６】
測定ポイント群決定部２９は、データ比較部２８から供給されたデータに基づいて、良否判定基準範囲Ｌの範囲外となる不良品サンプルがより多くなるアドレス対を予め設定された被試験体の要求仕様に応じて検索し、量産テスト用のアドレス対群（第１または第２の組合わせのアドレス対）として抽出し、この量産テスト用アドレス対群を良否判定基準範囲Ｌとともに出力する。
【００６７】
図１２に戻り、ＩｄｄＱ測定部３０は、量産テスタ３２とデータ取得部３４と良否判定部３６とを含む。
【００６８】
データ取得部３４は、測定ポイント決定部２０から量産テスト用アドレス対群および良否判定基準範囲Ｌのデータの供給を受け、量産テスタ３２および良否判定部３６に量産テスト用アドレス対群を供給し、また、良否判定部３６に良否判定基準範囲Ｌのデータを供給する。
【００６９】
量産テスタ３２は、データ取得部３４から供給された量産テスト用アドレス対群のデータに基づいて、量産された被試験体のＩｄｄＱ測定を実行し、測定結果をデータ取得部３４に供給する。データ取得部３４はまた演算手段をも構成し、量産テスタ３２によるＩｄｄＱ測定の結果から被試験体毎に各アドレス対に対応して電流値変化率（第２の電流値変化率）を算出し、算出結果を良否判定部３６に供給する。
【００７０】
良否判定部３６は、データ取得部３４から供給された電流値変化率のデータと良否判定基準範囲Ｌのデータに基づいて各被試験体について良否を判定し、被試験体から得られた電流値変化率のうち、良否判定基準範囲Ｌの範囲外となる電流値変化率がある場合に、その被試験体を不良品と判別する。不良品でない場合は、次の被試験体の試験に進む。
【００７１】
結果表示部４０は、良否判定部３６から受けた判定結果を図示しないＣＲＴ（Cathode Ray Tube）などに表示する。
【００７２】
（３）記録媒体
（１）において前述した実施形態の半導体試験方法の一連の手順は、コンピュータに実行させるプログラムとしてフロッピーディスクやＣＤ−ＲＯＭ等の記録媒体に収納し、コンピュータに読込ませて実行させても良い。これにより、本発明にかかる半導体試験方法をワークステーション等の汎用コンピュータを備える試験装置を用いて実現することができる。記録媒体は、磁気ディスクや光ディスク等の携帯可能なものに限定されず、ハードディスク装置やメモリなどの固定型の記録媒体でも良い。また、前述した半導体試験方法の一連の手順を組込んだプログラムをインターネット等の通信回線（無線通信を含む）を介して頒布しても良い。さらに、前述した半導体試験方法の一連の手順を組込んだプログラムを暗号化したり、変調をかけたり、圧縮した状態で、インターネット等の有線回線や無線回線を介して、あるいは記録媒体に収納して頒布しても良い。
【００７３】
【発明の効果】
以上詳述したとおり、本発明は、以下の効果を奏する。
【００７４】
即ち、本発明にかかる半導体試験装置によれば、良品サンプルから得られた第１の電流値変化率に基づいて良否判定基準範囲を決定する決定手段と、被試験体から得られた第２の電流値変化率と上記良否判定基準範囲とをアドレス対毎に比較する判定手段とを備えるので、従来の試験装置では検出できなかった不良品を優れたスループットで検出することができる。
【００７５】
また、本発明にかかる半導体試験方法によれば、良品サンプルから得られた第１の電流値変化率に基づいて良否判定基準範囲をアドレス対毎に決定する工程と、被試験体から得られた第２の電流値変化率と上記良否判定基準範囲とを上記アドレス対毎に比較する工程とを備えるので、電流値を判定基準とした従来のＩｄｄＱ測定による試験方法では検出できなかった不良品を高いスループットで検出することができる。これにより、不良原因解明のための解析効率を向上させ、不具合に対する早期改善を図ることができる。また、量産テスト用のアドレス対は適宜組合わせることができるので、試験に要する時間を要求仕様に応じて柔軟に調整することができる。
【００７６】
また、本発明にかかる記録媒体によれば、上述した効果を奏する半導体試験方法を汎用のコンピュータを有する半導体試験装置を用いて実施することができる。
【図面の簡単な説明】
【図１】本発明にかかる半導体試験方法の実施の一形態を説明するフローチャートである。
【図２】本発明にかかる半導体試験方法の実施の一形態を説明するフローチャートである。
【図３】テストベクタの一例の説明図である。
【図４】図１および図２に示す方法により多ポイントにわたって良品サンプルをＩｄｄＱ測定した結果を示す説明図である。
【図５】図１および図２に示す方法により多ポイントにわたって不良品サンプルをＩｄｄＱ測定した結果を示す説明図である。
【図６】多ポイントにわたるＩｄｄＱ測定により得られた電流値と測定ポイントとの関係を示す説明図である。
【図７】電流値変化率の一定義例を示す説明図である。
【図８】電流値変化率の算出方法を示すフローチャートである。
【図９】良品の電流値変化率の一例を示す説明図である。
【図１０】良否判定基準範囲の一定義例を示す説明図である。
【図１１】不良品の電流値変化率の一例を示す説明図である。
【図１２】本発明にかかる半導体試験装置の実施の一形態の概略構成を示すブロック図である。
【図１３】図１２に示す半導体試験装置の測定ポイント決定部の具体的構成を示すブロック図である。
【符号の説明】
１半導体試験装置
１０データ読込み部
２０測定ポイント決定部
２２テスタ
２４，３４データ取得部
２５メモリ
２６電流値変化率算出部
２７基準範囲決定部
２８データ比較部
２９測定ポイント群決定部
３０ＩｄｄＱ測定部
３２量産テスタ
３６良否判定部
４０結果表示部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor test apparatus, a test method, and a recording medium. In particular, the present invention is directed to an IddQ test (Idd Quiescent power current test) in which a static power supply current of a semiconductor device after mounting is measured to determine its quality.
[0002]
[Prior art]
In recent years, with the miniaturization of semiconductor devices, an enormous scale circuit has been formed in one chip. If a defect occurs in such a complicated device, it is very difficult to detect this. In particular, when creating a test vector that is a test pattern for detecting a failure, it is very difficult to create a test vector with a high detection rate even if it is created manually or by an automatic test pattern generation tool (ATPG). It takes effort and time. The IddQ test is attracting attention as a test method for obtaining a higher failure detection rate using an existing test vector.
[0003]
Conventionally, when using an existing test vector as the measurement point for performing IddQ measurement, the measurement point considered appropriate in the circuit is selected at the judgment of the circuit designer, and the test vector corresponding to this is adopted. It was. Further, as an effective method that has been performed recently, a commercially available IddQ measurement point extraction tool has been used.
[0004]
[Problems to be solved by the invention]
However, in the recent complicated semiconductor integrated circuits, it is very difficult to select a point that seems to be appropriate in the IddQ measurement based on the judgment of the circuit designer. It was not effective. As a result, time was spent on performing measurement at a measurement point that overlooked a measurement point that was originally effective and had little detection effect. In addition, in order to use a commercially available IddQ measurement point extraction tool, it is necessary to prepare an environment for executing the tool. In other words, it is necessary to first prepare a tool, and a machine disk for installing the tool, and further, it is necessary to convert information such as circuits and patterns into a format for executing the tool. The conversion of the format for executing this tool requires a lot of work, and there is even a need to develop a dedicated tool for that purpose. On the other hand, commercially available IddQ measurement point extraction tools only extract measurement points that are estimated to be effective as a result of executing simulation on a computer. For this reason, it cannot be said that all of the extracted measurement points are actually effective. In many cases, defective products that become a problem after actual mass production are limited in phenomena and circuit parts that are considered to be the cause of defects. On the other hand, since the measurement points extracted by the computer simulation described above are subject to measurement for the entire circuit, it is necessary to determine the defective product whose faulty part has already been limited. There were no measurement points included, and wasted time was spent in IddQ measurement. Also, the current value is used as a criterion for judging defective products by IddQ measurement. A current value that is a certain standard is used as a judgment reference current value, a sample that exceeds this value is judged as a defective product, and other products are judged as good products. Was. For this reason, even in the sample where the failure phenomenon appears as an abnormality in the current trend (current value change rate), if the current value at each measurement point does not exceed the above criterion value, it is judged as a non-defective product. The detection of was missed.
[0005]
The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor test apparatus, a semiconductor test method, and a recording medium having a high failure detection rate and excellent throughput.
[0006]
[Means for Solving the Problems]
The inventor of the present application pays attention to the fact that the rate of change between the measurement points for the current values measured at a plurality of measurement points differs between a non-defective product and a defective product, and a semiconductor test apparatus that solves the above problems by the following means, A semiconductor test method and a recording medium have been devised.
[0007]
That is, according to the present invention,
Reading means for reading measurement data including a first quantity of test vectors, the test vector is input to the semiconductor device, and the current value output from the semiconductor device is measured in association with the address of the test vector. Measuring means, two different addresses as address pairs, calculation means for calculating the current value change rate between the two current values corresponding to the address pairs for each address pair, and the first sample for the non-defective sample Determining means for determining a pass / fail judgment reference range serving as a reference for judging pass / fail of a semiconductor device as a device under test based on a first current value change rate obtained by inputting a test vector of a quantity of The second current value change rate obtained by inputting the test vector into the body and the pass / fail judgment reference range are compared for each address pair, and based on the comparison result, the test target is compared. Body semiconductor testing device comprising determining means for determining a defective or non-defective, is provided.
[0008]
According to the semiconductor test apparatus, the pass / fail judgment reference range is determined based on the first current value change rate obtained from the non-defective sample, and the pass / fail judgment reference range and the second current value obtained from the DUT. Since the change rate is compared, it is possible to detect defective products that could not be detected by the conventional test apparatus.
[0009]
The determination means preferably determines the pass / fail judgment reference range based on the plurality of first current value change rates obtained for the plurality of non-defective samples.
[0010]
The determination means extracts a maximum value and a minimum value for each address pair for a plurality of the first current value change rates, and determines a non-defective product change rate range for each address pair based on the maximum value and the minimum value. Furthermore, the determination means determines the pass / fail judgment reference range by taking a predetermined error into consideration for the pass rate change rate range.
[0011]
The determining means compares the third current value change rate obtained by inputting the first quantity of test vectors to the defective sample and the pass / fail judgment reference range for each address pair, and The address pair corresponding to the third current value change rate that falls outside the pass / fail criterion range is extracted from the address pairs of the first quantity of test vectors, and is used as a first combination of address pairs. Preferably, the measuring means includes a measuring range determining means for determining, and the measuring means inputs the test vector corresponding to the address pair group of the first combination to the device under test.
[0012]
As a result, it is possible to exclude addresses for which the possibility of failure detection is extremely small from the addresses for mass production. As a result, a test vector corresponding to a substantially effective measurement point can be extracted.
[0013]
The measurement range determining means compares the plurality of third current value change rates obtained for a plurality of defective product samples with the pass / fail judgment reference range for each address pair, and out of the pass / fail judgment reference range. The second combination of address pairs to be input to the DUT according to the number of defective samples from which the third current value change rate is obtained is the first combination of address pairs. Better to pick from the group.
[0014]
Thereby, the test vector used for the mass production test can be selected from the descending order of detection efficiency. As a result, the measurement points can be further narrowed down according to the required specifications.
[0015]
Moreover, according to the present invention,
A first quantity of test vectors is input to the first semiconductor device, which is a non-defective sample, and the current value output from the non-defective sample is measured in association with the address of the test vector and output as the first current value. And calculating the rate of change between the two first current values corresponding to the address pair for each address pair, using the two different addresses as an address pair, and calculating the first current value rate of change as the first current value rate of change. A process of outputting;
A step of determining a pass / fail judgment reference range as a pass / fail judgment reference for each address pair based on the first current value change rate; and a test of the first quantity on the second semiconductor device as a device under test A step of inputting a vector and measuring a current value output from the second semiconductor device in association with the address and outputting the current value as a second current value; and two second second values corresponding to the address pair The step of calculating the rate of change between the current values for each address pair and outputting it as the second rate of change in current value, and the second rate of change in current value and the pass / fail criterion range for each pair of addresses And a step of determining whether the second semiconductor device is a good product or a defective product based on the comparison result.
[0016]
In the semiconductor test method, the first semiconductor device includes a plurality of non-defective samples, and the first current value and the first current value change rate are output for each non-defective sample, and the pass / fail judgment criteria The range is desirably determined based on a plurality of the first current value change rates.
[0017]
In the semiconductor test method, the first quantity of the test vectors is input to a third semiconductor device which is a defective product sample, and the current value output from the third semiconductor device corresponds to the address. Then, a step of measuring and outputting as a third current value and a rate of change between the two third current values corresponding to the address pair are calculated for each address pair. A step of outputting as a rate of change;
The third current value change rate and the pass / fail judgment reference range are compared for each address pair, and the address pair corresponding to the third current value change rate outside the pass / fail judgment reference range is set to the first address pair. A step of extracting from the address having the first quantity as one combination of address pairs, and a step of measuring the second current value further comprising the step of extracting the first combination of address pairs. It is preferable that the test vector corresponding to is input to the second semiconductor device and measured.
[0018]
The third semiconductor device includes a plurality of defective samples, and the third current value and the third current value change rate are output for each defective sample, and the plurality of defective products are output. The step of comparing the third current value change rate obtained for the sample with the pass / fail judgment reference range for each address pair, and the third current value change rate that is outside the pass / fail judgment reference range. Selecting a second combination of address pairs from the first combination of address pairs according to the quantity of the obtained defective product samples, and measuring the second current value May be a step of inputting and measuring the test vector corresponding to the address pair of the second combination to the second semiconductor device.
[0019]
Moreover, according to the present invention,
Reading means for reading measurement data including a test vector, measuring means for inputting the test vector to a semiconductor device and measuring a current value output from the semiconductor device, and the device under test based on the current value And a determination means for determining whether the product is a non-defective product or a defective product, and a first quantity of test vectors is input to a first semiconductor device that is a good product sample, A procedure for measuring an output current value in association with an address of the test vector and outputting it as a first current value, and two different first addresses corresponding to the address pair with two different addresses as address pairs The rate of change between the current values is calculated for each of the address pairs and output as the first current value change rate, and based on the first current value change rate. A procedure for determining a pass / fail judgment reference range as a judgment reference for each of the address pairs, and inputting the first quantity of test vectors to the second semiconductor device as a device under test from the second semiconductor device. The output current value is measured in association with the address and output as a second current value, and the rate of change between the two second current values corresponding to the address pair is determined for each address pair. The second current value change rate and the second current value change rate are compared for each address pair, and the second current value change rate and the pass / fail judgment reference range are compared for each address pair. And a computer-readable recording medium on which a program for causing a computer to execute a semiconductor test method including a procedure for determining whether the semiconductor device of 2 is a non-defective product or a defective product is provided.
[0020]
According to the recording medium of the present invention, it is possible to carry out the above-described semiconductor test method capable of detecting a defective product that is excellent in throughput and cannot be detected by a conventional test method, using a semiconductor test apparatus having a general-purpose computer. it can.
[0021]
In the semiconductor test method, the first semiconductor device includes a plurality of non-defective samples, and the first current value and the first current value change rate are output for each non-defective sample, and the pass / fail judgment criteria The range is desirably determined based on a plurality of the first current value change rates.
[0022]
In the semiconductor test method, the first quantity of the test vectors is input to a third semiconductor device which is a defective product sample, and the current value output from the third semiconductor device corresponds to the address. Then, a procedure for measuring and outputting as a third current value and a rate of change between the two third current values corresponding to the address pair are calculated for each address pair, and the third current value is calculated. The procedure for outputting as a change rate, the third current value change rate and the pass / fail judgment reference range are compared for each address pair, and the third current value change rate that falls outside the pass / fail judgment reference range. And extracting the address pair corresponding to the first address pair as the first address pair from the address having the first quantity. The procedure for measuring the second current value is further extracted. The above The test vector corresponding to the combination of address pairs are preferred If it is the procedure for measuring are input to the second semiconductor device.
[0023]
The third semiconductor device includes a plurality of defective samples, and the third current value and the third current value change rate are output for each defective sample, and the semiconductor test method includes A procedure for comparing the third current value change rate obtained for the plurality of defective product samples and the pass / fail judgment reference range for each address pair, and the third out of the pass / fail judgment reference range. And a step of selecting a second combination of address pairs from the first combination of address pairs in accordance with the number of defective sample samples from which the current value change rate is obtained. The procedure for measuring the current value is preferably a procedure in which the test vector corresponding to the address pair of the second combination is input to the second semiconductor device and measured.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, some embodiments of the present invention will be described in detail in the order of a test method, a test apparatus, and a recording medium.
[0025]
(1) One embodiment of semiconductor test method
An embodiment of a semiconductor test method according to the present invention will be described with reference to the drawings. The first feature of the present embodiment is that the failure detection rate is improved by using the rate of change between the current values obtained at different measurement points as a quality criterion for the semiconductor device. The second feature of the present embodiment is effective for mass production tests by performing IddQ measurement over a large number of points on each of good and defective samples and statistically processing the obtained measurement result information. By extracting the measurement points, it is possible to increase the throughput of the IddQ test by excluding the measurement points where the possibility of failure detection is low in the mass production test.
[0026]
First, an outline of the test method of the present embodiment will be described with reference to the flowcharts of FIGS.
[0027]
First, as shown in FIG. 1, data necessary for measurement is read (step S10). In addition to existing test programs and test vector data, the measurement data includes data (sample names and the like) relating to prepared good samples and defective samples.
[0028]
Subsequently, an IddQ measurement is performed over a large number of measurement points (hereinafter simply referred to as “multiple points”) for each of the above-mentioned non-defective samples and defective samples using the current value measuring device (steps S20 and S30). A measurement result is acquired for each address of the corresponding test vector (steps S. 40, 50).
[0029]
Next, the current value change rate for each sample is calculated for each of the two measurement addresses (hereinafter referred to as address pairs) from these measurement results (step S60), and the current value change rate (first current value) of the good product sample is calculated. Change rate) and the current value change rate (third current value change rate) of the defective product sample (steps S70, 80).
[0030]
Subsequently, the maximum value and the minimum value of the current value change rate of the non-defective product are extracted for each address pair from the current value change rate data of the non-defective sample, and based on these, the range of the change rate that can be accepted as a non-defective product (hereinafter referred to as the non-defective product). Change rate range) is acquired (step S90).
[0031]
Next, the current value change rate of the defective product is compared with the non-defective product change rate range for each address (step S100).
[0032]
Next, as shown in FIG. 2, as a result of the comparison, an address pair corresponding to the current value change rate that falls outside the non-defective product change rate range is extracted, and a combination of address pairs effective for failure detection (hereinafter referred to as effective). As an address pair) (step S110).
[0033]
Next, based on the non-defective product change rate range, a pass / fail judgment reference range L that is a pass / fail judgment standard in the mass production test is determined for each extracted effective address pair (step S120).
[0034]
Next, the current value change rate of the defective product is compared with the pass / fail judgment reference range L (step S130), and the current value change rate outside the pass / fail judgment reference range L is obtained based on the number of defective products. Then, an address pair for mass production test is selected from the effective address pairs described above according to the required specifications (step S140).
[0035]
Finally, the IddQ measurement in the mass production test is performed using the information on the mass production test address pair and the information on the pass / fail judgment reference range L thus obtained (step S150).
[0036]
The above procedure will be described more specifically with reference to the drawings.
[0037]
First, general test vector information will be described with reference to FIG. The test vector information includes a test vector (group) name 51 and a test vector 53 including an input signal group that is an input pattern and an output signal group that is an output pattern. FIG. 4A shows an example of test vector information given a test vector name AAA, and FIG. 4B shows an example of test vector information given a test vector name BBB. Each test vector is assigned an address 55 (also called step or cycle).
[0038]
When measuring at multiple points, the test vector of which of these test vectors is used may be measured at a random address or at an address extracted by a predetermined method. . However, it is of course desirable to measure at as many points as possible to obtain more reliable data. Since the output signal group is an expected value signal in the logic test, only the input signal group in the test vector 53 is used in the present embodiment.
[0039]
Specific examples of measurement results obtained using such test vectors (first quantity of test vectors) are shown in FIGS. FIG. 4 shows the measurement results obtained for the three non-defective samples PA, PB, and PC, and FIG. 5 shows the measurement results obtained for the three defective product samples FA, FB, and FC. As shown in both figures, the pattern name (PAT), address number (ADR), and current value (IdQ) are obtained for each sample by multipoint measurement.
[0040]
FIG. 6 is a graph that visually represents the relationship between successive addresses (address pair groups) and current values corresponding to the respective addresses based on the measurement result information shown in FIGS. 4 and 5. FIG. 4A shows the relationship between the current values of the non-defective samples PA, PB, and PC and the respective measurement points, and FIG. 5B shows the relationship between the current values of the defective product samples FA, FB, and FC and the respective measurement points.
[0041]
As is clear from the comparison between FIGS. 9A and 9B, in the example shown in the figure, within the section where the current value of the non-defective product is stable (ADR 87 of pattern name AAA to ADR 30 of pattern name BBB). It can be seen that there is a portion where the current value of the defective product is unstable, that is, a portion where the change in the current value is large.
[0042]
Here, FIG. 7 shows an example of the concept of the characteristic current value change rate in this embodiment. The rate of change is how much it changes. In this embodiment, when the current values acquired at the measurement points corresponding to each address are a and b for any combination of address pairs, the current The value change rate C is defined as (ba) / a or (ab) / b. The definition of the current value change rate is not limited to the method shown in the figure, and it is needless to say that the current value change rate can be determined according to the type of the test object and the required specifications such as a differential value.
[0043]
The procedure for calculating the current value change rate according to the definition shown in FIG. 7 (FIG. 1, step S60) will be specifically described with reference to the flowchart of FIG.
[0044]
First, a combination of address pairs is determined based on the current value data for each address obtained by the multipoint IddQ measurement (FIG. 1, steps S20 and S30) (step S61). Next, in each address pair, the current value data a and b at each measurement address are substituted into the calculation formula shown in FIG. 7 (step S62), and the current value change rate C is obtained for each address pair (step S62). S63).
[0045]
Next, a method for calculating the non-defective product change rate range (FIG. 1, step S90) will be described.
[0046]
FIG. 9 is an explanatory diagram showing the current value change rate in the non-defective sample shown in FIG. 4 for each address pair. As shown in the reference range column of the figure, if the minimum value is Cs and the maximum value is Cl among the current value change rates corresponding to the same address pair in the three non-defective samples PA, PB and PC, an arbitrary Non-defective rate change range C in address pair _P Is Cs <C _P <Cl.
[0047]
Here, out of the current value change rate of the defective product sample, this non-defective product change rate range C _P It can be determined that the address pair corresponding to the current value change rate belonging to the group is extremely unlikely to detect a failure in the mass production test.
[0048]
Therefore, non-defective rate change range C _P And the current value change rate of the defective product for each address pair (FIG. 1, step S100), and the non-defective product change rate range C among the current value change rates of the defective products. _P By extracting an address pair (address pair of the first combination) corresponding to those not belonging to the group (step S110 in FIG. 2), it is possible to select an effective address pair in which failure detection can be expected.
[0049]
After selecting the effective address pairs in this way, the pass / fail judgment reference range L used for the mass production test is determined for each of the selected address pairs (FIG. 2, step S120).
[0050]
FIG. 10 shows a definition example of the non-defective product determination reference range L. Since the mass production test is generally performed in consideration of errors, in the example shown in FIG. 10, the non-defective product change rate range C calculated using the current value change rate of FIG. _P Is defined in consideration of the error α. In this embodiment, the error α is (maximum value Cl−minimum value Cs) / 2.
[0051]
Furthermore, according to the present embodiment, the measurement point in the mass production test can be further narrowed down according to the required specification by comparing the pass / fail judgment reference range L defined in this way with the current value change rate of the defective product sample. it can.
[0052]
FIG. 11 is an explanatory diagram including the result of calculating the change rate of the current value of the defective product sample shown in FIG. 5 corresponding to each address pair of the non-defective product sample shown in FIG. In the figure, the calculated current value change rate of the defective product is shown in comparison with the pass / fail judgment reference range L.
[0053]
In the example shown in the drawing, the current value change rates between the address pairs 21 and 43 when PAT = AAA and between the address pairs 28 and 30 when PAT = BBB are both included in the pass / fail judgment reference range L. It can be seen that failure detection cannot be expected even if a mass production test is performed with these address pairs. Accordingly, these address pairs are not included in the address pairs of the first combination described above.
[0054]
On the other hand, between PAT = AAA address pair 109 and 111, PAT = AAA address 113 and PAT = BBB address 17 address pair, PAT = BBB address pair 17, 19 address pair 21, 24, the address pair 24, 26, the current value change rate between the address pair 36, 37 and the address pair 37, 49 at PAT = CCC are all within the range of the pass / fail judgment reference range L for one defective product. Therefore, according to these address pairs, it can be expected to detect a defective product corresponding to one defective product sample.
[0055]
Also, between the address pairs 43 and 65 at PAT = AAA, between 65 and 87, between 87 and 109, between 111 and 113, between the address pairs 26 and 28 at PAT = BBB, PAT = BBB address 30 and PAT = The current value change rate between the address pair with the address 33 of the CCC and between the address pair 33 and 36 with the PAT = CCC is outside the range of the pass / fail judgment reference range L for the two defective products. Therefore, according to these address pairs, it can be expected that defective products corresponding to two defective product samples are detected.
[0056]
Furthermore, since the rate of change in the current value between PAT = BBB19 and 21 is not within the pass / fail criterion range L for all three defective products, the defective product corresponding to the three defective samples with this pair of addresses. It can be seen that the mass production test using this address pair is the most efficient.
[0057]
As described above, since the possibility that a defective product can be detected differs depending on the combination of address pairs, the above-mentioned pass / fail judgment criterion is selected after selecting an address pair (address pair of the third combination) according to the required specifications. If IddQ measurement is performed in the mass production test using the information in the range L (FIG. 2, step S130), defective products that could not be detected by the conventional IddQ measurement test method using the current value as a criterion will be high throughput. It can be detected. This makes it possible to analyze a failure that could not be detected in the past, and to provide feedback more quickly to the design department and the process department. As a result, it is possible to improve the analysis efficiency for elucidating the cause of the defect and to make early improvement for the defect.
[0058]
Further, since the test vector address pairs used for measurement can be combined as appropriate, the time required for the test can be flexibly adjusted according to the required specifications.
[0059]
(2) One embodiment of a semiconductor test apparatus
Next, an embodiment of a semiconductor test apparatus according to the present invention will be described with reference to the drawings.
[0060]
FIG. 12 is a block diagram showing a schematic configuration of the semiconductor test apparatus of the present embodiment. The semiconductor test apparatus 1 shown in FIG. 1 includes a data reading unit 10, a measurement point determination unit 20 as a determination unit, an IddQ measurement unit 30, and a result display unit 40, and the semiconductor test method according to the present invention described above. Works according to.
[0061]
The data reading unit 10 reads the test program, the test vector, and the data related to the non-defective product and the defective product and supplies them to the measurement point determination unit 20.
[0062]
FIG. 13 is a block diagram illustrating a detailed configuration of the measurement point determination unit 20. As shown in the figure, the measurement point determination unit 20 includes a data acquisition unit 24, a tester 22, a memory 25, a current value change rate calculation unit 26, a reference range determination unit 27, a data comparison unit 28, and a measurement range determination unit. A certain measurement point group determination unit 29 is included.
[0063]
The data acquisition unit 24 is supplied with a test program, test vector data, and the like from the data reading unit 10, and multipoint IddQ is performed on the non-defective product sample and the defective product sample prepared in advance by the tester 22 based on these data. Perform the measurement. The current value as the measurement result is stored in the memory 25 in association with the address of each test vector. The current value change rate calculation unit 26 extracts data such as current values and test vector addresses from the memory 25, calculates the current value change rate for each address pair for each of the non-defective product and the defective product, and calculates the calculation result of the good product sample. The result is supplied to the reference range determination unit 27 and the calculation result of the defective product sample is supplied to the data comparison unit 28.
[0064]
The reference range determination unit 27 receives the calculation result of the current value change rate of the non-defective product from the current value change rate calculation unit 26 and receives the non-defective product change rate range C _P The pass / fail judgment reference range L is calculated and supplied to the data comparison unit 28.
[0065]
The data comparison unit 28 mutually determines the current value change rate of the defective product supplied from the current value change rate calculation unit 26 and the pass / fail judgment reference range L supplied from the reference range determination unit 27 for each address pair. The comparison is made, and the sample name of the defective product for which the current value change rate outside the pass / fail criterion range L is obtained and the address pair of the test vector at that time are supplied to the measurement point group determination unit 29.
[0066]
Based on the data supplied from the data comparison unit 28, the measurement point group determination unit 29 requests a device under test in which an address pair in which there are more defective product samples outside the pass / fail judgment reference range L is set. Search according to the specification, extract as an address pair group for mass production test (address pair of first or second combination), and output this mass production test address pair group together with pass / fail judgment reference range L.
[0067]
Returning to FIG. 12, the IddQ measurement unit 30 includes a mass production tester 32, a data acquisition unit 34, and a quality determination unit 36.
[0068]
The data acquisition unit 34 is supplied with the data of the mass production test address pair group and the quality determination reference range L from the measurement point determination unit 20, and supplies the mass production test address pair group to the mass production tester 32 and the quality determination unit 36. In addition, the quality determination unit 36 is supplied with data of the quality determination reference range L.
[0069]
The mass production tester 32 performs IddQ measurement of the mass-produced test object based on the data of the mass production test address pair group supplied from the data acquisition unit 34 and supplies the measurement result to the data acquisition unit 34. The data acquisition unit 34 also constitutes a calculation means, and calculates a current value change rate (second current value change rate) corresponding to each address pair for each DUT from the result of IddQ measurement by the mass production tester 32. The calculation result is supplied to the pass / fail judgment unit 36.
[0070]
The pass / fail determination unit 36 determines pass / fail for each device under test based on the current value change rate data supplied from the data acquisition unit 34 and the data of the pass / fail determination reference range L, and the current value obtained from the test device. When there is a current value change rate out of the pass / fail judgment reference range L among the change rates, the device under test is determined to be defective. If not defective, proceed to the next test of the device under test.
[0071]
The result display unit 40 displays the determination result received from the pass / fail determination unit 36 on a CRT (Cathode Ray Tube) (not shown) or the like.
[0072]
(3) Recording medium
The series of procedures of the semiconductor test method of the embodiment described above in (1) may be stored in a recording medium such as a floppy disk or a CD-ROM as a program to be executed by the computer, and read and executed by the computer. Thereby, the semiconductor test method according to the present invention can be realized using a test apparatus including a general-purpose computer such as a workstation. The recording medium is not limited to a portable medium such as a magnetic disk or an optical disk, but may be a fixed recording medium such as a hard disk device or a memory. Further, a program incorporating a series of procedures of the semiconductor test method described above may be distributed via a communication line (including wireless communication) such as the Internet. Furthermore, the program incorporating the series of procedures of the semiconductor test method described above is encrypted, modulated, or compressed, and stored in a recording medium via a wired line or a wireless line such as the Internet. You may distribute it.
[0073]
【The invention's effect】
As described above in detail, the present invention has the following effects.
[0074]
That is, according to the semiconductor test apparatus of the present invention, the determination means for determining the pass / fail judgment reference range based on the first rate of change in current value obtained from the non-defective sample, and the second means obtained from the device under test. Since the determination means for comparing the current value change rate and the above pass / fail judgment reference range for each address pair is provided, defective products that could not be detected by the conventional test apparatus can be detected with excellent throughput.
[0075]
Further, according to the semiconductor test method of the present invention, the step of determining the pass / fail judgment reference range for each address pair based on the first current value change rate obtained from the non-defective sample and the test object A step of comparing the second current value change rate and the pass / fail judgment reference range for each address pair, so that defective products that could not be detected by the conventional test method based on IddQ measurement using the current value as the judgment reference are provided. It can be detected with high throughput. Thereby, the analysis efficiency for elucidating the cause of the defect can be improved, and an early improvement for the defect can be achieved. Further, since the address pairs for mass production test can be combined as appropriate, the time required for the test can be flexibly adjusted according to the required specifications.
[0076]
Further, according to the recording medium of the present invention, the semiconductor test method having the above-described effects can be performed using a semiconductor test apparatus having a general-purpose computer.
[Brief description of the drawings]
FIG. 1 is a flowchart for explaining an embodiment of a semiconductor test method according to the present invention.
FIG. 2 is a flowchart illustrating an embodiment of a semiconductor test method according to the present invention.
FIG. 3 is an explanatory diagram of an example of a test vector.
4 is an explanatory diagram showing the result of IddQ measurement of a non-defective sample over many points by the method shown in FIGS. 1 and 2. FIG.
FIG. 5 is an explanatory diagram showing the result of IddQ measurement of a defective sample over multiple points by the method shown in FIGS. 1 and 2;
FIG. 6 is an explanatory diagram showing a relationship between a current value obtained by IddQ measurement over multiple points and a measurement point.
FIG. 7 is an explanatory diagram illustrating a definition example of a current value change rate.
FIG. 8 is a flowchart showing a method of calculating a current value change rate.
FIG. 9 is an explanatory diagram showing an example of a current value change rate of a non-defective product.
FIG. 10 is an explanatory diagram illustrating a definition example of a pass / fail judgment reference range.
FIG. 11 is an explanatory diagram showing an example of a current value change rate of a defective product.
FIG. 12 is a block diagram showing a schematic configuration of an embodiment of a semiconductor test apparatus according to the present invention.
13 is a block diagram showing a specific configuration of a measurement point determination unit of the semiconductor test apparatus shown in FIG.
[Explanation of symbols]
1 Semiconductor test equipment
10 Data reading part
20 Measurement point determination section
22 Tester
24, 34 Data acquisition unit
25 memory
26 Current value change rate calculation unit
27 Reference range determination unit
28 Data comparison part
29 Measurement point group determination unit
30 IddQ measurement unit
32 Mass production tester
36 Pass / Fail Judgment Unit
40 Result display area

Claims

Reading means for reading measurement data including a first quantity of test vectors;
Measuring means for inputting the test vector to a semiconductor device and measuring the current value output from the semiconductor device in association with the address of the test vector;
Calculating means for calculating, for each address pair, a current value change rate between the two current values corresponding to the address pair with two different addresses as address pairs;
Based on the first current value change rate obtained by inputting the first quantity of test vectors to a non-defective product sample, a pass / fail judgment reference range serving as a reference for judging pass / fail of the semiconductor device as the device under test is determined. A determination means;
The second current value change rate obtained by inputting the test vector to the device under test is compared with the pass / fail judgment reference range for each address pair, and based on the comparison result, the device under test is a non-defective product. A determination means for determining whether the product is defective or defective,
A semiconductor testing apparatus comprising:

2. The semiconductor test apparatus according to claim 1, wherein the determination unit determines the pass / fail judgment reference range based on a plurality of the first current value change rates obtained for a plurality of non-defective samples.

The determining means includes
A third current value change rate obtained by inputting the first quantity of test vectors to a defective product sample is compared with the pass / fail judgment reference range for each address pair, and is out of the pass / fail judgment reference range. Measuring range determining means for extracting the address pair corresponding to the third current value change rate to be a first combination address pair group by extracting from the address pairs of the first quantity of test vectors. Including
3. The semiconductor test apparatus according to claim 1, wherein the measuring unit inputs the test vector corresponding to the first combination of address pairs to the device under test.

The measurement range determining means compares the plurality of third current value change rates obtained for a plurality of defective product samples with the pass / fail judgment reference range for each address pair, and out of the pass / fail judgment reference range. The second combination of address pairs to be input to the device under test according to the quantity of the defective samples from which the third current value change rate is obtained is the first combination of address pairs. 4. The semiconductor test apparatus according to claim 3, wherein the semiconductor test apparatus is selected from a group.

A first quantity of test vectors is input to a first semiconductor device that is a non-defective sample, and a current value output from the non-defective sample is measured in association with an address of the test vector, and output as a first current value. And a process of
Calculating a change rate between the two first current values corresponding to the address pair as two different addresses as an address pair, and outputting the change rate as the first current value change rate; ,
Determining a pass / fail judgment reference range, which is a pass / fail judgment reference, for each address pair based on the first current value change rate;
A second current value is obtained by inputting the first quantity of test vectors to a second semiconductor device, which is a device under test, and measuring a current value output from the second semiconductor device in association with the address. And a process of outputting as
Calculating a change rate between the two second current values corresponding to the address pair for each address pair, and outputting the second current value change rate as a second current value change rate;
A step of comparing the second current value change rate and the pass / fail judgment reference range for each address pair, and determining whether the second semiconductor device is a non-defective product or a defective product based on the comparison result. When,
A semiconductor test method comprising:

The first semiconductor device comprises a plurality of non-defective samples,
The first current value and the first current value change rate are output for each non-defective sample,
The semiconductor test method according to claim 5, wherein the pass / fail judgment reference range is determined based on a plurality of the first current value change rates.

A third current is obtained by inputting the first quantity of the test vectors to a third semiconductor device, which is a defective sample, and measuring a current value output from the third semiconductor device in association with the address. Outputting as a value;
Calculating a rate of change between the two third current values corresponding to the address pair for each address pair, and outputting the rate as a third current value rate of change;
The third current value change rate and the pass / fail judgment reference range are compared for each address pair, and the address pair corresponding to the third current value change rate that falls outside the pass / fail judgment reference range is set to Extracting from the address consisting of the first quantity as one combination of address pairs;
Further comprising
The step of measuring the second current value is a step of inputting and measuring the test vector corresponding to the extracted address pair of the first combination to the second semiconductor device. The semiconductor test method according to claim 5 or 6.

The third semiconductor device includes a plurality of defective samples,
The third current value and the third current value change rate are output for each defective product sample,
Comparing the third current value change rate obtained for a plurality of the defective product samples and the pass / fail judgment reference range for each address pair;
According to the quantity of the defective samples from which the third current value change rate that is outside the pass / fail judgment reference range is obtained, the first combination address pair to the second combination address pair are changed. A process to elect,
Further comprising
The step of measuring the second current value is a step of inputting and measuring the test vector corresponding to the address pair of the second combination into the second semiconductor device. 8. The semiconductor test method according to 7.

Reading means for reading measurement data including a test vector, measuring means for inputting the test vector to a semiconductor device and measuring a current value output from the semiconductor device, and the device under test based on the current value A determination means for determining whether the product is a non-defective product or a defective product, and a semiconductor test system comprising:
A first quantity of test vectors is input to a first semiconductor device that is a non-defective sample, and a current value output from the non-defective sample is measured in association with an address of the test vector, and output as a first current value. And the steps to
A procedure for calculating a rate of change between the two first current values corresponding to the address pair as two different addresses as an address pair for each address pair and outputting the rate as a first current value rate of change; ,
A procedure for determining a pass / fail judgment reference range that is a pass / fail judgment reference based on the first current value change rate for each address pair;
A second current value is obtained by inputting the first quantity of test vectors to a second semiconductor device, which is a device under test, and measuring a current value output from the second semiconductor device in association with the address. And the procedure to output as
Calculating a rate of change between the two second current values corresponding to the address pair for each address pair and outputting the rate as a second current value rate of change;
A procedure for comparing the second current value change rate and the pass / fail judgment reference range for each address pair, and determining whether the second semiconductor device is a non-defective product or a defective product based on the comparison result. When,
A computer-readable recording medium on which a program for causing a computer to execute a semiconductor test method is recorded.

The first semiconductor device comprises a plurality of non-defective samples,
The first current value and the first current value change rate are output for each non-defective sample,
The recording medium according to claim 9, wherein the pass / fail judgment reference range is determined based on a plurality of the first current value change rates.

The semiconductor test method includes:
A third current is obtained by inputting the first quantity of the test vectors to a third semiconductor device, which is a defective sample, and measuring a current value output from the third semiconductor device in association with the address. A procedure to output as a value,
Calculating a rate of change between the two third current values corresponding to the address pair for each address pair and outputting the rate as a third current value rate of change;
The third current value change rate and the pass / fail judgment reference range are compared for each address pair, and the address pair corresponding to the third current value change rate that falls outside the pass / fail judgment reference range is set to Extracting from the address of the first quantity as one combination of address pairs;
The procedure for measuring the second current value is a procedure for inputting and measuring the test vector corresponding to the extracted address pair of the first combination to the second semiconductor device. The recording medium according to claim 9 or 10.

The third semiconductor device includes a plurality of defective samples,
The third current value and the third current value change rate are output for each defective product sample,
The semiconductor test method includes:
A procedure for comparing the third current value change rate obtained for a plurality of the defective product samples and the pass / fail judgment reference range for each address pair;
According to the quantity of the defective samples from which the third current value change rate that is outside the pass / fail judgment reference range is obtained, the first combination address pair to the second combination address pair are changed. And a procedure for selecting,
The procedure of measuring the second current value is a procedure of inputting and measuring the test vector corresponding to the address pair of the second combination to the second semiconductor device. 11. The recording medium according to 11.