JP5521423B2 - Semiconductor integrated circuit evaluation method, semiconductor integrated circuit, and semiconductor integrated circuit evaluation apparatus - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit evaluation method, a semiconductor integrated circuit, and a semiconductor integrated circuit evaluation in which a defective transistor is detected in an evaluation circuit configured on a large-scale semiconductor integrated circuit and characteristics of the defective transistor are measured at high speed. Relates to the device.

  When developing micro processes for semiconductors, a TEG (Test Element Group) is created to evaluate elements of various dimensions in order to evaluate and analyze the characteristics of micro elements (transistors, resistor elements, etc.). We have developed devices that can withstand mass production. In the process development so far, the characteristics and characteristics of each transistor have been evaluated and analyzed, and the optimum process and transistor have been set. However, as the miniaturization has progressed, variations in the characteristics of a plurality of transistors cannot be ignored. In addition, the phenomenon that the stress changes depending on the state of the element and the characteristics of the transistor change cannot be ignored.

  For example, in a fine process with a processing level of 45 nm, the characteristics of adjacent transistors vary, and the detection margin and the amplification circuit that detect a minute signal such as SRAM (Static Random Access Memory) with a pair transistor decrease the operation margin. Or is expected to become inoperable. In this case, sufficient data cannot be obtained in the evaluation of individual transistors, statistical processing is performed on a large amount of element characteristics, analysis is performed, and characteristic differences due to transistor configuration and arrangement, characteristic differences due to variations can be separated and analyzed, Large-scale TEG has become necessary.

  Conventionally, as a TEG for performing large-scale element evaluation, for example, there is a DMA (Device Matrix Array) -TEG (Test Element Group) in which evaluation circuits composed of a plurality of transistors can be arranged and evaluated (non-elementary). (See Patent Document 1).

In addition, with the increase in the scale of large-scale semiconductor integrated circuits and the increased integration of transistors due to process miniaturization, the number of transistors integrated in one semiconductor device (device) increases, resulting in a decrease in yield. Yes.
For example, in a certain semiconductor device, in the case of a process in which the variation of the threshold value Vth of a transistor is allowable up to ± 6σ (σ (sigma) is a standard deviation), the device is “1 chip = 1M as shown in FIG. In the “transistor”, 2 chips out of 1000 chips are defective. On the other hand, as shown in FIG. 16B, when the device is “1 chip = 1G transistor”, all chips may be defective. Each square in FIG. 16 indicates one transistor, and conceptually indicates that a plurality of transistors are arranged in each chip.

  In order to improve the yield, it is necessary to analyze a defective transistor outside the range of ± 6σ. As shown in the example of the normal distribution of the threshold value Vth shown in FIG. 15, there are only two of the 1G transistors that are statistically defective, and therefore a DMA-TEG that can measure at least 1G transistors is used. It is necessary to measure the threshold value Vth of the transistor and its variation.

  In this case, for example, when calculating extrapolation Vth for measurement of threshold value Vth, or when defining a gate voltage at which a current of 100 nA flows as threshold value Vth, about 10 points are required to calculate one threshold value Vth. Requires measurement data. These measurements are current measurements and take time to converge. For this reason, it has been required to shorten the measurement time required for measuring a huge number of transistors.

  Therefore, the inventor of the present application reduces the measurement time by performing the following measurement. As shown in FIG. 17A, in the measurement, in order to examine transistors out of the 6σ distribution, detailed evaluation (voltage measurement of threshold Vth, evaluation of Vg-Id characteristics, etc.) is performed on all 1G transistors. Therefore, enormous measurement time was required. Therefore, as shown in FIG. 17B, first, transistors that deviate from the distribution within ± 5σ (287 as expected values for calculation) are selected. The transistors configured on the DMA-TEG are determined by the threshold Vth determination mode shown in FIG. 18 to determine whether they are included in the distribution within ± 5σ, and are selected by detecting the transistors not included in the distribution within ± 5σ. Is done. In this threshold Vth determination mode, the threshold Vth of the measurement target transistor Tr in the evaluation cell array 11 shown in FIG. 18A is determined at high speed by the sense amplifier SA. Then, as shown in FIG. 18B, transistors that are out of the distribution within 5σ (287 as expected values for calculation) are selected. (Details of this threshold Vth determination mode will be described later.)

  Then, with respect to the transistor Tr selected from the threshold Vth determination mode and deviating from the distribution within 5σ, the detailed transistor characteristics are evaluated by the threshold Vth measurement mode (transistor characteristic measurement mode) shown in FIG. The measurement time is shortened. That is, the transistor to be measured Tr determined to be defective in the evaluation cell array 11 is selected, and the drain voltage / gate voltage / source voltage is applied to the transistor to be measured Tr, and the transistor characteristics such as the accurate threshold Vth are measured. . (Details of this threshold Vth measurement mode will be described later.) Thus, in a large-scale semiconductor integrated circuit such as DMA-TEG, detection of a defective transistor and measurement of transistor characteristics of the defective transistor are performed at high speed (short time). Can be done.

  In addition, as an invention related to the above problem, the present inventor has previously filed a patent application regarding a semiconductor integrated circuit and an evaluation method (see Patent Document 1). According to the semiconductor integrated circuit and the evaluation method disclosed in Patent Document 1, a transistor to be measured is configured as a pair transistor, and the threshold value Vth is not directly measured, but the difference between the threshold values Vth of the transistors is increased at high speed using an amplifier. By judging, an abnormal transistor whose characteristic deviates from the normal distribution can be found. With this method, the measurement time can be made about 1000 times faster than the conventional method.

  In the above-described semiconductor integrated circuit such as DMA-TEG, when considering further enlargement and further increase in measurement speed, it is necessary to use a plurality of sense amplifiers in order to increase the number of transistors that can be measured simultaneously. FIG. 20 shows an arrangement image of a plurality of sense amplifiers. As shown in FIG. 20, in the 1-Gbit DMA-TEG, the evaluation cell array is divided into 32 blocks A1 to A32 in units of 32 Mbits, and each of the blocks A1 to A32 is divided into two units in units of 16 Mbits. By providing four, four systems can be measured simultaneously in the threshold Vth determination mode. Thereby, measurement time can be shortened.

JP 2008-171920 A

IEEE 2002 Unt. Conference on Microelectronic Test Structure (ICMTS 2002), pp49-54 April 2002

  However, when the threshold value Vth is determined using a plurality of sense amplifiers, it is ideal that the same condition is applied to all the transistors Tr. However, in the above-described DMA-TEG, the sense amplifier SA is 4 in number. Therefore, variations in the sense amplifier characteristics such as an offset difference occur due to variations in the characteristics of the MOS transistors constituting each sense amplifier SA. For this reason, the accuracy of the threshold Vth determination deteriorates due to the offset difference between the sense amplifiers SA.

  For example, when the distribution characteristic of the threshold value Vth when the number of sense amplifiers SA shown in FIG. 21A is one and the distribution characteristic of the threshold value Vth when there are four sense amplifiers SA shown in FIG. When there are four sense amplifiers SA, the distribution of the measured threshold value Vth also varies due to variations in MOS transistor characteristics within the sense amplifier SA. Due to this variation, a non-defective transistor may be determined as a defective transistor and selected in the threshold Vth determination mode. For this reason, there is a possibility that the number of transistors Tr that are selected as being out of the distribution within ± 5σ may increase, and the measurement time increases due to an increase in the number of transistors whose characteristics should be measured in detail. For this reason, it is necessary to adjust (cancel) the offset difference of the sense amplifier SA.

  For example, FIG. 22 illustrates an example in which two sense amplifiers, that is, a sense amplifier SA_A and a sense amplifier SA_B are used. In the example shown in FIG. 22, the evaluation cell array is divided into two evaluation cell arrays 11 and 12, a sense amplifier SA_A is provided for the evaluation cell array 11, and a sense amplifier SA_B is provided for the evaluation cell array 12. In this case, since the sense amplifier SA_A and the sense amplifier SA_B do not necessarily have the same characteristics, the threshold value Vth determination criterion varies in the threshold Vth determination mode. For example, even in the case of transistors Tr having the same threshold Vth, the output states of the sense amplifiers SA_A and SA_B may be different. Therefore, when the threshold value Vth of the transistor Tr group in the evaluation cell arrays 11 and 12 is determined using the plurality of sense amplifiers SA_A and SA_B, there is a problem that the determination accuracy of the threshold value Vth is lowered.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide an offset between sense amplifiers when a threshold value Vth of a transistor group in an evaluation cell array is determined using a plurality of sense amplifiers. An object of the present invention is to provide a semiconductor integrated circuit evaluation method, a semiconductor integrated circuit, and a semiconductor integrated circuit evaluation apparatus capable of canceling the difference and determining the threshold value Vth with high accuracy.

The present invention has been made to solve the above-described problems. A semiconductor integrated circuit evaluation method according to the present invention includes an evaluation cell array in which MOS transistors to be measured are arranged in a matrix, and a plurality of senses. The evaluation cell array is divided into a plurality of transistor groups corresponding to each of the plurality of sense amplifiers, and the first input terminal of each of the plurality of sense amplifiers includes the evaluation cell array. An output signal of the selected measurement target transistor in the cell array is input, and a reference signal for comparison with the output signal of the measurement target transistor is input to the second input terminal of each of the plurality of sense amplifiers. in the semiconductor integrated circuit configured to, in the drain when given a predetermined voltage to the drain of the measurement target transistor A semiconductor integrated circuit evaluation method for measuring the detection and characterization of defects transistors in the evaluation cell array by performing determination threshold value Vth is a gate voltage when a constant current flows, the IN terminal condition setting section, A first measurement step of applying an input signal of the same condition to a first input terminal of each of the plurality of sense amplifiers, and an offset difference adjustment unit configured to apply the same condition to a first input terminal of each of the plurality of sense amplifiers. In the state where the input signal is applied, a variable signal is input to the second input terminal of each of the plurality of sense amplifiers, and a change in the output of each of the plurality of sense amplifiers is detected, thereby the plurality of sense amplifiers the different reference signals in response to the offset difference between the second measurement step of measuring for each of said plurality of sense amplifiers, poor Transistor identification unit, while applying a predetermined gate voltage to the measured transistor among the evaluation cell array, the output signal of the measurement target transistor to said plurality of sense amplifiers and the reference respectively different for each of said plurality of sense amplifiers A third measurement step for determining a defective transistor whose threshold value Vth is out of a predetermined range based on the outputs of the plurality of sense amplifiers, and a transistor characteristic measurement unit configured to detect the defective transistor by the third measurement step. And a fourth measurement step for measuring transistor characteristics.

  In the semiconductor integrated circuit evaluation method of the present invention, the sense amplifier is a current-type sense amplifier.

  In the semiconductor integrated circuit evaluation method of the present invention, the sense amplifier is a voltage-type sense amplifier.

  In the semiconductor integrated circuit evaluation method of the present invention, in the third measurement step, the threshold value Vth of the measurement target transistor is a distribution within 5σ (σ is a standard deviation) with respect to the normal distribution curve of the threshold value Vth. The transistor to be measured that has deviated is determined to be the defective transistor, and in the fourth measurement step, the transistor characteristics are measured for the defective transistor that has deviated from the distribution in which the threshold Vth is within 5σ. Features.

The semiconductor integrated circuit according to the present invention has an evaluation cell array in which transistors to be measured are arranged in a matrix, and the measurement target transistors in the evaluation cell array are selected by signals output from a column decoder and a row decoder. A plurality of sense amplifiers, and the evaluation cell array is divided into a plurality of transistor groups corresponding to each of the plurality of sense amplifiers. An output signal of a selected transistor in the evaluation cell array is input to a first input terminal of the sense amplifier, and the plurality of sense amplifiers are input to a second input terminal of each of the plurality of sense amplifiers. Different reference signals are input according to the offset difference between the amplifiers.

  In the semiconductor integrated circuit of the present invention, the plurality of sense amplifiers are configured by current-type sense amplifiers, and the reference current of the reference signal input to the second input terminal of each of the plurality of sense amplifiers is adjusted. Thus, when the same input is applied to the first input terminal regardless of the offset difference between the plurality of sense amplifiers, the outputs of the plurality of sense amplifiers match each other.

  In the semiconductor integrated circuit of the present invention, the current-type sense amplifier has a current mirror circuit composed of a pair of P-channel MOS transistors, and the reference current flowing through the second input terminal is used as the current mirror. It is a simple current mirror type sense amplifier configured to flow to the reference current side of the circuit.

    In the semiconductor integrated circuit of the present invention, the current-type sense amplifier includes two current mirror circuits each composed of a pair of P-channel MOS transistors connected in cascade and flowing to the second input terminal. It is a cascade simple current mirror type sense amplifier configured to flow a reference current to a reference current side of the current mirror circuit.

  Further, in the semiconductor integrated circuit of the present invention, the current sense amplifier has three P-channel MOSs that use the current flowing through the first input terminal as a reference current and supply the first and second mirror currents. A first current mirror circuit composed of a transistor and a pair of N-channel MOS transistors, and a first current mirror circuit driven by using a first mirror current flowing from the first current mirror circuit as a reference current A second current mirror composed of a current sink circuit and three P-channel MOS transistors that supply the first and second mirror currents using the reference current flowing through the second input terminal as a reference current And a first mirror current flowing from the second current mirror circuit as a reference current. A second current sink circuit that is driven, wherein a second mirror current flowing from the first current mirror circuit is caused to flow as a mirror current of the second current sink circuit, and the second current sink circuit The second mirror current flowing from the mirror circuit is configured to flow as the mirror current of the first current sink circuit.

  In the semiconductor integrated circuit of the present invention, the plurality of sense amplifiers are voltage-type sense amplifiers, and the reference voltage of the reference signal input to the second input terminal of each of the plurality of sense amplifiers is adjusted. Thus, when the same input is applied to the first input terminal regardless of the offset difference between the plurality of sense amplifiers, the outputs of the plurality of sense amplifiers match each other.

  In the semiconductor integrated circuit of the present invention, the voltage-type sense amplifier includes a pair of N-channel MOS transistors constituting a differential input pair, and a pair of N-channel MOS transistors connected as a load to the pair of N-channel MOS transistors. And a current amplification circuit comprising a P-channel MOS transistor.

According to another aspect of the present invention, there is provided a semiconductor integrated circuit evaluation apparatus for evaluating the semiconductor integrated circuit described above, wherein signals applied to first input terminals of the plurality of sense amplifiers have the same condition. An input terminal condition setting mode to be set to, an offset difference adjustment mode to adjust an offset difference between the plurality of sense amplifiers, and a predetermined voltage is applied to the drain of the measurement target transistor using the plurality of sense amplifiers A threshold Vth determination mode for determining a threshold Vth that is a gate voltage when a predetermined current flows through the drain, and a threshold Vth measurement mode for measuring the transistor characteristics of the measurement target transistor determined to be defective by the threshold Vth determination mode In the measurement mode switching unit for switching between and the input terminal condition setting mode, the plurality of sense arrays In the offset difference adjustment mode, the input terminal condition setting unit causes the first input terminals of the plurality of sense amplifiers to be input to the first input terminals of the plurality of sense amplifiers. By inputting a variable signal to the second input terminal of each of the plurality of sense amplifiers in a state where signals of the same condition are input, and detecting a change in the output of the sense amplifier, In the offset difference adjustment unit that measures the reference signal according to the offset difference of each of the plurality of sense amplifiers and the threshold Vth determination mode, the measurement target transistor in the evaluation cell array is sequentially selected, and the selected measurement is performed. A defective transistor based on output signals from the plurality of sense amplifiers by applying a predetermined gate voltage to the target transistor A defective transistor identifying unit that identifies and stores an address of the identified defective transistor in a storage unit; and in the threshold Vth measurement mode, selects a measurement target transistor that is determined to be defective by the defective transistor identifying unit, and the selection And a transistor characteristic measuring unit that measures a transistor characteristic by applying a desired gate voltage to the gate of the transistor to be measured.

In the semiconductor integrated circuit evaluation method of the present invention, a reference signal corresponding to an offset difference between a plurality of sense amplifiers is measured for each sense amplifier. Then, the output signal of the transistor to be measured and the reference signal are compared by a sense amplifier, a defective transistor whose threshold value Vth is out of a predetermined range is determined, and the transistor characteristics of the transistors that are determined as defective transistors are measured.
Thus, when a plurality of sense amplifiers are used to determine the threshold value Vth of the transistor group in the evaluation cell array, different determinations are made among the plurality of sense amplifiers regardless of the offset difference between the sense amplifiers. It is possible to determine the threshold Vth with no high accuracy. For this reason, even in a large-scale semiconductor integrated circuit such as a DMA-TEG, the characteristics of an abnormal transistor outside a predetermined distribution range can be evaluated with high accuracy and at high speed (in a short time).

Further, in the semiconductor integrated circuit evaluation method of the present invention, a transistor to be measured whose threshold value Vth of the transistor to be measured deviates from a distribution within ± 5σ (σ is a standard deviation) with respect to the normal distribution curve of the threshold value Vth is detected. To do.
As a result, even in a large-scale DMA-TEG having a memory capacity of 1 G (giga) bits, it is possible to narrow down to defective transistors that deviate from the ± 5σ distribution, and to measure the transistor characteristics of the narrowed measurement target transistors. For this reason, detection of a defective transistor and measurement of transistor characteristics of the defective transistor can be performed at high speed (in a short time).

The semiconductor integrated circuit of the present invention has a plurality of sense amplifiers for determining the threshold value Vth of the measurement target transistor in the evaluation cell array, and the evaluation cell array has a plurality of systems corresponding to each of the plurality of sense amplifiers. Divided into a plurality of transistor groups. The output signal of the measurement target transistor is input to the first input terminal of each sense amplifier, and the reference signal corresponding to the offset difference is input to the second input terminal of each sense amplifier. . Then, the output signal of the transistor to be measured and the reference signal are compared by a sense amplifier, and the transistor to be measured whose threshold value Vth is outside the predetermined range is determined as a defective transistor.
Thus, when the threshold value Vth of the transistor group in the evaluation cell array is determined using a plurality of sense amplifiers, the threshold value Vth can be determined with high accuracy regardless of the offset difference between the sense amplifiers. . For this reason, even in a large-scale semiconductor integrated circuit such as a DMA-TEG, the characteristics of an abnormal transistor outside a predetermined distribution range can be evaluated with high accuracy and at high speed (in a short time).

In the semiconductor integrated circuit evaluation apparatus of the present invention, a reference signal corresponding to the offset difference between the sense amplifiers in the semiconductor integrated circuit is measured for each sense amplifier, and this reference signal is given to each sense amplifier. Then, based on the comparison result between the output signal of the measurement target transistor output from the sense amplifier and the reference signal, the measurement target transistor whose threshold value Vth falls outside the predetermined range is determined as a defective transistor, and is determined as a defective transistor. Measure the transistor characteristics of the thing.
Thus, when the threshold value Vth of the transistor group in the evaluation cell array is determined using a plurality of sense amplifiers, the threshold value Vth can be determined with high accuracy regardless of the offset difference between the sense amplifiers. . For this reason, even in a large-scale semiconductor integrated circuit such as a DMA-TEG, the characteristics of an abnormal transistor outside a predetermined distribution range can be evaluated with high accuracy and at high speed (in a short time).

It is a figure explaining the basic idea of the semiconductor integrated circuit evaluation method of this invention. It is a figure explaining the setting method of IN electric current which flows into the IN terminal of a sense amplifier. It is a figure explaining the adjustment method of the reference current REF which flows into the REF terminal of a sense amplifier. It is a figure explaining the threshold Vth determination mode (high-speed sense mode) by a sense amplifier. It is a figure explaining threshold Vth measurement mode (transistor characteristic measurement mode). It is a flowchart which shows the measurement procedure in the semiconductor integrated circuit evaluation method of this invention. It is a figure which shows the structural example of a current type sense amplifier. FIG. 6 is a diagram for explaining the operation of a current writing type sense amplifier. It is a figure which shows the structural example of a voltage type sense amplifier. It is a figure which shows the 1st example of a setting of the input current to the IN terminal of a sense amplifier. It is a figure which shows the 2nd example of a setting of the input current to the IN terminal of a sense amplifier. It is a figure which shows the 3rd example of a setting of the input current to the IN terminal of a sense amplifier. It is a figure which shows the 4th example of a setting of the input current to the IN terminal of a sense amplifier. It is a figure which shows the structural example of the semiconductor integrated circuit evaluation apparatus of this invention. It is a figure which shows the example of the normal distribution of the dispersion | variation in the threshold value Vth. It is a figure explaining the problem in the highly integrated device accompanying process miniaturization. It is a figure explaining the example which selects a transistor by threshold value Vth determination mode. It is a figure explaining the threshold value Vth determination mode. It is a figure explaining the threshold value Vth measurement mode. It is a figure which shows the arrangement | positioning image of several sense amplifier. It is a figure which shows the example of the variation in the distribution characteristic of threshold value Vth by using a some sense amplifier. It is a figure explaining the problem of the fall of the determination precision of the threshold value Vth by several sense amplifiers.

[Basic Concept of Semiconductor Integrated Circuit Evaluation Method of the Present Invention]
FIG. 1 is a diagram for explaining the basic concept of the semiconductor integrated circuit evaluation method of the present invention. FIG. 1A shows the distribution characteristics of the threshold value Vth (100 nA / Vg) of the transistor Tr group and the determination result of the threshold value Vth in the two sense amplifiers SA_A and SA_B in the case of the prior art. FIG. 1B shows the distribution characteristics of the threshold value Vth (100 nA / Vg) of the transistor Tr group and the determination result of the threshold value Vth in the two sense amplifiers SA_A and SA_B in the present invention.

  Here, the threshold value Vth (100 nA / Vg) is defined as a gate voltage when a current of 100 nA flows through the drain when a voltage of 1 V is applied to the drain of the MOS transistor, for example. Further, the gate voltage when a current of 1 μA flows through the drain is defined as a threshold Vth (1 μA / Vg). In the present embodiment, a threshold value Vth (100 nA / Vg) is used.

  In the case of the prior art shown in FIG. 1A, the reference current REF input to the sense amplifier SA_A shown on the upper side of the drawing and SA_B shown on the lower side of the drawing is the same 100 nA. However, an offset difference is generated between the sense amplifiers SA_A and SA_B due to a difference in characteristics between the sense amplifier SA_A and the sense amplifier SA_B. Due to this offset difference, when the determination result of the threshold value Vth by the sense amplifier SA_A is compared with the determination result of the threshold value Vth by the sense amplifier SA_B, the sense amplifier SA_B has a defect “sense amplifier output OUT = H (high level)”. The range expands.

  On the other hand, in the case of the present invention, as shown in FIG. 1B, the reference current REF of the sense amplifier SA_A shown on the upper side of the drawing is set to 100 nA, and the reference current REF of the sense amplifier SA_B shown on the lower side of the drawing is set. In the threshold Vth determination mode by the sense amplifiers SA_A and SA_B, the current value of the reference current REF is changed to 120 nA, for example, according to the offset difference, regardless of the offset difference between the sense amplifiers SA_A and SA_B. The same result is output for the input. Hereinafter, changing the current value of the reference current REF to match the result of the threshold Vth determination mode regardless of the offset difference of the plurality of sense amplifiers SA is referred to as canceling the offset difference.

  In this way, by adjusting the reference current REF input to the sense amplifier, the range in which the sense (SA output OUT = H) becomes defective in the Vth determination by the sense amplifier SA_B is made to coincide with the case of the sense amplifier SA_A. Can do. As described above, in the present invention, when a plurality of sense amplifiers are used, the threshold Vth for the transistor Tr group is determined after the offset difference between the sense amplifiers is canceled by adjusting the reference current REF.

[Description of Specific Procedure of Semiconductor Integrated Circuit Evaluation Method of the Present Invention]
2 to 5 are diagrams showing specific procedures of the semiconductor integrated circuit evaluation method according to the present invention. Hereinafter, the procedure of the semiconductor integrated circuit evaluation method of the present invention will be described with reference to FIGS.

  FIG. 2 is a diagram showing a first step in the semiconductor integrated circuit evaluation method of the present invention. This first step is an IN terminal condition setting mode in which the input current conditions are the same at the input terminals IN of the sense amplifier SA_A and the sense amplifier SA_B.

  In this first step (IN terminal condition setting mode), as shown in FIG. 2A, a certain transistor Tr is selected by a column select signal and a row select signal in the evaluation cell array 11 connected to the sense amplifier SA_A. Then, the gate voltage when a predetermined current is passed between the drain and the source is measured (step S1).

  For example, when a voltage of 1 V is applied to the drain of the transistor Tr by a signal DBC (Drain Bias Control), a gate voltage Vg (100 nA / Vg) when a current of 100 nA flows between the drain and the source is represented by the drain, source, and gate. , And a four-terminal measurement performed by applying a voltage to the back gate.

  Similarly, as shown in FIG. 2B, for a certain transistor Tr in the evaluation cell array 12 connected to the sense amplifier SA_B, a gate voltage Vg (100 nA / 100 g) when a current of 100 nA flows between the drain and source. Vg) is investigated (measured) by 4-terminal measurement (step S1 ′).

  Accordingly, the gate voltage Vg (100 nA / Vg) of the transistor Tr when the same current (100 nA) is supplied to the IN terminals of the sense amplifier SA_A and the sense amplifier SA_B can be measured. Then, the current (hereinafter also referred to as “current IN”) flowing through the respective IN terminals of the sense amplifier SA_A and the sense amplifier SA_B is set to 100 nA.

  In the example of this embodiment, as described above, the gate voltage Vg (100 nA / Vg) when a current of 100 nA flows through the transistor Tr is defined as the threshold value Vth. This is, for example, 1 μA in the transistor Tr. The gate voltage Vg (1 μA / Vg) at the time of flowing the current may be defined as the threshold value Vth.

  FIG. 3 is a diagram showing a second step in the semiconductor integrated circuit evaluation method of the present invention. The second step is an offset for measuring a reference current (hereinafter also referred to as “reference current REF”) that flows to the REF terminal so that the offset difference between the sense amplifier SA_A and the sense amplifier SA_B is canceled. This is the difference adjustment mode.

  As shown in FIG. 3A, when the reference current REF is adjusted for the sense amplifier SA_A, the reference current REF is gradually increased under the condition of “input current IN <input current REF”, and the sense amplifier SA_A The reference current REF at which the output OUT becomes “L (low level)” from “H (high level)” is investigated (measured) (step S2). In this example, when the reference current REF is 110 nA, the output OUT of the sense amplifier SA_A transitions from “H” to “L”, resulting in “reference current REF = 110 nA”.

  Similarly, as shown in FIG. 3B, when the reference current REF is adjusted for the sense amplifier SA_B, the reference current REF is gradually increased under the condition of “input current IN <input current REF”. Then, the reference current REF at which the output OUT of the sense amplifier SA_B changes from “H” to “L” is investigated (step S2 ′). In this example, when the reference current REF is 110 nA, the output OUT of the sense amplifier SA_B remains “H”, and when the reference current REF is 120 nA, the output OUT of the sense amplifier SA_A changes from “H” to “L”. ”And becomes“ reference current REF = 120 nA ”.

  Thereby, the reference current REF in which the offset difference between the sense amplifier SA_A and the sense amplifier SA_B is canceled can be measured.

  FIG. 4 is a diagram showing a third step in the semiconductor integrated circuit evaluation method of the present invention. This third step is a threshold Vth determination mode (high-speed sense mode) that senses at high speed whether or not the threshold value Vth of the transistor Tr group in the evaluation cell arrays 11 and 12 is out of the distribution within 5σ. .

  In this threshold Vth determination mode, as shown in FIG. 4A, the threshold Vth of each transistor Tr in the evaluation cell array 11 is determined at high speed by the sense amplifier SA_A using the value of the reference current REF with the offset difference canceled. (Step S3). In this example, 110 nA is supplied as the reference current REF to the REF terminal, and is compared with the current flowing through each transistor Tr through the IN terminal. In this determination, for example, the transistor Tr that remains “H” without the output OUT of the sense amplifier SA_A being switched from “H” to “L” is specified as a defective transistor.

  This threshold Vth determination mode will be further described supplementarily. As shown in FIG. 18A, when the threshold voltage Vth of the transistor Tr group in the evaluation cell array 11 is sensed at high speed by the sense amplifier SA, the gate voltage / drain voltage / A source voltage is applied and the threshold value Vth is determined.

  The current at the IN terminal of the sense amplifier SA is a current signal flowing through the transistor Tr to be measured, and the current at the REF terminal of the sense amplifier SA is a reference signal (reference current REF). For example, the offset difference is adjusted. The resulting current is 110 nA (substantially 100 nA).

  In this configuration, a certain transistor Tr is selected by a column select signal and a row select signal in the evaluation cell array 11 connected to the sense amplifier SA. Then, for example, a gate voltage is applied to the transistor Tr in a state where a voltage of 1 V is applied to the drain of the transistor Tr by a signal DBC (Drain Bias Control), and a current flowing through the transistor Tr and a reference current REF are generated by the sense amplifier SA. Compare.

  In this case, for example, as shown in FIG. 18B, in the transistor Tr group in the evaluation cell array 11, the distribution of the gate voltage Vg (100 nA / Vg) when a current of 100 nA flows between the drain and the source is It is assumed that a normal distribution with a center value of 0.8 V is shown. The gate voltage Vg (100 nA / Vg) exceeding the range of variation 5σ is 1.0 V or more and 0.6 V or less.

  In this case, 1.0 V is input to the gate voltage Vg of the transistor Tr to be evaluated, the transistor Tr group in the evaluation cell array 11 is selected, and the current IN flowing through the selected transistor Tr and the reference current REF are sensed. Comparison is made by the amplifier SA. Then, it is determined whether or not the transistor Tr satisfies “current IN <reference current REF”, and determines that the transistor Tr satisfies “current IN> reference current REF” as a defective transistor, thereby determining the defective transistor Tr. Sort out.

  Similarly, 0.6V is input to the gate voltage Vg of the transistor Tr, the transistor Tr group in the evaluation cell array 11 is selected, and the current IN flowing through the selected transistor Tr and the reference current REF are converted to the sense amplifier SA. Compare with Then, the transistor Tr that satisfies “current IN <reference current REF” is selected as a defective transistor. Accordingly, it is possible to select transistors whose threshold Vth voltage (gate voltage Vg) is out of the distribution within 5σ, including the high side and the low side. The above 6σ is an example and may be 4σ or 5σ, and can be arbitrarily selected as necessary.

  In the above-described example, the gate voltage Vg of the transistor Tr is changed to select a transistor whose threshold Vth voltage (gate voltage Vg) is out of the distribution of 5σ within the high side and the low side. As described above, the selection can be performed by keeping the gate voltage Vg of the transistor Tr constant and increasing or decreasing the value of the reference current REF.

  Similarly, as shown in FIG. 4B, the threshold value Vth of each transistor Tr in the evaluation cell array 12 is determined at high speed by the sense amplifier SA_B using the value of the reference current REF with the offset difference canceled (step S3 ′). In this example, 120 nA is supplied as the reference current REF, and compared with the current flowing through each transistor Tr through the IN terminal, the defective transistor Tr whose threshold value Vth is out of the distribution within 5σ is specified.

  FIG. 5 is a diagram showing a fourth step in the semiconductor integrated circuit evaluation method of the present invention. In the fourth step, four-terminal measurement is performed on the specified defective transistor Tr in the evaluation cell array in the third step (threshold Vth determination mode) in the threshold Vth measurement mode (transistor characteristic measurement mode), and transistor characteristics are measured. (Accurate threshold Vth, Vg-Id characteristics, etc.) are measured.

  That is, as shown in FIG. 5A, for the evaluation cell array 11, the defective transistor Tr selected in the threshold Vth determination mode (high-speed sense mode) is selected by the column select signal and the row select signal. Then, a gate voltage, a drain voltage, a source voltage, and a back gate voltage are applied to the transistor Tr to be measured, and transistor characteristics are measured by four-terminal measurement (step S4).

  In this case, a desired voltage is applied to the drain of the transistor Tr to be measured by a signal DF (Drain Force). Further, by changing the gate voltage (word line voltage) of the transistor Tr according to the row select signal and measuring the current flowing through the drain, the accurate threshold value Vth or Vg−Id of the defective transistor Tr to be measured is measured. Characteristics and the like can be measured.

  Similarly, as shown in FIG. 5B, for the evaluation cell array 12, the defective transistor Tr selected in the threshold Vth determination mode (high-speed sense mode) is selected by the column select signal and the row select signal, and the measurement target A gate voltage, a drain voltage, a source voltage, and a back gate voltage are applied to the transistor Tr to be a four-terminal measurement (step S4 ′). Thereby, in the evaluation cell array 12, the accurate threshold value Vth, Vg-Id characteristic, etc. of the defective transistor Tr to be measured can be measured.

  In this way, by determining and selecting a transistor in which the threshold value Vth of each transistor constituting the evaluation cell arrays 11 and 12 exceeds a predetermined distribution range, and measuring the transistor characteristics of the selected transistor, DMA-TEG or the like In such a large-scale semiconductor integrated circuit, detection of a defective transistor and measurement of transistor characteristics of the defective transistor can be performed at high speed (in a short time).

  FIG. 6 is a flowchart showing the measurement procedures (steps) in the semiconductor integrated circuit evaluation method of the present invention described with reference to FIGS. Among these, FIG. 6A shows a processing flow as a more specific example, and FIG. 6B shows a more general general-purpose flow.

  In FIG. 6A, first, “IN = 100 nA” is set (step S1). In this step S1, in order to make the current conditions of the IN terminals of the sense amplifiers SA_B and SA_B the same for each sense amplifier, the current flowing through the transistor Tr (current flowing through the IN terminal) is adjusted to, for example, 100 nA.

  Next, “adjustment of the reference current REF value” is performed (step S2). In this step S2, in order to cancel the offset difference between the sense amplifiers SA_B and SA_B, the OUT terminal is changed from “H” to “L” while the current conditions of the IN terminals of the sense amplifiers SA_A and SA_B are the same. The current condition of the REF terminal is investigated (measured). The measured current condition is set as the reference current REF.

  Subsequently, “determination of threshold value Vth” is performed (step S3). In this step S3, the threshold value Vth of the measurement target transistor Tr is determined at high speed using a sense amplifier based on a preset reference threshold value Vth, and the reference threshold value Vth from a large number of transistors Tr. A nearby transistor Tr is specified. For example, the transistor Tr outside the range of 5σ distribution is specified.

  Then, “measurement of threshold value Vth” is performed (step S4). In step S4, for the specified transistor Tr, an accurate threshold value Vth is measured by four-terminal measurement, and, if desired, a Vg-Id characteristic is measured.

  In the general-purpose processing flowchart shown in FIG. 6B, first, the IN terminal condition is set to be the same between the sense amplifiers SA in the IN terminal condition setting mode (step S1A). Then, the offset difference between the sense amplifiers SA is canceled in the offset difference adjustment mode (step S2A).

  Next, the threshold value Vth of the measurement target transistor Tr is determined at high speed using the sense amplifier SA in the threshold value Vth measurement mode (step S3A). As a result, the transistor Tr near the reference threshold value Vth is identified from a large number of transistors Tr. For example, the transistor Tr outside the range of 5σ distribution is specified.

  Then, the transistor characteristics specified in step S3A are measured in the threshold Vth measurement mode, and the transistor characteristics such as the accurate threshold Vth and Vg-Id characteristics are measured by the four-terminal measurement (step S4A).

  In the procedure of the semiconductor integrated circuit evaluation method of the present invention described with reference to FIGS. 2 to 6, the first measurement step described above includes the IN terminal in which the current condition of the IN terminal is the same in each of the sense amplifiers SA_A and SA_B. This corresponds to the condition setting mode, and the second measurement step corresponds to an offset difference adjustment mode in which the offset difference between the sense amplifiers SA_A and SA_B is cancelled. The above-described third measurement step corresponds to the threshold Vth of the transistor Tr. This corresponds to the threshold Vth determination mode in which determination is performed, and the above-described fourth measurement step corresponds to a threshold Vth measurement mode (transistor characteristic measurement mode) in which the transistor characteristics of the transistors Tr selected in the threshold Vth determination mode are measured. The first input terminal of the sense amplifier corresponds to the IN terminals of the sense amplifiers SA_A and SA_B, and the second input terminal corresponds to the REF terminals of the sense amplifiers SA_A and SA_B. The reference signal described above corresponds to the reference current REF.

  With the above configuration, when the threshold value Vth of the transistor Tr group in the evaluation cell arrays 11 and 12 is determined using a plurality of sense amplifiers, the offset difference between the sense amplifiers is canceled and the threshold value Vth is highly accurate. Can be determined. For this reason, even in a large-scale semiconductor integrated circuit such as a DMA-TEG, the characteristics of an abnormal transistor outside a predetermined distribution range can be evaluated with high accuracy and at high speed (in a short time).

[Description of configuration example of sense amplifier]
FIG. 7 is a diagram showing a configuration example of the sense amplifier SA used in the present invention, which is an example of a current type sense amplifier.

  FIG. 7A shows a simple current mirror type sense amplifier, which forms a current mirror circuit by a pair of P-channel MOS transistors Q1 and Q2, connects the REF terminal to the drain of the transistor Q2 on the reference current side, and IN In this configuration, the terminal and the OUT terminal are connected to the drain of the transistor Q1 on the mirror current side.

  FIG. 7B shows a cascade simple current mirror type sense amplifier, which includes a current mirror circuit composed of a P-channel MOS transistor pair Q1, Q2, and a current mirror circuit composed of a P-channel MOS transistor pair Q3, Q4. Are connected in cascade. The REF terminal is connected to the drain of the transistor Q4 on the reference current side, and the IN terminal and the OUT terminal are connected to the drain of the transistor Q3 on the mirror current side. In this cascade simple current mirror type sense amplifier, fluctuations in the output current value due to fluctuations in the output OUT can be suppressed.

  FIG. 7C illustrates a current-spray type sense amplifier. This current erasing type sense amplifier circuit includes a first current mirror circuit composed of a P channel MOS transistor pair Q11, Q12, Q13 and a second current mirror circuit composed of a P channel MOS transistor pair Q21, Q22, Q23. A current mirror circuit; a first current sink circuit composed of an N-channel MOS transistor pair Q31, Q32; and a second current sink circuit composed of an N-channel MOS transistor pair Q41, Q42. Is done.

  In this current-passing sense amplifier, the first current sink circuit is driven by the current flowing from the first current mirror circuit (current flowing from Q12), and the current flowing from the second current mirror circuit (current flowing from Q22). As a result, the second current sink circuit is driven. The drain of the P channel MOS transistor Q13, the drain of the N channel MOS transistor Q41, the drain of the P channel MOS transistor Q21, and the drain of the N channel MOS transistor Q32 are connected in a brushed manner. Configured.

  FIG. 8 is a diagram for explaining the operation of the current-plow type sense amplifier shown in FIG. When the current at the IN terminal is larger than the reference current REF, I (Q13)> I (Q41) as shown in the operation characteristic curve on the right side of FIG. On the other hand, when the current at the IN terminal is smaller than the reference current REF, as shown in the operation characteristic curve on the right side of FIG. (B), I (Q13) <I (Q41) and the output OUT becomes a low voltage.

  Each of the current-type sense amplifiers shown in FIGS. 7A, 7B, and 7C has a configuration that can adjust the offset difference caused by the characteristics of the transistor Tr by the value of the reference current REF. is there.

  FIG. 9 is an example of a voltage type sense amplifier. The voltage-type sense amplifier shown in FIG. 9 includes a first current mirror circuit composed of P-channel MOS transistor pairs Q5 and Q6, N-channel MOS transistor pairs Q7 and Q8 constituting a differential input pair, and a constant current source. The N channel MOS transistor Q9 has a well-known configuration.

  Also in the voltage-type sense amplifier shown in FIG. 9, the offset difference of the sense amplifier can be canceled by adjusting the value of the reference voltage REF.

  When this voltage-type sense amplifier is used, in the above-described IN terminal condition setting mode (see FIG. 2), signals of the same condition input to the IN terminals of the sense amplifiers SA_A and SA_B are voltage signals. Also in the offset difference adjustment mode (see FIG. 3), the voltage input to the REF terminal is adjusted and the reference voltage REF is investigated (measured) in the state where the voltage signal of the same condition is input to the IN terminal. Will do. In the threshold Vth determination mode (see FIG. 4), the drain voltage of the measurement target transistor Tr is input to the IN terminals of the sense amplifiers SA_A and SA_B, and compared with the reference voltage REF input to the REF terminal. For example, the transistor Tr whose threshold voltage Vth (drain voltage) deviates from the distribution within 5σ is determined.

  7C, the first current mirror circuit described above corresponds to P-channel MOS transistors Q11, Q12, and Q13, and the second current mirror circuit includes P Channel MOS transistors Q21, Q22, and Q23 correspond. The first current sink circuit described above corresponds to N channel MOS transistors Q31 and Q32, and the second current sink circuit corresponds to N channel MOS transistors Q41 and Q42. The first mirror current in the first current mirror circuit corresponds to the current flowing from the transistor Q12, and the second mirror current corresponds to the current flowing from the transistor Q13. The first mirror current in the second current mirror circuit corresponds to the current flowing from the transistor Q22, and the second mirror current corresponds to the current flowing from the transistor Q21.

  7C, the current plow-type sense amplifier has three P-channel MOS transistors Q11 that supply the first and second mirror currents using the current flowing through the IN terminal as a reference current. A first current mirror circuit composed of Q12 and Q13 and a pair of N-channel MOS transistors Q31 and Q32, and a first mirror current flowing from the first current mirror circuit (Q12) is used as a reference current. The first current sink circuit (Q31, Q32) driven as the three currents and three P-channel MOS transistors Q21, Q22 that supply the first and second mirror currents using the current flowing through the REF terminal as a reference current. , Q23, and a pair of N-channel MOS transistors Q41, Q42. And a second current sink circuit driven by using a first mirror current flowing from the second current mirror circuit (Q22) as a reference current, and a second mirror current flowing from the first current mirror circuit (Q13) As the mirror current (Q41 current) of the second current sink circuit, and the second mirror current flowing from the second current mirror circuit (Q21) is used as the mirror current (Q32 of the first current sink circuit). Current).

[Explanation of setting example of IN terminal condition of sense amplifier]
FIG. 10 is a diagram illustrating a first setting example of the input current condition of the IN terminal of the sense amplifier. This example is an example in which an IN condition is set in the sense amplifier by using any one transistor Tr from the transistor Tr group to be measured in the evaluation cell array 11 as in the example described in FIG.

In the first setting example, as shown in FIG. 10, any one transistor Tr is used from the transistor Tr group in the evaluation cell arrays 11 and 12. When the sense amplifiers SA_A and SA_B are current sense amplifiers, the gate and drain voltages of the transistor Tr are adjusted to generate a constant current. That is, the gate voltage of the transistor Tr is adjusted so that the current flowing through the IN terminal is constant for each sense amplifier SA.
As described above, a constant current is applied to the IN terminal of the sense amplifier to determine a voltage to be applied to the signal DBC (Drain Bias Control). As a result, the variation in current applied from the IN terminal generated between the plurality of sense amplifiers can be corrected, and the same input current condition can be defined for the plurality of sense amplifiers.

  FIG. 11 is a diagram illustrating a second setting example of the input current condition of the IN terminal of the sense amplifier. This second setting example is an example in which a current input to the IN terminal is given from the outside.

  As shown in FIG. 11, the N-channel MOS transistor Q101 is turned on for the sense amplifier SA_A, the current flowing through the IN terminal is input from the external terminal EXIN, and the current at the IN terminal for the sense amplifier SA_A is adjusted.

  Similarly, for the sense amplifier SA_B, the N-channel MOS transistor Q102 is turned on, the current flowing through the IN terminal is input from the external terminal EXIN, and the current at the IN terminal with respect to the sense amplifier SA_B is adjusted.

  As a result, the current conditions flowing through the IN terminals in the sense amplifiers SA_A and SA_B are made the same. In the case where the offset cancellation is performed simultaneously by a plurality of sense amplifiers SA_A and SA_B, the EXIN terminal may be divided into a plurality.

  FIG. 12 is a diagram illustrating a third setting example of the input current condition of the IN terminal of the sense amplifier. This third setting example is an example in which a dedicated current generating transistor is used in each sense amplifier SA_A, SA_B.

  In the example shown in FIG. 12, current generating transistors Q111 and Q112 and select transistors Q113 and Q114 arranged exclusively for the sense amplifiers SA_A and SA_B are used. Since each of the current generating transistors Q111 and Q112 has a smaller WL characteristics by increasing the WL size, the conditions of the IN terminal can be set using the same gate voltage. In addition, a plurality of sense amplifiers SA_A and SA_B can be set at a time.

  FIG. 13 is a diagram illustrating a fourth setting example of the input current condition of the IN terminal of the sense amplifier. The fourth setting example is an example in which a common current generating transistor Q121 is used in each sense amplifier. In the example shown in FIG. 13, the current generating transistor Q121 common to the sense amplifiers SA_A and SA_B and the select transistors Q122 and Q123 for flowing current to the IN terminals of the sense amplifiers SA_A and SA_B are used.

In this configuration, since the current generating transistor Q121 is the same in each of the sense amplifiers SA_A and SA_B, there is an advantage that the IN terminal conditions can be easily made the same.
Using any one of the first setting example to the fourth setting example described above, the variation in the current applied from the IN terminal between the plurality of sense amplifiers is corrected, and the same is applied to the plurality of sense amplifiers. Define input current conditions.

[Configuration of Semiconductor Integrated Circuit Evaluation Apparatus of the Present Invention]
FIG. 14 is a diagram showing a configuration of a semiconductor integrated circuit evaluation apparatus according to the present invention. For example, FIG. 14 is a diagram showing a processing unit included in a semiconductor integrated circuit evaluation apparatus that evaluates a 1-Gbit DMA-TEG.

  In the semiconductor integrated circuit evaluation apparatus 20 of the present invention shown in FIG. 14, the measurement mode switching unit 21 includes an IN terminal condition setting mode, an offset difference adjustment mode, a Vth determination mode (high-speed sense mode), and a Vth measurement mode (transistor characteristics). Switch the operation mode to (measurement mode).

  In the IN terminal condition setting mode, the IN terminal condition setting unit 22 performs processing for setting the input current conditions of the IN terminals of the plurality of sense amplifiers SA_A and SA_B to the same state. For example, the gate voltage of the transistor Tr in the evaluation cell arrays 11 and 12 is adjusted so that the current flowing through the IN terminals of the sense amplifiers SA_A and SA_B becomes 100 nA.

  In the offset difference adjustment mode, the offset difference adjustment unit 23 measures the condition of the input current at the REF terminal when the input current condition at the IN terminal is the same in order to cancel the offset difference between the plurality of sense amplifiers SA_A and SA_B. Perform the process.

  In the threshold Vth determination mode (high-speed sense mode), the defective transistor identification unit 24 identifies a transistor having a threshold Vth outside the 5σ distribution range based on the “H” / “L” determination signal output from the sense amplifier. Process. The defective transistor identification unit 24 stores the address of the measurement target transistor identified as defective in the bitmap storage memory 24A.

  The transistor characteristic measurement unit 25 selects these defective transistors for the defective transistors (those whose addresses are stored in the bit map storage memory 24A) determined by the defective transistor identification unit 24 to have a threshold value Vth exceeding 5σ. A process for measuring transistor characteristics such as a threshold value Vth and a Vg-Id characteristic is performed.

  The address selection unit 26 performs random or serial address selection of transistors in the evaluation cell array 11 in the semiconductor integrated circuit 1 through a column decoder (CDEC) 28 and a row decoder (RDEC) 29. In the address selection unit 26, in the threshold Vth determination mode (high-speed sense mode), a transistor is selected by updating the address continuously in the serial mode. In the Vth measurement mode (transistor characteristic measurement mode), the address of a defective transistor (transistor with a threshold Vth exceeding 5σ) is selected in the random mode.

  The reference signal output unit 27 inputs a predetermined reference current REF from the outside to the sense amplifiers SA_A and SA_B in the semiconductor integrated circuit (DMA-TEG) 1. In the offset difference adjustment mode and the threshold Vth determination mode, the sense amplifiers SA_A and SA_B compare the reference current REF with the output current (current IN) of the measurement target transistor. The reference signal output unit 27 outputs a reference current REF when the sense amplifiers SA_A and SA_B are current type sense amplifiers shown in FIG. 7, and the reference voltage REF when the sense amplifiers SA_A and SA_B are voltage type sense amplifiers shown in FIG. Is output.

  The semiconductor integrated circuit evaluation apparatus 20 shown in FIG. 14 has a computer system inside. A series of processes related to the above-described process is stored in a computer-readable recording medium in the form of a program, and the above-described process is performed by the computer reading and executing this program.

  That is, each process in the semiconductor integrated circuit evaluation device 20 is realized by a central processing unit such as a CPU reading the above program into a main storage device such as a RAM and executing information processing and arithmetic processing. Is.

  Here, the computer-readable recording medium means a magnetic disk, a magneto-optical disk, a CD-ROM, a DVD-ROM, a semiconductor memory, or the like. Alternatively, the computer program may be distributed to the computer via a communication line, and the computer that has received the distribution may execute the program.

  Further, it is assumed that an input device, a display device, etc. (none of them are displayed) are connected to the semiconductor integrated circuit evaluation device 20 as peripheral devices. Here, the input device refers to an input device such as a keyboard and a mouse. The display device refers to a CRT (Cathode Ray Tube), a liquid crystal display device, or the like.

  Further, when there is a commercially available semiconductor tester that can realize the function of the semiconductor integrated circuit evaluation apparatus 20 of the present invention, this commercially available semiconductor tester may be used.

  In the semiconductor integrated circuit evaluation apparatus 20 shown in FIG. 14, the measurement mode switching unit described above corresponds to the measurement mode switching unit 21, and the input terminal condition setting unit corresponds to the IN terminal condition setting unit 22. The offset difference adjustment unit corresponds to the offset difference adjustment unit 23, the above-described defective transistor identification unit corresponds to the defective transistor identification unit 24, and the above-described transistor characteristic measurement unit corresponds to the transistor characteristic measurement unit 25. The reference signal described above corresponds to the reference current REF, the first input terminal described above corresponds to the IN terminal, and the second input terminal corresponds to the REF terminal.

  With the above-described configuration, when the threshold value Vth of the transistor group in the evaluation cell arrays 11 and 12 is determined using the plurality of sense amplifiers SA_A and SA_B, the offset difference between the sense amplifiers SA_A and SA_B is canceled. The threshold value Vth can be determined with high accuracy. For this reason, even in a large-scale semiconductor integrated circuit such as a DMA-TEG, the characteristics of an abnormal transistor outside a predetermined distribution range can be evaluated with high accuracy and at high speed (in a short time).

  Although the embodiments of the present invention have been described above, the semiconductor integrated circuit and the semiconductor integrated circuit evaluation apparatus of the present invention are not limited to the above-described illustrated examples, and do not depart from the gist of the present invention. Of course, various changes can be made.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit 11, 12 ... Evaluation cell array, 20 ... Semiconductor integrated circuit evaluation apparatus, 21 ... Measurement mode switching part, 22 ... IN terminal condition setting part, 23 ... Offset difference adjustment part, 24 ... Defect transistor identification part, 24A ... Bitmap storage memory, 25 ... Transistor characteristic measurement unit, 26 ... Address selection unit, 27 ... Reference signal output unit

Claims (12)

An evaluation cell array in which MOS transistors to be measured are arranged in a matrix and a plurality of sense amplifiers, and the evaluation cell array corresponds to each of the plurality of sense amplifiers, and a plurality of transistor groups And the output signal of the selected transistor to be measured in the evaluation cell array is input to the first input terminal of each of the plurality of sense amplifiers, and the second input of each of the plurality of sense amplifiers In a semiconductor integrated circuit configured to receive a reference signal for comparison with an output signal of the measurement target transistor at a terminal, a predetermined voltage is applied to the drain when a predetermined voltage is applied to the drain of the measurement target transistor. the evaluation Seruare by judging the threshold value Vth is a gate voltage when the current flows A semiconductor integrated circuit evaluation method for measuring the detection and characterization of defects transistor in,
A first measurement step in which an IN terminal condition setting unit applies an input signal of the same condition to a first input terminal of each of the plurality of sense amplifiers;
The offset difference adjustment unit inputs a variable signal to the second input terminal of each of the plurality of sense amplifiers in a state where the input signal of the same condition is applied to the first input terminal of each of the plurality of sense amplifiers. A second measurement step of measuring, for each of the plurality of sense amplifiers, a different reference signal according to an offset difference between the plurality of sense amplifiers by detecting a change in output of each of the plurality of sense amplifiers; ,
In a state where a predetermined gate voltage is applied to the measurement target transistor in the evaluation cell array, the defective transistor identification unit is different from the output signal of the measurement target transistor to each of the plurality of sense amplifiers. A third measurement step of inputting a reference signal and determining a defective transistor having a threshold value Vth outside a predetermined range based on outputs of the plurality of sense amplifiers;
A transistor characteristic measuring unit for measuring a transistor characteristic for the transistor determined as the defective transistor in the third measuring step;
A method for evaluating a semiconductor integrated circuit, comprising: The semiconductor integrated circuit evaluation method according to claim 1, wherein the plurality of sense amplifiers are current-type sense amplifiers. The semiconductor integrated circuit evaluation method according to claim 1, wherein the sense amplifier is a voltage-type sense amplifier. In the third measurement step, the measurement target transistor in which the threshold Vth of the measurement target transistor deviates from a distribution within 5σ (σ is a standard deviation) with respect to the normal distribution curve of the threshold Vth is determined as the defective transistor. And
In the fourth measurement step, transistor characteristics are measured for the defective transistor whose threshold Vth is out of the distribution within 5σ.
The semiconductor integrated circuit evaluation method according to claim 1, wherein: A semiconductor integrated circuit having an evaluation cell array in which transistors to be measured are arranged in a matrix, and whose characteristics are evaluated by selecting the transistor to be measured in the evaluation cell array based on signals output from a column decoder and a row decoder Because
A plurality of sense amplifiers, and the evaluation cell array is divided into a plurality of transistor groups corresponding to each of the plurality of sense amplifiers;
An output signal of a selected transistor in the evaluation cell array is input to first input terminals of the plurality of sense amplifiers,
A different reference signal is input to each of the second input terminals of each of the plurality of sense amplifiers according to an offset difference between the plurality of sense amplifiers. The plurality of sense amplifiers are configured by current-type sense amplifiers,
By adjusting the reference current of the reference signal input to the second input terminal of each of the plurality of sense amplifiers, the same input to the first input terminal regardless of the offset difference between the plurality of sense amplifiers. The semiconductor integrated circuit according to claim 5, wherein outputs of the plurality of sense amplifiers coincide with each other. The current-type sense amplifier has a current mirror circuit composed of a pair of P-channel MOS transistors, and is configured to flow the reference current flowing through the second input terminal to the reference current side of the current mirror circuit. The semiconductor integrated circuit according to claim 6, wherein the semiconductor integrated circuit is a simple current mirror type sense amplifier. In the current type sense amplifier, two current mirror circuits each composed of a pair of P-channel MOS transistors are connected in cascade, and the reference current flowing in the second input terminal is used as a reference current of the current mirror circuit. The semiconductor integrated circuit according to claim 6, wherein the semiconductor integrated circuit is a cascade simple current mirror type sense amplifier configured to flow to the side. The current type sense amplifier is:
A first current mirror circuit composed of three P-channel MOS transistors that supply a first and a second mirror current with a current flowing through the first input terminal as a reference current;
A first current sink circuit configured by a pair of N-channel MOS transistors and driven by using a first mirror current flowing from the first current mirror circuit as a reference current;
A second current mirror circuit composed of three P-channel MOS transistors that supply the first and second mirror currents using the reference current flowing through the second input terminal as a reference current;
A second current sink circuit configured by a pair of N-channel MOS transistors and driven by using a first mirror current flowing from the second current mirror circuit as a reference current;
With
The second mirror current flowing from the first current mirror circuit is caused to flow as the mirror current of the second current sink circuit, and the second mirror current flowing from the second current mirror circuit is changed to the first current mirror circuit. The semiconductor integrated circuit according to claim 6, wherein the current is passed as a mirror current of the current sink circuit. The plurality of sense amplifiers are configured by voltage-type sense amplifiers,
By adjusting the reference voltage of the reference signal input to the second input terminal of each of the plurality of sense amplifiers, the same input to the first input terminal regardless of the offset difference between the plurality of sense amplifiers. The semiconductor integrated circuit according to claim 5, wherein outputs of the plurality of sense amplifiers coincide with each other. The voltage type sense amplifier is:
A differential comprising a pair of N-channel MOS transistors constituting a differential input pair and a current mirror circuit comprising a pair of P-channel MOS transistors connected as a load to the pair of N-channel MOS transistors Amplifying circuit,
The semiconductor integrated circuit according to claim 10. A semiconductor integrated circuit evaluation apparatus for evaluating a semiconductor integrated circuit according to any one of claims 6 to 11,
An input terminal condition setting mode for setting signals applied to first input terminals of the plurality of sense amplifiers to have the same condition; an offset difference adjustment mode for adjusting an offset difference between the plurality of sense amplifiers; A threshold Vth determination mode for determining a threshold Vth which is a gate voltage when a predetermined current flows through the drain when a predetermined voltage is applied to the drain of the transistor under measurement using the plurality of sense amplifiers; A measurement mode switching unit for switching between a threshold Vth measurement mode for measuring the transistor characteristics of the measurement target transistor determined to be defective in the Vth determination mode;
In the input terminal condition setting mode, an input terminal condition setting unit that inputs a signal of the same condition to each of the first input terminals of the plurality of sense amplifiers;
In the offset difference adjustment mode, a second input terminal of each of the plurality of sense amplifiers in a state where a signal of the same condition is input to a first input terminal of each of the plurality of sense amplifiers by the input terminal condition setting unit. An offset difference adjustment unit that measures a reference signal corresponding to the offset difference between the plurality of sense amplifiers for each of the plurality of sense amplifiers by inputting a variable signal to the output signal and detecting a change in the output of the sense amplifier. When,
In the threshold Vth determination mode, the measurement target transistors in the evaluation cell array are sequentially selected, a predetermined gate voltage is applied to the selected measurement target transistors, and defective based on output signals from the plurality of sense amplifiers. A defective transistor identifying unit for identifying a transistor and storing an address of the identified defective transistor in a storage unit;
In the threshold Vth measurement mode, a transistor that measures a transistor characteristic by selecting a measurement target transistor determined to be defective by the defective transistor identification unit and applying a desired gate voltage to the gate of the selected measurement target transistor A characteristic measurement unit;
A semiconductor integrated circuit evaluation apparatus comprising:

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