US20120179412A1 - Circuits and Methods for Characterizing Random Variations in Device Characteristics in Semiconductor Integrated Circuits - Google Patents

Circuits and Methods for Characterizing Random Variations in Device Characteristics in Semiconductor Integrated Circuits Download PDF

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US20120179412A1
US20120179412A1 US13/423,624 US201213423624A US2012179412A1 US 20120179412 A1 US20120179412 A1 US 20120179412A1 US 201213423624 A US201213423624 A US 201213423624A US 2012179412 A1 US2012179412 A1 US 2012179412A1
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transistors
pull
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device
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Azeez Bhavnagarwala
David J. Frank
Stephen V. Kosonocky
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GlobalFoundries Inc
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    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • G11C29/50004Marginal testing, e.g. race, voltage or current testing of threshold voltage
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30Marginal testing, e.g. by varying supply voltage
    • G01R31/3016Delay or race condition test, e.g. race hazard test
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31725Timing aspects, e.g. clock distribution, skew, propagation delay
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31727Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3173Marginal testing
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuit
    • G01R31/3193Tester hardware, i.e. output processing circuit with comparison between actual response and known fault free response
    • G01R31/31937Timing aspects, e.g. measuring propagation delay
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • G01R31/2601Apparatus or methods therefor
    • G01R31/2603Apparatus or methods therefor for curve tracing of semiconductor characteristics, e.g. on oscilloscope
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5002Characteristic

Abstract

Circuits for measuring and characterizing random variations in device characteristics of integrated circuit devices.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a Divisional Application of U.S. application Ser. No. 10/643,193, filed on Aug. 18, 2003, the disclosure of which is herein incorporated by reference in its entirety.
  • TECHNICAL FIELD
  • The present invention relates generally to circuits and methods for measuring and characterizing random variations in device characteristics in semiconductor devices. The present invention further relates to circuits and methods for measuring and characterizing device mismatch of semiconductor transistors due to local variations in device characteristics resulting from random sources, and in particular, Vt (threshold voltage) variations between neighboring MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) of SRAM (Static Random Access Memory) cells or other logic devices.
  • BACKGROUND
  • In the design of semiconductor integrated circuits, it is very important to consider variations in device characteristics (device mismatch) such as Vt (threshold voltage) for a given circuit design, in order to achieve circuit robustness and obtain high manufacturing functional yields for such devices.
  • In general, variations in device characteristics include “systematic” variations and “random” variations. Systematic variations (or process variations) are variations in a manufacturing process that equally affect some or all N-doped or P-doped elements of a local circuit depending on, e.g., the orientation, geometry and/or location of a device. For example, when manufacturing a semiconductor chip, systematic variations in device characteristics can result from variations in mask dimensions (which causes geometry variations), variations in material properties of wafers, resists, etc., variations in the manufacturing equipment and environment (e.g., lens aberrations, flow turbulence, oven temperature, etc.) and variations in process settings (implant dose, diffusion time, focus, exposure energy, etc.). Systematic variations typically have significant spatial correlations, i.e., circuits/devices that are near each other can be expected to have the same/similar amount of variations due to systematic sources of variation.
  • Given the high spatial correlation for systematic variations in device characteristics between local devices, body biasing methods for compensating/mitigating the sensitivity of circuit performance due to such systematic variations are well known and can be readily applied.
  • In contrast, random variations in device characteristics between devices of a circuit, wafer, chip or lot, are uncorrelated. Random sources of variations, which cause device mismatch between neighboring devices in a circuit, can adversely affect circuit behavior even more drastically that systematic variations in circuits such as SRAM cells and sense amplifiers. Indeed, since systematic sources of variation equally affect neighboring devices, device mismatch between neighboring devices as a result of systematic sources is negligible as compared to device mismatch due to random sources of device characteristic variation. Thus, random variations in device characteristics (device mismatch) cause significantly more deviation especially in circuit performance of the above mentioned circuits, than systematic variations. Since random variations in device characteristics are uncorrelated, methods for characterizing or modeling such random variations are difficult and inaccurate. Providing the necessary “fixes” at the device and circuit levels so as to limit the adverse effects of such random variations on circuit performance, are expansive by way of silicon area consumed as compared to those for systematic variations.
  • Although device mismatch may be caused by any number of variations in device characteristics, random variations in Vt (threshold voltage) mismatch have significant impact on circuit performance for various types of MOS circuits. In MOSFET devices, for example, random variations in Vt between neighboring transistors are due primarily to fluctuations in number and position of dopant atoms, but other sources include, for example, randomness in line edge roughness of devices. Variations in Vt mismatch of MOSFETs of an SRAM cell can significantly degrade cell stability as is understood by those of ordinary skill in the art. Furthermore, Vt mismatches of transistors of a sense amplifier can adversely impact the offset voltage. In particular, because a sense amplifier senses a differential voltage applied at the gates of two neighboring sensing devices (transistors), if there is a Vt mismatch between such devices, the mismatch adds to the voltage that the sense amplifier must counter before it can amplify the desired signal. By way of further example, Vt mismatches can affect the performance of CMOS inverters, e.g., a Vt mismatch can cause variations in the trip voltage, that is, the point at which the output of the inverter switches between logic states “1” and “0”.
  • As semiconductor integrated circuits become more highly integrated with sub-micron features sizes of MOS devices, and as power supply voltages are reduced (for low power applications), the adverse effects of circuit performance due to random variations in device mismatch are enhanced because such variations do not scale down with feature size and/or supply voltage.
  • Accordingly, in order to provide robust circuit designs and enhance functional yield for a given process, circuit designers will try to accurately assess/characterize the random contributions of device mismatch, such as Vt mismatch, for example, that results from a given fabrication process so as to determine the effects of such random variations on circuit performance.
  • Various simulations and experimental methods have been proposed and developed for characterizing variations in device characteristics to determine the effect of device mismatch in integrated circuit design. In general, such methods are based on statistical analysis or statistical modeling of device mismatches and performance differences that result from device mismatch. Statistical design methods enable a circuit designer to determine the quantitative effect of device mismatch.
  • For instance, CAD (computer-aided design) tools and applications have been developed for statistical circuit design and performing statistical simulations using Monte
  • Carlo analysis. Monte Carlo simulation requires construction of a statistical model of device mismatch, for example, which model is used for simulating device mismatch. In general, with Monte Carlo analysis, parameter distributions (e.g., Normal/Gaussian) are assigned to desired model parameters and then Monte Carlo simulations are performed using such parameter distributions.
  • There are various disadvantages associated with methods such as Monte Carlo simulations. For instance, the characterization accuracy of such methods are limited based on the accuracy of the model that is employed. Moreover, such simulations typically do not capture all the sources of Vt mismatch. Moreover, Monte Carlo simulations are expensive in terms of time and effort to develop.
  • Experimental techniques for characterizing device mismatch include performing statistical analysis on actual test data that is measured from test structures. For example, FIG. 1 is a diagram that illustrates a conventional test circuit and method for characterizing device mismatch. The test circuit of FIG. 1 comprises an array of NFETs or PFETs, wherein all the source terminals of the transistors in the array are commonly connected to terminal “S”. The gate terminals of the transistors in a given column of the array (10) are commonly connected to a Gi (e.g., i=1, . . . , 256) terminal, and the drain terminals of the transistors in a given row of the array (10) are commonly connected to a Di (e.g., i=1, . . . , 32) terminal. A counter and decoder circuit (11) is responsive to a clock CLK signal for generating output signals to sequentially activate one of the Gi terminals.
  • With the circuit of FIG. 1, test data is collected by selectively activating the transistors, one at a time, in a given sequence, to measure the drain current ID vs. gate voltage VG (I-V) characteristics for each transistor in the array (10). For example, transistor T1 in the array (10) is activated by applying Vdd to terminals G1 and D1, and then the current flowing in terminal S would be measured to obtain the I-V characteristics of T1. Then, sequential activation of the terminals Gi and Di would continue until each device in the array is measured. For instance, D1 would be maintained at Vdd while each Gi terminal would be sequentially activated under control of the counter (11) to obtain the I-V characteristics in the first row of the array (10), and this process would be repeated by sequentially activating G1-Gi for each activated row Di.
  • After the I-V measurements are collected for all the transistors in the array (10) and stored in a database, the data can be retrieved and processed to extract various parameters such a Vt, transconductance, drain currents, etc. and generate distributions for such parameters. In addition, the Vt of neighboring devices in the array could be compared to generate a distribution of the Vt mismatch between neighboring devices. Assuming that the transistors in the array are the same (e.g., the same channel lengths and widths), the measured distributions can be used to characterize device mismatch between the same or similar transistors to be included in a desired circuit design.
  • Although techniques which characterize device mismatch based on actual test data measured using test structures (such as in FIG. 1) can effectively determine parameter mismatch variance to some degree, uncertainty can be included in the test data as a result of variations from sources from other than the MOSFET being characterized, which result from the testing procedure and/or testing circuit architecture, can reduce the accuracy of device mismatch analysis. For example, in the test circuit of FIG. 1, test data that is measured for a given transistor includes uncertainty resulting from gate leakage and subthreshold leakage from unselected devices in the activated row and column.
  • More specifically, by way of example, when terminals G1 and D1 are activated (at Vdd) to collect data for transistor T1, the unselected transistors (T2 . . . T3) in the row D1 drive subthreshold leakage currents (current that flows from the drain to source terminal when gate voltage is below the threshold voltage), which contribute to variations in the drain current Id of transistor T1 that is being measured in terminal S. Furthermore, the unselected transistors (e.g., T4, T5) in column G1 drive gate leakage current (leakage through gate oxide from gate terminal to source terminal), which further adds to the uncertainties of the test data being measured for T1.
  • With the test structure of FIG. 1, other sources of variation that can add to the uncertainty include systematic (process) variations that exist when the array is too large. For instance, when the array is too large, variations in channel length of transistors in the array (10) may occur due to process variations, which contribute to parameter variations (e.g., Vt) in devices across the array (10).
  • Moreover, when the array is too large, the increase in temperature of the devices in the array during testing of transistors can add to the uncertainty of measured Vt, which is exponentially dependent on temperature.
  • Accordingly, when attempting to characterize device mismatch due to random sources, the sources of uncertainty, which result from the testing circuit and/or methodology, can contribute to the variance of the test data. As such, device mismatch due to random Vt fluctuations cannot be accurately characterized and is overestimated. This is not desirable since, as noted above, accurate characterization of random variation of device mismatch (e.g., Vt mismatch) between neighboring devices is important for circuit analysis due to the significantly adverse effects such random mismatches can have on circuit performance, functionality and yield.
  • Thus, it is highly desirable to develop circuits and methods that allow random Vt variations in device characteristics to be accurately and efficiently characterized for purposes of integrated circuit design.
  • BRIEF SUMMARY
  • The present invention is directed to circuits and methods for measuring and characterizing random variations in device characteristics of semiconductor integrated circuit devices. More specifically, circuits and methods according to embodiments of the invention enable circuit designers to accurately measure and characterize random variations in device characteristics (such as transistor threshold voltage (Vt)) resulting from random placement of dopant atoms or line edge roughness, for purposes of integrated circuit design. Methods and circuits according to embodiments of the invention are preferably implemented for determining variations in Vt mismatch between neighboring MOSFETs of a given circuit being analyzed/designed, such as SRAM cells or other logic devices, and using the determined variations in Vt mismatch to characterize random variations of the given circuit. Preferably, circuits and methods according to the present invention for characterizing device mismatch between transistors preferably measure subthreshold DC voltage characteristics (VC) of pairs of devices (i.e., gate voltage is below Vt), which eliminates uncertainty that arises from gate leakage through unselected devices.
  • In one embodiment of the invention, method for characterizing random variations in device mismatch (e.g., Vt mismatch) between neighboring devices comprises the steps of obtaining subthreshold DC voltage characteristic data (Vout vs. Vin) for a plurality of device pairs of the neighboring devices, analyzing such data to determine a distribution of Vin for a given Vout, and obtaining a distribution for Vt mismatch based on the distribution of Vin. A distribution in Vt mismatch for a pair of transistors, for example, can be directly measured using subthreshold DC voltage characteristic data that is obtained from multiple pairs of such neighboring devices.
  • In another embodiment of the invention, a method for characterizing device mismatch in a semiconductor integrated circuit comprises: obtaining DC voltage characteristic data for one or more selected device pairs of an integrated circuit, wherein the device pairs comprise pairs of neighboring transistors in the integrated circuit; determining a distribution of Vt (threshold voltage) mismatch for a selected device pair using corresponding DC voltage characteristic data for the device pair; determining a Vt variation of transistors in the integrated circuit using one or more determined distributions of Vt mismatch for selected device pairs; and characterizing random variations of the integrated circuit using one or more determined Vt variations of transistors of the integrated circuit. Preferably, the step of obtaining DC voltage characteristic data for a selected device pair of an integrated circuit comprises obtaining subthreshold DC voltage characteristic data while biasing the transistors of the device pair in a subthreshold region.
  • These and other exemplary embodiments, aspects, features, and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments, which is to be read in connection with the accompanying drawings.
  • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • FIG. 1 is a diagram that illustrates a conventional test circuit that is used for measuring device parameters for characterizing device mismatch.
  • FIG. 2 is an exemplary circuit diagram that can be used for characterizing random device mismatches between a pair of transistors, according to an embodiment of the invention.
  • FIG. 3 is an exemplary circuit diagram that can be used for characterizing random device mismatches between a pair of transistors, according to another embodiment of the invention.
  • FIG. 4 is an exemplary circuit diagram that can be used for characterizing random device mismatches between a pair of transistors, according to another embodiment of the invention.
  • FIG. 5 a is an exemplary model according to an embodiment of the invention for characterizing device mismatch using the circuit of FIG. 2.
  • FIG. 5 b is an exemplary graphical diagram illustrating subthreshold DC voltage characteristics that were measured for a plurality of circuits as depicted in FIG. 2.
  • FIG. 6 is an exemplary model according to an embodiment of the invention for characterizing device mismatch using the circuit of FIG. 3.
  • FIG. 7 a is an exemplary model according to an embodiment of the invention for characterizing device mismatch using the circuit of FIG. 4.
  • FIG. 7 b is an exemplary graphical diagram illustrating subthreshold DC voltage characteristics that were measured for a plurality of circuits as depicted in FIG. 4.
  • FIG. 8 is an exemplary graphical diagram illustrating correlations of measurements of neighboring pairs of transistors in a SRAM cell to verify that measured variations in device parameters, which are characterized using circuits and methods of the invention, are the result of random sources.
  • FIG. 9 is an exemplary graphical diagram comparing the distribution densities of Vt mismatch that are obtained using conventional models of dopant fluctuations, with a distribution density of Vt mismatch as measured using circuits and methods according to the invention for characterizing Vt mismatch.
  • FIG. 10 is a flow diagram of a method for characterizing random variation in Vt of a semiconductor integrated circuit, according to an embodiment of the invention.
  • FIG. 11 is an exemplary circuit diagram of a circuit that can be used for characterizing device mismatch of transistors pairs of an SRAM cell, according to an embodiment of the invention.
  • FIG. 12 is an exemplary circuit diagram of a circuit that can be used for characterizing device mismatch of transistors pairs of an SRAM cell, according to another embodiment of the invention.
  • FIG. 13 is an exemplary circuit diagram of a circuit that can be used for characterizing device mismatch of transistors pairs of an SRAM cell, according to another embodiment of the invention.
  • FIG. 14 is an exemplary circuit diagram of a circuit that can be used for characterizing device mismatch of transistors pairs of an SRAM cell, according to another embodiment of the invention.
  • FIG. 15 is a diagram of a testing apparatus according to an embodiment of the invention for measuring device parameters for characterizing device mismatch.
  • DETAILED DESCRIPTION
  • In general, circuits and methods according to embodiments of the invention are used for measuring and characterizing random variations in device characteristics of semiconductor integrated circuit devices. More specifically, circuits and methods according to embodiments of the invention enable circuit designers to accurately measure and characterized random variations in device characteristics (such as transistor threshold voltage (Vt)) resulting from random sources, for purposes of integrated circuit design. Methods and circuits according to embodiments of the invention are preferably implemented for determining variations in Vt mismatch between neighboring MOSFETs of a given circuit being analyzed/designed, such as SRAM cells or other logic devices, and using the determined variations in Vt mismatch to characterize random Vt variation of the given circuit.
  • In general, circuits and methods according to the present invention for characterizing device mismatch preferably measure subthreshold DC voltage characteristics (VC) of pairs of devices, which is to be contrasted with the conventional method discussed above with reference to FIG. 1 which measures drain current ID vs. gate voltage VG of individual devices. Preferably, the DC voltage characteristic are measured in the sub threshold region (i.e., gate voltage is below Vt), which eliminates uncertainty that arises from unselected devices and gate leakage.
  • In accordance with an embodiment of the present invention, a method for characterizing random variations in device mismatch (e.g., Vt mismatch) between neighboring devices is performed by obtaining subthreshold DC voltage characteristic data (Vout vs. Vin) for a plurality of device pairs of the neighboring devices, analyzing such data to determine a distribution of Vin for a given Vout, and obtaining a distribution for Vt mismatch based on the distribution of Vin. In other words, a distribution in Vt mismatch for a pair of transistors, for example, can be directly measured using DC voltage characteristic data that is obtained from multiple pairs of such neighboring devices.
  • By way of example, FIGS. 2, 3 and 4 are exemplary circuit diagrams depicting circuits that can be used for characterizing random device mismatches (e.g., Vt mismatch) between MOSFETs. More specifically, FIG. 2 is an exemplary diagram illustrating a circuit comprising a pair of NMOS FETs, which can be used for measuring random Vt mismatches between NFETs. The circuit comprises a first NFET (20) having a channel width W1 and length L1, and a second NFET (21) having a channel width W2 and length L2. Further, FIG. 3 is an exemplary diagram illustrating a circuit comprising a pair of PMOS FETs, which can be used for measuring random Vt mismatches between PFETs. The circuit comprises a first PFET (22) having a channel width W1 and length L1, and a second PFET (23) having a channel width W2 and length L2. In addition, FIG. 4 is an exemplary diagram illustrating a circuit comprising a pair of MOSFETs, which can be used for measuring random Vt mismatches between an NFET and a PFET. The circuit comprises a PFET (24) having a channel width W1 and length L1, and an NFET (25) having a channel width W2 and length L2.
  • In general, in each of the exemplary circuits, DC voltage characteristics are measured by sweeping an input voltage, VIN, and measuring the output voltage, Vout. More specifically, in the circuit of FIG. 2, the input voltage VIN, which is applied to the gate terminal of NFET (21), and a constant voltage VB1 , which is applied to the gate terminal of NFET (20) are preferably selected to maintain the NFETS (20) and (21) in the subthreshold region for VDD>Vt. In addition, in the circuit of FIG. 3, the input voltage, VIN, which is applied to the gate terminal of PFET (23), and a constant voltage, VB2, which is applied to the gate terminal of PFET (22), are preferably selected to maintain the PFETS (22) and (23) in the subthreshold region for VDD>Vt. Further, in the circuit of FIG. 4, the input voltage, VIN, which is applied to the gate terminals of both the PFET (24) and the NFET (25) is preferably selected to maintain the FETs (24) and (25) in the subthreshold region for VDD>Vt.
  • In one exemplary embodiment, the DC voltage characteristic data is measured in circuits of FIGS. 2-4 at VDD=to 250 mV or 1V, and maintaining VB1 and VB2 at about less than 250 mv while varying VIN from 0v to about less than 250 mV. Advantageously, in the circuits of FIGS. 2-4, since the input voltages are kept low to maintain the MOSFETs in the subthreshold region, accurate characterization of Vt mismatch is achieved at full VDD, where the Vt spreads (standard deviations) would be larger. In addition, there is no contribution from gate leakage current and, as explained below, there is no contribution of unselected devices during testing. It is be appreciated that the physical orientation of the MOSFETs in FIGS. 2, 3 and 4 can be in the same direction or orthogonal.
  • As noted above, characterizing device mismatch (e.g., Vt mismatch) between neighboring transistors of a given circuit can be performed using one of the circuits of FIGS. 2-4 depending on the transistor types. For example, to characterize the variation in Vt mismatch between two neighboring NFETs of a given circuit design, subthreshold DC voltage characteristic data (Vout vs. Vin) would be measured for each of a plurality of the same/similar circuits comprising device pairs as shown in FIG. 2. The DC data would then be analyzed to determine a distribution of Vin for a given Vout, and a distribution for Vt mismatch would be determined using the measured distribution of Vin.
  • For example, FIG. 5 b is an exemplary graphical diagram illustrating subthreshold DC voltage characteristics (Vout vs. Vin) that were measured for a plurality of circuits as depicted in FIG. 2. Using the data shown in FIG. 5 b, a distribution of Vin was determined for a given Vout (as indicated by the dotted line). Preferably, Vout is selected to be less than 0.5 VDD. More specifically, in the exemplary diagram of FIG. 5 b, Vout is preferably selected for a region (to the right of line A) where the transfer characteristics (Vout vs. Vout) are essentially linear across Vin (see dotted line). In the region of the data to the left of line A, the DC curves (Vout vs. Vin) are not linear when Vout is selected to be higher than the Vout of the dotted line, and the nonlinear portion of the DC curves reflect contributions from other transistors in the circuit.
  • Then, for the selected Vout, the distribution of Vt mismatch is determined using the measured distribution of Vin. More specifically, in accordance with FIG. 5 a of the present invention, it has been demonstrated that the distribution of Vin corresponds to the distribution of the Vt mismatch between NFET devices. FIG. 5 a depicts an analytical model for the data plotted in FIG. 5 b. As shown in FIG. 5 a, the distribution of Vin corresponds to the Vt mismatch between NFET devices (i.e., VtN2-VtN1) of FIG. 2. In FIG. 5 a, μ denotes the subthreshold slope factor (how quickly a device turns off as the gate voltage decreases), β denotes the reciprocal of terminal voltage (which is 26 mv at room temperature), μ on denotes the low field carrier mobility, k is a coefficient (in mA/V2) that denotes the ratio of Id/(Vgs-Vt)2, W/L is the ratio of channel width to channel length, and Cox denotes the gate oxide capacitance.
  • Likewise, to characterize the variation in Vt mismatch between two neighboring PFETs of a given circuit design, subthreshold DC voltage characteristic data (Vout vs. Vin) would be measured for each of a plurality of the same/similar circuits comprising device pairs as shown in FIG. 3. In this circumstance, DC transfer curves obtained would be similar to the curves shown in FIG. 5 b for Vout vs. Vin, but the curves would be flipped about the vertical axis, as is understood by those of ordinary skill in the art.
  • The DC data would then be analyzed to determine a distribution of Vin for a given Vout, and a distribution for Vt mismatch would be determined using the determined distribution of Vin. In accordance with the present invention, it has been demonstrated that the distribution of Vin corresponds to the distribution of the Vt mismatch between PFET devices. More specifically, FIG. 6 depicts an analytical model for characterizing Vt mismatch variation between neighboring PFETS, wherein it is shown that the distribution of Vin is equal to the Vt mismatch between PFET devices (i.e., VtP2-VtP1) of FIG. 3.
  • Furthermore, to characterize the variation in Vt mismatch between two neighboring NFET and PFET transistors of a given circuit design, subthreshold DC voltage characteristic data (Vout vs. Vin) would be measured for each of a plurality of identical circuits comprising device pairs as shown in FIG. 4. The DC data would then be analyzed to determine a distribution of Vin for a given Vout, and a distribution for Vt mismatch would be determined using the determined distribution of Vin.
  • For example, FIG. 7 b is an exemplary graphical diagram illustrating subthreshold DC voltage characteristics (Vout vs. Vin) that were measured for a plurality of circuits as depicted in FIG. 4. Using the data shown in FIG. 7 b, a distribution of Vin was determined for a given Vout (as indicated by the dotted line). Preferably, Vout is selected to be less than 0.5 VDD. More specifically, in the exemplary diagram of FIG. 7 b, Vout is preferably selected for a region where the transfer characteristics (Vout vs. Vout) are essentially linear across Vin. In the region of the selected Vout in FIG. 7 b, the DC curves (Vout vs. Vin) are linear, but the curves become more nonlinear as Vout is increased or decreased in relation to the dotted line.
  • Then, for the selected Vout, the distribution of Vt mismatch is determined using the measured distribution of Vin. More specifically, in accordance with the present invention, it has been determined that the distribution of Vin corresponds to the distribution of one-half (½) the Vt mismatch between an NFET and PFET device. FIG. 7 a depicts an analytical mismatch model for the data plotted in FIG. 7 b. As is shown in FIG. 7 a, the distribution of Vin is equal to ½ the Vt mismatch between the devices (i.e., (VtN1-VtP1)/2) shown in FIG. 4.
  • FIG. 10 is a high-level flow diagram illustrating a method for characterizing random Vt variation of a semiconductor integrated circuit according to an embodiment of the invention. In general, characterization of random Vt variation of a given semiconductor integrated circuit can be quantitatively assessed by determining a random Vt variation for each transistor of the circuit. Preferably, to determine the random Vt variation of the circuit transistors, the method of FIG. 10 implements the methods described herein for characterizing Vt mismatch of transistor pairs using subthreshold DC voltage characteristics, wherein the distributions of Vt mismatch between various transistor pairs within the circuit are first measured, and then used for determining the random Vt variation for each transistor in the circuit.
  • A method for characterizing the random Vt variation of a semiconductor integrated circuit according to an embodiment of the invention will now be described in detail with reference to FIG. 10. For purposes of illustration, the method of FIG. 10 will be described with reference to an exemplary embodiment for characterizing random Vt variation of a conventional 6-transistor (6-T) SRAM cell. Referring to FIG. 10, a preferred characterization process begins by obtaining DC voltage characteristic data for various device pairs of a given circuit (step 30) and then determining a distribution of Vt mismatch for each of the device pairs using the corresponding DC voltage characteristic data (step 31).
  • The DC voltage characteristic data may be obtained by retrieving previously measured test data that is stored in a database. Preferably, the test data is collected using various test circuits (which are preferably similar to the desired circuit design) for measuring subthreshold DC voltage characteristic data for different transistor pairs in the circuit.
  • By way of example, the exemplary device pairs illustrated in FIGS. 2, 3 and 4, are commonly found in 6-transistor SRAM cells, as well as other semiconductor integrated circuit devices that comprise NMOS and/or PMOS transistors. Accordingly, to characterize the random Vt variation of a 6-T SRAM cell, various test circuits of a 6-T SRAM cell can be constructed for measuring subthreshold DC voltage characteristics for different transistor pairs in the SRAM cell and then determining the Vt mismatch distribution of neighboring transistors in the 6-T SRAM cell using, for example, the methods described above with reference to FIGS. 2-7. FIGS. 11, 12, 13 and 14 are examples of test circuits that can be used for measuring DC voltage characteristics of different transistor pairs of a conventional 6-T SRAM Cell. As explained below with reference to FIG. 15, multiple implementations of the test circuits of FIGS. 11-14 are preferably incorporated within a testing apparatus, such as the exemplary testing apparatus depicted in FIG. 15, for obtaining sufficient DC voltage characteristic data for statistical analysis.
  • FIG. 11 illustrates a conventional 6-T SRAM cell. The SRAM cell comprises a pair of NMOS access transistors N1 and N2 that allow data bits on bitline pair BLC, BLT to be read and written to storage nodes S1 and S2, respectively. The gate terminals of access (AC) transistors N1 and N2 are commonly connected to a wordline. The SRAM cell further comprises NMOS pull-down transistors N3 and N4, which are coupled in a positive feedback configuration with PMOS pull-up transistors P1 and P2. The operation of a 6-T SRAM cell is well-known in the art.
  • FIG. 11 further illustrates an exemplary test circuit that can be constructed for measuring subthreshold DC voltage characteristics of NMOS transistor pair N2 and N4 of the 6T SRAM cell using the methods described above with reference to FIG. 2 to determine the distribution of random Vt mismatch between the NFETs N2 and N4. More specifically, the DC voltage characteristics, Vout vs. Vin, for the transistor pair N2, N4 are preferably measured by applying a constant voltage VB1 to the gate terminal (wordline) of N2, while sweeping the input voltage, Vin, applied to the gate of N4, and measuring the output voltage, Vout, at storage node S2. In one embodiment, the subthreshold DC voltage characteristics, Vout vs. Vin, for the transistor pair N2, N4 are measured by setting VDD to about 250 mv or lv and setting VB1 to a constant voltage of less than about 250 mv, while sweeping Vin from 0v to a voltage that is less than about 250 mv. These DC voltage measurements are repeated for each of a plurality of the same test circuits of FIG. 11, to thereby obtain a sufficient amount of data to characterize the transistor pair mismatch. Preferably, the data is statistically analyzed (step 31, FIG. 10) to determine the standard deviation of the random distribution of the Vt mismatch of transistor pair N2, N4, that is:

  • σ(VtN4-VtN2)   (1)
  • It is to be appreciated that given the proximity of transistors an SRAM cell, it can be assumed that the measure (1) would be the same or similar with respect to the transistor pair comprising pull-down (PD) transistor N3 and access (AC) transistor N1. Therefore, for transistor pairs (N4, N2) and (N3, N1), measure (1) can be generally represented as:

  • σ(VtPD-VtAC)   (1a)
  • Next, FIG. 12 illustrates an exemplary test circuit that can be constructed for measuring subthreshold DC voltage characteristics of transistor pair P2 and P1 of the 6T SRAM cell using the methods described above with reference to FIG. 3 to determine the random Vt mismatch distribution between the PFETs P2 and P1. More specifically, the DC voltage characteristics, Vout vs. Vin, for the transistor pair P2, P1 are preferably measured by applying a constant voltage VB2 to the gate terminal of P1, while sweeping the input voltage, Vin, applied to the gate terminal of P2, and measuring the output voltage, Vout, at node S3. Furthermore, in the test circuit of FIG. 12, to accurately measure the Vt variation of the transistor pair P2, P1 and eliminate uncertainties due to leakage currents from other transistors in the circuit, the feedback connections between the storage nodes S1, S2 and gate terminals of storage cell transistors are removed and the gate terminals of transistors N1-N4 are grounded.
  • In one embodiment, the subthreshold DC voltage characteristics, Vout vs. Vin, for the transistor pair P2, P1 are measured by setting VDD to about 250 mv or lv and setting VB2 to a constant voltage less than about 250 mv, while sweeping Vin from 0v to a voltage that is less than about 250 mv. These DC voltage measurements are repeated for each of a plurality of the same test circuits of FIG. 12, to thereby obtain a sufficient amount of data to characterize the transistor pair mismatch. Preferably, the data is statistically analyzed (step 31, FIG. 10) to measure the standard deviation of the random distribution of the Vt mismatch of transistor pair P2, P1, that is:

  • σ(VtP2-VtP1)=√{square root over (2)}·σVtP PU   (2)
  • It is to be appreciated that since the channel length an width of pull-up (PU) transistors P2 and P1 in an SRAM cell are the same, and given the proximity of such pull-up transistors an SRAM cell, it can be assumed that the standard deviation of the Vt mismatch between transistor pair is equal to the square root of 2 multiplied by the Vt distribution of either device.
  • FIG. 13 illustrates an exemplary test circuit that can be constructed for measuring subthreshold DC voltage characteristics of transistor pair N4 and P2 of the 6T SRAM cell using the methods described above with reference to FIG. 4 to determine the random Vt mismatch distribution between the transistors N4 and P2. More specifically, the DC voltage characteristics, Vout vs. Vin, for the transistor pair N4, P2 are preferably measured by sweeping the input voltage, Vin, applied to the gates of N4 and P2, and measuring the output voltage, Vout, at storage node S2. In one embodiment, the subthreshold DC voltage characteristics, Vout vs. Vin, for the transistor pair N4, P2 are measured by setting VDD to about 250 mv or lv, while sweeping Vin from 0v to a voltage that is less than about250 mv. These DC voltage measurements are repeated for each of a plurality of the same test circuits of FIG. 13, to thereby obtain a sufficient amount of data to characterize the transistor pair mismatch. Preferably, the data is statistically analyzed (step 31, FIG. 10) to measure the standard deviation of the random distribution of the Vt mismatch of transistor pair N4, P2, that is:

  • σ(VtN4-VtP 2)   (3)
  • It is to be appreciated that given the proximity of transistors an SRAM cell, the measure (3) would be the same or similar with respect to pull-down (PD) transistor N3 and pull-up (PU) transistor P1. Therefore, for transistor pairs (N4, P2) and (N3, P1), measure (3) can be generally represented as:

  • σ(VtPD-vTPU)   (3a)
  • FIG. 14 illustrates an exemplary test circuit that can be constructed for measuring subthreshold DC voltage characteristics of transistor pair N3 and N4 of the 6T SRAM cell using the methods described above with reference to FIG. 2 to determine the random Vt mismatch distribution between the NFETs N3 and N4. More specifically, the DC voltage characteristics, Vout vs. Vin, for the transistor pair N3, N4 are preferably measured by applying a constant voltage VB1 to the gate terminal of N3, while sweeping the input voltage, Vin, applied to the gate of N4, and measuring the output voltage, Vout, at node S4. In one embodiment, the subthreshold DC voltage characteristics, Vout vs. Vin, for the transistor pair N3, N4 are measured by setting VDD to about 250 mv or lv and setting VB1 to a constant voltage less than about 250 mv, while sweeping Vin from 0v to a voltage that is less than about 250 mv. These DC voltage measurements are repeated for each of a plurality of the same test circuits of FIG. 14, to thereby obtain a sufficient amount of data to characterize the transistor pair mismatch. Preferably, the data is statistically analyzed (step 31, FIG. 10) to measure the standard deviation of the random distribution of the Vt mismatch of transistor pair N4, N3, that is:

  • σ(VtNA-VtN3)=√{square root over (2)}·σVtN PD   (4)
  • It is to be appreciated that since the channel length an width of pull-down (PD) transistors N4 and N3 in an SRAM cell are designed to be the same, and given the proximity of such pull-down transistors an SRAM cell, it can be assumed that the standard deviation of the Vt mismatch between transistor pair is equal to the square root of 2 multiplied by the Vt distribution of either device.
  • Referring again to FIG. 10, once the random distributions of Vt mismatch for the desired device pairs are determined (step 31), the measured Vt mismatch distributions are preferably used for determining the random Vt variation for each of the devices in the circuit (step 32). For instance, in the exemplary embodiment of an SRAM cell as described above, measures (1a) and (4) are used for determining σVtAC, measure (2) yields σVtPU, and measure (4) yields σVtPD, for the exemplary voltages noted above. Measures 3a and 4 can also yield σVtPU.
  • The measured Vt variations can then be used to quantitatively assess/characterize the overall random Vt variation of the circuits and determine the affects of such random Vt variation on circuit performance (step 33).
  • It is to be understood that the methods described herein for collecting and statistically analyzing subthreshold DC voltage data may be implemented in various forms of hardware, software, firmware, special purpose processors, or a combination thereof. For instance, the method of FIG. 10 may be implemented as an application comprising program instructions that are tangibly embodied on one or more program storage devices (e.g., hard disk, magnetic floppy disk, RAM, ROM, CD ROM, etc.) and executable by any device or machine comprising suitable architecture.
  • FIG. 15 is an exemplary diagram illustrating a testing apparatus according to an embodiment of the present invention, which can be used for measuring DC voltage characteristic data for test circuits. FIG. 15 a illustrates an exemplary testing apparatus (40) comprising a plurality of cell columns (C1, C2, . . . C1) and a plurality of corresponding multiplexers (M1, M2, . . . Mi). Each cell column Ci comprises a plurality of test circuits (1, 2, . . . , 2 N) that are constructed for measuring test data. For example, each test circuit in a given column Ci could correspond to any of the circuits depicted in FIGS. 2-4 or FIGS. 11-14. Each column Ci is identical with respect to its constituent test circuits, e.g., test circuit 1 in each column Ci is the same, and so on.
  • Preferably, each column Ci is designed to include a variety of circuits that would provide sufficient test data to effectively characterize the circuits) under considerations. For instance, each cell column may comprise multiple configurations of the circuits shown in FIGS. 2-4 with variations in channel widths W1, W2, channels lengths L1, L2 and orientation of the device pairs. Furthermore, for measuring DC voltage characteristic data for a 6T SRAM cell as discussed above, each cell column (Ci) may include multiple configuration of the circuits shown in FIGS. 11-14. For example, assume that N=8 and, thus, there are 1024 cells in each column. Then, in each column Ci, the first 256 cells may comprise the test circuit depicted in FIG. 11, the next 256 cells may comprise the test circuit depicted in FIG. 12, the next 256 cells may comprise the test circuit depicted in FIG. 13, and the last 256 cells may comprise the test circuit depicted in FIG. 14.
  • FIG. 15 b illustrates one of the cell columns (e.g., C1) and corresponding multiplexer (e.g., M1) in the testing apparatus (40), although it is understood that all cell columns are identical in structure. As shown in FIG. 15( b), a Vin terminal of the testing apparatus (40) is commonly connected to Vin terminals of each test circuit in the column C1 (as well as the other columns across the testing apparatus). During operation, the multiplexer M1 selects one of the 2N cell Vouts with N address bits using CMOS pass gates of the Multiplexer M1. More specifically, Vout measurements are simultaneously obtained for each corresponding cell in all cell columns across the testing apparatus. Furthermore, a mechanism is provided for applying Vin to only those circuits whose outputs are being selected by the multiplexer. In one embodiment, a decoder that selects a pass-gate in the multiplexer enables only the selected cell corresponding to the pass-gate to be measured. Thus, the multiplexers comprise decoders and pass-gates.
  • It is to be appreciated that the testing apparatus (40) can be operated under the control of computer or any control system as is known in the art, which can generate control signals (e.g., address bits N) and measure and collect test data that is output from the testing apparatus.
  • Preferably, the transistors (CMOS pass gates) of the multiplexer M1 are constructed to have long and wide device widths, which significantly reduces/eliminates the uncertainty that could be added to the measured voltage characteristics as a result of leakage currents from the Mux transistors. In addition, the multiplexer M1 preferably operates with a low VDD1 and RBB (reverse body bias) to further reduce the uncertainty that could be added to the measured voltage characteristics. Moreover, the value N can be selected based on the leakage uncertainty from the Mux transistors to Vout.
  • To verify that the measurements shown in FIGS. 5 b and 7 b, for example, were the result of random sources and not systematic (manufacturing) sources, the Vt mismatch for the right side of an SRAM cell was compared with the Vt mismatch for the left side of the SRAM cell and the data was plotted. FIG. 8 is an exemplary graphical diagram illustrating correlations of measurements of neighboring pairs of transistors in a SRAM cell to verify that measured variations in device parameters, which are characterized using circuits and methods of the invention, are the result of random sources. If the variation was due to systematic sources, there would be spatial correlation. For instance, the measured Vin as shown in FIG. 5 b or 7 b for each characteristic would move in the same direction for the left or right side of the cell, due to spatial correlation of systematic sources of variation , i.e., the mismatch of two neighboring devices would move in the same direction due to systematic sources of variation. However, as shown in FIG. 8, the correlation coefficients were determined to be less than 0.05, which indicates a marginal correlation between data measurements between the right and left side of the cell (i.e., the variations are overwhelmingly random).
  • FIG. 9 is an exemplary graphical diagram comparing the distribution densities of Vt mismatch that were obtained using conventional models of dopant fluctuations, with a distribution density of Vt mismatch as measured using circuits and methods according to the invention for characterizing Vt mismatch. In particular, FIG. 9 depicts the measured distribution of Vt mismatch that was obtained using the data shown in FIGS. 5 b and 7 b as compared with analytical models for Vt variations that are obtained from dopant fluctuations. As shown in FIG. 9, the measured distribution is similar to the distributions determined from the analytical models. Thus, it can reasonably be concluded that the circuits and methods described herein in accordance with the present invention effectively measure random sources of variation due to dopant fluctuations, which is a primary source for random Vt variation in neighboring devices.
  • Although exemplary embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the present system and method is not limited to those precise embodiments, and that various other changes and modifications may be affected therein by one skilled in the art without departing from the scope or spirit of the invention. All such changes and modifications are intended to be included within the scope of the invention as defined by the appended claims.

Claims (18)

1. A testing apparatus for characterizing device mismatch in a semiconductor integrated circuit, comprising:
a plurality of test circuits, wherein each test circuit is configured for obtaining subthreshold DC voltage characteristic data for a device pair of an integrated circuit; and
a multiplexer, for selectively outputting an output voltage from each test circuits.
2. The testing apparatus of claim 1, wherein a portion of the plurality of test circuits are configured for testing the same device pair.
3. The testing apparatus of claim 1, wherein the plurality of test circuits are divided into groups of test circuits, wherein each group of the test circuits comprises the same test circuits.
4. The testing apparatus of claim 1, wherein each group of test circuits is associated with a multiplexer, wherein the multiplexers are controlled such that the output voltages from similar test circuits in each group are simultaneously measured.
5. The testing apparatus of claim 1, further comprising a database for storing the subthreshold DC voltage characteristic data.
6. The testing apparatus of claim 5, further comprising a processing unit for statistically processing the subthreshold DC voltage characteristic data stored in database for determining a distribution of device mismatch of the integrated circuit.
7. A testing apparatus for characterizing device mismatch in a semiconductor integrated circuit, comprising:
a plurality of test circuits, wherein each test circuit is configured for obtaining subthreshold DC voltage characteristic data for a device pair of an integrated circuit, the device pair selected by a test circuit of the plurality of test circuits corresponding to the device pair, wherein the device pair comprise neighboring first and second transistors, wherein the subthreshold DC voltage characteristic data for the selected device pair comprises an output DC voltage VouT as a function of an input DC voltage VIN, wherein VIN is applied to a gate of at least one of the first and second transistors and wherein VouT is obtained at a common node connection of the first and second transistors, and wherein the DC voltage characteristic data is obtained with the first and second transistor devices operating in a subthreshold region; and
a multiplexer, for selectively outputting an output voltage from each test circuits.
8. The testing apparatus of claim 7, wherein at least two of the plurality of test circuits are configured for testing the device pair.
9. The testing apparatus of claim 7, wherein the plurality of test circuits are divided into groups of test circuits, wherein each group of the test circuits comprises a same type of test circuit.
10. The testing apparatus of claim 9, wherein each group of test circuits is associated with a different multiplexer, wherein the multiplexers are controlled such that the output voltages from the same type test circuits in each group are simultaneously measured.
11. The testing apparatus of claim 9, further comprising a database for storing the subthreshold DC voltage characteristic data.
12. The testing apparatus of claim 12, further comprising a processing unit for statistically processing the subthreshold DC voltage characteristic data stored in database for determining a distribution of device mismatch of the integrated circuit.
13. A test circuit comprising:
a pair of access transistors;
a bitline pair comprising a first bitline and a second bitline connected to respective transistors of the pair of access transistors, respectively;
a pair of storage nodes connected to respective transistors of the pair of access transistors;
a wordline commonly connected to gate terminals of the pair of access transistors; and
a pair of pull-down transistors coupled with a pair of pull-up transistors, wherein each storage node of the pair of storage nodes is disposed between a respective pull-down transistor and a respective pull-up transistor.
14. The test circuit of claim 13, wherein gates of the pair of pull-down transistors are connected to a ground voltage.
15. The test circuit of claim 13, wherein gates of the pair of access transistors are connected to a ground voltage.
16. The test circuit of claim 13, wherein gates of the pair of access transistors are connected to a constant voltage.
17. The test circuit of claim 13, wherein a first storage node of the pair of storage nodes is connected to a gate terminal of a first pull-down transistor of the pair of pull-down transistors and connected to a drain terminal of a second pull-down transistor of the pair of pull-down transistors, and a second storage node of the pair of storage nodes is connected to a gate terminal of a second pull-down transistor of the pair of pull-down transistors and connected to a drain terminal of a first pull-down transistor of the pair of pull-down transistors.
18. The test circuit of claim 13, wherein a first storage node of the pair of storage nodes is connected to a gate terminal of a first pull-up transistor of the pair of pull-down transistors and connected to a source terminal of a second pull-up transistor of the pair of pull-up transistors, and a second storage node of the pair of storage nodes is connected to a gate terminal of a second pull-up transistor of the pair of pull-down transistors and connected to a drain terminal of a first pull-up transistor of the pair of pull-up transistors.
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